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2025
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G/S
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Integrated circuits; semiconductors; system-on-chip devices; microprocessors; processors [central... |
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G/S
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Integrated circuits; semiconductors; system-on-chip devices; microprocessors; processors [ centra... |
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G/S
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Integrated circuits; Semiconductors; System-on-chips; Microprocessors; Computer central processin... |
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G/S
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Integrated circuits; semiconductors; system-on-chip devices;
microprocessors; processors [centra... |
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G/S
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Integrated circuits; semiconductors; electronic circuits for
system- on-chip devices; microproce... |
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G/S
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Computer hardware and recorded computer software, namely, computer subsystems featuring standardi... |
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G/S
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Computer hardware and computer software, namely, compute subsystems featuring standardized and op... |
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G/S
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Development of voluntary standards for the interoperability and security of computer instruction ... |
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Invention
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Method and apparatus for instruction checkpointing in a data processing device powered by an unpr... |
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G/S
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Computer software development tools in the field of artificial intelligence; computer software an... |
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Invention
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Block matching between first data and second data.
A processor, method, and non-transitory compu... |
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Invention
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Tag way-halting. A memory subsystem can include a preamble tag memory and one or more prologue ta... |
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Invention
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Method of memory access with efficient tag pipeline latency. A method of memory access includes, ... |
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Invention
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Optimized tag lookup in a way halting cache. A method of performing an address lookup process in ... |
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Invention
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Optimized error correction code architecture for memory. A memory circuitry with optimized error ... |
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Invention
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Graphics processing systems.
A tile-based graphics processor comprises a data encoder configured... |
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Invention
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Data processing systems.
When performing rendering in a graphics processor that comprises plural... |
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Invention
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Cell arrangement for semiconductor device layout. Subject matter disclosed herein relates general... |
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Invention
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Technique for managing compression of data in an apparatus. An apparatus is described having a pr... |
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Invention
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Exception handling. Apparatuses, methods, computer programs and computer readable storage media a... |
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Invention
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Restriction of bandwidth utilisation. There is provided an apparatus, a method, and a computer pr... |
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Invention
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Black box circuitry for data processing apparatus. A data processing apparatus is implemented on ... |
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G/S
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Electronic data processing equipment; computer hardware; integrated circuits; semiconductors; sys... |
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2024
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G/S
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Downloadable open-source computer software for accelerating and optimizing artificial intelligenc... |
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Invention
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Fulfilment of transaction requests. There is provided an apparatus, a method, a system, a chip co... |
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Invention
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Cell arrangement for semiconductor device layout.
Subject matter disclosed herein relates genera... |
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Invention
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Common control and/or observation for internal state tracking.
The present disclosure relates ge... |
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Invention
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Efficient data processing. A method and processing unit for mapping coordinates of a tensor to a ... |
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Invention
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Branch prediction. An apparatus comprises storage circuitry to maintain a data-dependent branch p... |
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Invention
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Prediction circuitry.
An apparatus comprises fetch circuitry configured to fetch instructions fo... |
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Invention
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Invalidate-write hazard detection.
An apparatus comprises invalidation range tracking circuitry ... |
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Invention
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Circuits, systems and/or processes for instruction sequence test error tracking.
The present dis... |
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Invention
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Ic cell layout alternative geometry verification.
Briefly, example apparatuses, articles of manu... |
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Invention
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Rapid power ready signaling in a memory array.
A first memory instance comprises one or more fir... |
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Invention
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Compare circuitry for a fast and glitchless compare in memory.
A compare circuitry that can be i... |
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Invention
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Technique for managing compression of data in an apparatus.
An apparatus is described having a p... |
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Invention
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Optimized tag lookup in a way halting cache.
A method of performing an address lookup process in... |
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Invention
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Tag way-halting.
A memory subsystem can include a preamble tag memory and one or more prologue t... |
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|
Invention
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Method of memory access with efficient tag pipeline latency.
A method of memory access includes,... |
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Invention
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Optimized error correction code architecture for memory.
A memory circuitry with optimized error... |
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Invention
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Method and apparatus for reduction of recurring cache misses. A control circuit is configured to ... |
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Invention
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Prefetch request generation.
An apparatus has decoding circuitry to decode instructions defined ... |
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Invention
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Accessing transaction configuration data.
Apparatuses, systems, methods, computer-readable media... |
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Invention
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Access time in a memory array.
A memory device includes a bitcell array having at least a first ... |
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Invention
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Graphics processing.
One or more tasks for a processing job are distributed to processing cores ... |
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Invention
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Graphics processing.
When performing ray tracing in a graphics processing system, relative numbe... |
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Invention
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Restriction of bandwidth utilisation.
There is provided an apparatus, a method, and a computer p... |
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Invention
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Graphics processing.
When performing ray tracing in a graphics processing system a ray tracing a... |
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Invention
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Graphics processing.
When generating a render output representing a view of a scene comprising o... |
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Invention
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Halting instruction execution.
A data processing apparatus is provided that includes storage cir... |
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Invention
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Determining a block size associated with a task to be processed.
A method of determining a block... |
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Invention
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Graphics processing.
A tile-based graphics processor is disclosed. One or more bounding boxes th... |
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Invention
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Graphics processing.
A tile-based graphics processor that generates and traverses a hierarchy of... |
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Invention
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Graphics processing.
A tile-based graphics processor that generates and processes packets of pri... |
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Invention
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Efficient data processing.
A processor and method for handling data, by obtaining operations fro... |
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2023
|
G/S
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Instruction set architectures (computer programs); interfaces for computers namely computer inter... |
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G/S
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Graphics processing units (GPUs); semiconductors; integrated circuits; computer software used in,... |
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G/S
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Instruction set architectures (computer programs);
interfaces between computer hardware and comp... |
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G/S
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Instruction set architectures; interfaces between computer hardware and computer software; microp... |
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Invention
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Distributed processing provision.
A device and method, comprising: determining a quantum of data... |
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Invention
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Vector extract and merge instruction.
There is provide an apparatus, method and medium. The appa... |
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Invention
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Integrity checking.
An apparatus has processing circuitry to execute instructions. The processin... |
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Invention
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Methods and apparatus for branch instruction security.
Aspects of the present disclosure relate ... |
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Invention
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Technique for performing outer product operations.
An apparatus has processing circuitry to perf... |
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2022
|
G/S
|
Graphics processing units (GPUs); semiconductors; integrated
circuits; computer software used in... |
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G/S
|
Graphics processing units (GPUs); semiconductors; integrated circuits; downloadable computer soft... |
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G/S
|
Instruction set architectures, namely, downloadable computer software instructions designed to fu... |
