|
2025
|
Invention
|
Structure and method for providing line end extension for fin-type regions.
A semiconductor stru... |
|
2023
|
Invention
|
Clock mode determination in a memory system. A clock mode configuration circuit for a memory devi... |
|
|
Invention
|
Structure and method for providing line end extensions for fin-type active regions. A semiconduct... |
|
|
Invention
|
Nand flash memory with vertical cell stack structure and method for manufacturing same. Disclosed... |
|
|
Invention
|
Non-volatile memory device with concurrent bank operations. An apparatus, system, and method for ... |
|
2022
|
Invention
|
Semiconductor chip. A semiconductor chip includes a substrate and a transistor. The transistor is... |
|
2021
|
G/S
|
Commercial administration of intellectual property licensing programs; Procuring of contracts for... |
|
|
Invention
|
Three-dimensional nonvolatile memory cell structure. A three-dimensional integrated circuit non-v... |
|
|
G/S
|
Procuring of contracts for the purchase and sale of intellectual property; Business management se... |
|
|
Invention
|
Dram, memory controller and associated training method. A training method for a memory system is ... |
|
|
Invention
|
Integrated erase voltage path for multiple cell substrates in nonvolatile memory devices.
A non-... |
|
|
G/S
|
Commercial administration of intellectual property licensing programs for others, namely providin... |
|
|
Invention
|
Method for erasing memory cells in a flash memory device using a positive well bias voltage and a... |
|
2020
|
Invention
|
Systems and methods for minimizing static leakage of an integrated circuit. A leakage manager sys... |
|
|
Invention
|
Through semiconductor via structure with reduced stress proximity effect.
An integrated circuit ... |
|
|
Invention
|
Manufacturing method of semiconductor chip. A semiconductor chip includes a substrate and a trans... |
|
|
Invention
|
Power managers for an integrated circuit. Systems and methods manage power in an integrated circu... |
|
|
Invention
|
Flash memory system. A method and system for controlling an MBC configured flash memory device to... |
|
|
Invention
|
Non-volatile semiconductor memory having multiple external power supplies. A memory device includ... |
|
|
Invention
|
Dynamic impedance control for input/output buffers. A system and method of performing off chip dr... |
|
2019
|
Invention
|
Three-dimensional nonvolatile memory cell structure with upper body connection. A three-dimension... |
|
|
Invention
|
Charge pump for pll/dll. A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes... |
|
|
Invention
|
Non-volatile memory device. An apparatus, system, and method for controlling data transfer to an ... |
|
2018
|
Invention
|
Semiconductor chip and manufacturing method thereof. A semiconductor chip includes a substrate an... |
|
|
Invention
|
Memory device with manufacturable cylindrical storage node. A high capacitance embedded capacitor... |
|
|
Invention
|
Circuit for clamping current in a charge pump. A circuit for clamping current in a charge pump is... |
|
|
Invention
|
Memory with output control. An apparatus, system, and method for controlling data transfer to an ... |
|
2017
|
Invention
|
Method and system for accessing a flash memory device. An apparatus, system, and computer-impleme... |
|
|
Invention
|
Manufacturing method of solid-state image sensor. A single crystal silicon layer is formed on a p... |
|
2013
|
Invention
|
Synchronous memory read data capture. A method of snap-shot data training to determine the optimu... |
|
2007
|
G/S
|
Apparatus and instruments for conducting, switching, transforming, accumulating, regulating or co... |
