2025
|
Invention
|
Method for making nanostructure transistors with source/drain trench contact liners.
A method fo... |
2024
|
Invention
|
Integrated circuit chip including arrays of multi-threaded dynamic random access memory unit cell... |
|
Invention
|
Single-ended sense amplifiers and methods for operating same. A bit line is pre-charged to ground... |
|
Invention
|
Interconnect structure for an array of multi-threaded dynamic random access memory systems. An ar... |
|
Invention
|
Interconnect structure for an array of multi-threaded dynamic random access memory systems.
An a... |
|
Invention
|
Single-ended sense amplifiers and methods for operating same.
A bit line is pre-charged to groun... |
|
Invention
|
Semiconductor device including a superlattice and an asymmetric channel and related methods.
A s... |
|
Invention
|
Semiconductor device including superlattice with o18 enriched monolayers.
A semiconductor device... |
|
Invention
|
Method for making a semiconductor device using superlattices with different non-semiconductor the... |
|
Invention
|
Method for making gate-all-around (gaa) device including a superlattice.
A method for making a s... |
|
Invention
|
Method for making nanostructure transistors with flush source/drain dopant blocking structures in... |
|
Invention
|
Method for making nanostructure transistors with offset source/drain dopant blocking structures i... |
|
Invention
|
Method of fabricating semiconductor devices with isolated superlattice structures. A method for m... |
|
Invention
|
Method of fabricating semiconductor devices with isolated superlattice structures.
A method for ... |
|
Invention
|
Methods for making semiconductor transistor devices with recessed superlattice over well regions.... |
|
Invention
|
Method for making a non-volatile memory including a depletion layer with a superlattice.
A metho... |
|
Invention
|
Non-volatile memory including a depletion layer with a superlattice and related methods.
A memor... |
|
Invention
|
Non-volatile memory including a depletion layer with nanocrystals.
A memory device may include a... |
|
Invention
|
Method for making a non-volatile memory including a depletion layer with nanocrystals.
A method ... |
|
Invention
|
Non-volatile memory including a depletion layer with a superlattice and related methods. A memory... |
|
Invention
|
Non-volatile memory including a depletion layer with nanocrystals and related methods. A memory d... |
|
Invention
|
Complementary field effect transistor (cfet) devices including superlattice isolation layer and a... |
|
Invention
|
Complementary field effect transistor (cfet) devices including superlattice isolation layer.
A s... |
|
Invention
|
Method for making complementary field effect transistor (cfet) devices including superlattice iso... |
|
Invention
|
Method for making memory device including a superlattice gettering layer. A method for making a s... |
|
Invention
|
Memory device including a superlattice gettering layer and associated methods. A semiconductor de... |
|
Invention
|
Memory device including a superlattice gettering layer.
A semiconductor device may include a sem... |
|
Invention
|
Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial... |
|
Invention
|
Radio frequency (rf) semiconductor devices including a ground plane layer having a superlattice. ... |
|
Invention
|
Methods for making radio frequency (rf) semiconductor devices including a ground plane layer havi... |
|
Invention
|
Dmos devices including a superlattice and field plate for drift region diffusion.
A double-diffu... |
|
Invention
|
Method for making dmos devices including a superlattice and field plate for drift region diffusio... |
|
Invention
|
Dmos devices including a superlattice and field plate for drift region diffusion and related meth... |
|
Invention
|
Methods for making semiconductor devices including localized semiconductor-on-insulator (soi) reg... |
|
Invention
|
Semiconductor devices including localized semiconductor-on-insulator (soi) regions.
A semiconduc... |
|
Invention
|
Semiconductor devices including localized semiconductor-on-insulator (soi) regions and related me... |
|
Invention
|
Nanostructure transistors with flush source/drain dopant blocking structures including a superlat... |
|
Invention
|
Nanostructure transistors with offset source/drain dopant blocking structures including a superla... |
|
Invention
|
Nanostructure transistors with source/drain trench contact liners and associated methods. A semic... |
|
Invention
|
Nanostructure transistors with source/drain trench contact liners.
A semiconductor device may in... |
|
Invention
|
Method for making nanostructure transistors with source/drain trench contact liners. A method for... |
|
Invention
|
Method for making a radio frequency silicon-on-insulator (rfsoi) wafer including a superlattice. ... |
|
Invention
|
Method for making radio frequency silicon-on-insulator (rfsoi) structure including a superlattice... |
2020
|
G/S
|
Downloadable software for designing and manufacturing semiconductors and semiconductor chips, dev... |
2015
|
G/S
|
Providing licensing of semiconductor intellectual property |
2006
|
G/S
|
semiconductor materials, namely, group IV semiconductors and compound, modified and enhanced semi... |