A method of testing semiconductor wafers includes receiving a wafer bin map for a semiconductor wafer, wherein the wafer bin map includes a plurality of points corresponding to a plurality of defective dies fabricated on the semiconductor wafer, identifying a cluster of points in the wafer bin map from the plurality of points, and generating a filtered bin map using the cluster of points. The method also includes extracting a set of features for the filtered bin map, wherein the set of features comprises a set of global features common to the semiconductor wafer and a set of cluster features specific to the filtered bin map, executing a trained machine learning model using the set of features as inputs to generate a pattern classification, and determining, based on the pattern classification, that the semiconductor wafer includes a pattern of defective dies caused by a defective manufacturing process.
A method of identifying defects in an electronic assembly, comprising, by a processing unit, obtaining a grid of nodes representative of a location of electronic units of an electronic assembly, wherein each node is neighboured by at most eight other nodes, wherein a first plurality of nodes represents failed electronic units according to at least one test criterion, and a second plurality of nodes represents passing electronic units according to the least one first test criterion, based on the grid, determining at least one first and second straight lines, and attempting to connect the first and second straight lines into a new line, wherein if at least one node from the new line belongs to the second plurality of nodes, concluding that an electronic unit represented by the node on the grid is a failed electronic unit, thereby facilitating identification of a failed electronic unit on the substrate.
A method for generating a reliability performance model includes developing a reliability prediction machine learning model for predicting reliability performance of a product based on data obtained from manufacturing and testing of the product, and obtaining feature names for the reliability prediction machine learning model and their predictive power values. The feature names may correspond to features from the data obtained from manufacturing and testing of the product. The method may further include extracting a set of feature names corresponding to features having highest predictive power values from the feature names, and generating a reliability performance model using one or more model parameters derived from the set of feature names.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G06F 119/02 - Reliability analysis or reliability optimisationFailure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
A method for analyzing device test data includes accessing a core analytics rule that is based on manufacturing data of a plurality of devices. Each of the plurality of devices are produced in one of a plurality of manufacturing facilities and are of a same type as a first device being tested on a tester. The method also includes receiving initial test results of a plurality of other devices of a same type tested at a testing facility, generating, based on the initial test results, an edge analytics rule, modifying the core analytics rule based on the edge analytics rule, wherein the modified core analytics rule including modified binning limits, applying the modified core analytics rule to testing data obtained by testing the first device, and determining, based on applying the modified core analytics rule, that the first device is an outlier with respect to the modified binning limits.
G01R 31/01 - Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass productionTesting objects at points as they pass through a testing station
A method of sorting an electronic device includes receiving first data generated by a test tool that is performing a test operation on the electronic device according to a test program, and a provisional binning assignment for the electronic device determined from the first data. The method also includes defining a permanent binning assignment for the electronic device based at least in part on applying a first algorithm and a second algorithm to the first data, the first algorithm and the second algorithm being different. The method further includes outputting the permanent binning assignment so that after the test operation is completed, the electronic device is removed from the test tool and placed in one of a plurality of bins according to the permanent binning assignment.
Methods and systems include receiving a product attribute that identifies a product. A first component attribute and a second component attribute are received. The first component attribute identifies a first component included in the product and the second component attribute identifies a second component included in the product. The methods and systems further includes receiving first manufacturing data associated with the first component and second manufacturing data associated with the second component, applying a set of compatibility rules to the first manufacturing data and the second manufacturing data, determining pairing data from the application of the set of compatibility rules to the first manufacturing data and the second manufacturing data, applying a set of pairing rules to the pairing data, determining one or more actions from the application of the set of pairing rules to the pairing data, and performing the one or more actions.
A method comprising, by a processing unit and a memory: obtaining a training set of data; dividing sets of data into a plurality of groups, wherein all sets of data for which feature values meet at least one similarity criterion, are in the same group, storing in a reduced training set of data, for each group, at least one aggregated set of data, wherein, for a plurality of the groups, a number of aggregated sets of data is less than a number of the sets of data of the group, wherein the reduced training set of data is suitable to be used in a classification algorithm for determining a relationship between the at least one label and the features of the electronic items, thereby reducing computation complexity when processing the reduced training set of data, compared to processing the training set of data.
A method of identifying defects in an electronic assembly, comprising, by a processing unit, obtaining a grid of nodes representative of a location of electronic units of an electronic assembly, wherein each node is neighboured by at most eight other nodes, wherein a first plurality of nodes represents failed electronic units according to at least one test criterion, and a second plurality of nodes represents passing electronic units according to the least one first test criterion, based on the grid, determining at least one first and second straight lines, and attempting to connect the first and second straight lines into a new line, wherein if at least one node from the new line belongs to the second plurality of nodes, concluding that an electronic unit represented by the node on the grid is a failed electronic unit, thereby facilitating identification of a failed electronic unit on the substrate.
A method for generating an augmented reliability performance model for a product includes obtaining a reliability performance model for the product, developing a reliability prediction machine learning model for predicting reliability performance of the product based on data obtained from manufacturing and testing of the product, and obtaining, from development of the machine learning model, feature names for the machine learning model and their predictive power values. The feature names may correspond to features from the data obtained from manufacturing and testing of the product. The method may further include extracting a set of feature names corresponding to features having highest predictive power values from the feature names, and generating the augmented reliability performance model for the product by modifying the reliability performance model to incorporate model parameters derived from the set of feature names.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G06F 119/02 - Reliability analysis or reliability optimisationFailure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
10.
Method and system for real time outlier detection and product re-binning
A method for identifying outlier devices during testing, includes: establishing binning limits for a device being tested based on one or more rules generated from external test results data of tests involving similar devices; receiving test results data in real time for the device being tested while the device is on a device tester; applying the one or more rules to the test results data for the device in real time; determining in real time, based on results of applying the one or more rules to the test results data, whether the device is an outlier with respect to the binning limits; and in response to determining that the device is an outlier, binning the outlier device separately from tested devices having test results data falling within the binning limits.
G01R 31/01 - Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass productionTesting objects at points as they pass through a testing station
iQA,2 is met if data representative of passing first bin assignment obtained for electronic units which have been tested on the first site, meets a quality criteria.
A method of identifying defects in an electronic assembly, comprising, by a processing unit, obtaining a grid of nodes representative of a location of electronic units of an electronic assembly, wherein each node is neighboured by at most eight other nodes, wherein a first plurality of nodes represents failed electronic units according to at least one test criterion, and a second plurality of nodes represents passing electronic units according to the least one first test criterion, based on the grid, determining at least one first and second straight lines, and attempting to connect the first and second straight lines into a new line, wherein if at least one node from the new line belongs to the second plurality of nodes, concluding that an electronic unit represented by the node on the grid is a failed electronic unit, thereby facilitating identification of a failed electronic unit on the substrate.
Systems and methods for sorting an electronic device undergoing a final test operation in accordance with a test program, into one of a plurality of bins. In one embodiment, an evaluator defines the binning of the electronic device while the device is still socketed, and the defined binning may or may not concur with the binning assigned by the test program.
A method includes receiving, from a system manufacturer, system test data for a plurality of electronic systems. Each of the plurality of electronic systems includes a plurality of electronic components. The method also includes determining a relationship between a set of electronic components from the plurality of electronic components and the electronic systems upon which the electronic components of the set of electronic components are assembled and receiving, from a component manufacturer, manufacturing attributes for the set of electronic components. The method further includes selecting a data subset from the system test data corresponding to a subgroup of the set of electronic components. The subgroup includes components from a same fabrication cluster. Additionally, the method includes identifying an outlier relative to the data subset and communicating information about the outlier to at least one of the system manufacturer or the component manufacturer.
A method includes receiving system test data for a plurality of electronic systems. Each of the electronic systems includes a plurality of electronic components. The method also includes determining a relationship between a set of electronic components and the electronic systems upon which the electronic components of the set of electronic components are assembled and receiving manufacturing attributes including spatial data for the set of electronic components. The method further includes selecting a data subset from the system test data corresponding to a subgroup of the set of electronic components. The subgroup includes components within an area defined on a substrate according to a spatial pattern and that is fewer than all of the set of electronic components on the substrate. Additionally, the method includes identifying an outlier relative to the data subset and communicating information about the outlier to at least one of a system or a component manufacturer.
G06Q 10/06 - Resources, workflows, human or project managementEnterprise or organisation planningEnterprise or organisation modelling
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A method includes receiving, from a system manufacturer, system test data for a plurality of electronic systems. Each of the plurality of electronic systems includes a plurality of electronic components. The method also includes determining a relationship between a set of electronic components from the plurality of electronic components and the electronic systems upon which the electronic components of the set of electronic components are assembled and receiving, from a component manufacturer, manufacturing attributes for the set of electronic components. The method further includes selecting a data subset from the system test data corresponding to a subgroup of the set of electronic components. The subgroup includes components from a same fabrication cluster. Additionally, the method includes identifying an outlier relative to the data subset and communicating information about the outlier to at least one of the system manufacturer or the component manufacturer.
A method of augmenting a reliability model for a manufactured product includes receiving a product attribute identifying a product, receiving a first component attribute and a second component attribute, and receiving first manufacturing data and second manufacturing data, the first manufacturing data comprising manufacturing data associated with the first component and the second manufacturing data comprising manufacturing data associated with the second component. The method can include applying a set of compatibility rules to the first manufacturing data and the second manufacturing data, determining pairing data from the application of the set of compatibility rules to the first manufacturing data and the second manufacturing data, obtaining a reliability model of products including the product, augmenting the reliability model based on the pairing data, and performing one or more actions with the augmented reliability model.
G06Q 10/06 - Resources, workflows, human or project managementEnterprise or organisation planningEnterprise or organisation modelling
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
Embodiments describe a method of manufacture including receiving a product attribute identifying a product, and receiving a first component attribute and a second component attribute, the first component attribute identifying a first component included in the product and the second component attribute identifying a second component included in the product. The method further includes receiving first manufacturing data associated with the first component and second manufacturing data associated with the second component, applying a set of compatibility rules to the first manufacturing data and the second manufacturing data, determining pairing data from the application of the set of compatibility rules to the first manufacturing data and the second manufacturing data, applying a set of pairing rules to the pairing data, determining one or more actions from the application of the set of pairing rules to the pairing data, and performing the one or more actions.
G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
G06F 17/30 - Information retrieval; Database structures therefor
Methods and systems include receiving a product attribute that identifies a product. A first component attribute and a second component attribute are received The first component attribute identifies a first component included in the product and the second component attribute identifies a second component included in the product. The methods and systems further includes receiving first manufacturing data associated with the first component and second manufacturing data associated with the second component, applying a set of compatibility rules to the first manufacturing data and the second manufacturing data, determining pairing data from the application of the set of compatibility rules to the first manufacturing data and the second manufacturing data, applying a set of pairing rules to the pairing data, determining one or more actions from the application of the set of pairing rules to the pairing data, and performing the one or more actions.
Disclosed are methods, systems and computer program products where an item may or may not be determined as counterfeit based on result(s) of a comparison between test data for the item, and test data for items that are associated with manufacturing data in the cluster that is most likely to include manufacturing data that is associated with attribute data obtained for the item. In some embodiments, such methods, systems and computer program products may allow automated, universal non-destructive, and/or non-invasive detection of counterfeit electronic items. In some embodiments, counterfeit detection may be integrated into existing supply chains, including high volume manufacturing supply chains, and may be performed for a large variety of items without a need for a major adjustment to manufacturing. However, the counterfeit detection in some embodiments may not necessarily be integrated into manufacturing and may occur at any time, even when an item is in use.
A method for modifying the execution sequence of tests for testing an object on a test system. The tests include a group of tests that is a candidate for replacement. The method includes: while executing the tests according to the execution sequence and before executing the group of tests, modifying, in real time, the execution sequence including: executing a delay instead of the group of tests, wherein the delay is related to the group of tests.
A method for modifying the execution sequence of tests for testing an object on a test system. The tests include a group of tests that is a candidate for replacement. The method includes: while executing the tests according to the execution sequence and before executing the group of tests, modifying, in real time, the execution sequence including: executing a delay instead of the group of tests, wherein the delay is related to the group of tests.
G06F 9/44 - Arrangements for executing specific programs
G06F 11/36 - Prevention of errors by analysis, debugging or testing of software
G06F 19/00 - Digital computing or data processing equipment or methods, specially adapted for specific applications (specially adapted for specific functions G06F 17/00;data processing systems or methods specially adapted for administrative, commercial, financial, managerial, supervisory or forecasting purposes G06Q;healthcare informatics G16H)
23.
CORRELATION BETWEEN MANUFACTURING SEGMENT AND END- USER DEVICE PERFORMANCE
Disclosed are methods, systems and computer program products for concluding whether or not there is a correlation between a set of manufacturing condition(s) and performance of in-field end user devices. Also disclosed are methods, systems and computer program products for concluding whether or not there is an inconsistency in in-field end user devices data and/or manufacturing data associated with electronic elements included in end-user devices. In one example, a method includes analyzing received in-field data and/or data computed based on received in-field data, in order to determine whether or not there is a statistically significant difference in in-field performance between end-user devices including elements from a first population and end-user devices including elements from a second population, where manufacturing of the first population corresponds to a set of one or more manufacturing conditions, but manufacturing of the second population does not correspond to the set.
Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.
Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.
Systems and methods for deciding whether or not to indicate misalignment. In some examples, an analysis of parametric data relating to tests sensitive to misalignment is performed in order to determine which data is incongruous and to identify corresponding probes or socket contacts as suspected misaligned. In some examples, additionally or alternatively, a spatial analysis quantifies the placement of a set of identified suspected misaligned probes, which were identified from pass/fail test data and/or parametric test data, with respect to a contiguous or non-contiguous area on one or more wafers.
G01C 9/00 - Measuring inclination, e.g. by clinometers, by levels
G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
Methods, systems, computer-program products and program-storage devices for determining whether or not to perform an action based at least partly on an estimated maximum test-range. One method comprises: attaining results generated from a parametric test on semiconductor devices included in a control set; selecting from the semiconductor devices at least one extreme subset including at least one of a high-scoring subset and a low-scoring subset; plotting at least results of the at least one extreme subset; fitting a plurality of curves to a plurality of subsets of the results; extending the curves to the zero-probability axis for the low-scoring subset or the one-probability axis for the high-scoring subset to define a corresponding plurality of intersection points; defining an estimated maximum test range based on at least one of the intersection points; and determining whether or not to perform an action based at least partly on the estimated maximum test range.
Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.
Systems and methods for sorting an electronic device undergoing a final test operation in accordance with a test program, into one of a plurality of bins. In one embodiment, an evaluator defines the binning of the electronic device while the device is still socketed, and the defined binning may or may not concur with the binning assigned by the test program.
A parametric test time reduction method for reducing time expended to conduct a test program flow on a population of semiconductor devices, the test program flow comprising at least one parametric test having a specification defining a known pass value range characterized in that a result of the test is considered a passing result if the result falls within the known pass value range, the method including: computing an estimated maximum test range, at a given confidence level, on a validation set including a subset of the population of semiconductor devices, the estimated maximum test range including the range of values into which all results from performing the test on the set will statistically fall at the given confidence level and at least partly disabling the at least one parametric test based at least partly on a comparison of the estimated maximum test range and the known pass value range.
Methods and systems for semiconductor testing. In one embodiment, a semiconductor testing method includes one or more of the following stages: defining a rule relating to semiconductor testing, validating the rule, bundling the rule with other rules, correlating the rule with other rules, publishing the rule, actualizing the rule, and follow up relating to the rule. In one embodiment, a semiconductor testing system includes one or more of the following modules: rule creation module(s), analysis module(s), simulation module(s), real time production module(s), and offline production module(s). In one embodiment, user friendly graphical user interface(s) can be used for defining the building blocks of a rule and/or for viewing an optional hierarchy of categories to which the rule belongs.
Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.
Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted.
Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted.
Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted.
Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted.
Methods and systems for semiconductor testing. In one embodiment, a semiconductor testing method includes one or more of the following stages: defining a rule relating to semiconductor testing, validating the rule, bundling the rule with other rules, correlating the rule with other rules, publishing the rule, actualizing the rule, and follow up relating to the rule. In one embodiment, a semiconductor testing system includes one or more of the following modules: rule creation module(s), analysis module(s), simulation module(s), real time production module(s), and offline production module(s). In one embodiment, user friendly graphical user interface(s) can be used for defining the building blocks of a rule and/or for viewing an optional hierarchy of categories to which the rule belongs.
Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.
Parallel dies testing, mostly implemented on memory ICs—Integrated Circuits, significantly reduced overall test time. In order to minimize the need for physical probing, wafer probe card technology to allow simultaneous probing, ATE—Automated Test Equipment with enough channels and CPU power to handle the parallel testing. While new devices are designed with enough channels, and probe cards are designed and manufactured for each new device, the need to purchase new ATE to benefit from the technology is a heavy burden on parallel testing. It is proposed to interpose a multiplexer between the probe card and the ATE accompanied by a system that optimizes tester resources. The proposed system will allow test houses to benefit most from their investment without paying the full penalty of keeping less capable ATE.
G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
G01R 31/26 - Testing of individual semiconductor devices
G06F 19/00 - Digital computing or data processing equipment or methods, specially adapted for specific applications (specially adapted for specific functions G06F 17/00;data processing systems or methods specially adapted for administrative, commercial, financial, managerial, supervisory or forecasting purposes G06Q;healthcare informatics G16H)
40.
Augmenting semiconductor's devices quality and reliability
A method for augmenting quality or reliability of semiconductor units, including providing few populations of semiconductor units that are subject to quality or reliability testing. The populations include few quality or reliability fail candidate populations and other population(s). The method includes the step of associating test flows to the populations. Each test flow includes stress testing sequence. The stress testing sequence for the quality or reliability fail candidate population includes a stress test of increased duration compared to duration of a stress test in the test flow of the other population. The stress test sequence for the other population includes a stress test of increased voltage compared to corresponding operating voltage specification for a semiconductor unit. The method further includes the step of applying, within a sort testing stage, the corresponding test flow to the populations and identifying any unit which failed the stress sequence.
G06F 19/00 - Digital computing or data processing equipment or methods, specially adapted for specific applications (specially adapted for specific functions G06F 17/00;data processing systems or methods specially adapted for administrative, commercial, financial, managerial, supervisory or forecasting purposes G06Q;healthcare informatics G16H)
patents
