An example system-on-chip (SoC) device for a communication system includes a peripheral component interconnect express (PCIe) interface configured to receive data from a backhaul field programmable gate array (FPGA) of the communication system, and a producer port linked with a consumer port through direct memory access (DMA). Data received by the PCIe interface is assigned to the producer port. The device includes dual hardware media access controls (MACs) configured to consume the data assigned to the producer port, and at least one processor configured to supply the data to a wireless interface for transmission to another wireless communication device of the communication system at a frequency of at least sixty Gigahertz.
A communication system includes a first communication cable coupled with a first peer node of a data network, a first wireless host device including a first wireless interface and a second wireless interface, a first adapter coupled between the first wireless host device and an end point of the first communication cable, a second communication cable coupled with a second peer node of the data network, and a second wireless host device including a third wireless interface and a fourth wireless interface. The third wireless interface is configured to communicate with the first wireless interface via a first wireless communication channel, and the fourth wireless interface is configured to communicate with the second wireless interface via a second wireless communication channel. A second adapter is coupled between the second wireless host device and the second communication cable.
An example communication system includes a distributed unit of a fronthaul communication system architecture, wherein the distributed unit is in communication with a core network of the communication system, a radio unit of the fronthaul communication system architecture, wherein the radio unit is electrically coupled with at least one cellular antenna, and the radio unit is configured to transmit and receive wireless cellular signals, and a wireless communication link between the distributed unit and the radio unit. The wireless communication link includes a first system-on-chip (SoC) device electrically coupled with the radio unit, and a second SoC device electrically coupled with the distributed unit, wherein the first SoC device and the second SoC device are configured to wirelessly transmit communication signals between the radio unit and the distributed unit at a frequency of at least sixty Gigahertz.
H01Q 21/06 - Arrays of individually energised antenna units similarly polarised and spaced apart
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
H04W 74/0816 - Non-scheduled access, e.g. ALOHA using carrier sensing, e.g. carrier sense multiple access [CSMA] with collision avoidance
An example system-on-chip (SoC) device for a communication system includes a peripheral component interconnect express (PCIe) interface configured to receive data from a backhaul field programmable gate array (FPGA) of the communication system, and a producer port linked with a consumer port through direct memory access (DMA). Data received by the PCIe interface is assigned to the producer port. The device includes dual hardware media access controls (MACs) configured to consume the data assigned to the producer port, and at least one processor configured to supply the data to a wireless interface for transmission to another wireless communication device of the communication system at a frequency of at least sixty Gigahertz.
A communication system includes a first communication cable coupled with a first peer node of a data network, a first wireless host device including a first wireless interface and a second wireless interface, a first adapter coupled between the first wireless host device and an end point of the first communication cable, a second communication cable coupled with a second peer node of the data network, and a second wireless host device including a third wireless interface and a fourth wireless interface. The third wireless interface is configured to communicate with the first wireless interface via a first wireless communication channel, and the fourth wireless interface is configured to communicate with the second wireless interface via a second wireless communication channel. A second adapter is coupled between the second wireless host device and the second communication cable.
An example communication system includes a distributed unit of a fronthaul communication system architecture, wherein the distributed unit is in communication with a core network of the communication system, a radio unit of the fronthaul communication system architecture, wherein the radio unit is electrically coupled with at least one cellular antenna, and the radio unit is configured to transmit and receive wireless cellular signals, and a wireless communication link between the distributed unit and the radio unit. The wireless communication link includes a first system-on-chip (SoC) device electrically coupled with the radio unit, and a second SoC device electrically coupled with the distributed unit, wherein the first SoC device and the second SoC device are configured to wirelessly transmit communication signals between the radio unit and the distributed unit at a frequency of at least sixty Gigahertz.
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
H01Q 21/06 - Arrays of individually energised antenna units similarly polarised and spaced apart
An antenna array system and a method for making the antenna system. The system includes at least two antenna elements serving as transmitter elements, and at least two antenna elements serving as receiver elements. Each of the transmitter antenna and receiver antenna elements include a pair of curved arms, wherein a first arm in the pair of curved arms is configured to be connected from a signal trace of the antenna system. The second arm in the pair of curved arms is configured to be connected to a ground plane.
A circuit comprises a first amplifier coupled to a first and a second node; a differential capacitive load coupled to the first and the second node, the differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit; a current mirror coupled to a source of each transistor; and a capacitor coupled between the sources of the transistors. A plurality of amplifiers can be coupled to the differential capacitive load, wherein each amplifier comprises a clock-less pre-amplifier of a comparator. The amplifiers may be abutted to one another such that an active transistor of a first differential stage in a first amplifier behaves as a dummy transistor for an adjacent differential stage in a second amplifier.
H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise
H03M 1/18 - Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
Processors are arranged in a pipeline structure to operate on multiple layers of data, each layer comprising multiple groups of data. An input to a memory is coupled to an output of the last processor in the pipeline, and the memory's output is coupled to an input of the first processor in the pipeline. Multiplexing and de-multiplexing operations are performed in the pipeline. For each group in each layer, a stored result read from the memory is applied to the first processor in the pipeline structure. A calculated result of the stored result is output at the last processor and stored in the memory. Once processing for the last group of data in a first layer is completed, the corresponding processor is configured to process data in a next layer before the pipeline finishes processing the first layer. The stored result obtained from the next layer comprises a calculated result produced from a layer previous to the first layer.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
10.
High linearly WiGig baseband amplifier with channel select filter
A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.
Local oscillator (LO) leakage and Image are common and undesirable effects in typical transmitters. Typically, fairly complex hardware and algorithms are used to calibrate and reduce these impairments. A single transistor that draws essentially no dc current and occupies a very small area detects the LO leakage and Image signals. The single transistor operating as a square-law device is used to mix the signals at the input and output ports of a power amplifier. The mixed signal generated by the single transistor enables the simultaneous calibration of the LO leakage and Image Rejection.
H03D 7/12 - Transference of modulation from one carrier to another, e.g. frequency-changing by means of semiconductor devices having more than two electrodes
12.
High linearly WiGig baseband amplifier with channel select filter
A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.
A circuit comprises a first amplifier coupled to a first and a second node; a differential capacitive load coupled to the first and the second node, the differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit; a current mirror coupled to a source of each transistor; and a capacitor coupled between the sources of the transistors. A plurality of amplifiers can be coupled to the differential capacitive load, wherein each amplifier comprises a clock-less pre-amplifier of a comparator. The amplifiers may be abutted to one another such that an active transistor of a first differential stage in a first amplifier behaves as a dummy transistor for an adjacent differential stage in a second amplifier.
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
Local oscillator (LO) leakage and Image are common and undesirable effects in typical transmitters. Typically, fairly complex hardware and algorithms are used to calibrate and reduce these impairments. A single transistor that draws essentially no dc current and occupies a very small area detects the LO leakage and Image signals. The single transistor operating as a square-law device is used to mix the signals at the input and output ports of a power amplifier. The mixed signal generated by the single transistor enables the simultaneous calibration of the LO leakage and Image Rejection.
H03D 7/12 - Transference of modulation from one carrier to another, e.g. frequency-changing by means of semiconductor devices having more than two electrodes
15.
High linearly WiGig baseband amplifier with channel select filter
A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.
A receiver comprises a Low Noise Amplifier (LNA) configured to amplify an input signal and a resonant circuit coupled to the LNA. A first switch couples current from the resonant circuit to a first capacitor integrating a first voltage, wherein the first switch is enabled with a clock signal. A second switch couples current from the resonant circuit to a second capacitor integrating a second voltage, wherein the second switch is enabled with an inverse clock signal. A differential amplifier comprises a positive input for receiving the first voltage and a negative input for receiving the second voltage in order to produce a sum and a difference frequency spectrum between a signal spectrum carried within the current and a frequency of the clock signal.
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
A circuit comprises a first amplifier coupled to a first and a second node; a differential capacitive load coupled to the first and the second node, the differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit; a current mirror coupled to a source of each transistor; and a capacitor coupled between the sources of the transistors. A plurality of amplifiers can be coupled to the differential capacitive load, wherein each amplifier comprises a clock-less pre-amplifier of a comparator. The amplifiers may be abutted to one another such that an active transistor of a first differential stage in a first amplifier behaves as a dummy transistor for an adjacent differential stage in a second amplifier.
H03M 1/34 - Analogue value compared with reference values
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
Processors are arranged in a pipeline structure to operate on multiple layers of data, each layer comprising multiple groups of data. An input to a memory is coupled to an output of the last processor in the pipeline, and the memory's output is coupled to an input of the first processor in the pipeline. Multiplexing and de-multiplexing operations are performed in the pipeline. For each group in each layer, a stored result read from the memory is applied to the first processor in the pipeline structure. A calculated result of the stored result is output at the last processor and stored in the memory. Once processing for the last group of data in a first layer is completed, the corresponding processor is configured to process data in a next layer before the pipeline finishes processing the first layer. The stored result obtained from the next layer comprises a calculated result produced from a layer previous to the first layer.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
19.
Method and apparatus of an input resistance of a passive mixer to broaden the input matching bandwidth of a common source/gate LNA
A cascode amplifier circuit comprises a first spiral inductor coupled to a source of a first transistor; a second spiral inductor coupled to a drain of a second transistor; a third inductor connecting the first transistor to the second transistor; a first capacitor coupled in parallel to the third inductor forming a bandpass filter; and a second capacitor coupled in parallel to the second spiral inductor forming a resonant circuit, wherein the resonant circuit oscillates at a center frequency.
H03F 3/04 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
H03F 1/42 - Modifications of amplifiers to extend the bandwidth
H03F 3/387 - DC amplifiers with modulator at input and demodulator at outputModulators or demodulators specially adapted for use in such amplifiers with semiconductor devices only
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
H03D 7/12 - Transference of modulation from one carrier to another, e.g. frequency-changing by means of semiconductor devices having more than two electrodes
A negative-capacitance circuit comprises a first node coupled to a drain of a first transistor and a gate of a second transistor; a second node coupled to a drain of the second transistor and a gate of the first transistor; a capacitor coupled between a source of the first transistor and a source of the second transistor; a first current mirror coupled between a supply voltage and the source of the first transistor; and a second current mirror coupled between the supply voltage and the source of the second transistor. The circuit can be configured to drive the differential capacitive load between the first and second nodes in a shorter time period, thereby increasing the transfer bandwidth of the differential signal.
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise
H03M 1/18 - Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
21.
Method and apparatus to detect LO leakage and image rejection using a single transistor
LO leakage and Image are common and undesirable effects in typical transmitters. Typically, thirty complex hardware and algorithms are used to calibrate and reduce these two impairments. A single transistor that draws essentially no de current and occupies a very small area, is used to detect the LO leakage and Image Rejection signals. The single transistor operating as a square law device, is used to mix the signals at the input and output ports of the power amplifier (PA). The mixed signal generated by the single transistor enables the simultaneous calibration of the LO leakage and Image Rejection.
This invention eliminates the need for “capacitor coupling” or “transformer coupling,” and the associated undesirable parasitic capacitance and inductance associated with these coupling techniques when designing high frequency (˜60 GHz) circuits. At this frequency, the distance between two adjacent stages needs to be minimized. A resonant circuit in series with the power or ground leads is used to isolate a biasing signal from a high frequency signal. The introduction of this resonant circuit allows a first stage to be “directly coupled” to a next stage using a metallic trace. The “direct coupling” technique passes both the high frequency signal and the biasing voltage to the next stage. The “direct coupling” approach overcomes the large die area usage when compared to either the “AC coupling” or “transformer coupling” approach since neither capacitors nor transformers are required to transfer the high frequency signals between stages.
H03K 3/012 - Modifications of generator to improve response time or to decrease power consumption
H01Q 1/50 - Structural association of antennas with earthing switches, lead-in devices or lightning protectors
H03K 17/56 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices
G05F 3/16 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
H04B 5/00 - Near-field transmission systems, e.g. inductive or capacitive transmission systems
23.
Method and apparatus of an architecture to switch equalization based on signal delay spread
The 60 GHz channel between the transmitter and receiver can have AWGN characteristics allowing a Time Domain Equalizer (TDE) to be used at the receiver instead of a Frequency Domain Equalizer (FDE). The complexity of performing matrix inversion on a received signal is reduced when directional antennas are used in a 60 GHz system. Incorporating the TDE in place of the FDE saves almost an order of magnitude in power dissipation. For portable units, such a savings is beneficial since the battery life can be extended. The signal quality of wireless channel is based on the characteristics of the received signal to switch the equalization operation from a system performing FDE to TDE and vice versa. The receiver adapts to the received signal to reduce the power dissipation of the system.
A plurality of three bit units (called triplets) are permuted by a shuffler to shuffle the positions of the triplets into different patterns which are used to specific the read/write operation of a memory. For example, the least significant triplet in a conventional counter can be placed in the most significant position of a permuted three triplet pattern. The count of this permuted counter triplet generates addresses that jump 64 positions each clock cycle. These permutations can then be used to generate read and write control information to read from/write to memory banks conducive for efficient Radix-8 Butterfly operation. In addition, one or more triplets can also determine if a barrel shifter or right circular shift is required to shift data from one data lane to a second data lane. The triplets allow efficient FFT operation in a pipelined structure.
The architecture is able to switch to Non-blocking check-node-update (CNU) scheduling architecture which has better performance than blocking CNU scheduling architecture. The architecture uses an Offset Min-Sum with Beta=1 with a clock domain operating at 440 MHz. The constraint macro-matrix is a spare matrix where each “1’ corresponds to a sub-array of a cyclically shifted identity matrix which is a shifted version of an identity matrix. Four core processors are used in the layered architecture where the constraint matrix uses a sub-array of 42 (check nodes)×42 (variable nodes) in the macro-array of 168×672 bits. Pipeline processing is used where the delay for each layer only requires 4 clock cycles.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
26.
Method and apparatus for an active negative-capacitor circuit to cancel the input capacitance of comparators
The differential output of a Programmable Gain Amplifier (PGA) is loaded by the input differential gate capacitance of a plurality of Analog to Digital convertors (ADC) comparators and the differential metal layer traces to interconnect these comparators to the PGA. The differential capacitive load presented to the PGA is quite large and reduces the bandwidth of this interconnect between the PGA and ADC. To overcome the performance degradation due to the differential capacitive load, an active negative-capacitor circuit cancels the effect of the large input capacitance of the ADC comparators. This cancelation extends the gain characteristics of the interconnect between the PGA's output and the inputs of the first stage of the comparators. The active negative-capacitance is comprised of a cross pair NMOS with a capacitor connecting their sources where each NMOS is biased by a current source.
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise
H03M 1/18 - Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
A portable unit with an endfire antenna and operating at 60 GHz makes an optimum communication channel with an endfire antenna in an array of antennas distributed over the area of a ceiling. The portable unit is pointed towards the ceiling and the system controlling the ceiling units selects and adjusts the positioning of an endfire antenna mounted on a 3-D adjustable rotatable unit. Several transceivers can be mounted together, offset from one another, to provide a wide coverage in both azimuth direction and elevation direction. These units can be rigidly mounted as an array in a ceiling, apparatus. The system controlling the ceiling array selects one of the transceivers in one of the units to make the optimum communication channel to the portable unit. The system includes the integration of power management features by switching between Wi-Fi in favor of the 60 GHz channel.
H01Q 1/24 - SupportsMounting means by structural association with other equipment or articles with receiving set
H01Q 1/38 - Structural form of radiating elements, e.g. cone, spiral, umbrella formed by a conductive layer on an insulating support
H01Q 1/52 - Means for reducing coupling between antennas Means for reducing coupling between an antenna and another structure
H01Q 3/24 - Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the orientation by switching energy from one active radiating element to another, e.g. for beam switching
H01Q 9/16 - Resonant antennas with feed intermediate between the extremities of the antenna, e.g. centre-fed dipole
H01Q 21/28 - Combinations of substantially independent non-interacting antenna units or systems
H01Q 25/00 - Antennas or antenna systems providing at least two radiating patterns
H01Q 3/04 - Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system using mechanical movement of antenna or antenna system as a whole for varying one co-ordinate of the orientation
m transistor feedback allows a mixer to saturate at a reduced input signal swing voltage when compared to a conventional mixer allowing the mixer to enter into the current mode operation at a reduced signal input voltage range. The linearity of the baseband signal path can be traded against the mixer gain and is improved if the signal swing in the baseband signal path is reduced. The input mixer transistors operate in the saturated mode at a reduced input signal swing voltage causing the power efficiency of the system to increase since the transmit chain operates at a class-D power efficient. Efficiency is very important in mobile applications to save and extend the battery power of a mobile phone providing a better utilization of the available power since most of that power is supplied to the energy of the outgoing modulated signal.
In an up-converter path of a transmitter, wide-band signal system like direct conversion WiGig, a high pass filter (HPF) is placed in the baseband path after the low pass filter (LPF) but before the mixers. The baseband signal of WiGig can have a bandwidth of 800 MHz. The HPF removes the frequencies from 0-40 MHz from the baseband signal and degrades the overall signal of the baseband by a dB or so. However, the frequency pulling is significantly reduced since oscillator frequency and Radio frequency (RF) transmitter frequencies after conversion become further separated when compared a system using to the conventional approach. This causes the injected signal to fall outside the locking range of the oscillator. The concern of substrate coupling is reduced and allows for a reduction in the physical distance between the oscillator and the mixer and reduces a shift in the desired target frequency of operation.
Capacitive adjustment in an RCL resonant circuit is typically performed by adjusting a DC voltage being applied to one side of the capacitor. One side of the capacitor is usually connected to either the output node or the gate of a regenerative circuit in an RCL resonant circuit. The capacitance loading the resonant circuit becomes a function of the DC voltage and the AC sinusoidal signal generated by the resonant circuit. By capacitively coupling both nodes of the capacitor, a DC voltage can control the value of the capacitor over the full swing of the output waveform. In addition, instead of the RCL resonant circuit driving a single differential function loading the outputs, each output drives an independent single ended function; thereby providing two simultaneous operations being determined in place of the one differential function.
H03B 5/08 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
H03L 7/00 - Automatic control of frequency or phaseSynchronisation
H03L 1/02 - Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
H03B 1/00 - GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNERGENERATION OF NOISE BY SUCH CIRCUITS Details
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
31.
Method and apparatus of an input resistance of a passive mixer to broaden the input matching bandwidth of a common source-gate LNA
A cascode common source and common gate LNAs operating at 60 GHz are introduced and described. The cascode common source LNA is simulated to arrive at an optimum ratio of upper device width to the lower device width. The voltage output of the cascode common source LNA is translated into a current to feed and apply energy to the mixer stage. These input current signals apply the energy associated with the current directly into the switched capacitors in the mixer to minimize the overall power dissipation of the system. The LNA is capacitively coupled to the mixer switches in the I and Q mixers and are enabled and disabled by the clocks generated by the quadrature oscillator. These signals are then amplified by a differential amplifier to generate the sum and difference frequency spectra.
H03F 3/19 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
H03F 3/387 - DC amplifiers with modulator at input and demodulator at outputModulators or demodulators specially adapted for use in such amplifiers with semiconductor devices only
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
H03D 7/12 - Transference of modulation from one carrier to another, e.g. frequency-changing by means of semiconductor devices having more than two electrodes
A large gain is used to start up the oscillation of the crystal quickly. Once the oscillation starts, the amplitude is detected. A control circuit determines based on the measured amplitude to disable a low resistance path in the controlled switch array to reduce the applied gain below the power dissipation specification of the crystal. Another technique introduces a mixed-signal controlled power supply multi-path resistive array which tailors the maximum current to the crystal. A successive approximation register converts the amplitude into several partitions and enables/disables one of several power routing paths to the inverter of the oscillator. This allows a better match between the crystal selected by the customer and the on-chip drive circuitry to power up the oscillator without stressing the crystal. The “l/f” noise of the oscillator circuit is minimized by operating transistors in the triode region instead of the linear region.
H03L 5/00 - Automatic control of voltage, current, or power
H03B 5/36 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
33.
Method and apparatus for an active negative-capacitor circuit to cancel the input capacitance of comparators
The differential output of a Programmable Gain Amplifier (PGA) is loaded by the input differential gate capacitance of a plurality of Analog to Digital converters (ADC) comparators and the differential metal layer traces to interconnect these comparators to the PGA. The differential capacitive load presented to the PGA is quite large and reduces the bandwidth of this interconnect between the PGA and ADC. To overcome the performance degradation due to the differential capacitive load, an active negative-capacitor circuit cancels the effect of the large input capacitance of the ADC comparators. This cancellation extends the gain characteristics of the interconnect between the PGA's output and the inputs of the first stage of the comparators. The active negative-capacitance is comprised of a cross pair NMOS with a capacitor connecting their sources where each NMOS is biased by a current source.
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise
H03M 1/18 - Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
Herein is presented, a low power on-die 60 GHz distribution network for a beamforming system that can be scaled as the number of transmitters increases. The transmission line based power splitters and quadrature hybrids whose size would be proportional to a quarter wavelength (˜600 μm) if formed using transmission lines are instead constructed by inductors/capacitors and reduce the area by more than 80%. An input in-phase I clock and an input quadrature Q clock are combined into a single composite clock waveform locking the phase relation between the in-phase I clock and quadrature Q clock. The composite clock is transferred over a single transmission line formed using a Co-planar Waveguide (CPW) coupling the source and destination locations over the surface of a die. Once the individuals the in-phase I and quadrature Q clocks are required, they can be generated at the destination from the composite clock waveform.
H03B 27/00 - Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs
G01S 5/02 - Position-fixing by co-ordinating two or more direction or position-line determinationsPosition-fixing by co-ordinating two or more distance determinations using radio waves
35.
Method and apparatus for a class-E load tuned beamforming 60 GHz transmitter
The class-E amplifier can be tuned to pass only the fundamental frequency to the antenna by optimizing the second harmonics at the drain of the final PA driver transistor. A CPW in series with a capacitor between the PA transistor and the load forms a band pass filter that only allows the fundamental frequency to pass to the load of the antenna. A supply inductor to couple the drain of the final PA driver transistor to the power supply is tuned at the second harmonic with the parasitic capacitance of the drain of the PA transistor. A load capacitance is adjusted at the fundamental frequency to insure that the current waveform and voltage waveforms at the drain of the PA driver transistor do not overlap, thereby minimizing the parasitic power dissipation and allowing maximum energy to be applied to the antenna.
H03F 3/16 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
36.
Differential source follower having 6dB gain with applications to WiGig baseband filters
Sallen-Key filters require an operational amplifier with a large input impedance and a small output impedance to meet the external filter characteristics. This invention eliminates the need for internal feedback path for stability and increases the gain of a source follower which has characteristics matching the operational amplifier in the Sallen-Key filter. The source follower provides 6 dB of AC voltage gain and is substituted for the operational amplifier in the Sallen-Key filter. The Sallen-Key filter requires a differential configuration to generate all the required signals with their complements and uses these signals in a feed forward path. Furthermore, since the source follower uses only two n-channel stacked devices, the headroom voltage is maximized to several hundred millivolts for a 1.2V voltage supply in a 40 nm CMOS technology. Thus, the required 880 MHz bandwidth of the Sallen-Key filter can be easily met using the innovative source follower.
H03F 3/50 - Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower
H03H 3/00 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
A portable unit with an endfire antenna and operating at 60 GHz makes an optimum communication channel with an endfire antenna in an array of antennas distributed over the area of a ceiling. The portable unit is pointed towards the ceiling and the system controlling the ceiling units selects and adjusts the positioning of an endfire antenna mounted on a 3-D adjustable rotatable unit. Several transceivers can be mounted together, offset from one another, to provide a wide coverage in both azimuth direction and elevation direction. These units can be rigidly mounted as an array in a ceiling apparatus. The system controlling the ceiling array selects one of the transceivers in one of the units to make the optimum communication channel to the portable unit. The system includes the integration of power management features by switching between Wi-Fi in favor of the 60 GHz channel.
H01Q 1/24 - SupportsMounting means by structural association with other equipment or articles with receiving set
H01Q 1/38 - Structural form of radiating elements, e.g. cone, spiral, umbrella formed by a conductive layer on an insulating support
H01Q 1/52 - Means for reducing coupling between antennas Means for reducing coupling between an antenna and another structure
H01Q 3/24 - Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the orientation by switching energy from one active radiating element to another, e.g. for beam switching
H01Q 21/28 - Combinations of substantially independent non-interacting antenna units or systems
H01Q 25/00 - Antennas or antenna systems providing at least two radiating patterns
38.
Method and apparatus of cancelling inductor coupling
This invention compensates for the unintentional magnetic coupling between a first and second inductor of two different closely spaced inductors separated by a conversion circuit. A cancellation circuit formed from transistors senses the magnetic coupling in the first inductor and feeds a current opposite to the induced magnetic coupling captured by the second inductor such that the coupled magnetic coupling can be compensated and allows the first and second inductors to behave independently with regards to the coupled magnetic coupling between the first and second inductors. This allows the distance between the first and second inductors to be minimized which saves silicon area. In addition, the performance is improved since the overall capacitance in both circuits can be decreased. This cancellation technique to reduce the magnetic coupling between two closed placed inductively loaded circuits allows the design of a more compact and faster performing circuit.
H03B 5/08 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
39.
Method and apparatus for improving the performance of a DAC switch array
One of the critical design parameters occurs when a digital signal is converted into an analog signal. As the supply voltage drops to less than 2 times of threshold voltage to reduce leakage and save power, generating a relative large swing with a resistor-ladder DAC becomes more difficult. For a 5 bit DAC, 32 sub-arrays are used to select the appropriate voltage from the series coupled resistor network. Each sub-array uses p-channel transistors where the sub-array extracting the lowest voltage 700 mV only has a 100 mV of gate to source voltage. To compensate for the reduced gate to source voltage, the sub-arrays are partitioned into four groups. In each group, the p-channel width is increased from 2 um to 5 um, as the tap voltage drops from 1.2 V to 0.7 V. This allows the p-channel transistor with a small gate to source voltage to have a larger width thereby improving performance.
A differential amplifier comprising a first upper device and a first lower device series coupled between two power supplies and a second upper device and a second lower device series coupled between the two power supplies. A first DC voltage enables the first upper device and the second upper device and a second DC voltage regulates current flow in the first lower device and the second lower device. An AC signal component is coupled to the first upper device and the second lower device while the AC signal complement is coupled to the first lower device and the second upper device. Separate RC networks couple the AC signals to their respective device. A first and second output signal forms between the upper device and the lower device, respectively. All the devices are same channel type.
Transceiver calibration is a critical issue for proper transceiver operation. The transceiver comprises at least one RF transmit chain and one RF receive chain. A closed loop path is formed from the digital block, the RF transmit chain, the substrate coupling, the RF receive chain back to the digital block and is used to estimate and calibrate the transceiver parameters over the operating range of frequencies. The substrate coupling eliminates the need for the additional circuitry saving area, power, and performance. In place of the additional circuitry, the digital block which performs baseband operations can be reconfigured into a software or/and hardware mode to calibrate the transceiver. The digital block comprises a processor and memory and is coupled to the front end of the RF transmit chain and the tail end of the RF receive chain.
H04B 1/38 - Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
42.
Method and apparatus of a resonant oscillator separately driving two independent functions
Capacitive adjustment in an RCL resonant circuit is typically performed by adjusting a DC voltage being applied to one side of the capacitor. One side of the capacitor is usually connected to either the output node or the gate of a regenerative circuit in an RCL resonant circuit. The capacitance loading the resonant circuit becomes a function of the DC voltage and the AC sinusoidal signal generated by the resonant circuit. By capacitively coupling both nodes of the capacitor, a DC voltage can control the value of the capacitor over the full swing of the output waveform. In addition, instead of the RCL resonant circuit driving a single differential function loading the outputs, each output drives an independent single ended function; thereby providing two simultaneous operations being determined in place of the one differential function.
H03B 1/00 - GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNERGENERATION OF NOISE BY SUCH CIRCUITS Details
43.
Method and apparatus of an input resistance of a passive mixer to broaden the input matching bandwidth of a common source/gate LNA
A cascode common source and common gate LNAs operating at 60 GHz are introduced and described. The cascode common source LNA is simulated to arrive at an optimum ratio of upper device width to the lower device width. The voltage output of the cascode common source LNA is translated into a current to feed and apply energy to the mixer stage. These input current signals apply the energy associated with the current directly into the switched capacitors in the mixer to minimize the overall power dissipation of the system. The LNA is capacitively coupled to the mixer switches in the I and Q mixers and are enabled and disabled by the clocks generated by the quadrature oscillator. These signals are then amplified by a differential amplifier to generate the sum and difference frequency spectra.
An analog-to-digital converter comprises a first set of comparators configured for generating a coarse digital measurement of an analog input signal, and a second set of comparators for performing a fine digital measurement of the analog input signal. The second set comprises a plurality of dynamic comparators, wherein each dynamic comparator is configurable for being activated by a clock signal. An activation circuit processes the coarse measurement and an input clock signal for generating a set of activation signals, which activate a subset of the dynamic comparators to generate the fine digital measurement.
H03M 1/16 - Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
45.
High performance divider using feed forward, clock amplification and series peaking inductors
A phase lock loop (PLL) is an important component in wireless systems. CMOS technology offers voltage controlled oscillator designs operating at 60 GHz. One of the difficulties is dividing the high frequency clock down to a manageable clock frequency using conventional CMOS. Although injection locked dividers can divide down this clock frequency, these dividers have limitations. A divide by 2 is presented that uses several techniques; feed forward, clock amplification and series peaked inductors to overcome these limitations.
A differential amplifier comprising a first upper device and a first lower device series coupled between two power supplies and a second upper device and a second lower device series coupled between the two power supplies. A first DC voltage enables the first upper device and the second upper device and a second DC voltage regulates current flow in the first lower device and the second lower device. An AC signal component is coupled to the first upper device and the second lower device while the AC signal complement is coupled to the first lower device and the second upper device. A first output signal between the first upper device and the first lower device. Separate RC networks couple the AC signals to their respective device. A first and second output signal forms between the upper device and the lower device, respectively. All the devices are same channel type.
Very high frequency circuits suffer from parasitic resistances. At 60 GHz, conventional layout techniques can introduce loss into the circuit at critical locations. One critical interconnect between the output of a pre-driver and the gate of the final output stage causes 1 or 2 dB of loss due to the layout. By minimizing the number of via contacts, this conventional loss can be recovered using this new layout technique. In addition, a tap point of a via stack is used to modify the resonant characteristics of the interconnect. Finally, cross coupled devices in a resonant circuit are used to reduce the common mode noise at the expense of the common mode gain.
This invention eliminates the need for “capacitor coupling” or “transformer coupling,” and the associated undesirable parasitic capacitance and inductance associated with these coupling techniques when designing high frequency (˜60 GHz) circuits. At this frequency, the distance between two adjacent stages needs to be minimized. A resonant circuit in series with the power or ground leads is used to isolate a biasing signal from a high frequency signal. The introduction of this resonant circuit allows a first stage to be “directly coupled” to a next stage using a metallic trace. The “direct coupling” technique passes both the high frequency signal and the biasing voltage to the next stage. The “direct coupling” approach overcomes the large die area usage when compared to either the “AC coupling” or “transformer coupling” approach since neither capacitors nor transformers are required to transfer the high frequency signals between stages.
H03G 3/10 - Manually-operated control in untuned amplifiers having semiconductor devices
H04B 5/00 - Near-field transmission systems, e.g. inductive or capacitive transmission systems
G05F 3/16 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
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