Abstract

A method for manufacturing a semiconductor structure is provided. A substrate is recessed from an upper surface toward a lower surface to form a trench. A semiconductor material is filled in the trench. A patterned metal layer is formed on the semiconductor material and a patterned hard mask is formed on the patterned metal layer. A portion of the semiconductor material is etched by using the patterned metal layer as a mask, in which a remaining portion of the semiconductor material includes a first portion and a second portion below the first portion, and the second portion is wider than the first portion. A passivation layer is formed on a sidewall of the first portion. The passivation layer is removed and the second portion of the remaining portion of the semiconductor material is etched by using the patterned metal layer as a mask, thereby forming a semiconductor layer.

IPC Classes  ?

• H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 21/311 - Etching the insulating layers
• H01L 21/321 - After-treatment

Abstract

A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a base structure, a patterned circuit structure, a capacitor structure and a vertical transistor. The patterned circuit structure is disposed over the base structure. The capacitor structure is disposed over the patterned circuit structure. The vertical transistor is disposed over the capacitor structure.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a base structure, a patterned circuit structure, a capacitor structure and a vertical transistor. The patterned circuit structure is disposed over the base structure. The capacitor structure is disposed over the patterned circuit structure. The vertical transistor is disposed over the capacitor structure.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a base structure, a patterned circuit structure, a capacitor structure and a vertical transistor. The patterned circuit structure is disposed over the base structure. The capacitor structure is disposed over the patterned circuit structure. The vertical transistor is disposed over the capacitor structure.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A wafer handling apparatus includes a housing, a load port, a robotic arm, a sensor group and a processing unit. The load port is mounted on a side of the housing and configured to receive a wafer container which accommodates at least one wafer. The robotic arm is disposed inside the housing and configured to transfer the wafer into or out of the wafer container. The robotic arm includes a handling portion and a moving portion. The handling portion is configured to hold the wafer. The moving portion is connected with the handling portion and configured to move the handling portion relative to the load port. The sensor group is disposed on the load port. The sensor group includes at least one first sensor configured to obtain a first height level of the handling portion. The processing unit is signally connected with the sensor group.

IPC Classes  ?

• B25J 9/16 - Programme controls
• B25J 11/00 - Manipulators not otherwise provided for
• B25J 13/08 - Controls for manipulators by means of sensing devices, e.g. viewing or touching devices
• H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
• H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
• H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

Abstract

A method of fabricating a semiconductor device that includes forming a dummy channel structure, forming a gate electrode surrounding the dummy channel structure, forming a word line surrounding the gate electrode, removing the dummy channel structure to form an opening, forming a gate dielectric in the opening, and forming a channel structure in the opening.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A duty cycle correction device and a duty cycle correction method thereof are disclosed. A duty cycle adjustment circuit adjusts a duty cycle of an input clock signal to output an output clock signal. An integrator circuit generates an integral signal according to the output clock signal. A correction control circuit periodically controls the duty cycle adjustment circuit to adjust an adjustment amount of the duty cycle according to a change of a logic level of the integral signal.

IPC Classes  ?

• H03K 5/156 - Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
• H03K 5/13 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals

Abstract

A capacitor structure and a manufacturing method thereof are provided. The capacitor structure includes a bottom electrode, an insulation layer, a top electrode and an interfacial layer. The insulation layer is disposed on the bottom electrode. The top electrode is disposed over the insulation layer. The interfacial layer is disposed between the insulation layer and the top electrode. A composition of the interfacial layer has at least one element in common with elements containing in the insulation layer and at least one element in common with elements containing in the top electrode.

IPC Classes  ?

• H01G 4/33 - Thin- or thick-film capacitors
• H01G 2/06 - Mountings specially adapted for mounting on a printed-circuit support
• H01G 4/008 - Selection of materials
• H01G 4/12 - Ceramic dielectrics

Abstract

A manufacturing method of a semiconductor device includes forming a plurality of photoresist strips on a substrate, in which an opening is formed in each of the photoresist strips; forming a plurality of contacts in the openings of the photoresist strips, in which an outer contour of each of the contacts is a string shape; and using the photoresist strips to form a plurality of bit lines.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 23/528 - Layout of the interconnection structure
• H01L 29/40 - Electrodes

Abstract

A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a base structure, a bit line structure and a cell contact structure. The bit line structure is disposed over the base structure. The cell contact structure is disposed around the bit line structure, and has a first surface and a second surface facing the bit line structure. A first distance between the first surface of the cell contact structure and the bit line structure is different from a second distance between the second surface of the cell contact structure and the bit line structure.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a base structure, a bit line structure and a cell contact structure. The bit line structure is disposed over the base structure. The cell contact structure is disposed around the bit line structure, and has a first surface and a second surface facing the bit line structure. A first distance between the first surface of the cell contact structure and the bit line structure is different from a second distance between the second surface of the cell contact structure and the bit line structure.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a base structure, a bit line structure and a cell contact structure. The bit line structure is disposed over the base structure. The cell contact structure is disposed around the bit line structure, and has a first surface and a second surface facing the bit line structure. A first distance between the first surface of the cell contact structure and the bit line structure is different from a second distance between the second surface of the cell contact structure and the bit line structure.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A semiconductor device includes two active areas, an isolation structure between the active areas, two word lines, and protection pillars covering the word lines and in direct contact with the isolation structure. Each of the word lines is between one of the active areas and the isolation structure, and the protection pillars are rhombus-shaped.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a pad structure positioned above the substrate and including a bottom portion and two side portions, wherein the bottom portion is positioned parallel to a top surface of the substrate, and the two side portions are positioned on two sides of the bottom portion and extending along a direction parallel to a normal of the top surface of the substrate; and an insulator film surrounding the pad structure. A top surface of the insulator film is at a vertical level greater than a vertical level of a top surface of the pad structure.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The present application provides a semiconductor structure including a first die, a second die and a first via. The first die includes a first substrate, a first interconnect structure having a first conductive pad, and a first bonding layer over the first conductive pad. The second die includes a second bonding layer bonded to the first bonding layer, a second substrate over the second bonding layer, and a second interconnect structure. The first via extends through the second die and the first bonding layer and coupled to the first conductive pad. The first via includes a first portion having a first width and a second portion coupled to the first portion and having a second width different from the first width, wherein the first portion is surrounded by the first bonding layer and adjacent to the second interconnect structure, and the second portion is surrounded by the second substrate.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

The present application provides a semiconductor structure including a first die, a second die and a first via. The first die includes a first substrate, a first interconnect structure having a first conductive pad, and a first bonding layer over the first conductive pad. The second die includes a second bonding layer bonded to the first bonding layer, a second substrate over the second bonding layer, and a second interconnect structure. The first via extends through the second die and the first bonding layer and coupled to the first conductive pad. The first via includes a first portion having a first width and a second portion coupled to the first portion and having a second width different from the first width, wherein the first portion is surrounded by the first bonding layer and adjacent to the second interconnect structure, and the second portion is surrounded by the second substrate.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a supporting substrate; and a channel layer positioned parallel to a top surface of the supporting substrate, extending along a first direction, and including, in a sequence along the first direction, a drain, a channel, and a source. A top surface of the channel deviates less than three times its root mean square roughness.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a supporting substrate; and a channel layer positioned parallel to a top surface of the supporting substrate, extending along a first direction, and including, in a sequence along the first direction, a drain, a channel, and a source. A top surface of the channel deviates less than three times its root mean square roughness.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a channel layer including a channel extending along a first direction and including a first region and a second region in sequence along the first direction, a source extending from the second region along the first direction, and a drain extending from the first region in inverse of the first direction; and a word line structure including an inner word line dielectric layer surrounding the first region of the channel, an outer word line dielectric layer surrounding the second region of the channel and the inner word line dielectric layer, and a word line conductive layer surrounding the outer word line dielectric layer.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a channel layer including a channel extending along a first direction and including a first region and a second region in sequence along the first direction, a source extending from the second region along the first direction, and a drain extending from the first region in inverse of the first direction; and a word line structure including an inner word line dielectric layer surrounding the first region of the channel, an outer word line dielectric layer surrounding the second region of the channel and the inner word line dielectric layer, and a word line conductive layer surrounding the outer word line dielectric layer.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The present application discloses an expandable negative photoresist and a method for adjusting a profile of a spacer oxide using the expandable negative photoresist. The expandable negative photoresist includes a polymer material, a suspension material and a photoacid generator. The suspension material contains a plurality of expandable molecules. An expansion coefficient of the suspension material is greater than that of the polymer material

IPC Classes  ?

• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
• G03F 7/38 - Treatment before imagewise removal, e.g. prebaking

Abstract

The present application discloses an etching system. The etching system includes a process chamber, an image and temperature control device, and an artificial intelligence control module. The process chamber is configured to execute an etching process based on a first etching recipe on a first wafer. The image and temperature control device is configured to generate a thermal image of the first wafer during the etching process. The artificial intelligence control module is configured to determine whether the thermal image is compliant with a predetermined requirement. When the thermal image is not compliant with the predetermine requirement, the artificial intelligence control module is configured to update the first etching recipe according to the plurality of parameters so as to generate a second etching recipe.

IPC Classes  ?

• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
• G05B 13/02 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric
• H01J 37/32 - Gas-filled discharge tubes
• H01L 21/3065 - Plasma etchingReactive-ion etching
• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

Abstract

The present application discloses an etching system. The etching system includes a process chamber, an image and temperature control device, and an artificial intelligence control module. The process chamber is configured to execute an etching process based on a first etching recipe on a first wafer. The image and temperature control device is configured to generate a thermal image of the first wafer during the etching process. The artificial intelligence control module is configured to determine whether the thermal image is compliant with a predetermined requirement. When the thermal image is not compliant with the predetermine requirement, the artificial intelligence control module is configured to update the first etching recipe according to the plurality of parameters so as to generate a second etching recipe.

IPC Classes  ?

• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
• G05B 13/02 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric
• H01J 37/32 - Gas-filled discharge tubes
• H01L 21/3065 - Plasma etchingReactive-ion etching
• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

Abstract

The present application discloses an expandable negative photoresist and a method for adjusting a profile of a spacer oxide using the expandable negative photoresist. The expandable negative photoresist includes a polymer material, a suspension material and a photoacid generator. The suspension material contains a plurality of expandable molecules. An expansion coefficient of the suspension material is greater than that of the polymer material.

IPC Classes  ?

• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
• G03F 7/38 - Treatment before imagewise removal, e.g. prebaking

Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a channel layer positioned over the substrate, extending along a first direction perpendicular to a top surface of the substrate, and including an inverted trapezoid cross-sectional profile; and a word line including a word-line dielectric layer conformally and laterally surrounding the channel layer, and a word-line conductive layer laterally and partially surrounding the word-line dielectric layer, extending along a second direction parallel to the top surface of the substrate, and including an inverted trapezoid cross-sectional profile.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

An operation method of the overhead hoist transport device includes acquiring a first image of a first car by an image acquisition device on a second car; calculating a regression distance between the first car and the second car by using the first image as an input of a CNN model; adjusting a real distance between the first car and the second car based on the regression distance; and performing a CNN regression to adjusting a focus of the image acquisition device on the second car based on the regression distance.

IPC Classes  ?

• B66C 15/04 - Safety gear for preventing collisions, e.g. between cranes or trolleys operating on the same track
• B66C 19/00 - Cranes comprising trolleys or crabs running on fixed or movable bridges or gantries

Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a channel layer positioned over the substrate, extending along a first direction perpendicular to a top surface of the substrate, and including an inverted trapezoid cross-sectional profile; and a word line including a word-line dielectric layer conformally and laterally surrounding the channel layer, and a word-line conductive layer laterally and partially surrounding the word-line dielectric layer, extending along a second direction parallel to the top surface of the substrate, and including an inverted trapezoid cross-sectional profile.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a channel layer positioned over the substrate, extending along a first direction perpendicular to a top surface of the substrate, and including an inverted trapezoid cross-sectional profile; and a word line including a word-line dielectric layer conformally and laterally surrounding the channel layer, and a word-line conductive layer laterally and partially surrounding the word-line dielectric layer, extending along a second direction parallel to the top surface of the substrate, and including an inverted trapezoid cross-sectional profile.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

An electronic device, an assembly structure and a manufacturing method are provided. The electronic device includes a base portion, a circuit structure, an insulation structure, a first conductive layer, a via structure, a first outer layer and a second outer layer. The circuit structure is disposed on a first surface of the base portion. The insulation structure is disposed on the circuit structure. The first conductive layer is disposed on the insulation structure. The via structure extends through the insulation structure, and electrically connects the first conductive layer and the circuit structure. The first outer layer is disposed on the first conductive layer. The second outer layer is disposed on the first outer layer. The second outer layer includes an oxide material so as to improve a coplanarity of an outermost surface of the second outer layer.

IPC Classes  ?

• H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits

Abstract

A manufacturing method of a semiconductor structure is provided. The method includes the following steps. A target layer and a hardmask layer are sequentially formed on a substrate. A part of the hardmask layer is removed to form a recess. A plurality of first patterns are formed on a top surface of the hardmask layer and a plurality of second patterns are formed in the recess simultaneously. A pattern density of the plurality of first patterns is smaller than that of the plurality of second patterns. The hardmask layer and the target layer are patterned using the first patterns and the second patterns as a mask to form a plurality of first target patterns corresponding to the plurality of first patterns and a plurality of second target patterns corresponding to the plurality of second patterns in the target layer. The first and second patterns and the hardmask layer are removed.

IPC Classes  ?

• H01L 21/311 - Etching the insulating layers
• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
• H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

Abstract

An electronic device, an assembly structure and a manufacturing method are provided. The electronic device includes a base portion, a circuit structure, an insulation structure, a first conductive layer, a via structure, a first outer layer and a second outer layer. The circuit structure is disposed on a first surface of the base portion. The insulation structure is disposed on the circuit structure. The first conductive layer is disposed on the insulation structure. The via structure extends through the insulation structure, and electrically connects the first conductive layer and the circuit structure. The first outer layer is disposed on the first conductive layer. The second outer layer is disposed on the first outer layer. The second outer layer includes an oxide material so as to improve a coplanarity of an outermost surface of the second outer layer.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A signal receiver includes a data receiver and a data strobe signal receiver. The data receiver includes a plurality of current mode logic circuits and a plurality of data latches. A first stage current mode logic circuit receives a data signal, and a final stage current mode logic circuit outputs an amplified data signal. The plurality of data latches receive the amplified data signal, wherein each of the data latches sums the amplified data signal and a plurality of feedback data to obtain a summing data, and latches the summing data to output an output data according to one of a plurality of amplified data strobe signals. The data strobe signal receiver receives a data strobe signal, and generates the plurality of amplified data strobe signals by dividing a frequency of the data strobe signal.

IPC Classes  ?

• G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
• G11C 11/4076 - Timing circuits
• H03K 3/037 - Bistable circuits
• H03K 17/56 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
• H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks

Abstract

A method of fabricating a semiconductor structure includes depositing a first dielectric layer on a substrate; depositing a second dielectric layer on the first dielectric layer; forming a capacitor in the first dielectric layer and the second dielectric layer; depositing a first insulating layer on the second dielectric layer and the capacitor; forming a word line structure on the first insulating layer; depositing a second insulating layer on the word line structure; forming a channel hole in the second insulating layer, the word line structure, and the first insulating layer, wherein the channel hole includes a first section with a trumpet shape opening and a second section below the first section; forming a vertical channel in the second section of the channel hole; and forming a landing pad in the first section of the channel hole. A semiconductor structure is also disclosed.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A detection method of an overhead hoist transport device includes obtaining a position information of a car at a rail and a vibration information corresponding to the position information. A vibration peak data is generated based on the position information and the vibration information. An analyzing operation is performed on the vibration peak data to generate an analyzed result. Whether the analyzed result indicates a critical gap position at the rail is determined.

IPC Classes  ?

• B61K 9/08 - Measuring installations for surveying permanent way

Abstract

A method of manufacturing a semiconductor structure includes the following steps. A substrate is received with a top electrode of an embedded capacitor exposed from the substrate. An oxide layer is formed on the substrate. A patterned sacrificial layer is formed on the oxide layer and a portion of the oxide layer is exposed. A metal layer is formed to cover the portion of the oxide layer. A patterned dielectric layer is formed on the metal layer. A spacer is formed on a sidewall of the patterned dielectric layer. The metal layer is patterned by using the spacer and the patterned dielectric layer as a mask to form a gap. The gap is filled with a filler. The patterned sacrificial layer is removed to expose the top electrode of the embedded capacitor. A gate structure is formed on the top electrode of the embedded capacitor.

IPC Classes  ?

• H01L 29/40 - Electrodes

Abstract

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, an electronic component, and an encapsulant. The substrate has a lower surface and an upper surface opposite to the lower surface. The electronic component is disposed on the upper surface of the substrate. The encapsulant is disposed on the upper surface of the substrate. The encapsulant includes a first portion penetrating the substrate at a central region of the substrate and a second portion penetrating the substrate at a peripheral region of the substrate.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H05K 1/02 - Printed circuits Details
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, an isolation spacer, a conductive layer, a landing pad, and an air gap protection structure. The substrate includes a plurality of liners disposed on side surfaces of a trench in the substrate. The bit line is disposed on the substrate. The isolation spacer is disposed on a sidewall of the bit line. The isolation spacer includes an air gap. The conductive layer is disposed over the substrate and next to the isolation spacer. The landing pad is disposed over the bit line. The air gap protection structure covers the landing pad and the air gap. The air gap protection structure includes an upper portion above a top surface of the landing pad and a lower portion below the upper portion.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 21/764 - Air gaps
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

Abstract

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, an electronic component, and an encapsulant. The substrate has a lower surface and an upper surface opposite to the lower surface. The electronic component is disposed on the upper surface of the substrate. The encapsulant is disposed on the upper surface of the substrate. The encapsulant includes a first portion penetrating the substrate at a central region of the substrate and a second portion penetrating the substrate at a peripheral region of the substrate.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H05K 1/02 - Printed circuits Details
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

A label dispensing device includes a housing having a label outlet, a collection reel, a feeding reel, a driving mechanism and a peeling mechanism. The collection reel and the feeding reel are rotatably disposed in the housing. The driving mechanism drives one of the feeding reel and the collection reel for conveying a label strip from the feeding reel to the collection reel. The peeling mechanism is disposed in the housing and used to change a conveying direction of the label strip being pulled from the feeding reel towards the label outlet into a recycled direction intersected with the conveying direction from the peeling mechanism downwardly for peeling off one of label stickers from the label strip when the label sticker is passing the peeling mechanism.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, an isolation spacer, a conductive layer, a landing pad, and an air gap protection structure. The substrate includes a plurality of liners disposed on side surfaces of a trench in the substrate. The bit line is disposed on the substrate. The isolation spacer is disposed on a sidewall of the bit line. The isolation spacer includes an air gap. The conductive layer is disposed over the substrate and next to the isolation spacer. The landing pad is disposed over the bit line. The air gap protection structure covers the landing pad and the air gap. The air gap protection structure includes an upper portion above a top surface of the landing pad and a lower portion below the upper portion.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 21/764 - Air gaps
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

Abstract

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, an isolation spacer, a conductive layer, a landing pad, and an air gap protection structure. The substrate includes a plurality of liners disposed on side surfaces of a trench in the substrate. The bit line is disposed on the substrate. The isolation spacer is disposed on a sidewall of the bit line. The isolation spacer includes an air gap. The conductive layer is disposed over the substrate and next to the isolation spacer. The landing pad is disposed over the bit line. The air gap protection structure covers the landing pad and the air gap. The air gap protection structure includes an upper portion above a top surface of the landing pad and a lower portion below the upper portion.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 21/764 - Air gaps
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

Abstract

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, an isolation spacer, a conductive layer, a landing pad, and an air gap protection structure. The substrate includes a plurality of liners disposed on side surfaces of a trench in the substrate. The bit line is disposed on the substrate. The isolation spacer is disposed on a sidewall of the bit line. The isolation spacer includes an air gap. The conductive layer is disposed over the substrate and next to the isolation spacer. The landing pad is disposed over the bit line. The air gap protection structure covers the landing pad and the air gap. The air gap protection structure includes an upper portion above a top surface of the landing pad and a lower portion below the upper portion.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 21/764 - Air gaps
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

Abstract

A manufacturing method of a semiconductor structure is provided. The method includes following steps. A substrate is provided, and the substrate has a first array region, a second array region, and a periphery region. A first lower conductive layer is formed on the substrate, the first lower conductive layer continuously has a first portion in the first array region, a second portion in the second array region, and a third portion in the periphery region. The first portion of the first lower conductive layer and the second portion of the first lower conductive layer are removed. A second lower conductive layer is formed on the substrate. The second lower conductive and the first lower conductive layer comprise the same material such that the second lower conductive and the first lower conductive layer form a lower conductive layer collectively.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices
• H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

The present application discloses a semiconductor device with a protruding contact and a method of fabricating the semiconductor device. The semiconductor device includes a substrate, a bit line structure on the substrate, a capacitor contact structure next to the bit line structure, and a landing pad layer covering a portion of a top surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A method for manufacturing a semiconductor structure includes the following steps. A substrate is received, in which the substrate has a functional area and a dummy area surrounding the functional area. A functional pattern is formed on the functional area and a dummy pattern is formed on the dummy area in a same process step. A closet distance between the dummy pattern and the functional pattern is from 15 nm to about 50 nm. The dummy pattern is removed.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a first substrate comprising a front side and a back side parallel to the front side; a bonding dielectric positioned on the front side of the first substrate; a redistribution layer positioned between the bonding dielectric and the front side of the first substrate; a first dielectric layer positioned between the front side of the first substrate and the redistribution layer; a capping layer positioned between the redistribution layer and the bonding layer; a first conductive pad positioned between the capping layer and the bonding layer; a second dielectric layer positioned between the capping layer and the bonding layer, wherein a surface of the second dielectric layer is coplanar with a surface of the first conductive pad; and a conductive feature positioned in the bonding dielectric and the first conductive pad.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

The present disclosure provides a method of forming a semiconductor structure. The method includes the following operations. A first hard mask stack is formed on a dielectric layer, in which the dielectric layer includes an array region. The first hard mask stack is etched to form a second hard mask stack and a first trench extending along a first direction above the array region and in the second hard mask stack. A second trench is formed in the second hard mask stack extending along a second direction different from the first direction, in which the first trench and the second trench cross each other to form an intersection. The second hard mask stack and the dielectric layer directly below the intersection are etched to form a through-hole. A first landing pad is formed in the through-hole.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 21/311 - Etching the insulating layers

Abstract

The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a first substrate comprising a front side and a back side parallel to the front side; a bonding dielectric positioned on the front side of the first substrate; a redistribution layer positioned between the bonding dielectric and the front side of the first substrate; a first dielectric layer positioned between the front side of the first substrate and the redistribution layer; a capping layer positioned between the redistribution layer and the bonding layer; a first conductive pad positioned between the capping layer and the bonding layer; a second dielectric layer positioned between the capping layer and the bonding layer, wherein a surface of the second dielectric layer is coplanar with a surface of the first conductive pad; and a conductive feature positioned in the bonding dielectric and the first conductive pad.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

The present application discloses a semiconductor device with a protruding contact and a method of fabricating the semiconductor device. The semiconductor device includes a substrate, a bit line structure on the substrate, a capacitor contact structure next to the bit line structure, and a landing pad layer covering a portion of a top surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The present application discloses a semiconductor device with a protruding contact and a method of fabricating the semiconductor device. The semiconductor device includes a substrate, a bit line structure on the substrate, a capacitor contact structure next to the bit line structure, and a landing pad layer covering a portion of a top surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The present application discloses a semiconductor device with a protruding contact and a method of fabricating the semiconductor device. The semiconductor device includes a substrate, a bit line structure on the substrate, a capacitor contact structure next to the bit line structure, and a landing pad layer covering a portion of a top surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A temperature detection apparatus and method are provided. The apparatus captures an image and a thermal image of an object. The apparatus determines a first contour of the object in the image based on the image. The apparatus overlaps the first contour in the image onto the thermal image to generate a second contour in the thermal image. The apparatus generates a temperature record of the object based on a plurality of temperature values among the second contour in the thermal image.

IPC Classes  ?

• G06T 7/564 - Depth or shape recovery from multiple images from contours
• G06T 1/00 - General purpose image data processing
• G06T 7/62 - Analysis of geometric attributes of area, perimeter, diameter or volume

Abstract

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, an electronic component, an encapsulant, and a dam structure. The substrate has a lower surface and an upper surface opposite to the first surface. The electronic component is disposed on the upper surface of the substrate. The encapsulant is disposed on the upper surface of the substrate and has a portion penetrating the substrate. The dam structure vertically overlaps the portion of the encapsulant.

IPC Classes  ?

• H01L 23/16 - Fillings or auxiliary members in containers, e.g. centering rings
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates

Abstract

A manufacturing method of a memory device, including forming a hard mask layer over a substrate, in which the hard mask layer is made of an oxide-based material, and the hard mask layer has a first width, forming a trench in the substrate through the hard mask layer, performing a first cleaning process to the substrate, in which the first width of the hard mask layer is reduced to a second width after the first cleaning process is complete, forming a first dielectric layer lining the trench, forming a first word line layer in the trench, forming a second word line layer in the trench and over the first word line layer, forming a cap layer in the trench and over the second word line layer, removing the hard mask layer, and forming a gate contact layer over the cap layer.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A dynamic random-access memory (DRAM) device is provided. The DRAM device includes a slave DRAM chip and a master DRAM chip. The slave DRAM chip includes a slave control circuit and a slave power circuit. The slave control circuit generates a slave control signal according to a slave category signal and a setting signal. The slave power circuit stops generating at least one of slave voltages in response to a first value of the slave control signal and generates the slave voltages in response to a second value of the slave control signal. The master DRAM chip includes a master control circuit. The master control circuit generates a master control signal according to a master category signal and the setting signal, and controls the master DRAM chip to generate master voltages according to the master control signal. The slave category signal is different from the master category signal.

IPC Classes  ?

• G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• G11C 11/4099 - Dummy cell treatmentReference voltage generators

Abstract

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, an electronic component, an encapsulant, and a dam structure. The substrate has a lower surface and an upper surface opposite to the first surface. The electronic component is disposed on the upper surface of the substrate. The encapsulant is disposed on the upper surface of the substrate and has a portion penetrating the substrate. The dam structure vertically overlaps the portion of the encapsulant.

IPC Classes  ?

• H01L 23/16 - Fillings or auxiliary members in containers, e.g. centering rings
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates

Abstract

A delay locked loop device is provided, which includes a receiver, a delay line, a frequency detection and control circuit, a phase detector, and a delay control circuit. The receiver compares an input clock signal and a reference voltage to generate a first signal, and generate a reference clock signal based on the input clock signal. The delay line delays the first signal to generate a second signal based on a delay control signal. The frequency detection and control circuit detects an operating frequency of the reference clock signal to generate an enable signal. The phase detector detects, in response to the enable signal, a phase difference between the reference clock signal and a feedback clock signal to generate a phase detection result. The delay control circuit is configured to generate the delay control signal for the delay line based on the phase detection result.

IPC Classes  ?

• H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
• G11C 11/4076 - Timing circuits
• H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
• H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Abstract

A delay locked loop device is provided, which includes a receiver, a delay line, a frequency detection and control circuit, a phase detector, and a delay control circuit. The receiver compares an input clock signal and a reference voltage to generate a first signal, and generate a reference clock signal based on the input clock signal. The delay line delays the first signal to generate a second signal based on a delay control signal. The frequency detection and control circuit detects an operating frequency of the reference clock signal to generate an enable signal. The phase detector detects, in response to the enable signal, a phase difference between the reference clock signal and a feedback clock signal to generate a phase detection result. The delay control circuit is configured to generate the delay control signal for the delay line based on the phase detection result.

IPC Classes  ?

• H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
• G11C 11/4076 - Timing circuits
• H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
• H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Abstract

A manufacturing method of a semiconductor device includes stacking a first hard mask layer on an active area layer; coating a photoresist on the first hard mask layer, in which the photoresist covers a first peripheral portion of the first hard mask layer; partially etching the first hard mask layer; side etching the photoresist to expose a second peripheral portion of the first hard mask layer; etching the first hard mask layer and the active area layer, in which after the etching, the active area layer has a ladder-shaped upper surface; and depositing a dielectric layer on the ladder-shaped upper surface.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The present disclosure provides a method of forming a semiconductor structure. The method includes the following operations. A diamond-like carbon hard mask layer is formed on a substrate, in which an absorbance of the diamond-like carbon hard mask layer is smaller than or equal to 0.5. A dielectric anti-reflective coating layer is formed on the diamond-like carbon hard mask layer. A bottom anti-reflective coating layer is formed on the dielectric anti-reflective coating layer.

IPC Classes  ?

• H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
• H01L 21/311 - Etching the insulating layers

Abstract

The present application discloses a photoresist structure, a semiconductor device including the photoresist structure, and a method for fabricating the semiconductor device including the photoresist structure. The photoresist structure includes a bottom photoresist layer; a top photoresist layer positioned on the bottom photoresist layer. A coefficient of thermal expansion of the top photoresist layer is greater than a coefficient of thermal expansion of the bottom photoresist layer.

IPC Classes  ?

• G03F 7/09 - Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
• G03F 7/033 - Non-macromolecular photopolymerisable compounds having carbon-to-carbon double bonds, e.g. ethylenic compounds with binders the binders being polymers obtained by reactions only involving carbon-to-carbon unsaturated bonds, e.g. vinyl polymers

Abstract

An electronic device and a manufacturing method are provided. The electronic device includes a first semiconductor chip, a second semiconductor chip, a third semiconductor chip, a fourth semiconductor and a fifth semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip, and is electrically connected to the first semiconductor chip by hybrid bonding. The fourth semiconductor chip is stacked on the third semiconductor chip, and is electrically connected to the third semiconductor chip by hybrid bonding. The third semiconductor chip is stacked on the second semiconductor chip, and is electrically connected to the second semiconductor chip through a plurality of bumps. The fifth semiconductor chip disposed below the first semiconductor chip, and is electrically connected to the first semiconductor chip through a plurality of electrical connectors.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/498 - Leads on insulating substrates
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

The present application discloses a photoresist structure, a semiconductor device including the photoresist structure, and a method for fabricating the semiconductor device including the photoresist structure. The photoresist structure includes a bottom photoresist layer and a top photoresist layer positioned on the bottom photoresist layer. A coefficient of thermal expansion of the top photoresist layer is greater than a coefficient of thermal expansion of the bottom photoresist layer.

IPC Classes  ?

• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
• G03F 7/38 - Treatment before imagewise removal, e.g. prebaking
• H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
• H01L 21/311 - Etching the insulating layers

Abstract

A label dispensing device includes a housing having a label outlet, a collection reel, a feeding reel, a driving mechanism and a peeling mechanism. The collection reel and the feeding reel are rotatably disposed in the housing. The driving mechanism drives one of the feeding reel and the collection reel for conveying a label strip from the feeding reel to the collection reel. The peeling mechanism is disposed in the housing and used to change a conveying direction of the label strip being pulled from the feeding reel towards the label outlet into a recycled direction intersected with the conveying direction from the peeling mechanism downwardly for peeling off one of label stickers from the label strip when the label sticker is passing the peeling mechanism.

IPC Classes  ?

• B65C 9/18 - Label feeding from strips, e.g. from rolls
• B65C 9/00 - Details of labelling machines or apparatus
• B65C 11/02 - Manually-controlled or manually-operable label dispensers, e.g. modified for the application of labels to articles having printing equipment

Abstract

The present application discloses a capacitor structure and a method for fabricating the capacitor structure. The capacitor structure includes a first electrode including carbon nanotubes; a second electrode including graphene and vanadium oxide; a separator separating the first electrode and the second electrode; and a first type electrolyte surrounding the first electrode, the second electrode, and the separator.

IPC Classes  ?

• H01G 11/04 - Hybrid capacitors
• H01G 11/28 - Electrodes characterised by their structure, e.g. multi-layered, porosity or surface features arranged or disposed on a current collectorLayers or phases between electrodes and current collectors, e.g. adhesives
• H01G 11/36 - Nanostructures, e.g. nanofibres, nanotubes or fullerenes
• H01G 11/46 - Metal oxides
• H01G 11/52 - Separators
• H01G 11/70 - Current collectors characterised by their structure

Abstract

An electronic device and a manufacturing method are provided. The electronic device includes a first semiconductor chip, a second semiconductor chip, a third semiconductor chip, a fourth semiconductor and a fifth semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip, and is electrically connected to the first semiconductor chip by hybrid bonding. The fourth semiconductor chip is stacked on the third semiconductor chip, and is electrically connected to the third semiconductor chip by hybrid bonding. The third semiconductor chip is stacked on the second semiconductor chip, and is electrically connected to the second semiconductor chip through a plurality of bumps. The fifth semiconductor chip disposed below the first semiconductor chip, and is electrically connected to the first semiconductor chip through a plurality of electrical connectors.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

The present application discloses a capacitor structure and a method for fabricating the capacitor structure. The capacitor structure includes a first electrode including carbon nanotubes; a second electrode including graphene and vanadium oxide; a separator separating the first electrode and the second electrode; and a first type electrolyte surrounding the first electrode, the second electrode, and the separator.

IPC Classes  ?

• H01G 11/04 - Hybrid capacitors
• H01G 11/28 - Electrodes characterised by their structure, e.g. multi-layered, porosity or surface features arranged or disposed on a current collectorLayers or phases between electrodes and current collectors, e.g. adhesives
• H01G 11/36 - Nanostructures, e.g. nanofibres, nanotubes or fullerenes
• H01G 11/46 - Metal oxides
• H01G 11/52 - Separators
• H01G 11/70 - Current collectors characterised by their structure

Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first bottom conductive layer positioned in the substrate; a bottom porous dielectric layer positioned on the substrate; a top porous dielectric layer positioned on the bottom porous dielectric layer; a middle porous dielectric layer positioned between the bottom porous dielectric layer and the top porous dielectric layer; and a mixing-area conductive structure positioned along the top porous dielectric layer, the middle porous dielectric layer, and the bottom porous dielectric layer, and positioned on the first bottom conductive layer. A porosity of the top porous dielectric layer is greater than a porosity of the middle porous dielectric layer. The porosity of the middle porous dielectric layer is greater than a porosity of the bottom porous dielectric layer.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions

Abstract

The present application provides a memory device having an ultra-lightly doped region and a manufacturing method of the memory device. The memory device includes a semiconductor substrate including a word line extending into the semiconductor substrate, wherein the semiconductor substrate is defined with a source region, a drain region and an ultra-lightly doped region under the drain region, the word line is disposed between the source region and the drain region, and the ultra-lightly doped region is disposed at a sidewall of the word line.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The present disclosure provides a capacitor structure. The capacitor structure includes a bottom electrode, a first dielectric layer, and a first top electrode. The bottom electrode includes a bottom portion and a side portion, in which the side portion extends upward from an edge of the bottom portion, the side portion includes a first portion and a second portion on the first portion, in which a first width of the first portion is smaller than a second width of the second portion. The first dielectric layer is on the bottom electrode. The first top electrode is on the first dielectric layer.

IPC Classes  ?

• H10D 1/00 - Resistors, capacitors or inductors
• H10D 1/68 - Capacitors having no potential barriers

Abstract

The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate and a word line. The word line is embedded in the substrate and includes a high work function layer and a low work function layer on the high work function layer, in which an average work function of the high work function layer is larger than an average work function of the low work function layer, the low work function layer includes a lower portion and an upper portion on the lower portion, and an average grain size of the lower portion is smaller than an average grain size of the upper portion.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A semiconductor structure includes a semiconductor substrate, a bit-line structure, and a bit-line spacer. The bit-line structure is disposed on the semiconductor substrate. The bit-line spacer covers the bit-line structure, in which the bit-line spacer includes a SiCO layer, an insulating oxide layer, and an insulating nitride layer. The SiCO layer covers the bit-line structure, in which an oxygen concentration of the SiCO layer is equal to or greater than 55 at %. The insulating oxide layer covers the SiCO layer. The insulating nitride layer covers the insulating oxide layer.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A wafer transfer device detection system includes detectors, a filling device, a wafer transfer device and a control center. Detectors are disposed between a plurality of process equipment in a process. Filling device performs a filling procedure. Wafer transfer device includes body and sensor disposed in body. Wafer transfer device transmits wafer of process. Sensor detects a gas concentration inside wafer transfer device during a transportation stage of the process. If gas concentration is higher than a preset gas concentration, sensor generates a wireless communication signal. Control center is coupled to detectors and filling device. If detectors receive the wireless communication signal. Detectors notify control center so that the control center transmits wafer transfer device to filling device from process. Control center controls the filling device to perform filling procedure so as to adjust gas concentration to a target gas concentration to retransmit wafer transfer device back to process.

IPC Classes  ?

• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
• G01N 33/00 - Investigating or analysing materials by specific methods not covered by groups
• H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers

Abstract

A method for fabricating a capacitor is provided. The method includes following steps. A mold is formed on an interconnect layer. A recess is formed in the mold. A bottom electrode layer is deposited on the mold and into the recess. A metal oxide layer is disposed on the bottom electrode layer and into the recess. A surface oxide layer is formed on the metal oxide layer. A non-O2 wet etching process is performed to remove the surface oxide layer, the metal oxide layer, and the mold from the bottom electrode layer.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A method of manufacturing a patterned photoresist layer over a base material and a method of manufacturing a plurality of openings in a base layer are provided. The method includes: providing a base material; forming a photoresist layer over the base material, wherein the photoresist layer includes a negative expansion coefficient material; patterning the photoresist layer to form a first actual pattern having a first critical dimension; and applying an energy to the photoresist layer so that the first actual pattern becomes a second actual pattern, wherein the second actual pattern has a second critical dimension different from the first critical dimension of the first actual pattern.

IPC Classes  ?

• G03F 7/40 - Treatment after imagewise removal, e.g. baking

Abstract

This invention provides a method for forming conductors and their contacts which carry signals for advanced semiconductor memory devices with self-aligned STI support beams, during the method process a patterning layer including a sub shallow trench isolation pattern in a first direction and a sub support beam pattern in a second direction perpendicular to the first direction is provided over a substrate, a STI etching is performed in a way that an anisotropic STI etching is executed in the second direction and a STI tilt etching is executed in the first direction simultaneously, whereby shallow trenches in the second direction with the support beams inside them hanging underneath the sub support beam pattern and adjoining the substrate underneath the sub shallow trench isolation pattern are provided. The support beams mechanically support the shallow trenches during the whole STI manufacturing to suppress the bending, deforming, or tilting of STI.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The present disclosure provides a method of forming a patterned structure. The method includes the following operations. A photoresist layer on a target layer is patterned to form a first opening in a patterned photoresist layer. A directed self-assembly layer is formed on the patterned photoresist layer and in the first opening, in which a directed self-assembly material in the directed self-assembly layer separates into a first phase on the patterned photoresist layer and a second phase in the first opening by the first phase being attracted by a polarity of the patterned photoresist layer. The second phase is removed to form a second opening through the directed self-assembly layer. The target layer is etched through the second opening.

IPC Classes  ?

• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
• H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
• H01L 21/311 - Etching the insulating layers

Abstract

A method of forming a memory device includes forming a trench in a substrate, forming a first dielectric layer lining the trench, forming a first conductive layer into the trench, etching back the first conductive layer, resulting in a native oxide layer being formed over the first conductive layer, performing an etching process to remove the native oxide layer to expose the first conductive layer and to trim a portion of the first dielectric layer exposed by the first conductive layer, and forming a second conductive layer into the trench and in contact with the first conductive layer.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

Embodiments of this disclosure provide a semiconductor structure, including an active device layer disposed over a substrate and a capacitor structure disposed on the active device layer. The capacitor structure includes a first conductive layer disposed on the active device layer, an insulating layer disposed on the first conductive layer, a second conductive layer disposed on the insulating layer, a third conductive layer disposed on the second conductive layer, a bottom inner insulating layer surrounding the first conductive layer in a top view, a second inner conductive layer surrounding the bottom inner insulating layer in the top view, and a third inner conductive layer surrounding the second inner conductive layer in the top view. Additionally, a method of manufacturing a semiconductor structure is also disclosed in this disclosure.

IPC Classes  ?

• H10D 1/00 - Resistors, capacitors or inductors
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H10D 1/68 - Capacitors having no potential barriers

Abstract

A semiconductor device includes a substrate including a source region and a drain region; a word line structure including a word line dielectric layer in the substrate, a word line conductive layer on the word line dielectric layer and within the substrate, and a word line capping layer on the word line conductive layer; a top thickening layer between the word line conductive layer and the word line capping layer, and between the word line dielectric layer and the word line capping layer; a bottom capping layer on the substrate and adjacent to the word line dielectric layer; a top capping layer covering the bottom capping layer and the word line structure; a bit line penetrating through the top and bottom capping layers and extending into the source region; and a cell contact penetrating through the top and bottom capping layers and extending into the drain region.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The present disclosure provides a method of testing a semiconductor device. The method includes: providing a wafer on a chuck; moving the chuck to a first expected position under a probe card; moving the chuck from the first expected position to a second expected position so that a plurality of dies of the wafer contact a plurality of pins of the probe card; testing a first portion of the dies of the wafer; moving the chuck to the second expected position so that the dies of the wafer abut against the pins of the probe card; and testing a second portion of the dies of the wafer.

IPC Classes  ?

• G01R 1/073 - Multiple probes
• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate, a bit line structure, a seed layer, a first spacer, a second spacer, a third spacer, and an air gap. The substrate has a recess, wherein the recess has a sharp corner. The bit line structure is on the substrate, wherein the recess surrounds the bit line structure. The seed layer is located on a sidewall of the bit line structure. The first spacer is located on a sidewall of the seed layer and on a bottom surface of the recess. The second spacer is filled in the recess. The third spacer is located on the substrate and adjacent to the first spacer. The air gap is between the first spacer and the third spacer; wherein a bottom of the air gap exposes a portion of a top surface of the second spacer.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A method of fabricating a semiconductor device that includes providing an initial structure, where the initial structure includes a bit line structure, a landing pad adjacent to the bit line structure, and an isolation layer adjacent to the landing pad, depositing a first dielectric layer on the initial structure, modifying an etch property of the first dielectric layer, performing an etching process on the first dielectric layer to form a first opening, and forming a capacitor structure in the first opening.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A semiconductor device includes a substrate including a source region and a drain region; a word line structure including a word line dielectric layer in the substrate, a word line conductive layer on the word line dielectric layer and within the substrate, and a word line capping layer on the word line conductive layer; a top thickening layer between the word line conductive layer and the word line capping layer, and between the word line dielectric layer and the word line capping layer; a bottom capping layer on the substrate and adjacent to the word line dielectric layer; a top capping layer covering the bottom capping layer and the word line structure; a bit line penetrating through the top and bottom capping layers and extending into the source region; and a cell contact penetrating through the top and bottom capping layers and extending into the drain region.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/49 - Metal-insulator semiconductor electrodes

Abstract

A method of manufacturing a patterned photoresist layer over a base material and a method of manufacturing a plurality of openings in a base layer are provided. The method includes: providing a base material; forming a photoresist layer over the base material, wherein the photoresist layer includes a negative expansion coefficient material; patterning the photoresist layer to form a first actual pattern having a first critical dimension; and applying an energy to the photoresist layer so that the first actual pattern becomes a second actual pattern, wherein the second actual pattern has a second critical dimension different from the first critical dimension of the first actual pattern.

IPC Classes  ?

• G03F 7/40 - Treatment after imagewise removal, e.g. baking

Abstract

A semiconductor device includes a gate structure disposed over a semiconductor substrate, and a dielectric layer surrounding the gate structure. The semiconductor device also includes a source region and a drain region disposed in the semiconductor substrate and on opposite sides of the gate structure. The semiconductor device further includes a first dipole portion disposed over the semiconductor substrate and covering the source region, and a first dielectric spacer disposed over the first dipole portion and adjacent to the dielectric layer.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

Abstract

A semiconductor device includes a gate structure disposed over a semiconductor substrate, and a dielectric layer surrounding the gate structure. The semiconductor device also includes a source region and a drain region disposed in the semiconductor substrate and on opposite sides of the gate structure. The semiconductor device further includes a first dipole portion disposed over the semiconductor substrate and covering the source region, and a first dielectric spacer disposed over the first dipole portion and adjacent to the dielectric layer.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/66 - Types of semiconductor device

Abstract

A memory device includes a first chip, a second chip and a processor. The second chip is coupled to the first chip at a first node. The second chip includes a first capacitor and a first variable resistor. The first capacitor is coupled to the first node. The first variable resistor is coupled in series with the first capacitor. The processor is coupled to the first node, and is configured to perform a first read operation to the first chip via the first node. A method for operating a memory device is also disclosed herein.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
• H01C 10/16 - Adjustable resistors including plural resistive elements

Abstract

Embodiments of this disclosure provide a semiconductor structure, including an active area disposed in a substrate, a gate structure disposed on the active area, two source/drain regions disposed in the substrate on both sides of the gate structure, two bit line contacts disposed on the both sides of the gate structure, a first dielectric layer surrounding an upper portion of the gate structure and a second dielectric layer surrounding an upper portion of each of the two bit line contacts. Each of the two bit line contacts directly contacts a portion of each of the two source/drain regions. Additionally, a method of manufacturing a semiconductor structure is also provided in this disclosure.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 21/8234 - MIS technology
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/66 - Types of semiconductor device

Abstract

A method for manufacturing a memory device includes forming a hard mask structure over a dielectric structure. The hard mask structure includes a first hard mask layer, a second hard mask layer over the first hard mask layer, and a third hard mask layer over the second hard mask layer. The method further includes forming a spacer layer having a pattern over the hard mask structure. The method further includes performing a patterning process to transfer the pattern of the spacer layer to the first hard mask layer and the second hard mask layer of the hard mask structure. The method further includes removing the second hard mask layer from the first hard mask layer after the patterning process is complete. The method further includes etching the dielectric structure through the first hard mask layer.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A method of manufacturing a semiconductor structure includes forming bit line structures on a substrate; forming a dielectric layer on the substrate and between the bit line structures; forming a layer stack including a plasma treated oxygen-rich ARC layer and a silicon-rich ARC layer on the dielectric layer; forming a patterned mask layer including a mask feature and an opening on the layer stack, the opening has a first width smaller than a pitch between adjacent two of the bit line structures; trimming the patterned mask layer to enlarge the opening such that the opening has a second width greater than the first width; patterning the layer stack by using patterned mask layer as a mask after trimming the patterned mask layer; and etching the substrate to form a contact hole between the bit line structures by using the patterned layer stack as a hard mask.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
• H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
• H01L 21/311 - Etching the insulating layers

Abstract

A semiconductor device includes a bottom electrode structure disposed over a semiconductor substrate. The bottom electrode structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer, arranged from bottom to top. The first metal layer, the third metal layer and the fifth metal layer include a first metal material, and the second metal layer and the fourth metal layer include a second metal material different from the first metal material. The semiconductor device also includes a high-k dielectric structure disposed on opposite sidewalls of the bottom electrode structure. The opposite sidewalls of the bottom electrode structure are step-shaped. The semiconductor device further includes a top electrode structure laterally surrounding the bottom electrode structure and separated from the bottom electrode structure by the high-k dielectric structure.

IPC Classes  ?

• H10D 1/68 - Capacitors having no potential barriers

Abstract

A semiconductor device includes a bottom electrode structure disposed over a semiconductor substrate. The bottom electrode structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer, arranged from bottom to top. The first metal layer, the third metal layer and the fifth metal layer include a first metal material, and the second metal layer and the fourth metal layer include a second metal material different from the first metal material. The semiconductor device also includes a high-k dielectric structure disposed on opposite sidewalls of the bottom electrode structure. The opposite sidewalls of the bottom electrode structure are step-shaped. The semiconductor device further includes a top electrode structure laterally surrounding the bottom electrode structure and separated from the bottom electrode structure by the high-k dielectric structure.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 21/3105 - After-treatment
• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• H01L 21/764 - Air gaps

Abstract

A semiconductor structure includes a substrate and a capacitor structure. The substrate includes a semiconductor substrate, a dielectric layer disposed on the semiconductor substrate, and a plurality of metal contacts disposed in the dielectric layer. The capacitor structure includes a plurality of vertical capacitor cups coupled to the metal contacts, respectively. Each of the vertical capacitor cups has an inside height and an outside height, in which the inside height is smaller than the outside height. A method of forming the semiconductor structure is also disclosed.

IPC Classes  ?

• H10D 1/00 - Resistors, capacitors or inductors
• H10D 1/68 - Capacitors having no potential barriers

Abstract

A chemical mechanical polishing (CMP) pad includes a pad body. The pad body has a polishing surface and a plurality of inner surfaces respectively connected with the polishing surface. The inner surfaces are separated from each other and respectively surround to define a columnar hole. The polishing surface is configured to polish against a workpiece. The columnar holes are configured to accommodate a polishing slurry.

IPC Classes  ?

• B24B 37/26 - Lapping pads for working plane surfaces characterised by the shape of the lapping pad surface, e.g. grooved

Abstract

A manufacturing method of a semiconductor device includes depositing, using a first atomic layer deposition, a first thin poly silicon layer on an active area, in which the active area includes a trench; depositing, using a second atomic layer deposition, a second thin poly silicon layer on the active area; and depositing, using a chemical vapor deposition, a poly silicon layer on the active area to form a poly silicon structure, in which a gas for the chemical vapor deposition includes disilane, a thickness of the poly silicon layer in a bottom of the trenches is substantially zero.

IPC Classes  ?

• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions

Abstract

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, and a word line. The substrate includes an active region. The word line is embedded within the substrate and extends along a first direction. The bit line is disposed over the substrate and extends along a second direction different from the first direction. The active region includes a first semiconductor layer with a first dopant concentration and a second semiconductor layer with a second dopant concentration less than the first dopant concentration.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a gate structure on the substrate; a plurality of inner spacer layers on sidewalls of the gate structure; a plurality of outer spacer layers on the plurality of inner spacer layers; a plurality of air gaps between the inner spacer layers and the outer spacer layers; a bottom dielectric layer on the substrate and laterally surrounding the outer spacer layers; a bottom capping layer on the bottom dielectric layer, the inner spacer layers, the air gaps, the outer spacer layers, and the gate structure; a conductive layer on the bottom capping layer and including a plurality of conductive wires; a top capping layer positioned on the conductive layer; and a plurality of air spacers positioned between the conductive wires.

IPC Classes  ?

• H01L 29/49 - Metal-insulator semiconductor electrodes
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions
• H01L 29/51 - Insulating materials associated therewith
• H01L 29/66 - Types of semiconductor device

Abstract

A method of forming a semiconductor device includes forming a first metal material lining a trench in a semiconductor substrate at a first temperature. The method further includes forming a second metal material lining the first metal material at a second temperature higher than the first temperature. The method further includes performing an annealing process to the first and second metal materials.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, and a word line. The substrate includes an active region. The word line is embedded within the substrate and extends along a first direction. The bit line is disposed over the substrate and extends along a second direction different from the first direction. The active region includes a first semiconductor layer with a first dopant concentration and a second semiconductor layer with a second dopant concentration less than the first dopant concentration.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions