Monolithic 3D Inc.

United States of America

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2023 1
Before 2020 5
IPC Class
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS 2
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration 2
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND 2
H01L 27/11551 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels 2
G06N 3/08 - Learning methods 1
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Found results for  patents

1.

A 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH HEAT SPREADER

      
Application Number US2022044165
Publication Number 2023/049132
Status In Force
Filing Date 2022-09-21
Publication Date 2023-03-30
Owner MONOLITHIC 3D INC. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Cronquist, Brian

Abstract

A semiconductor device, the device including: a first level including a plurality of first transistors, where at least one of the plurality of first transistors includes a single crystal channel; a first interconnect layer disposed on top of the plurality of first transistors; a plurality of ground lines disposed underneath the plurality of first transistors, the plurality of ground lines connecting from a ground to at least one of the plurality of first transistors; a plurality of power lines disposed underneath the plurality of first transistors, the plurality of power lines connecting from power to at least one of the plurality of first transistors; and a heat conductive material disposed so to be in contact with the plurality of ground lines and the plurality of power lines, where the heat conductive material includes diamond molecules.

IPC Classes  ?

  • H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/367 - Cooling facilitated by shape of device
  • H04L 25/02 - Baseband systems Details
  • H04L 27/26 - Systems using multi-frequency codes
  • G06N 3/08 - Learning methods

2.

3D SEMICONDUCTOR DEVICE, STRUCTURE AND METHODS

      
Application Number US2018052332
Publication Number 2019/060798
Status In Force
Filing Date 2018-09-23
Publication Date 2019-03-28
Owner MONOLITHIC 3D INC. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Cronquist, Brian
  • Lusky, Eli

Abstract

A first and a second 3D device, both devices including: at least a first level including logic circuits; at least a second level including an array of memory cells; at least a third level including special circuits; and at least a fourth level including special connectivity structures, where the special connectivity structures include one of the following: a. optical waveguides, or b. differential signaling, or c. radio frequency transmission lines, or d. Surface Waves Interconnect (SWI) lines, where the second level overlays the first level, the third level overlays the second level, and the fourth level overlays the third level, where the first level includes a substrate included of single crystal silicon, where the first device is much larger in surface area than the second device, and where the fourth level of the second device is very similar to a portion of the fourth level of the first device.

IPC Classes  ?

  • H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
  • H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND

3.

3D SEMICONDUCTOR DEVICE AND STRUCTURE

      
Application Number US2018016759
Publication Number 2018/144957
Status In Force
Filing Date 2018-02-03
Publication Date 2018-08-09
Owner MONOLITHIC 3D INC. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Lusky, Eli

Abstract

A 3D device, the device including: at least four active transistor layers, each layer including a plurality of transistors; and at least one per-layer programmable contact for each layer of the at least four active transistor layers.

IPC Classes  ?

  • H01L 27/11551 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
  • H01L 27/11529 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region of memory regions comprising cell select transistors, e.g. NAND
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

4.

3D SEMICONDUCTOR DEVICE AND STRUCTURE

      
Application Number US2017052359
Publication Number 2018/071143
Status In Force
Filing Date 2017-09-19
Publication Date 2018-04-19
Owner MONOLITHIC 3D INC. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Cronquist, Brian
  • Lusky, Eli

Abstract

A 3D device, the device comprising: a first stratum comprising a first bit-cell array, the first bit-cell array includes three independent first rows; a second stratum including a second bit-cell array, the second bitcell array includes three independent second rows, where the second stratum overlays the first stratum; and at least three vertical bitlines each connected to respective three horizontal first bitlines and three horizontal second bitlines, where the three horizontal first bitlines include control of the first bit-cell array, where the three horizontal second bitlines include control of the second bit-cell array, and where each of the three vertical bitlines could be used to control a different one of the three independent first rows, or control a different one of the three independent second rows

IPC Classes  ?

  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 27/11551 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H01L 27/108 - Dynamic random access memory structures
  • H01L 27/11 - Static random access memory structures

5.

3D SEMICONDUCTOR DEVICE AND STRUCTURE

      
Application Number US2016052726
Publication Number 2017/053329
Status In Force
Filing Date 2016-09-21
Publication Date 2017-03-30
Owner MONOLITHIC 3D INC (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo

Abstract

A multilevel semiconductor device including a first level including a first array of first memory cells; a second level including a second array of second memory cells, the first level is overlaid by the second level, where at least one of the first memory cells includes a vertically oriented first transistor, and where at least one of the second memory cells includes a vertically oriented second transistor, and where the first transistor includes a first single crystal channel, and where the second transistor includes a second single crystal channel, and where the first transistor is self-aligned to the second transistor

IPC Classes  ?

  • H01L 27/115 - Electrically programmable read-only memories; Multistep manufacturing processes therefor
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

6.

SEMICONDUCTOR DEVICE AND STRUCTURE

      
Application Number US2011042071
Publication Number 2012/015550
Status In Force
Filing Date 2011-06-28
Publication Date 2012-02-02
Owner MONOLITHIC 3D, INC. (USA)
Inventor
  • Or-Bach, Zvi
  • Sekar, Deepak C.
  • Cronquist, Brian
  • Wurman, Zeev

Abstract

A method for fabrication of semiconductor device comprising a first wafer comprising first single crystal layer comprising first transistors, first alignment marks, and first transistors interconnect layers comprising at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum; and comprising a step of implant and high temperature activation to form a conductive layer within a second wafer; and forming a second crystallized layer on top of said first wafer by transferring said conductive layer using ion-cut process, and forming second transistors on said second crystallized layer wherein said second transistors source and drain comprises portion of said first conductive layer.

IPC Classes  ?

  • H01L 21/336 - Field-effect transistors with an insulated gate
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors