Monolithic 3D Inc.

United States of America

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H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration 142
H01L 23/00 - Details of semiconductor or other solid state devices 124
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate 124
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group 112
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements 105
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1.

3D SEMICONDUCTOR DEVICE, STRUCTURE AND METHODS WITH MEMORY ARRAYS AND CONNECTIVITY STRUCTURES

      
Application Number 18739083
Status Pending
Filing Date 2024-06-10
First Publication Date 2025-01-30
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Cronquist, Brian
  • Lusky, Eli

Abstract

A 3D semiconductor device including dicing including an etch process; and including: a first level including a single crystal layer, and a memory control circuit which includes first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors—which may include a metal gate—disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; a memory array including word-lines and at least four memory mini arrays (each mini array includes at least four rows by four columns of memory cells), each memory cell includes at least one second transistor or at least one third transistor; and a connection path from fourth metal to third metal, the path includes a via disposed through the memory array.

IPC Classes  ?

  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
  • H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

2.

3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH SINGLE-CRYSTAL LAYERS

      
Application Number 18829107
Status Pending
Filing Date 2024-09-09
First Publication Date 2024-12-26
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak C.

Abstract

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a first oxide layer disposed atop of the first level; a second level including second transistors and at least one array of memory cells, where each of the memory cells includes at least one of the second transistors, where the second level overlays the first level, where the at least one of the second transistors includes a recessed channel, and where the second level is directly bonded to the first level.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 20/00 - Read-only memory [ROM] devices
  • H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

3.

3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH MEMORY CELLS AND MULTIPLE METAL LAYERS

      
Application Number 18798708
Status Pending
Filing Date 2024-08-08
First Publication Date 2024-12-05
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak C.

Abstract

A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 20/00 - Read-only memory [ROM] devices
  • H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

4.

3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH SLITS

      
Application Number 18800057
Status Pending
Filing Date 2024-08-10
First Publication Date 2024-12-05
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Lusky, Eli

Abstract

A semiconductor device including: a first level including memory control circuits (include a plurality of refresh circuits for the memory units) which include first transistors; a second level including a first array of memory cells including second transistors self-aligned to at least one of the third transistors; a third level disposed on top of the second level disposed on top of first level, the third level including a second array of memory cells including third transistors; a fourth level disposed on top of the third level, the fourth level including a third array of memory cells including fourth transistors, second level is bonded to the first level, a plurality of slits disposed through the second level, the third level, and the fourth level, the slits enable gate replacement of a plurality of the third transistors, where the second array of memory cells include a plurality of independently controlled memory units.

IPC Classes  ?

  • G11C 16/10 - Programming or data input circuits
  • H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

5.

DESIGN AUTOMATION METHODS FOR 3D INTEGRATED CIRCUITS AND DEVICES

      
Application Number 18800058
Status Pending
Filing Date 2024-08-10
First Publication Date 2024-12-05
Owner Monolithic 3D Inc (USA)
Inventor
  • Or-Bach, Zvi
  • Wurman, Zeev

Abstract

A method of designing a 3D Integrated Circuit including: partitioning at least one design into at least two levels, a first level and a second level, where the first level includes first transistors, where the second level includes second transistors and is disposed on top of the first level; levels connection pads (LCPs) disposed between the first level and second level; providing placement of the LCPs; performing a placement of the first level using a placer program executed by a computer, where the placement of the first level is based on the placement of the LCPs, where the placer is part of a Computer Aided Design (CAD) tool, where the first level includes first routing layers; performing a routing of the first level by routing layers using a router executed by a computer, where the router is a part of the CAD tool or a part of another CAD tool.

IPC Classes  ?

6.

METHOD TO PRODUCE A 3D MULTILAYER SEMICONDUCTOR DEVICE AND STRUCTURE

      
Application Number 18793939
Status Pending
Filing Date 2024-08-05
First Publication Date 2024-11-28
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo

Abstract

A method of making a 3D multilayer semiconductor device, including: providing a first substrate including a first level, the first level including a first single crystal silicon layer; providing a second substrate including a second level, the second level including a second single crystal silicon layer; performing an epitaxial growth of a SiGe layer on top of the second single crystal silicon layer; performing an epitaxial growth of a third single crystal silicon layer on top of the SiGe layer, the third silicon layer has an average thickness of less than 2,000 nm; forming a plurality of second transistors each including a single crystal channel; forming many metal layers interconnecting the plurality of second transistors; and then performing a bonding of the second level onto the first level, where performing the bonding includes making oxide-to-oxide bond zones; and performing removal of a majority of the second single crystal silicon layer.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

7.

Methods for producing a 3D semiconductor memory device and structure

      
Application Number 17942109
Grant Number 12154817
Status In Force
Filing Date 2022-09-09
First Publication Date 2024-11-26
Grant Date 2024-11-26
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak C.

Abstract

A method for producing a 3D memory device including: providing a first level including a first single-crystal layer and control circuits, where the first level includes at least two interconnecting metal layers; forming at least one second level disposed above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level; each of first memory cells include one first transistor and each of second memory cells include one second transistor, where first memory cells and second memory cells are a NAND nonvolatile type memory, and at least one of the second transistors include a metal gate.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 20/00 - Read-only memory [ROM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components

8.

3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH LOGIC CIRCUITS, MEMORY CELLS, AND PROCESSOR ARRAY

      
Application Number 18786372
Status Pending
Filing Date 2024-07-26
First Publication Date 2024-11-21
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Cronquist, Brian

Abstract

An integrated semiconductor device including: a first level; a second level, where the first level includes single crystal silicon and a plurality of logic circuits, where the plurality of logic circuits each include first transistors, where the second level is disposed above the first level and includes a plurality of arrays of first memory cells, where the second level includes second transistors, where each of the first memory cells includes at least one of the second transistors, where the first level is bonded to the second level; an array of processors; and a third level, where the third level includes third transistors, where the third level is disposed above the second level and includes a plurality of arrays of second memory cells, where each of the second memory cells includes at least one of the third transistors, where the device includes a substrate area greater than 1,000 mm2.

IPC Classes  ?

  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

9.

3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH THREE LEVELS AND ISOLATION LAYERS

      
Application Number 18778977
Status Pending
Filing Date 2024-07-20
First Publication Date 2024-11-14
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Sekar, Deepak C.
  • Cronquist, Brian

Abstract

A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, where the third level is bonded to the second level; and a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors.

IPC Classes  ?

  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
  • H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
  • H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/732 - Vertical transistors
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/808 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a PN junction gate
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

10.

3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS AND A POWER DELIVERY PATH

      
Application Number 18778978
Status Pending
Filing Date 2024-07-20
First Publication Date 2024-11-14
Owner Monolithic 3D Inc. (USA)
Inventor Or-Bach, Zvi

Abstract

A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, and where the third level is bonded to the second level; a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors; and a plurality of capacitors, where the plurality of capacitors include functioning as a decoupling capacitor to mitigate power supply noise.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • G11C 11/404 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
  • G11C 11/4097 - Bit-line organisation, e.g. bit-line layout, folded bit lines
  • G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
  • G11C 16/02 - Erasable programmable read-only memories electrically programmable
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
  • H10B 69/00 - Erasable-and-programmable ROM [EPROM] devices not provided for in groups , e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

11.

3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS

      
Application Number 18783965
Status Pending
Filing Date 2024-07-25
First Publication Date 2024-11-14
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian

Abstract

A semiconductor device including: a first level including: a first silicon layer including a first single crystal silicon layer; first transistors each including a single-crystal channel; a first metal layer connected to the first transistors and the second metal layer; a third metal layer connected to the second metal layer; a second level including second transistors; a third level including third transistors, the third level is disposed over the second level which is disposed over the first level; a fifth metal layer disposed over a fourth metal layer disposed over the third level; and a via disposed through the second level, where at least one of the second transistors includes a metal gate, where the device includes at least one temperature sensor, and where at least one element within at least one of the second transistors has been processed independently of the third transistors.

IPC Classes  ?

  • H01L 23/528 - Layout of the interconnection structure
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

12.

3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH CONNECTION PATHS

      
Application Number 18779059
Status Pending
Filing Date 2024-07-21
First Publication Date 2024-11-14
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian

Abstract

A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a plurality of second transistors, where the second level includes a third layer, the third layer including first conductive lines; a third level overlaying the second level, where the third level includes a plurality of third transistors, where the third level includes a fourth layer, the fourth layer including second conductive lines; and a plurality of connection paths, where the plurality of connection paths provides electrical connections at least from a plurality of the first transistors to the plurality of third transistors, and where the first level includes at least one voltage regulator.

IPC Classes  ?

  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

13.

MULTILEVEL SEMICONDUCTOR DEVICE AND STRUCTURE WITH IMAGE SENSORS AND WAFER BONDING

      
Application Number 18778976
Status Pending
Filing Date 2024-07-20
First Publication Date 2024-11-07
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Sekar, Deepak C.
  • Cronquist, Brian

Abstract

An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level including an oxide to oxide bond; a plurality of pixel control circuits; a third level disposed underneath the first level, where the third level includes a plurality of third transistors, where the plurality of third transistors each include a single crystal channel; and a plurality of recessed channel transistors.

IPC Classes  ?

14.

3D semiconductor device and structure with metal layers and memory cells

      
Application Number 18736423
Grant Number 12125737
Status In Force
Filing Date 2024-06-06
First Publication Date 2024-10-22
Grant Date 2024-10-22
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak C.

Abstract

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer, a third level including third transistors and overlaying the second level, a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 20/00 - Read-only memory [ROM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components

15.

3D semiconductor device and structure with logic and memory

      
Application Number 18527356
Grant Number 12120880
Status In Force
Filing Date 2023-12-03
First Publication Date 2024-10-15
Grant Date 2024-10-15
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo

Abstract

A 3D semiconductor device including: a first level including a single crystal layer and a memory control circuit including first transistors and at least one power-down control circuit; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors disposed atop the third metal layer with at least one including a metal gate; third transistors disposed atop the second transistors; a fourth metal layer atop the third transistors; a memory array including word-lines and at least four memory mini arrays, each including at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
  • H01L 29/47 - Schottky barrier electrodes
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels

16.

3D semiconductor device and structure with logic and memory

      
Application Number 18738721
Grant Number 12219769
Status In Force
Filing Date 2024-06-10
First Publication Date 2024-10-03
Grant Date 2025-02-04
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo

Abstract

A 3D semiconductor device including: a first level including a single crystal layer and a memory control circuit including first transistors and at least one cache memory unit; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors disposed atop the third metal layer with at least one including a metal gate; third transistors disposed atop the second transistors; a fourth metal layer atop the third transistors; a memory array including word-lines and at least four memory mini arrays, each including at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
  • H01L 29/47 - Schottky barrier electrodes
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels

17.

3D MEMORY SEMICONDUCTOR DEVICES AND STRUCTURES WITH MEMORY CELLS

      
Application Number 18738967
Status Pending
Filing Date 2024-06-10
First Publication Date 2024-10-03
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Lusky, Eli

Abstract

A 3D memory device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel, where the memory cell includes at least one charge trap structure, and where the at least one memory transistor is self-aligned to an overlaying another the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the control level includes a plurality of latch sense amplifiers, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

18.

3D MEMORY DEVICES AND STRUCTURES WITH MEMORY ARRAYS AND METAL LAYERS

      
Application Number 18731340
Status Pending
Filing Date 2024-06-02
First Publication Date 2024-09-26
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Cronquist, Brian

Abstract

A semiconductor device including: a first level including at least four independently controlled first memory arrays, where the first level includes first transistors; a second level disposed on top of the first level, where the second level includes second memory arrays; and a third level disposed on top of the second level, where the third level includes third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, where the second filled holes are aligned to the first filled holes with a more than 1 nm but less than 40 nm alignment error, and where the third level includes at least one SRAM memory array.

IPC Classes  ?

  • H10B 10/00 - Static random access memory [SRAM] devices
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

19.

3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS

      
Application Number 18668221
Status Pending
Filing Date 2024-05-19
First Publication Date 2024-09-26
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian

Abstract

A 3D semiconductor device including: a first level with first transistors, single crystal layer overlaid by at least one first metal layer which includes interconnects between the first transistors forming first control circuits with a sense amplifier, the first metal-layer(s) overlaid by a second metal-layer which is overlaid by a second level which includes first memory cells which include second transistors with a metal gate, overlaid by a third level which includes second memory cells which include third transistors and are partially disposed atop the control circuits, which control data written to second memory cells; a fourth metal-layer overlaying a third metal-layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within less than 100 nm, the average thickness of fourth metal-layer is at least twice the average thickness of second metal-layer; the fourth metal-layer includes a global power distribution grid.

IPC Classes  ?

  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

20.

3D semiconductor device and structure with bonding and memory cells preliminary class

      
Application Number 18677553
Grant Number 12144190
Status In Force
Filing Date 2024-05-29
First Publication Date 2024-09-19
Grant Date 2024-11-12
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak C.

Abstract

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; and a second level including a plurality of second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of memory cells, where each of the plurality of memory cells includes at least one of the second transistors, where the device includes at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.

IPC Classes  ?

  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

21.

3D semiconductor devices and structures with metal layers

      
Application Number 18668218
Grant Number 12199093
Status In Force
Filing Date 2024-05-19
First Publication Date 2024-09-12
Grant Date 2025-01-14
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian

Abstract

A semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, disposed over the third metal layer; a third level including a plurality of third transistors, disposed over the second level; a via disposed through the second and third levels; a fourth metal layer disposed over the third level; a fifth metal layer disposed over the fourth metal layer; and a fourth level including a second single crystal silicon layer and is disposed over the fifth metal layer, where each of the plurality of second transistors includes a metal gate, and the via has a diameter of less than 450 nm.

IPC Classes  ?

  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • G03F 9/00 - Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/45 - Ohmic electrodes
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/732 - Vertical transistors
  • H01L 29/786 - Thin-film transistors
  • H01L 29/808 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a PN junction gate
  • H01L 29/812 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a Schottky gate
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 20/00 - Read-only memory [ROM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

22.

MULTILEVEL SEMICONDUCTOR DEVICE AND STRUCTURE WITH OXIDE BONDING

      
Application Number 18622867
Status Pending
Filing Date 2024-03-30
First Publication Date 2024-09-05
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Sekar, Deepak C.
  • Cronquist, Brian

Abstract

A multi-level semiconductor device, the device comprising: a first level comprising integrated circuits; a second level comprising at least one electromagnetic wave receiver, wherein said second level is disposed above said first level, wherein said integrated circuits comprise single crystal transistors; and an oxide layer disposed between said first level and said second level, wherein said device comprises at least one read out circuit, wherein said second level is bonded to said oxide layer, and wherein said bonded comprises oxide to oxide bonds.

IPC Classes  ?

  • G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
  • H01L 23/00 - Details of semiconductor or other solid state devices

23.

3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH ELECTRONIC CIRCUIT UNITS

      
Application Number 18662468
Status Pending
Filing Date 2024-05-13
First Publication Date 2024-09-05
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Cronquist, Brian

Abstract

A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and overlaying the first level; at least four electronic circuit units (ECUs); a redundancy circuit, where each of the at least four ECUs includes a first circuit, which includes a portion of the first transistors, where each of the at least four ECUs includes a second circuit, the second circuit including some second transistors, where each of the at least four ECUs includes a vertical connectivity structure which includes pillars, where the pillars provide electrical connections between the first circuit and the second circuit, where each of the at least four ECUs includes at least one memory control circuit and at least one memory array, where the second level is bonded to the first level, and the bonded includes oxide to oxide and metal to metal bonding regions.

IPC Classes  ?

  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

24.

Method to produce a 3D multilayer semiconductor device and structure

      
Application Number 18622992
Grant Number 12100658
Status In Force
Filing Date 2024-03-31
First Publication Date 2024-08-15
Grant Date 2024-09-24
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo

Abstract

A method of making a 3D multilayer semiconductor device, the method comprising: providing a first substrate comprising a first level, said first level comprising a first single crystal silicon layer; providing a second substrate comprising a second level, said second level comprising a second single crystal silicon layer; performing an epitaxial growth of a SiGe layer on top of said second single crystal silicon layer; performing an epitaxial growth of a third single crystal silicon layer on top of said SiGe layer; forming a plurality of second transistors each comprising a single crystal channel; forming a plurality of metal layers interconnecting said plurality of second transistors; and then performing a bonding of said second level onto said first level, wherein performing said bonding comprises making oxide-to-oxide bond zones, and performing removal of a majority of said second single crystal silicon layer.

IPC Classes  ?

  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

25.

3D semiconductor device and structure with metal layers

      
Application Number 18623525
Grant Number 12100646
Status In Force
Filing Date 2024-04-01
First Publication Date 2024-08-15
Grant Date 2024-09-24
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian

Abstract

A semiconductor device including: a first silicon layer including a first single crystal silicon layer; first transistors with a single crystal channel and overlaid by a first metal layer; overlaid by a second metal layer; overlaid by a third metal layer; a second level with second transistors and including a metal gate, and then disposed over the third metal layer; the second level is overlaid by a third level with third transistors; and then overlaid by a fourth metal layer; fourth overlaid by a fifth metal layer; a via disposed through the second level; the device includes at least one temperature sensor; the fifth metal layer average thickness is greater than the third metal layer average thickness by at least 50%; at least one element within at least one of the second transistors has been processed independently of the third transistors.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

26.

3D SEMICONDUCTOR MEMORY DEVICES AND STRUCTURES

      
Application Number 18593884
Status Pending
Filing Date 2024-03-02
First Publication Date 2024-08-01
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo

Abstract

A 3D semiconductor device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a plurality of second transistors disposed atop the second metal layer; a third metal layer disposed above the plurality of second transistors; and a memory array including word-lines and memory cells, where the memory array includes at least four memory mini arrays, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors, and where the memory control circuit includes at least one power down control circuit.

IPC Classes  ?

  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

27.

3D SEMICONDUCTOR MEMORY DEVICES AND STRUCTURES WITH MEMORY CELLS

      
Application Number 18594804
Status Pending
Filing Date 2024-03-04
First Publication Date 2024-08-01
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo

Abstract

A 3D semiconductor device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer, a second metal layer overlaying the first metal layer, a plurality of second transistors disposed atop the second metal layer, a third metal layer disposed above the plurality of second transistors; and a memory array including word-lines and memory cells, where the memory array includes at least four memory mini arrays, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors, and where the memory control circuit includes at least one In-Out interface controller circuit.

IPC Classes  ?

  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

28.

3D semiconductor device and structure with metal layers and memory cells

      
Application Number 18429202
Grant Number 12094965
Status In Force
Filing Date 2024-01-31
First Publication Date 2024-07-25
Grant Date 2024-09-17
Owner Monolithic 3D Inc. (USA)
Inventor Or-Bach, Zvi

Abstract

3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer—which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; second metal layer overlaying first metal layer; a second level including second transistors, first memory cells and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells and include at least one sense amplifier; third metal layer disposed above third level; fourth metal layer includes global power distribution grid, has a thickness at least twice the second metal layer, disposed above third metal layer; fourth level includes single-crystal silicon, atop fourth metal layer.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • G11C 11/404 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
  • G11C 11/4097 - Bit-line organisation, e.g. bit-line layout, folded bit lines
  • G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
  • G11C 16/02 - Erasable programmable read-only memories electrically programmable
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
  • H10B 69/00 - Erasable-and-programmable ROM [EPROM] devices not provided for in groups , e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

29.

3D semiconductor memory devices and structures

      
Application Number 18592383
Grant Number 12178055
Status In Force
Filing Date 2024-02-29
First Publication Date 2024-07-25
Grant Date 2024-12-24
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo

Abstract

A 3D semiconductor device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a plurality of second transistors disposed atop the second metal layer; a third metal layer disposed atop the plurality of third transistors; and a memory array including word-lines and memory cells, where the memory array includes at least four memory mini arrays, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors, where the memory control circuit includes at least one digital to analog converter circuit, and where the device includes a hybrid bonding layer.

IPC Classes  ?

  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

30.

3D semiconductor device and structure with metal layers

      
Application Number 18604695
Grant Number 12051674
Status In Force
Filing Date 2024-03-14
First Publication Date 2024-07-04
Grant Date 2024-07-30
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian

Abstract

A 3D semiconductor device including: a first level with first transistors, single crystal layer overlaid by at least one first metal layer which includes interconnects between the first transistors forming first control circuits; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory cells which include second transistors, overlaid by a third level which includes second memory cells which include third transistors and are partially disposed over the control circuits, which control data written to second memory cells; and a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within less than 100 nm, and the average thickness of fourth metal layer is at least twice the average thickness of second metal layer; the fourth metal layer includes a global power distribution grid.

IPC Classes  ?

  • H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/66 - Types of semiconductor device
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

31.

3D memory semiconductor devices and structures with memory cells preliminary class

      
Application Number 18605401
Grant Number 12041792
Status In Force
Filing Date 2024-03-14
First Publication Date 2024-07-04
Grant Date 2024-07-16
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Lusky, Eli

Abstract

A 3D memory device, the device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel, where the memory cell includes at least one charge trap structure, and where the at least one memory transistor is self-aligned to an overlaying another the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the control level includes a plurality of temperature sensors, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.

IPC Classes  ?

  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • G11C 16/28 - Sensing or reading circuitsData output circuits using differential sensing or reference cells, e.g. dummy cells
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
  • G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits

32.

3D semiconductor devices and structures with metal layers

      
Application Number 18603526
Grant Number 12027518
Status In Force
Filing Date 2024-03-13
First Publication Date 2024-07-02
Grant Date 2024-07-02
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian

Abstract

A semiconductor device including: a first silicon level including a first single crystal silicon layer and first transistors; a first metal layer disposed over it; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including second transistors, disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 240 nm alignment error; where the fifth metal layer includes global power delivery; each of the third transistors comprises a metal gate; a via disposed through the second level and the third level, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.

IPC Classes  ?

  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • G03F 9/00 - Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/45 - Ohmic electrodes
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/732 - Vertical transistors
  • H01L 29/786 - Thin-film transistors
  • H01L 29/808 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a PN junction gate
  • H01L 29/812 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a Schottky gate
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 20/00 - Read-only memory [ROM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

33.

3D semiconductor device and structure with bonding and DRAM memory cells

      
Application Number 18424790
Grant Number 12068187
Status In Force
Filing Date 2024-01-27
First Publication Date 2024-06-27
Grant Date 2024-08-20
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak C.

Abstract

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layer; a second metal layer overlaying the first metal layer; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors and one capacitor, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 20/00 - Read-only memory [ROM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components

34.

3D SEMICONDUCTOR MEMORY DEVICES AND STRUCTURES

      
Application Number 18593727
Status Pending
Filing Date 2024-03-01
First Publication Date 2024-06-27
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo

Abstract

A 3D semiconductor device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a plurality of second transistors disposed atop the second metal layer; a third metal layer disposed atop the plurality of second transistors; and a memory array including word-lines and memory cells, where the memory array includes at least four memory mini arrays, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors, and where the memory control circuit includes at least one Look Up Table circuit (“LUT”).

IPC Classes  ?

  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

35.

METHOD FOR PRODUCING 3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH TRANSISTORS AND MEMORY CELLS

      
Application Number 18596623
Status Pending
Filing Date 2024-03-06
First Publication Date 2024-06-27
Owner Monolithic 3D Inc. (USA)
Inventor
  • Sekar, Deepak C.
  • Or-Bach, Zvi

Abstract

A method for producing a 3D semiconductor device including: providing a first level, including a single crystal layer; forming memory control circuits in and/or on the first level which include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the memory control circuits; performing a first etch step into the second level; forming at least one third level on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor including a metal gate, where each of the second memory cells include at least one third transistor; and performing bonding of the first level to the second level, where the bonding includes oxide to oxide bonding.

IPC Classes  ?

  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
  • H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/762 - Dielectric regions
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
  • H10N 70/20 - Multistable switching devices, e.g. memristors

36.

3D memory devices and structures with memory arrays and metal layers

      
Application Number 18431177
Grant Number 12041791
Status In Force
Filing Date 2024-02-02
First Publication Date 2024-06-20
Grant Date 2024-07-16
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Cronquist, Brian

Abstract

A semiconductor device including: a first level including a plurality of first memory arrays, a plurality of first transistors, and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays; and a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes (FFHs), where the second level includes second filled holes (SFHs), where the SFHs are aligned to the FFHs with a more than 1 nm but less than 40 nm alignment error, where the third level includes a plurality of Look-Up-Table circuits.

IPC Classes  ?

  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

37.

Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers

      
Application Number 18389577
Grant Number 12100611
Status In Force
Filing Date 2023-11-14
First Publication Date 2024-05-30
Grant Date 2024-09-24
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak C.

Abstract

A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one second level on top of or above the second metal layer; performing a lithography step on the second level; forming at least one third level on top of or above the second level; performing processing steps to form first memory cells within the second level and second memory cells within the third level, where the first memory cells include at least one second transistor, the second memory cells include at least one third transistor, second transistors comprise gate electrodes comprising metal, and then forming at least four independent memory arrays which include some first memory cells and/or second memory cells.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 20/00 - Read-only memory [ROM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components

38.

Multilevel semiconductor device and structure with image sensors and wafer bonding

      
Application Number 18432035
Grant Number 12080743
Status In Force
Filing Date 2024-02-04
First Publication Date 2024-05-30
Grant Date 2024-09-03
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Sekar, Deepak C.
  • Cronquist, Brian

Abstract

An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level including an oxide to oxide bond; a plurality of pixel control circuits; a third level disposed underneath the first level, where the third level includes a plurality of third transistors, where the plurality of third transistors each include a single crystal channel; and a plurality of memory circuits.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns

39.

3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH MEMORY

      
Application Number 18542757
Status Pending
Filing Date 2023-12-17
First Publication Date 2024-05-23
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak C.

Abstract

3D semiconductor device including: a first level including first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the first single-crystal transistors; a first metal layer disposed atop the first single-crystal transistors; a second metal layer disposed atop the first metal layer, a second level disposed atop the second metal layer includes second transistors and a memory array of first memory cells, a third level including second memory cells which include some third transistors, which themselves include a metal gate and is disposed above the second level; a third metal layer disposed above the third level; a fourth metal layer disposed above the third metal layer, a connective path from the third metal layer to the second metal layer with a thru second level via of a diameter less than 800 nm which also passes thru the memory array, different write voltages for different dies.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 20/00 - Read-only memory [ROM] devices
  • H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

40.

3D semiconductor device and structure with logic and memory

      
Application Number 18515255
Grant Number 11991884
Status In Force
Filing Date 2023-11-21
First Publication Date 2024-05-21
Grant Date 2024-05-21
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo

Abstract

A 3D semiconductor device including: a first level including a single crystal layer, a memory control circuit which includes a plurality of first transistors; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors which include a metal gate are disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; and a memory array including word-lines, the memory array includes at least four memory mini arrays, each including at least four rows by at least four columns of memory cells, where each of the memory cells includes at least one of the second transistors or at least one of the third transistors, the memory control circuit includes at least one digital to analog converter circuit.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
  • H01L 29/47 - Schottky barrier electrodes
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels

41.

Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers

      
Application Number 18542983
Grant Number 12033884
Status In Force
Filing Date 2023-12-18
First Publication Date 2024-05-02
Grant Date 2024-07-09
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak C.

Abstract

A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one (ALO) second level on top of or above the second metal layer; performing a lithography step on the second level; forming ALO third level on top of or above the ALO second level; performing processing steps to form first memory cells within the ALO second level and second memory cells within the ALO third level, first memory cells include ALO second transistor, second memory cells include ALO third transistor, first metal layer thickness is at least 50% greater than the second metal layer thickness, ALO first transistor controls power delivery to ALO second transistor; then dicing using a laser system.

IPC Classes  ?

  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 20/00 - Read-only memory [ROM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components

42.

3D semiconductor device and structure with metal layers and a connective path

      
Application Number 18534433
Grant Number 12080630
Status In Force
Filing Date 2023-12-08
First Publication Date 2024-04-18
Grant Date 2024-09-03
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Sekar, Deepak C.
  • Cronquist, Brian

Abstract

A 3D semiconductor device including: a first level including a plurality of first metal layers; a second level overlays the first level and includes at least one single crystal silicon layer, where the second level includes a plurality of transistors and a plurality of second metal layers, each transistor of the plurality of transistors includes a single crystal channel, where the plurality of second metal layers include interconnections between transistors of the plurality of transistors, where the second level is overlaid by a first isolation layer; a connective path from the plurality of transistors to the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, where each of at least one of the plurality of transistors includes a two sided gate, and where the single crystal silicon layer thickness is less than two microns.

IPC Classes  ?

  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
  • H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
  • H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/732 - Vertical transistors
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/808 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a PN junction gate
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

43.

3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH MEMORY

      
Application Number 18542761
Status Pending
Filing Date 2023-12-17
First Publication Date 2024-04-18
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak C.

Abstract

3D semiconductor device including: first level including first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the first single-crystal transistors; first metal layer disposed atop the first single-crystal transistors; a second metal layer disposed atop the first metal layer; a second level disposed atop the second metal layer includes second transistors and a memory array of first memory cells; third level including second memory cells which include some third transistors, which themselves include a metal gate and is disposed above the second level; a third metal layer disposed above the third level; a fourth metal layer disposed above the third metal layer; a connective path from the third metal layer to the second metal layer with a thru second level via of a diameter less than 800 nm which also passes thru the memory array, adjust memory cell write voltages based on temperature information.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 20/00 - Read-only memory [ROM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

44.

3D semiconductor device and structure with metal layers

      
Application Number 18395546
Grant Number 11961827
Status In Force
Filing Date 2023-12-23
First Publication Date 2024-04-16
Grant Date 2024-04-16
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian

Abstract

A semiconductor device, the device including: a first substrate; a first metal layer disposed over the first substrate; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors each include single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 200 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm, where the fourth metal layer provides a global power distribution, and where processing of the device includes use of a carrier wafer.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/66 - Types of semiconductor device
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

45.

3D memory semiconductor devices and structures with memory-line pillars

      
Application Number 18407096
Grant Number 11963373
Status In Force
Filing Date 2024-01-08
First Publication Date 2024-04-16
Grant Date 2024-04-16
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Lusky, Eli

Abstract

A 3D memory device, the device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; a plurality of memory-line pillars, where each memory-line pillar of the plurality of memory-line pillars is directly connected to a plurality of the source or the drain, where the plurality of memory-line pillars are vertically oriented, and where the at least one memory transistor is self-aligned to an overlaying another the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the memory controller circuit includes a row buffer, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.

IPC Classes  ?

  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

46.

3D semiconductor devices and structures with metal layers

      
Application Number 18128505
Grant Number 11984445
Status In Force
Filing Date 2023-03-30
First Publication Date 2024-04-11
Grant Date 2024-05-14
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian

Abstract

A semiconductor device, the semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 240 nm alignment error; where the fifth metal layer includes global power delivery; and a via disposed through the second level, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.

IPC Classes  ?

  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • G03F 9/00 - Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/45 - Ohmic electrodes
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/732 - Vertical transistors
  • H01L 29/786 - Thin-film transistors
  • H01L 29/808 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a PN junction gate
  • H01L 29/812 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a Schottky gate
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 20/00 - Read-only memory [ROM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

47.

3D semiconductor device, structure and methods with connectivity structures

      
Application Number 18389752
Grant Number 12021067
Status In Force
Filing Date 2023-12-19
First Publication Date 2024-04-11
Grant Date 2024-06-25
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Cronquist, Brian
  • Lusky, Eli

Abstract

A 3D device, the device including: at least one first level including logic circuits; at least one second level bonded to the first level, where the at least one second level includes a plurality of transistors; connectivity structures, where the connectivity structures include a plurality of transmission lines, where the plurality of transmission lines are designed to conduct radio frequencies (“RF”) signals, and where the bonded includes oxide to oxide bond regions and metal to metal bond regions; and a plurality of vias disposed through the at least one second level, where at least a majority of the plurality of vias have a diameter of less than 5 micrometers.

IPC Classes  ?

  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

48.

3D semiconductor device, structure and methods with connectivity structures

      
Application Number 18389769
Grant Number 12029050
Status In Force
Filing Date 2023-12-19
First Publication Date 2024-04-11
Grant Date 2024-07-02
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Cronquist, Brian
  • Lusky, Eli

Abstract

A 3D semiconductor device including: a first level including a single crystal layer, and a memory control circuit which includes at least one temperature sensor circuit and first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors—which may include a metal gate—disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; a memory array including word-lines and at least four memory mini arrays (each mini array includes at least four rows by four columns of memory cells), each memory cell includes at least one second transistor or at least one third transistor; and a connection path from fourth metal to third metal, the path includes a via disposed through the memory array.

IPC Classes  ?

  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

49.

3D semiconductor device and structure with single-crystal layers

      
Application Number 18527269
Grant Number 12136562
Status In Force
Filing Date 2023-12-02
First Publication Date 2024-04-04
Grant Date 2024-11-05
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak C.

Abstract

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; a first oxide layer disposed over the second metal layer; a second oxide layer disposed over the first oxide layer; and a second level including at least one array of memory cells and second transistors, where each of the memory cells includes at least one of the second transistors, where the second level overlays the first level, where at least one of the second transistors includes at least two independent gates, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.

IPC Classes  ?

  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 20/00 - Read-only memory [ROM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components

50.

3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH MEMORY

      
Application Number 18534475
Status Pending
Filing Date 2023-12-08
First Publication Date 2024-03-28
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak C.

Abstract

3D semiconductor device including: a first level including first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the first single-crystal transistors; a first metal layer disposed atop the first single-crystal transistors; a second metal layer disposed atop the first metal layer; a second level disposed atop the second metal layer includes second transistors and a memory array of first memory cells; a third level including second memory cells which include some third transistors, which themselves include a metal gate and is disposed above the second level; a third metal layer disposed above the third level; a fourth metal layer disposed above the third metal layer; a connective path from the third metal layer to the second metal layer with a thru second level via of a diameter less than 800 nm which also passes thru the memory array, memory control circuits for wear leveling.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 20/00 - Read-only memory [ROM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

51.

3D semiconductor devices and structures with electronic circuit units

      
Application Number 18389582
Grant Number 12021028
Status In Force
Filing Date 2023-11-14
First Publication Date 2024-03-21
Grant Date 2024-06-25
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Cronquist, Brian

Abstract

A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and is overlaying the first level; at least four electronic circuit units (ECUs); and a redundancy circuit, where each of the ECUs includes a first circuit which includes a portion of the first transistors, where each of the ECUs includes a second circuit, the second circuit including a portion of the second transistors, where each of the at least four ECUs includes a first vertical bus, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where each of the at least four ECUs includes at least one processor and at least one memory array, where the second level is bonded to the first level, and the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.

IPC Classes  ?

  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 69/00 - Erasable-and-programmable ROM [EPROM] devices not provided for in groups , e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

52.

3D SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE

      
Application Number 18385383
Status Pending
Filing Date 2023-10-31
First Publication Date 2024-03-14
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo

Abstract

A 3D semiconductor device, the device including: a first level including first single crystal transistors; and a second level including second single crystal transistors, where the first level is overlaid by the second level, where the first level includes a transferred layer and a bonded layer, where the second level is bonded to the first level, where the bonded second level includes oxide to oxide bonds, where the bonded second level includes metal to metal bonds, where the first level includes memory periphery circuits, where the second level includes a plurality of memory cells, and where the first level includes at least one Look up Table (“LUT”) circuit.

IPC Classes  ?

  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

53.

3D semiconductor device and structure with logic and memory

      
Application Number 18516958
Grant Number 12035531
Status In Force
Filing Date 2023-11-22
First Publication Date 2024-03-14
Grant Date 2024-07-09
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo

Abstract

A 3D semiconductor device including: a first level including a single crystal layer, a memory control circuit which includes a plurality of first transistors; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors which include a metal gate are disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; and a memory array including word-lines, the memory array includes at least four memory mini arrays, each including at least four rows by at least four columns of memory cells, where each of the memory cells includes at least one of the second transistors or at least one of the third transistors, the memory control circuit includes at least one Look Up Table circuit (“LUT”).

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
  • H01L 29/47 - Schottky barrier electrodes
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels

54.

3D memory devices and structures with metal layers

      
Application Number 18388840
Grant Number 11930648
Status In Force
Filing Date 2023-11-12
First Publication Date 2024-03-12
Grant Date 2024-03-12
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Cronquist, Brian

Abstract

A semiconductor device including: a first level including first memory arrays, a plurality of first transistors, and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes second memory arrays; a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, where the second filled holes are aligned to the first filled holes with a more than 1 nm but less than 40 nm alignment error, and where the third level includes decoder circuits.

IPC Classes  ?

  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

55.

3D semiconductor device and structure with metal layers

      
Application Number 18384883
Grant Number 11990462
Status In Force
Filing Date 2023-10-29
First Publication Date 2024-03-07
Grant Date 2024-05-21
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian

Abstract

A semiconductor device including: a first silicon layer including a first single crystal silicon layer; first transistors with a single crystal channel and overlaid by a first metal layer; overlaid by a second metal layer; overlaid by a third metal layer; a second level with second transistors and including a metal gate, and then disposed over the third metal layer; the second level is overlaid by a third level with third transistors; and then overlaid by a fourth metal layer; fourth overlaid by a fifth metal layer; parts of the second transistors are made with Atomic Layer Deposition (“ALD”); the fifth metal layer average thickness is greater than the third metal layer average thickness by at least 50%; at least one element within at least one of the second transistors has been processed independently of the third transistors.

IPC Classes  ?

  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

56.

Multilevel semiconductor device and structure with oxide bonding

      
Application Number 18388848
Grant Number 11984438
Status In Force
Filing Date 2023-11-12
First Publication Date 2024-03-07
Grant Date 2024-05-14
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Sekar, Deepak C.
  • Cronquist, Brian

Abstract

A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including at least one electromagnetic wave receiver, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the integrated circuits include at least one memory circuit, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

IPC Classes  ?

  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen

57.

3D semiconductor device and structure with metal layers and memory cells

      
Application Number 18388852
Grant Number 11935949
Status In Force
Filing Date 2023-11-12
First Publication Date 2024-03-07
Grant Date 2024-03-19
Owner Monolithic 3D Inc. (USA)
Inventor Or-Bach, Zvi

Abstract

3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; second metal layer overlaying first metal layer; a second level including second transistors, first memory cells (each including at least one second transistor) and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells; third metal layer disposed above third level; fourth metal layer includes global power distribution grid, has a thickness at least twice the second metal layer, disposed above third metal layer; fourth level includes single-crystal silicon, atop fourth metal layer.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • G11C 11/404 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
  • G11C 11/4097 - Bit-line organisation, e.g. bit-line layout, folded bit lines
  • G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
  • G11C 16/02 - Erasable programmable read-only memories electrically programmable
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
  • H10B 69/00 - Erasable-and-programmable ROM [EPROM] devices not provided for in groups , e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

58.

3D memory semiconductor devices and structures with bit-line pillars

      
Application Number 18384304
Grant Number 11910622
Status In Force
Filing Date 2023-10-26
First Publication Date 2024-02-20
Grant Date 2024-02-20
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Lusky, Eli

Abstract

A 3D memory device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of memory-line pillars, where each memory-line pillar of the plurality of memory-line pillars is directly connected to a plurality of the source or the drain, where the plurality of memory-line pillars are vertically oriented, where the channel is horizontally-oriented and a plurality are connected to a body pillar, where the body pillar is at least temporary connected to a negative bias, the at least one memory transistor is self-aligned to an overlaying another memory transistor, both being processed following a same lithography step; a control level including a memory controller circuit and is hybrid bonded to the first structure.

IPC Classes  ?

  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

59.

3D semiconductor device and structure with bonding

      
Application Number 18382468
Grant Number 11923230
Status In Force
Filing Date 2023-10-20
First Publication Date 2024-02-15
Grant Date 2024-03-05
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak C.

Abstract

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 20/00 - Read-only memory [ROM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components

60.

Multilevel semiconductor device and structure with image sensors and wafer bonding

      
Application Number 18382463
Grant Number 11929372
Status In Force
Filing Date 2023-10-20
First Publication Date 2024-02-08
Grant Date 2024-03-12
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Sekar, Deepak C.
  • Cronquist, Brian

Abstract

An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level with an oxide to oxide bond; a plurality of pixel control circuits; a plurality of memory circuits; and a third level disposed underneath the first level, where the third level includes a plurality of third transistors.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

61.

Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers

      
Application Number 18241990
Grant Number 11854857
Status In Force
Filing Date 2023-09-04
First Publication Date 2023-12-26
Grant Date 2023-12-26
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak C.

Abstract

A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one second level on top of or above the second metal layer; performing a lithography step on the second level; forming at least one third level on top of or above the second level; performing processing steps to form first memory cells within the second level and second memory cells within the third level, where the first memory cells include at least one second transistor, the second memory cells include at least one third transistor, first transistors control power delivery to some second transistors; and then forming at least four independent memory arrays which include some first memory cells and/or second memory cells.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 20/00 - Read-only memory [ROM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components

62.

3D memory devices and structures with control circuits

      
Application Number 18239117
Grant Number 11869591
Status In Force
Filing Date 2023-08-28
First Publication Date 2023-12-14
Grant Date 2024-01-09
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Cronquist, Brian

Abstract

A semiconductor device, the device including: a first level including a plurality of first memory arrays, where the first level includes a plurality of first transistors and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays; a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, and where the third level includes a plurality of decoder circuits.

IPC Classes  ?

  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 11/408 - Address circuits
  • G11C 16/08 - Address circuitsDecodersWord-line control circuits
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout

63.

3D memory semiconductor devices and structures with bit-line pillars

      
Application Number 18231235
Grant Number 11854646
Status In Force
Filing Date 2023-08-07
First Publication Date 2023-12-07
Grant Date 2023-12-26
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Lusky, Eli

Abstract

A 3D memory device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the plurality of bit-line pillars are vertically oriented, where the channel is horizontally oriented, where each of the at least one memory transistor is directly connected to at least one of the plurality of bit-line pillars, where the plurality of memory cells include a partially or fully metalized source structure and/or a partially or fully metalized drain structure, where the metalized source includes two metal structures, and where the two metal structures include a tungsten structure.

IPC Classes  ?

  • G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout

64.

3D semiconductor devices and structures with transistors

      
Application Number 18234368
Grant Number 11956976
Status In Force
Filing Date 2023-08-15
First Publication Date 2023-12-07
Grant Date 2024-04-09
Owner Monolithic 3D Inc. (USA)
Inventor
  • Sekar, Deepak C.
  • Or-Bach, Zvi

Abstract

A semiconductor device including: a plurality of transistors, where at least one of the transistors includes a first single crystal source, channel, and drain, where at least one of the transistors includes a second single crystal source, channel, and drain, where the second single crystal source, channel, and drain is disposed above the first single crystal source, channel, and drain, where at least one of the transistors includes a third single crystal source, channel, and drain, where the third single crystal source, channel, and drain is disposed above the second single crystal source, channel, and drain, where at least one of the transistors includes a fourth single crystal source, channel, and drain, where the fourth single crystal source, channel, and drain is disposed above the third single crystal source, channel, and drain, and where the fourth drain is aligned to the first drain with less than 40 nm misalignment.

IPC Classes  ?

  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
  • H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/762 - Dielectric regions
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
  • H10N 70/20 - Multistable switching devices, e.g. memristors

65.

3D semiconductor device and structure with metal layers

      
Application Number 18234784
Grant Number 11923374
Status In Force
Filing Date 2023-08-16
First Publication Date 2023-12-07
Grant Date 2024-03-05
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian

Abstract

A semiconductor device, the device including: a first silicon layer including a first single crystal silicon layer; a plurality of first transistors each including a single crystal channel; a first metal layer disposed over the plurality of first transistors; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer; a via disposed through the second level, where at least one of the plurality of second transistors includes a metal gate, where an average thickness of the fifth metal layer is greater than an average thickness of the third metal layer by at least 50%; and at least one Electrostatic discharge (“ESD”) structure.

IPC Classes  ?

  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

66.

3D semiconductor device and structure with metal layers

      
Application Number 18236325
Grant Number 11916045
Status In Force
Filing Date 2023-08-21
First Publication Date 2023-12-07
Grant Date 2024-02-27
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian

Abstract

A semiconductor device, the device including: a first substrate; a first metal layer disposed over the first substrate; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors each include single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 200 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm, where the fourth metal layer provides a global power distribution, and where the device includes at least one power supply circuit.

IPC Classes  ?

  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 29/66 - Types of semiconductor device
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

67.

3D SEMICONDUCTOR DEVICE AND STRUCTURE INCLUDING POWER DISTRIBUTION GRIDS

      
Application Number 18228907
Status Pending
Filing Date 2023-08-01
First Publication Date 2023-11-30
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak

Abstract

A 3D device includes a first level including a first single crystal layer with control circuitry, where the control circuitry includes first single crystal transistors; a first metal layer atop first single crystal layer; a second metal layer atop the first metal layer; a third metal layer atop the second metal layer; second level (includes a plurality of second transistors, including metal gate) atop the third metal layer; a fourth metal layer above the one second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid including the fifth metal layer; a local power distribution grid, the thickness of the fifth metal layer is at least 50% greater than the thickness of the second metal layer, a layer deposited by ALD.

IPC Classes  ?

  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections

68.

3D semiconductor device and structure with bonding

      
Application Number 18228675
Grant Number 11830757
Status In Force
Filing Date 2023-08-01
First Publication Date 2023-11-28
Grant Date 2023-11-28
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak C.

Abstract

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the at least one of the second transistors transistor channel includes non-silicon atoms, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 20/00 - Read-only memory [ROM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components

69.

3D semiconductor device and structure with metal layers and memory cells

      
Application Number 18227183
Grant Number 11869965
Status In Force
Filing Date 2023-07-27
First Publication Date 2023-11-23
Grant Date 2024-01-09
Owner Monolithic 3D Inc. (USA)
Inventor Or-Bach, Zvi

Abstract

A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; a second metal layer overlaying first metal layer; a second level including second transistors, first memory cells (each including at least one second transistor) and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells; third metal layer disposed above third level; fourth metal layer includes a global power distribution grid, has a thickness at least twice the second metal layer, and is disposed above third metal layer.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • G11C 16/02 - Erasable programmable read-only memories electrically programmable
  • G11C 11/404 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
  • G11C 11/4097 - Bit-line organisation, e.g. bit-line layout, folded bit lines
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 69/00 - Erasable-and-programmable ROM [EPROM] devices not provided for in groups , e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
  • G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

70.

3D semiconductor device and structure with metal layers and a connective path

      
Application Number 18215631
Grant Number 11881443
Status In Force
Filing Date 2023-06-28
First Publication Date 2023-10-26
Grant Date 2024-01-23
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Sekar, Deepak C.
  • Cronquist, Brian

Abstract

A 3D semiconductor device, the device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each transistor of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the transistors of the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path from the plurality of transistors to the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where at least one of the via includes a contact to at least one of the transistors.

IPC Classes  ?

  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/66 - Types of semiconductor device
  • H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
  • H01L 29/732 - Vertical transistors
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/808 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a PN junction gate
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
  • H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

71.

3D semiconductor device and structure with single-crystal layers

      
Application Number 18215062
Grant Number 11876011
Status In Force
Filing Date 2023-06-27
First Publication Date 2023-10-26
Grant Date 2024-01-16
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak C.

Abstract

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where at least one of the second transistors includes a raised source or raised drain transistor structure, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.

IPC Classes  ?

  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 20/00 - Read-only memory [ROM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components

72.

3D semiconductor device and structure with metal layers

      
Application Number 18214524
Grant Number 11967583
Status In Force
Filing Date 2023-06-27
First Publication Date 2023-10-19
Grant Date 2024-04-23
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian

Abstract

A semiconductor device, the device comprising: a first substrate; a first metal layer disposed over said substrate; a second metal layer disposed over said first metal layer; a first level comprising a plurality of transistors, said first level disposed over said second metal layer, wherein said plurality of transistors comprise single crystal silicon; a third metal layer disposed over said first level; a fourth metal layer disposed over said third metal layer, wherein said fourth metal layer is aligned to said first metal layer with a less than 200 nm alignment error; and a via disposed through said first level, wherein said via has a diameter of less than 450 nm, wherein said fourth metal layer provides a global power distribution, and wherein said via is directly connected to at least one of said plurality of transistors.

IPC Classes  ?

  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/66 - Types of semiconductor device
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

73.

3D DRAM memory devices and structures with control circuits

      
Application Number 18206040
Grant Number 11812620
Status In Force
Filing Date 2023-06-05
First Publication Date 2023-10-12
Grant Date 2023-11-07
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Cronquist, Brian

Abstract

A semiconductor device, the device including: a first level including a plurality of first memory arrays, where the first level includes a plurality of first transistors and a plurality of metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays, where the first level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the plurality of first memory arrays includes a plurality of first DRAM (Dynamic Random Access Memory) cells, and where the plurality of second memory arrays includes a plurality of second DRAM (Dynamic Random Access Memory) cells.

IPC Classes  ?

  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

74.

Automation methods for 3D integrated circuits and devices

      
Application Number 18208647
Grant Number 12093628
Status In Force
Filing Date 2023-06-12
First Publication Date 2023-10-12
Grant Date 2024-09-17
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Wurman, Zeev

Abstract

A method of designing a 3D Integrated Circuit including: partitioning at least one design into at least two levels, a first level and a second level; levels connection pads between the first level and the second level; providing placement data of the second level; performing a placement of the first level using a placer executed by a computer, where the placement of the first level is based on the placement of the levels connection pads, where the placer is part of a Computer Aided Design (CAD) tool, where the first level includes first routing layers; performing a routing of the first level by routing layers using a router executed by a computer, where the router is a part of the CAD tool or a part of another CAD tool, where at least one metal routing layer is in-between the first level first transistors and the second level second transistors.

IPC Classes  ?

75.

3D semiconductor devices and structures with electronic circuit units

      
Application Number 18104299
Grant Number 11800725
Status In Force
Filing Date 2023-02-01
First Publication Date 2023-10-12
Grant Date 2023-10-24
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Cronquist, Brian

Abstract

A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and overlaying the first level; and at least eight electronic circuit units (ECUs), where each of the at least eight ECUs includes a first circuit, the first circuit including a portion of the first transistors, where each of the at least eight ECUs includes a second circuit including a portion of the second transistors, where each of the at least eight ECUs includes a first vertical bus, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where each of the at least eight ECUs includes at least one processor and at least one memory array, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.

IPC Classes  ?

  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

76.

Efficient electrical passenger car with motor control

      
Application Number 18208259
Grant Number 11866028
Status In Force
Filing Date 2023-06-10
First Publication Date 2023-10-05
Grant Date 2024-01-09
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian

Abstract

An electrical passenger car, the electrical passenger car including: at least two electrically driven motors; motor control electronics, where the motor control electronics are connected to the at least two electrically driven motors; wheels, where the wheels are connected to the at least two electrically driven motors; and sensors, where the sensors are connected to at least the motor control electronics, where the wheels include a first wheel and a second wheel, where the second wheel has a radius at least 7% greater than a radius of the first wheel, where the motor control electronics control the at least two electrically driven motors to provide a greater torque to the first wheel than to the second wheel, and where the electrical passenger car is designed to operate efficiently on a paved road.

IPC Classes  ?

  • B60W 10/08 - Conjoint control of vehicle sub-units of different type or different function including control of propulsion units including control of electric propulsion units, e.g. motors or generators
  • B60W 10/20 - Conjoint control of vehicle sub-units of different type or different function including control of steering systems
  • B60W 10/04 - Conjoint control of vehicle sub-units of different type or different function including control of propulsion units

77.

Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers

      
Application Number 18200387
Grant Number 11804396
Status In Force
Filing Date 2023-05-22
First Publication Date 2023-09-28
Grant Date 2023-10-31
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak C.

Abstract

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one second level above the second metal layer; performing a first lithography step on the second level; forming a third level on top of the second level; performing processing steps to form first memory cells within the second level and form second memory cells within the third level, where the first memory cells include at least one second transistor, and the second memory cells include at least one third transistor; and then at performing at least one deposition step which deposits gate electrodes for both the second and the third transistors, and forming at least four independent memory arrays.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 20/00 - Read-only memory [ROM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components

78.

Multilevel semiconductor device and structure with image sensors and wafer bonding

      
Application Number 18141975
Grant Number 11869915
Status In Force
Filing Date 2023-05-01
First Publication Date 2023-08-31
Grant Date 2024-01-09
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Sekar, Deepak C.
  • Cronquist, Brian

Abstract

An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level, where the bonded includes an oxide to oxide bond; and a plurality of pixel control circuits, where each of the plurality of image sensors is directly connected to at least one of the plurality of pixel control circuits, and where the integrated device includes a plurality of memory circuits.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 27/148 - Charge coupled imagers
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns

79.

3D semiconductor device and structure with metal layers

      
Application Number 18141415
Grant Number 11784169
Status In Force
Filing Date 2023-04-29
First Publication Date 2023-08-24
Grant Date 2023-10-10
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian

Abstract

A semiconductor device, the device including: a first substrate; a first metal layer disposed over the substrate; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors include a second single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 100 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm, where the fourth metal layer provides a global power distribution, and where a typical thickness of the fourth metal layer is at least 50% greater than a typical thickness of the third metal.

IPC Classes  ?

  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 29/66 - Types of semiconductor device
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

80.

3D semiconductor device and structure including power distribution grids

      
Application Number 18138110
Grant Number 11756822
Status In Force
Filing Date 2023-04-23
First Publication Date 2023-08-17
Grant Date 2023-09-12
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak

Abstract

A 3D device includes a first level including a first single crystal layer with control circuitry, where the control circuitry includes first single crystal transistors; a first metal layer atop first single crystal layer; a second metal layer atop the first metal layer; a third metal layer atop the second metal layer; second level (includes a plurality of second transistors) atop the third metal layer; a fourth metal layer disposed above the one second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid, which includes the fifth metal layer; a local power distribution grid including at least one second transistor, the thickness of the fifth metal layer is at least 50% greater than the thickness of the second metal layer.

IPC Classes  ?

  • H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
  • H01L 23/498 - Leads on insulating substrates
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections

81.

3D semiconductor device and structure with metal layers and a connective path

      
Application Number 18136336
Grant Number 11735501
Status In Force
Filing Date 2023-04-19
First Publication Date 2023-08-10
Grant Date 2023-08-22
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Sekar, Deepak C.
  • Cronquist, Brian

Abstract

A 3D semiconductor device, the device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each transistor of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the transistors of the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path between the plurality of transistors and the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where at least one of the transistors includes a four sided gate.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/732 - Vertical transistors
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/808 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a PN junction gate
  • H01L 29/66 - Types of semiconductor device
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
  • H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
  • H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

82.

Multilevel semiconductor device and structure with oxide bonding

      
Application Number 18136335
Grant Number 11855100
Status In Force
Filing Date 2023-04-18
First Publication Date 2023-08-10
Grant Date 2023-12-26
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Sekar, Deepak C.
  • Cronquist, Brian

Abstract

A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the integrated circuits include at least one memory circuit, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

IPC Classes  ?

  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 21/762 - Dielectric regions
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
  • H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
  • G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof

83.

3D semiconductor device and structure with oxide bonding

      
Application Number 18125053
Grant Number 11757030
Status In Force
Filing Date 2023-03-22
First Publication Date 2023-07-13
Grant Date 2023-09-12
Owner Monolithic 3D Inc. (USA)
Inventor Or-Bach, Zvi

Abstract

A semiconductor device, the device including: a first silicon layer including first single crystal silicon; an isolation layer disposed over the first silicon layer; a first metal layer disposed over the isolation layer; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the isolation layer includes an oxide to oxide bond surface, where the plurality of transistors include a second single crystal silicon region; and a third metal layer disposed over the first level, where a typical first thickness of the third metal layer is at least 50% greater than a typical second thickness of the second metal layer.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • G11C 16/02 - Erasable programmable read-only memories electrically programmable
  • G11C 11/404 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
  • G11C 11/4097 - Bit-line organisation, e.g. bit-line layout, folded bit lines
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 69/00 - Erasable-and-programmable ROM [EPROM] devices not provided for in groups , e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

84.

Automation methods for 3D integrated circuits and devices

      
Application Number 18111567
Grant Number 11720736
Status In Force
Filing Date 2023-02-18
First Publication Date 2023-06-29
Grant Date 2023-08-08
Owner Monolithic 3D Inc (USA)
Inventor
  • Or-Bach, Zvi
  • Wurman, Zeev

Abstract

A method of designing a 3D Integrated Circuit, the method including: partitioning at least one design into at least two levels, a first level and a second level; providing placement data of the second level; performing a placement of the first level using a placer executed by a computer, where the placement of the first level is based on the placement data, where the placer is part of a Computer Aided Design (CAD) tool, and where the first level includes first routing layers; and performing a routing of the first level by routing layers using a router executed by a computer, where the router is a part of the Computer Aided Design (CAD) tool or a part of another CAD tool.

IPC Classes  ?

85.

3D semiconductor device and structure

      
Application Number 18111300
Grant Number 11791222
Status In Force
Filing Date 2023-02-17
First Publication Date 2023-06-29
Grant Date 2023-10-17
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian

Abstract

A semiconductor device, the device including: a first silicon layer including a first single crystal silicon layer; a first metal layer disposed over the first single crystal silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer; and a via disposed through the second level, where the via has a diameter of less than 450 nm, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the third metal layer by at least 50%.

IPC Classes  ?

  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 21/762 - Dielectric regions
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

86.

3D micro display device and structure

      
Application Number 18110362
Grant Number 12094892
Status In Force
Filing Date 2023-02-15
First Publication Date 2023-06-22
Grant Date 2024-09-17
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Sekar, Deepak C.

Abstract

A 3D micro display, the 3D micro display including: a first level including a first single crystal layer, the first single crystal layer includes a plurality of LED driving circuits; a second level including a first plurality of light emitting diodes (LEDs), where the second level is disposed on top of the first level, where the second level includes at least ten individual first LED pixels; and a bonding structure, where the second level includes a plurality of bond pads, where the bonding structure includes oxide to oxide bonding.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
  • H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
  • H01L 33/16 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
  • H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
  • H10K 19/00 - Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group
  • H10K 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one organic radiation-sensitive element covered by group
  • H10K 59/00 - Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group

87.

3D semiconductor device and structure with metal layers and a connective path

      
Application Number 18109254
Grant Number 11694944
Status In Force
Filing Date 2023-02-13
First Publication Date 2023-06-22
Grant Date 2023-07-04
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Sekar, Deepak C.
  • Cronquist, Brian

Abstract

A 3D semiconductor device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each transistor of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the transistors of the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path between the plurality of transistors and the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where the via includes contact with at least one of the plurality of transistors.

IPC Classes  ?

  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/732 - Vertical transistors
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/808 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a PN junction gate
  • H01L 29/66 - Types of semiconductor device
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
  • H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
  • H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

88.

3D memory devices and structures with control circuits

      
Application Number 18105856
Grant Number 11711928
Status In Force
Filing Date 2023-02-05
First Publication Date 2023-06-15
Grant Date 2023-07-25
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Cronquist, Brian

Abstract

A semiconductor device, the device including: a first level including control circuits, where the control circuits include a plurality of first transistors and a plurality of metal layers; and a memory level disposed on top of the first level, where the memory level includes an array of memory cells, where each of the memory cells includes at least one second transistor, where the control circuits control access to the array of memory cells, where the first level is bonded to the memory level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, and where at least a portion of the array of memory cells is disposed directly above at least one of the plurality of metal to metal bonding regions.

IPC Classes  ?

  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

89.

Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers

      
Application Number 18106757
Grant Number 11862503
Status In Force
Filing Date 2023-02-07
First Publication Date 2023-06-15
Grant Date 2024-01-02
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak C.

Abstract

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming a first metal layer on top of first level; forming a second metal layer on top of the first metal layer; forming at least one second level above the second metal layer; performing a first lithography step on the second level; forming a third level on top of the second level; performing a second lithography step on the third level; perform processing steps to form first memory cells within the second level and second memory cells within the third level, where first memory cells include at least one second transistor, and the second memory cells include at least one third transistor; and deposit a gate electrode for the second and the third transistors simultaneously.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 20/00 - Read-only memory [ROM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components

90.

3D semiconductor devices and structures

      
Application Number 18105041
Grant Number 11793005
Status In Force
Filing Date 2023-02-02
First Publication Date 2023-06-15
Grant Date 2023-10-17
Owner Monolithic 3D Inc. (USA)
Inventor
  • Sekar, Deepak C.
  • Or-Bach, Zvi

Abstract

A semiconductor device, the device comprising: a plurality of transistors, wherein at least one of said plurality of transistors comprises a first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a second single crystal source, channel, and drain, wherein said second single crystal source, channel, and drain is disposed above said first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a third single crystal source, channel, and drain, wherein said third single crystal source, channel, and drain is disposed above said second single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a fourth single crystal source, channel, and drain, and wherein said third single crystal channel is self-aligned to said fourth single crystal channel being processed following the same lithography step.

IPC Classes  ?

  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
  • H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/762 - Dielectric regions
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H10N 70/20 - Multistable switching devices, e.g. memristors
  • H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching

91.

Multilevel semiconductor device and structure with image sensors and wafer bonding

      
Application Number 18105881
Grant Number 11855114
Status In Force
Filing Date 2023-02-06
First Publication Date 2023-06-15
Grant Date 2023-12-26
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Sekar, Deepak C.
  • Cronquist, Brian

Abstract

An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of semiconductor devices; a third level overlaying the second level, where the third level includes a plurality of image sensors, where the first level includes a plurality of landing pads, where the second level is bonded to the first level, where the bonded includes an oxide to oxide bond; and an isolation layer disposed between the second mono-crystal layer and the third level.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
  • H01L 23/00 - Details of semiconductor or other solid state devices

92.

3D semiconductor device and structure with logic circuits and memory cells

      
Application Number 18106484
Grant Number 12183699
Status In Force
Filing Date 2023-02-07
First Publication Date 2023-06-15
Grant Date 2024-12-31
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo
  • Cronquist, Brian

Abstract

A 3D semiconductor device comprising: a first level; and a second level, wherein said first level comprises single crystal silicon and a plurality of logic circuits, wherein said plurality of logic circuits each comprise first transistors, wherein said second level is disposed above said first level and comprises a plurality of arrays of memory cells, said second level comprises a plurality of second transistors, wherein each of said memory cells comprises at least one of said second transistors, wherein said first level is bonded to said second level, wherein said bonded comprises regions of oxide to oxide bonds, wherein said bonded comprises regions of metal to metal bonds; and a thermal isolation layer disposed between said first level and said second level, wherein said thermal isolation layer provides a greater than 20° C. differential temperature between said first level and said second level during nominal operation of said device.

IPC Classes  ?

  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
  • H01L 23/66 - High-frequency adaptations
  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

93.

3D semiconductor device and structure with metal layers

      
Application Number 18105826
Grant Number 11676945
Status In Force
Filing Date 2023-02-04
First Publication Date 2023-06-13
Grant Date 2023-06-13
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian

Abstract

A semiconductor device, the device including: a first silicon layer including a first single crystal silicon; a first metal layer disposed over the first single crystal silicon layer; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors include a second single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; and a via disposed through the first level, where the fourth metal layer provides a global power distribution, and where a typical thickness of the fourth metal layer is at least 50% greater than a typical thickness of the third metal.

IPC Classes  ?

  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 29/66 - Types of semiconductor device
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

94.

3D semiconductor device and structure with bonding

      
Application Number 18092337
Grant Number 11784082
Status In Force
Filing Date 2023-01-01
First Publication Date 2023-06-01
Grant Date 2023-10-10
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak C.

Abstract

A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; and a second level comprising a second single crystal layer, said second level comprising second transistors, wherein said second level overlays said first level, wherein at least one of said first transistors controls power delivery for at least one of said second transistor, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 20/00 - Read-only memory [ROM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components

95.

Multilevel semiconductor device and structure with oxide bonding

      
Application Number 18102710
Grant Number 11694922
Status In Force
Filing Date 2023-01-28
First Publication Date 2023-06-01
Grant Date 2023-07-04
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Sekar, Deepak C.
  • Cronquist, Brian

Abstract

A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the integrated circuits include at least one processor, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

IPC Classes  ?

  • B23K 26/36 - Removing material
  • H01L 21/762 - Dielectric regions
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
  • G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
  • H01L 29/66 - Types of semiconductor device
  • H01L 23/00 - Details of semiconductor or other solid state devices

96.

3D semiconductor device and structure with memory

      
Application Number 18092727
Grant Number 11677021
Status In Force
Filing Date 2023-01-03
First Publication Date 2023-05-18
Grant Date 2023-06-13
Owner Monolithic 3D Inc. (USA)
Inventor Or-Bach, Zvi

Abstract

A semiconductor device, the device comprising: a first silicon layer comprising first single crystal silicon; an isolation layer disposed over said first silicon layer; a first metal layer disposed over said isolation layer; a second metal layer disposed over said first metal layer; a first level comprising a plurality of transistors, said first level disposed over said second metal layer, wherein said isolation layer comprises an oxide to oxide bond surface, wherein said plurality of transistors comprise a second single crystal silicon region; and a plurality of capacitors, wherein said plurality of capacitors comprise functioning as a decoupling capacitor to mitigate power supply noise.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • G11C 16/02 - Erasable programmable read-only memories electrically programmable
  • G11C 11/404 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
  • G11C 11/4097 - Bit-line organisation, e.g. bit-line layout, folded bit lines
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 69/00 - Erasable-and-programmable ROM [EPROM] devices not provided for in groups , e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
  • G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

97.

3D semiconductor device and structure with logic and memory

      
Application Number 17665560
Grant Number 12016181
Status In Force
Filing Date 2022-02-06
First Publication Date 2023-05-11
Grant Date 2024-06-18
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Han, Jin-Woo

Abstract

A 3D device, the device including: a first level including logic circuits; a second level including a plurality of memory circuits, where the first level is bonded to the second level, where the bonded includes oxide to oxide bonds, and where the first level includes at least one voltage regulator circuit.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
  • H01L 29/47 - Schottky barrier electrodes
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels

98.

3D semiconductor device and structure including power distribution grids

      
Application Number 18092253
Grant Number 11670536
Status In Force
Filing Date 2022-12-31
First Publication Date 2023-05-11
Grant Date 2023-06-06
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak

Abstract

A 3D device includes a first level including a first single crystal layer with control circuitry, where the control circuitry includes first single crystal transistors; a first metal layer atop first single crystal layer; a second metal layer atop the first metal layer; a third metal layer atop the second metal layer; second level (includes a plurality of second transistors) atop the third metal layer; a fourth metal layer disposed above the one second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid, which includes the fifth metal layer; a local power distribution grid, which includes the second metal layer, the thickness of the fifth metal layer is at least 50% greater than the thickness of the second metal layer.

IPC Classes  ?

  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections

99.

3D semiconductor device and structure with single-crystal layers

      
Application Number 18088602
Grant Number 11735462
Status In Force
Filing Date 2022-12-25
First Publication Date 2023-04-27
Grant Date 2023-08-22
Owner Monolithic 3D Inc. (USA)
Inventor
  • Or-Bach, Zvi
  • Cronquist, Brian
  • Sekar, Deepak C.

Abstract

A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; and a second level comprising a second single crystal layer, said second level comprising second transistors, wherein said second level overlays said first level, wherein at least one of said second transistors comprises a gate all around structure, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds.

IPC Classes  ?

  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
  • G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
  • H10B 10/00 - Static random access memory [SRAM] devices
  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H10B 20/00 - Read-only memory [ROM] devices
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components

100.

Automation methods for 3D integrated circuits and devices

      
Application Number 18090134
Grant Number 11615228
Status In Force
Filing Date 2022-12-28
First Publication Date 2023-03-28
Grant Date 2023-03-28
Owner MONOLITHIC 3D INC. (USA)
Inventor
  • Or-Bach, Zvi
  • Wurman, Zeev

Abstract

A method of designing a 3D Integrated Circuit, the method including: partitioning at least one design into at least two levels, a first level and a second level; providing connections placement data of the second level, where the connections include planned connections between the first level and the second level; performing a placement of the first level using a placer executed by a computer, where the placement of the first level is based on the connections placement data, where the placer is part of a Computer Aided Design (CAD) tool, and where the first level includes first routing layers; and performing a routing of the first level by routing layers using a router executed by a computer, where the router is a part of the Computer Aided Design (CAD) tool or a part of another CAD tool.

IPC Classes  ?

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