A computing device, including: a first level; a second level, where the first level includes a plurality of interconnect lines, where the second level is disposed above the first level and includes a plurality of processor arrays; and a memory structure disposed above the first level, where the memory structure includes a control level, a first array of memory cells overlaying the control level, and a second array of memory cells overlaying the first array of memory cells, where at least one of the plurality of interconnect lines connect over a distance of at least 40 mm, and where the plurality of processor arrays include at least one Graphic Processor Unit (“GPU”).
A semiconductor device, the device including: a first silicon layer including a first single crystal silicon; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a second level including a second single crystal silicon and a plurality of transistors, the second level is disposed over the second metal layer; a third metal layer disposed over the second level; a fourth metal layer disposed over the third metal layer; a via disposed through the second level, where the via has a diameter of less than 450 nm, where the second level thickness is less than four microns, and where the via includes contact to at least one of the plurality of transistors.
A semiconductor device, the device including: a first silicon layer including first single crystal silicon; an isolation layer disposed over the first silicon layer; a first metal layer disposed over the isolation layer; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the isolation layer includes an oxide to oxide bond surface, where the plurality of transistors include a second single crystal silicon region; and a third metal layer disposed over the first level, where a typical first thickness of the third metal layer is at least 50% greater than a typical second thickness of the second metal layer, and where the first level includes an array of memory cells.
G11C 11/404 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
G11C 11/4097 - Bit-line organisation, e.g. bit-line layout, folded bit lines
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 69/00 - Erasable-and-programmable ROM [EPROM] devices not provided for in groups , e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
4.
METHOD TO PRODUCE A 3D MULTILAYER SEMICONDUCTOR DEVICE AND STRUCTURE
Methods of making a 3D multilayer semiconductor device including: providing a first level with a first single crystal silicon layer (1stSCSL) and a second level including a 2ndSCSL; performing epitaxial growth of a first SiGe-layer on top of the 2ndSCSL; performing epitaxial growth of a 3rdSCSL on top of the first SiGe-layer, where the 3rdSCSL has an average thickness of less than 2,000 nm; forming first transistors each including a single crystal channel, where the forming of first transistors includes performing an epitaxial growth of a second SiGe-layer on top of the 3rdSCSL; forming metal layers interconnecting the first transistors; and then performing a bonding of the second level onto the first level, where performing the bonding includes making oxide-to-oxide bond zones; and performing removal of a majority of the second SCSL, where at least one of the first transistors include at least one gate-all-around channel.
A 3D semiconductor device, the device including: a first level including a first single crystal silicon layer; a second level including single crystal transistors, where the first level is overlaid by the second level; a transferred layer and a bonded layer, where the second level is bonded to the first level, where the second level includes a thickness less than 2 microns, and where the second level includes a plurality of memory cells; and a digital-to-analog converter, where the second level includes at least four memory arrays, and where each of the at least four memory arrays is independently controlled.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
6.
3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH FUNCTIONAL UNITS AND VERTICAL CONNECTIVITY STRUCTURES
A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and overlaying the first level; power decoupling capacitors; at least four functional units (FCUs); where each FCU includes a first circuit which includes a portion of the first transistors, and includes a second circuit which includes a portion of the second transistors, and includes a vertical connectivity structure (VCS), the VCS includes a plurality of pillars which provides electrical control connection between the first circuit and the second circuit. Each of the FCUs includes at least one memory control circuit and at least one memory array. The second level is bonded to the first level and includes metal to metal bonding regions. A third transistor and a fourth transistor are electrically connected and are at least 50 mm apart.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including a plurality of first metal layers; a second level overlaying the plurality of first metal layers, the second level including a second single crystal layer, a plurality of transistors, and a plurality of second metal layers, where at least one of the plurality of transistors includes a metal gate, where the second single crystal layer thickness is less than 2 microns, where the plurality of transistors includes one or more transistors with a first Threshold Voltage (Vt1), where the plurality of transistors includes one or more transistors with a second Threshold Voltage (Vt2), and where Vt1 is greater than Vt2.
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A 3D semiconductor device, the device including: a first level including logic circuits; a second level including a plurality of connectivity units, where the first level is overlaid by the second level, where each of the plurality of connectivity units includes at least one receiver circuit; and horizontally oriented transmission lines, where at least one of the plurality of connectivity units includes an Orthogonal Frequency Division Multiple Access (“OFDMA”) modulation circuit.
An integrated semiconductor device including: a first level including single crystal silicon and logic circuits each include first transistors; a second level, disposed above the first level and includes arrays of first memory cells, where the second level includes a plurality of second transistors, where each of the first memory cells includes at least one of the second transistors, where the first level is bonded to the second level; an array of processors; a plurality of SerDes circuits; and a third level, where the third level includes a plurality of third transistors, where the third level is disposed above the second level and includes a plurality of arrays of second memory cells, where each of the second memory cells includes at least one of the third transistors, where the device includes a substrate having an area greater than 1,000 mm2, and where the substrate includes at least one interconnect.
A 3D semiconductor device including: a first level including a single-crystal layer, a memory control-circuit including first transistors, a first metal layer, a second metal layer, a third metal layer; connection of the first transistors includes the first, and/or the second, and/or the third metal layer; a fourth metal layer disposed atop third transistors disposed atop second transistors disposed atop said first level; a memory array including word-lines, including at least four memory mini-arrays including at least four-rows-by-four-columns of memory cells, each of the memory cells includes at least one of the second transistors (at least one with a metal-gate) or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array; a semiconductor die, including second transistors and at least one alignment mark positioned toward the die edge, disposed atop said first level.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
H10D 62/834 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
H10D 64/64 - Electrodes comprising a Schottky barrier to a semiconductor
A 3D semiconductor device including: a first level including a single crystal layer, a memory control circuit, a first metal layer, a second metal layer, and a third metal layer; connection of the first transistors comprises the first, and/or the second, and/or the third metal layer; a fourth metal layer disposed atop third transistors disposed atop second transistors disposed atop said first level; a memory array including word-lines and at least four memory mini arrays which include at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors (at least one with a metal gate) or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array; the memory control circuit includes first transistors and voltage regulators.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
H10D 62/834 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
H10D 64/64 - Electrodes comprising a Schottky barrier to a semiconductor
A method to process a semiconductor device: processing the substrate forming a first level with a first single-crystal silicon-layer, first transistors, input-and-output (“IO”) circuits; forming a first metal-layer; forming a second metal-layer including a power-delivery network, where interconnection of the first transistors includes the first metal-layer and the second metal-layer; processing a second level including second transistors with metal gates and a first array of memory-cells; processing a third level including a plurality of third transistors with metal gates and a second array of memory-cells; third level disposed over the second level; forming a fourth metal-layer over a third metal-layer over the third-level; processing a fourth level including a second single-crystal silicon-layer, fourth level is disposed over the fourth metal-layer; forming a via disposed through the second and third levels, connections of the device to external devices includes the “IO”-circuits; the second level is disposed over the first level.
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10D 30/83 - FETs having PN junction gate electrodes
H10D 30/87 - FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Methods of designing a 3D Integrated Circuit including: partitioning at least one design into at least two levels, a first level and a second level, where the first level includes first transistors, where the second level includes second transistors is on top of the first level; providing placement data of the second level; performing a placement of the first level using a placer program executed by a computer, where the placement of the first level is based on the placement data, where the placer is part of a Computer Aided Design (CAD) tool, and where the first level includes first routing layers; performing a routing of the first level using a router {part of the CAD tool or another CAD tool) executed by a computer, where at least one metal routing layer is disposed in-between the first transistors and the second transistors, and the second level includes repeating structures.
Methods to fabricate a semiconductor device, the method including: forming a first level, the first level including a single crystal silicon layer, a plurality of transistors, and a plurality of first metal layers, where each transistor of the plurality of transistors includes a single crystal channel, and where the plurality of first metal layers include interconnections between the transistors of the plurality of transistors; thinning the single crystal silicon layer to a thickness of less than two microns; forming a second level, the second level including a plurality of second metal layers, where the second level is disposed underneath the first level; and forming a connection path between at least one of the transistors to at least one of the plurality of second metal layers, where the connective path includes at least one via disposed through at least the single crystal silicon layer.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
H10D 30/83 - FETs having PN junction gate electrodes
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 84/40 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or with at least one component covered by groups or , e.g. integration of IGFETs with BJTs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A semiconductor device including: a first level including a plurality of first metal layers; a second level overlaying the first level, where the second level includes at least one single-crystal silicon layer and a plurality of transistors, where each of the plurality of transistors includes a single-crystal channel, where the second level includes a plurality of second metal layers which includes interconnections between the plurality of transistors, the second level is overlaid by an isolation layer; a connective path from the plurality of transistors to the plurality of first metal layers, where at least one of the plurality of transistors includes a second single-crystal channel overlaying a first single-crystal channel, where each of at least one of the plurality of transistors includes at least a two sided gate, where the first single-crystal channel is self-aligned to the second single-crystal channel being processed following a same lithography step.
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
H10D 30/62 - Fin field-effect transistors [FinFET]
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
Methods of fabricating a 3D semiconductor device including: forming a first level including a first single crystal layer and first transistors, includes a single crystal channel; forming a first metal layer in the first level and a second metal layer overlaying the first metal layer; forming memory control circuits in the first level; forming a second level including second transistors, where at least one of the second transistors includes a metal gate; forming a third level including third transistors; forming a fourth level including fourth transistors, where the second level includes first memory cells, where the fourth level includes second memory cells, where the memory control circuits include control of data written into the first memory cells and into the second memory cells, where at least one of the transistors includes a hafnium oxide gate dielectric.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
A 3D device including: a first level including first transistors, a first interconnect; a second level including second transistors, the second level overlaying the first level and bonded to each other includes metal to metal bonding regions; at least four functional units each includes a first circuit which includes a portion of the first transistors; a redundancy circuit, where each of the at least four functional units includes a second circuit which includes a portion of the second transistors, and includes at least one memory control circuit and at least one memory array; where each of the at least four functional units includes a vertical connectivity structure which includes a plurality of pillars which provides electrical control connection between the first circuit and the second circuit; and a third transistor and a fourth transistor electrically connected to each other and are at least 100 mm apart.
A 3D semiconductor device including: a first level including a first single crystal layer, a memory control circuit, the memory control circuit including first transistors, a first, second, and third metal layer, where connection of the first transistors includes any of the three metal layers; second transistors disposed atop the first level; third transistors are atop the second transistors; a fourth metal layer is atop the third transistors; a memory array including word-lines and memory cells, includes at least four memory mini arrays, where each of the memory cells includes at least one of the second transistors or the third transistors, a connection path from the fourth metal to the third metal which includes a via thru the memory array; and a semiconductor die atop and bonded to the first level which includes second transistors, at least one alignment mark positioned toward an edge of the die.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
19.
Method to produce a 3D multilayer semiconductor device and structure
Methods of making a 3D multilayer semiconductor device, including: providing a first substrate including a first level, the first level including a first single crystal silicon layer (SCSL); providing a second substrate including a second level, the second level including a second SCSL; performing an epitaxial growth of a SiGe layer on top of the second SCSL; performing an epitaxial growth of a third SCSL on top of the SiGe layer, the third SCSL has an average thickness of less than 2,000 nm; forming second transistors each including a single crystal channel, where forming the second transistors includes growth of a second SiGe layer on top of the third SCSL; forming many metal layers interconnecting the second transistors; and then performing a bonding of the second level onto the first level, where performing the bonding includes making oxide-to-oxide bond zones; and performing removal of a majority of the second SCSL.
H10B 41/23 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/23 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
A method of manufacturing a 3D device including: forming a first level including first transistors and a first interconnect; forming a second level including second transistors; overlaying the second level on the first level; and bonding the second level to the first level; the bonding includes performing metal region to metal region bonding, the 3D device includes at least four electronic circuits (AL4ECs) and at least one redundancy circuit, where the AL4ECs each include a first circuit which includes a portion of the first transistors, where the AL4ECs include a second circuit which includes a portion of the second transistors, where the AL4ECs each include a vertical connectivity structure (VCSt), the VCSt includes pillars, where the pillars are configured to provide electrical connections between the first circuit and the second circuit, and where the AL4ECs each include at least one memory control circuit and at least one memory array.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H10B 10/00 - Static random access memory [SRAM] devices
H10B 99/00 - Subject matter not provided for in other groups of this subclass
H10D 80/20 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising capacitors, power FETs or Schottky diodes
A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a plurality of second transistors, where the second level includes a third layer, the third layer including first conductive lines; a third level overlaying the second level, where the third level includes a plurality of third transistors, where the third level includes a fourth layer, the fourth layer including second conductive lines; and a plurality of connection paths, where the plurality of connection paths provides electrical connections at least from a plurality of the first transistors to the plurality of third transistors, and where the first level includes at least one voltage regulator.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/528 - Layout of the interconnection structure
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
22.
3D semiconductor device and structure including power distribution grids
A 3D device includes a first level including a first single crystal layer with control circuitry which includes first single crystal transistors; a first metal layer atop first single crystal layer; a second, third, and fourth metal layer providing connections between the first transistors; at least one second level (includes a plurality of second transistors including metal gates, and a plurality of memory cells) atop the first level; a fourth metal layer above the second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid; a local power distribution grid, where the first level includes first Electrostatic Discharge (ESD) circuits, and the first single crystal transistors or second transistors include at least two FinFet transistors each having different threshold voltages.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
A semiconductor device including: a first level including: a first silicon layer including a first single crystal silicon; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a second level including a second single crystal silicon and a plurality of transistors, the second level is disposed over the second metal layer; a third metal layer disposed over the second level; a fourth metal layer disposed over the third metal layer; a via disposed through the second level, where the via has a diameter of less than 450 nm, where the second level thickness is less than four microns; and at least one temperature sensor.
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
24.
Methods for fabricating 3D memory devices and structures with memory arrays and metal layers
A method for fabricating a semiconductor device comprising: forming a first level; disposing a second level on top of the first level; disposing a third level on top of the second level; forming a via connection through the second level and the third level, where the first level comprises first transistors, at least four independently controlled first memory arrays, and first filled holes therein, where the second level comprises second memory arrays and second filled holes therein, where disposing the third level comprises third transistors, a plurality of third memory arrays, and at least one metal layer therein; disposing a fourth level on top of the third level, where the fourth level comprises fourth transistors and at least one SRAM memory array therein; and bonding the fourth level to the third level via metal-to-metal bonding regions.
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
A method for fabricating an integrated device, the method including: forming a first level including a first mono-crystal layer, where forming the first level includes forming a plurality of single crystal transistors, a plurality of pixel control circuits, and a plurality of recessed channel transistors therein; disposing an overlying oxide on top of the first level; providing a second level including a second mono-crystal layer, where the second mono-crystal layer includes a plurality of image sensors; bonding the second level to the first level via an oxide-to-oxide bond such that the second level overlays the oxide; and including disposing a third level underneath the first level, where the third level includes a plurality of third transistors, and where the plurality of third transistors each include a single crystal channel.
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
26.
3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH MEMORY CELLS
A semiconductor device, the device including: a first level including memory control circuits, the memory control circuits including first transistors, a second level disposed on top of the first level, the second level including a first array of memory cells including second transistors; a third level disposed on top of the second level, the third level including a second array of memory cells including third transistors; a fourth level disposed on top of the third level, the fourth level including a third array of memory cells including fourth transistors, where the second level is bonded to the first level, where the memory control circuits include cache memory, and where the second array of memory cells include a plurality of independently controlled memory units, and a plurality of refresh circuits for the memory units.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
27.
3D semiconductor device, structure and methods with memory arrays and connectivity structures
A 3D semiconductor device including: a first level including a first single crystal layer and a memory control circuit including first transistors and control circuit connectivity provided by first, second, and third metal layers; a second level including second transistors (one which includes a metal gate) disposed atop the first level; third transistors disposed atop second transistors with a fourth metal layer disposed atop; a memory array including word-lines, the memory array includes at least four memory mini arrays, where each mini array includes at least four rows by four columns of memory cells, and where each of the memory cells includes at least one of the second or third transistors; a connection path from the fourth metal to the third or second metal layer, which includes a via disposed through the second level, and where the memory control circuit includes at least one power down control circuit.
A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, and where the third level is bonded to the second level; a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors; and a plurality of capacitors, where the single crystal first transistors or the second transistors include at least two FinFet transistors, and where two of the at least two FinFet transistors have different threshold voltages (Vt).
G11C 11/404 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
G11C 11/4097 - Bit-line organisation, e.g. bit-line layout, folded bit lines
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 69/00 - Erasable-and-programmable ROM [EPROM] devices not provided for in groups , e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
29.
3D semiconductor device and structure with metal layers
A 3D semiconductor device including: a first level with first transistors, a single-crystal layer and at least one metal layer which includes interconnects between the first transistors forming first control circuits with a plurality of sense amplifiers; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory-cells which include second transistors with a metal-gate, overlaid by a third level which includes second memory cells which include third transistors which control the data written to second memory cells; a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within greater than 0.2 nm error, the first transistors or the second transistors comprise at least two FinFet transistors, and two of the FinFet transistors each have different threshold voltages.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including at least one electromagnetic wave receiver, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; an oxide layer disposed between the first level and the second level; at least one read out circuit, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds; a first structure designed to conduct electromagnetic waves; and an electromagnetic wave transmitter, where the transmitter includes at least one modulator.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
H01L 23/00 - Details of semiconductor or other solid state devices
31.
3D SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE WITH MEMORY CONTROL CIRCUITS
A 3D semiconductor device, including: a first level including a first single crystal layer, memory control circuits, and first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer connected to the first metal layer, at least one Phase-Lock-Loop or Digital-Lock-Loop circuit; a second level overlaying the first level including second transistors, a third level overlaying the second level and including third transistors; a fourth level overlaying the third level and including fourth transistors, the second level includes first memory cells, where each includes at least one of the second transistors which may include a metal gate, the fourth level includes second memory cells which each includes at least one of the fourth transistors, where the memory control circuits control writing to the second memory cells, where at least one of the second transistors includes a hafnium-oxide gate dielectric.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
A 3D memory device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel, where the memory cell includes at least one charge trap structure, and where the at least one memory transistor is self-aligned to an overlaying another of the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the control level includes a plurality of temperature sensors, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
33.
3D semiconductor device and structure including power distribution grids
A 3D device includes a first level including a first single crystal layer with control circuitry which includes first single crystal transistors; a first metal layer atop first single crystal layer; a second, third, and fourth metal layer providing connections between the first transistors; at least one second level (includes a plurality of second transistors including metal gates, and a plurality of memory cells) atop the first level; a fourth metal layer above the second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid; a local power distribution grid, where the first level includes first Electrostatic Discharge (ESD) circuits, and the second level includes second ESD circuits.
A method for producing a 3D semiconductor device including: providing a first level, including a single crystal layer; forming memory control circuits in and/or on the first level which include first single crystal transistors and at least two interconnection metal layers; forming at least one second level; performing a first etch step into the second level; forming at least one third level on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor including a metal gate, where each of the second memory cells include at least one third transistor; and performing bonding of the first level to the second level, where the first level includes control of power delivery to the at least one third transistor.
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
H10D 30/62 - Fin field-effect transistors [FinFET]
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
H10N 70/20 - Multistable switching devices, e.g. memristors
35.
3D semiconductor device and structure with metal layers and memory cells
A 3D semiconductor device, the device including: a first level including a first single crystal layer and including first transistors each of which includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors and overlaying the second metal layer, each of first memory cells include at least one second transistor; a third level including third transistors and overlaying the second level; a fourth level including fourth transistors and overlaying the third level, each of second memory cells include at least one fourth transistor, where at least one of the second transistors includes a metal gate, where the first level includes memory control circuits which control writing to the second memory cells, and at least one of the second transistors includes a hafnium oxide gate dielectric.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
36.
3D semiconductor device and structure with logic and memory
A 3D semiconductor device including: a first level including a single crystal layer and a memory control circuit including first transistors and a redundancy control circuit; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors disposed atop the third metal layer with at least one including a metal gate; third transistors disposed atop the second transistors; a fourth metal layer atop the third transistors; a memory array including word-lines and at least four memory mini arrays, each including at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
H10D 62/834 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
H10D 64/64 - Electrodes comprising a Schottky barrier to a semiconductor
A semiconductor device including: a first level including at least four independently controlled first memory arrays, where the first level includes first transistors; a second level disposed on top of the first level, where the second level includes second memory arrays; and a third level disposed on top of the second level, where the third level includes third transistors, at least one metal layer, and third memory arrays; a fourth level disposed on top of the third level, where the fourth level includes fourth transistors, another at least one metal layer, and is bonded to the third level, where the bonded includes metal-to-metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes; and a via connection through the second level and the third level, and where the fourth level includes at least one SRAM memory array.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
38.
3D semiconductor devices and structures with metal layers
A semiconductor device including: a first level including a first single crystal silicon layer, a plurality of first transistors, and input/output circuits; a first metal layer; a second metal layer which includes a power delivery network; where interconnection of the plurality of first transistors includes the first and second metal layers; a second level including a plurality of metal gate second transistors and first array of memory cells, disposed over the first level; a third level including a plurality of metal gate third transistors and a second array of memory cells, disposed over the second level; a via disposed through the second and third levels; a third metal layer disposed over the third level; a fourth metal layer disposed over the third metal layer; and a fourth level disposed over the fourth metal layer and including a second single crystal silicon layer.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10D 30/83 - FETs having PN junction gate electrodes
H10D 30/87 - FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
H01L 23/00 - Details of semiconductor or other solid state devices
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
39.
3D semiconductor device and structure with metal layers
A 3D semiconductor device including: a first level with first-transistors, a single crystal layer overlaid by at least one first metal-layer which includes interconnects between the first-transistors forming first control circuits with a sense amplifiers; the first metal-layer(s) overlaid by a second metal-layer which is overlaid by a second level which includes first memory cells which include second-transistors with a metal gate, overlaid by a third level which includes second memory cells which include third-transistors and are partially disposed atop the control circuits, which control the data written to second memory cells; a fourth metal-layer overlaying a third metal-layer which overlays the third level; where third-transistor gate locations are aligned to second-transistor gate locations within greater than 0.2 nm error, the average thickness of second metal-layer is at least twice the average thickness of the third metal-layer; the second metal-layer includes a global power distribution grid.
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A 3D semiconductor device including dicing including an etch process; and including: a first level including a single crystal layer, and a memory control circuit which includes first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors—which may include a metal gate—disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; a memory array including word-lines and at least four memory mini arrays (each mini array includes at least four rows by four columns of memory cells), each memory cell includes at least one second transistor or at least one third transistor; and a connection path from fourth metal to third metal, the path includes a via disposed through the memory array.
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
41.
3D semiconductor device and structure with metal layers and memory cells
A 3D semiconductor device, the device including: a first level including a first single crystal layer and including first transistors which each includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer; a third level including third transistors and overlaying the second level; a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where at least one of the second transistors includes a metal gate, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
42.
3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH SINGLE-CRYSTAL LAYERS
A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a first oxide layer disposed atop of the first level; a second level including second transistors and at least one array of memory cells, where each of the memory cells includes at least one of the second transistors, where the second level overlays the first level, where the at least one of the second transistors includes a recessed channel, and where the second level is directly bonded to the first level.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
43.
3D semiconductor device and structure with memory cells and multiple metal layers
A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
44.
3D semiconductor devices and structures with slits
A semiconductor device including: a first level including memory control circuits (include a plurality of refresh circuits for the memory units) which include first transistors; a second level including a first array of memory cells including second transistors self-aligned to at least one of the third transistors; a third level disposed on top of the second level disposed on top of first level, the third level including a second array of memory cells including third transistors; a fourth level disposed on top of the third level, the fourth level including a third array of memory cells including fourth transistors, second level is bonded to the first level, a plurality of slits disposed through the second level, the third level, and the fourth level, the slits enable gate replacement of a plurality of the third transistors, where the second array of memory cells include a plurality of independently controlled memory units.
H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
45.
Automation methods for 3D integrated circuits and devices
A method of designing a 3D Integrated Circuit including: partitioning at least one design into at least two levels, a first level and a second level, where the first level includes first transistors, where the second level includes second transistors and is disposed on top of the first level; levels connection pads (LCPs) disposed between the first level and second level; providing placement of the LCPs; performing a placement of the first level using a placer program executed by a computer, where the placement of the first level is based on the placement of the LCPs, where the placer is part of a Computer Aided Design (CAD) tool, where the first level includes first routing layers; performing a routing of the first level by routing layers using a router executed by a computer, where the router is a part of the CAD tool or a part of another CAD tool.
A method of making a 3D multilayer semiconductor device, including: providing a first substrate including a first level, the first level including a first single crystal silicon layer; providing a second substrate including a second level, the second level including a second single crystal silicon layer; performing an epitaxial growth of a SiGe layer on top of the second single crystal silicon layer; performing an epitaxial growth of a third single crystal silicon layer on top of the SiGe layer, the third silicon layer has an average thickness of less than 2,000 nm; forming a plurality of second transistors each including a single crystal channel; forming many metal layers interconnecting the plurality of second transistors; and then performing a bonding of the second level onto the first level, where performing the bonding includes making oxide-to-oxide bond zones; and performing removal of a majority of the second single crystal silicon layer.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
47.
Methods for producing a 3D semiconductor memory device and structure
A method for producing a 3D memory device including: providing a first level including a first single-crystal layer and control circuits, where the first level includes at least two interconnecting metal layers; forming at least one second level disposed above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level; each of first memory cells include one first transistor and each of second memory cells include one second transistor, where first memory cells and second memory cells are a NAND nonvolatile type memory, and at least one of the second transistors include a metal gate.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components
48.
3D semiconductor device and structure with logic circuits, memory cells, and processor array
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
49.
3D semiconductor device and structure with three levels and isolation layers
A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, where the third level is bonded to the second level; and a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
H10D 30/83 - FETs having PN junction gate electrodes
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 84/40 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or with at least one component covered by groups or , e.g. integration of IGFETs with BJTs
50.
3D semiconductor device and structure with metal layers and a power delivery path
A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, and where the third level is bonded to the second level; a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors; and a plurality of capacitors, where the plurality of capacitors include functioning as a decoupling capacitor to mitigate power supply noise.
G11C 11/404 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
G11C 11/4097 - Bit-line organisation, e.g. bit-line layout, folded bit lines
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 69/00 - Erasable-and-programmable ROM [EPROM] devices not provided for in groups , e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
51.
3D semiconductor device and structure with metal layers
A semiconductor device including: a first level including: a first silicon layer including a first single crystal silicon layer; first transistors each including a single-crystal channel; a first metal layer connected to the first transistors and the second metal layer; a third metal layer connected to the second metal layer; a second level including second transistors; a third level including third transistors, the third level is disposed over the second level which is disposed over the first level; a fifth metal layer disposed over a fourth metal layer disposed over the third level; and a via disposed through the second level, where at least one of the second transistors includes a metal gate, where the device includes at least one temperature sensor, and where at least one element within at least one of the second transistors has been processed independently of the third transistors.
H01L 23/528 - Layout of the interconnection structure
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
52.
3D semiconductor device and structure with connection paths
A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a plurality of second transistors, where the second level includes a third layer, the third layer including first conductive lines; a third level overlaying the second level, where the third level includes a plurality of third transistors, where the third level includes a fourth layer, the fourth layer including second conductive lines; and a plurality of connection paths, where the plurality of connection paths provides electrical connections at least from a plurality of the first transistors to the plurality of third transistors, and where the first level includes at least one voltage regulator.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level including an oxide to oxide bond; a plurality of pixel control circuits; a third level disposed underneath the first level, where the third level includes a plurality of third transistors, where the plurality of third transistors each include a single crystal channel; and a plurality of recessed channel transistors.
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
54.
3D semiconductor device and structure with metal layers and memory cells
A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer, a third level including third transistors and overlaying the second level, a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components
55.
3D semiconductor device and structure with logic and memory
A 3D semiconductor device including: a first level including a single crystal layer and a memory control circuit including first transistors and at least one power-down control circuit; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors disposed atop the third metal layer with at least one including a metal gate; third transistors disposed atop the second transistors; a fourth metal layer atop the third transistors; a memory array including word-lines and at least four memory mini arrays, each including at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/528 - Layout of the interconnection structure
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
56.
3D semiconductor device and structure with logic and memory
A 3D semiconductor device including: a first level including a single crystal layer and a memory control circuit including first transistors and at least one cache memory unit; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors disposed atop the third metal layer with at least one including a metal gate; third transistors disposed atop the second transistors; a fourth metal layer atop the third transistors; a memory array including word-lines and at least four memory mini arrays, each including at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/528 - Layout of the interconnection structure
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
57.
United states 3D memory semiconductor devices and structures with memory cells
A 3D memory device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel, where the memory cell includes at least one charge trap structure, and where the at least one memory transistor is self-aligned to an overlaying another the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the control level includes a plurality of latch sense amplifiers, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
58.
3D memory devices and structures with memory arrays and metal layers
A semiconductor device including: a first level including at least four independently controlled first memory arrays, where the first level includes first transistors; a second level disposed on top of the first level, where the second level includes second memory arrays; and a third level disposed on top of the second level, where the third level includes third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, where the second filled holes are aligned to the first filled holes with a more than 1 nm but less than 40 nm alignment error, and where the third level includes at least one SRAM memory array.
H10B 10/00 - Static random access memory [SRAM] devices
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
59.
3D semiconductor device and structure with metal layers
A 3D semiconductor device including: a first level with first transistors, single crystal layer overlaid by at least one first metal layer which includes interconnects between the first transistors forming first control circuits with a sense amplifier; the first metal-layer(s) overlaid by a second metal-layer which is overlaid by a second level which includes first memory cells which include second transistors with a metal gate, overlaid by a third level which includes second memory cells which include third transistors and are partially disposed atop the control circuits, which control data written to second memory cells; a fourth metal-layer overlaying a third metal-layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within less than 100 nm, the average thickness of fourth metal-layer is at least twice the average thickness of second metal-layer; the fourth metal-layer includes a global power distribution grid.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
60.
3D semiconductor device and structure with bonding and memory cells preliminary class
A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; and a second level including a plurality of second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of memory cells, where each of the plurality of memory cells includes at least one of the second transistors, where the device includes at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
61.
3D semiconductor devices and structures with metal layers
A semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, disposed over the third metal layer; a third level including a plurality of third transistors, disposed over the second level; a via disposed through the second and third levels; a fourth metal layer disposed over the third level; a fifth metal layer disposed over the fourth metal layer; and a fourth level including a second single crystal silicon layer and is disposed over the fifth metal layer, where each of the plurality of second transistors includes a metal gate, and the via has a diameter of less than 450 nm.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
G03F 9/00 - Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
62.
Multilevel semiconductor device and structure with oxide bonding
A multi-level semiconductor device, the device comprising: a first level comprising integrated circuits; a second level comprising at least one electromagnetic wave receiver, wherein said second level is disposed above said first level, wherein said integrated circuits comprise single crystal transistors; and an oxide layer disposed between said first level and said second level, wherein said device comprises at least one read out circuit, wherein said second level is bonded to said oxide layer, and wherein said bonded comprises oxide to oxide bonds.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
H01L 23/00 - Details of semiconductor or other solid state devices
63.
3D semiconductor devices and structures with electronic circuit units
A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and overlaying the first level; at least four electronic circuit units (ECUs); a redundancy circuit, where each of the at least four ECUs includes a first circuit, which includes a portion of the first transistors, where each of the at least four ECUs includes a second circuit, the second circuit including some second transistors, where each of the at least four ECUs includes a vertical connectivity structure which includes pillars, where the pillars provide electrical connections between the first circuit and the second circuit, where each of the at least four ECUs includes at least one memory control circuit and at least one memory array, where the second level is bonded to the first level, and the bonded includes oxide to oxide and metal to metal bonding regions.
A method of making a 3D multilayer semiconductor device, the method comprising: providing a first substrate comprising a first level, said first level comprising a first single crystal silicon layer; providing a second substrate comprising a second level, said second level comprising a second single crystal silicon layer; performing an epitaxial growth of a SiGe layer on top of said second single crystal silicon layer; performing an epitaxial growth of a third single crystal silicon layer on top of said SiGe layer; forming a plurality of second transistors each comprising a single crystal channel; forming a plurality of metal layers interconnecting said plurality of second transistors; and then performing a bonding of said second level onto said first level, wherein performing said bonding comprises making oxide-to-oxide bond zones, and performing removal of a majority of said second single crystal silicon layer.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
65.
3D semiconductor device and structure with metal layers
A semiconductor device including: a first silicon layer including a first single crystal silicon layer; first transistors with a single crystal channel and overlaid by a first metal layer; overlaid by a second metal layer; overlaid by a third metal layer; a second level with second transistors and including a metal gate, and then disposed over the third metal layer; the second level is overlaid by a third level with third transistors; and then overlaid by a fourth metal layer; fourth overlaid by a fifth metal layer; a via disposed through the second level; the device includes at least one temperature sensor; the fifth metal layer average thickness is greater than the third metal layer average thickness by at least 50%; at least one element within at least one of the second transistors has been processed independently of the third transistors.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
A 3D semiconductor device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a plurality of second transistors disposed atop the second metal layer; a third metal layer disposed above the plurality of second transistors; and a memory array including word-lines and memory cells, where the memory array includes at least four memory mini arrays, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors, and where the memory control circuit includes at least one power down control circuit, and where the device includes a hybrid bonding layer.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
67.
3D SEMICONDUCTOR MEMORY DEVICES AND STRUCTURES WITH MEMORY CELLS
A 3D semiconductor device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer, a second metal layer overlaying the first metal layer, a plurality of second transistors disposed atop the second metal layer, a third metal layer disposed above the plurality of second transistors; and a memory array including word-lines and memory cells, where the memory array includes at least four memory mini arrays, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors, and where the memory control circuit includes at least one In-Out interface controller circuit.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer—which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; second metal layer overlaying first metal layer; a second level including second transistors, first memory cells and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells and include at least one sense amplifier; third metal layer disposed above third level; fourth metal layer includes global power distribution grid, has a thickness at least twice the second metal layer, disposed above third metal layer; fourth level includes single-crystal silicon, atop fourth metal layer.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
G11C 11/404 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
G11C 11/4097 - Bit-line organisation, e.g. bit-line layout, folded bit lines
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 69/00 - Erasable-and-programmable ROM [EPROM] devices not provided for in groups , e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
A 3D semiconductor device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a plurality of second transistors disposed atop the second metal layer; a third metal layer disposed atop the plurality of third transistors; and a memory array including word-lines and memory cells, where the memory array includes at least four memory mini arrays, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors, where the memory control circuit includes at least one digital to analog converter circuit, and where the device includes a hybrid bonding layer.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
70.
3D semiconductor device and structure with metal layers
A 3D semiconductor device including: a first level with first transistors, single crystal layer overlaid by at least one first metal layer which includes interconnects between the first transistors forming first control circuits; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory cells which include second transistors, overlaid by a third level which includes second memory cells which include third transistors and are partially disposed over the control circuits, which control data written to second memory cells; and a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within less than 100 nm, and the average thickness of fourth metal layer is at least twice the average thickness of second metal layer; the fourth metal layer includes a global power distribution grid.
H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
71.
3D memory semiconductor devices and structures with memory cells preliminary class
A 3D memory device, the device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel, where the memory cell includes at least one charge trap structure, and where the at least one memory transistor is self-aligned to an overlaying another the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the control level includes a plurality of temperature sensors, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
G11C 16/28 - Sensing or reading circuitsData output circuits using differential sensing or reference cells, e.g. dummy cells
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
72.
3D semiconductor devices and structures with metal layers
A semiconductor device including: a first silicon level including a first single crystal silicon layer and first transistors; a first metal layer disposed over it; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including second transistors, disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 240 nm alignment error; where the fifth metal layer includes global power delivery; each of the third transistors comprises a metal gate; a via disposed through the second level and the third level, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
G03F 9/00 - Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
73.
3D semiconductor device and structure with bonding and DRAM memory cells
A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layer; a second metal layer overlaying the first metal layer; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors and one capacitor, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components
A 3D semiconductor device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a plurality of second transistors disposed atop the second metal layer; a third metal layer disposed atop the plurality of second transistors; and a memory array including word-lines and memory cells, where the memory array includes at least four memory mini arrays, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors, where the memory control circuit includes at least one Look Up Table circuit (“LUT”), and where the device includes a hybrid bonding layer.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
75.
Method for producing 3D semiconductor devices and structures with transistors and memory cells
A method for producing a 3D semiconductor device including: providing a first level, including a single crystal layer; forming memory control circuits in and/or on the first level which include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the memory control circuits; performing a first etch step into the second level; forming at least one third level on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor including a metal gate, where each of the second memory cells include at least one third transistor; and performing bonding of the first level to the second level, where the bonding includes oxide to oxide bonding.
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
H10N 70/20 - Multistable switching devices, e.g. memristors
76.
3D memory devices and structures with memory arrays and metal layers
A semiconductor device including: a first level including a plurality of first memory arrays, a plurality of first transistors, and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays; and a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes (FFHs), where the second level includes second filled holes (SFHs), where the SFHs are aligned to the FFHs with a more than 1 nm but less than 40 nm alignment error, where the third level includes a plurality of Look-Up-Table circuits.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
77.
Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one second level on top of or above the second metal layer; performing a lithography step on the second level; forming at least one third level on top of or above the second level; performing processing steps to form first memory cells within the second level and second memory cells within the third level, where the first memory cells include at least one second transistor, the second memory cells include at least one third transistor, second transistors comprise gate electrodes comprising metal, and then forming at least four independent memory arrays which include some first memory cells and/or second memory cells.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components
78.
Multilevel semiconductor device and structure with image sensors and wafer bonding
An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level including an oxide to oxide bond; a plurality of pixel control circuits; a third level disposed underneath the first level, where the third level includes a plurality of third transistors, where the plurality of third transistors each include a single crystal channel; and a plurality of memory circuits.
3D semiconductor device including: a first level including first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the first single-crystal transistors; a first metal layer disposed atop the first single-crystal transistors; a second metal layer disposed atop the first metal layer, a second level disposed atop the second metal layer includes second transistors and a memory array of first memory cells, a third level including second memory cells which include some third transistors, which themselves include a metal gate and is disposed above the second level; a third metal layer disposed above the third level; a fourth metal layer disposed above the third metal layer, a connective path from the third metal layer to the second metal layer with a thru second level via of a diameter less than 800 nm which also passes thru the memory array, different write voltages for different dies.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
80.
3D semiconductor device and structure with logic and memory
A 3D semiconductor device including: a first level including a single crystal layer, a memory control circuit which includes a plurality of first transistors; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors which include a metal gate are disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; and a memory array including word-lines, the memory array includes at least four memory mini arrays, each including at least four rows by at least four columns of memory cells, where each of the memory cells includes at least one of the second transistors or at least one of the third transistors, the memory control circuit includes at least one digital to analog converter circuit.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/528 - Layout of the interconnection structure
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
81.
Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one (ALO) second level on top of or above the second metal layer; performing a lithography step on the second level; forming ALO third level on top of or above the ALO second level; performing processing steps to form first memory cells within the ALO second level and second memory cells within the ALO third level, first memory cells include ALO second transistor, second memory cells include ALO third transistor, first metal layer thickness is at least 50% greater than the second metal layer thickness, ALO first transistor controls power delivery to ALO second transistor; then dicing using a laser system.
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components
82.
3D semiconductor device and structure with metal layers and a connective path
A 3D semiconductor device including: a first level including a plurality of first metal layers; a second level overlays the first level and includes at least one single crystal silicon layer, where the second level includes a plurality of transistors and a plurality of second metal layers, each transistor of the plurality of transistors includes a single crystal channel, where the plurality of second metal layers include interconnections between transistors of the plurality of transistors, where the second level is overlaid by a first isolation layer; a connective path from the plurality of transistors to the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, where each of at least one of the plurality of transistors includes a two sided gate, and where the single crystal silicon layer thickness is less than two microns.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/808 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a PN junction gate
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
3D semiconductor device including: first level including first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the first single-crystal transistors; first metal layer disposed atop the first single-crystal transistors; a second metal layer disposed atop the first metal layer; a second level disposed atop the second metal layer includes second transistors and a memory array of first memory cells; third level including second memory cells which include some third transistors, which themselves include a metal gate and is disposed above the second level; a third metal layer disposed above the third level; a fourth metal layer disposed above the third metal layer; a connective path from the third metal layer to the second metal layer with a thru second level via of a diameter less than 800 nm which also passes thru the memory array, adjust memory cell write voltages based on temperature information.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
84.
3D semiconductor device and structure with metal layers
A semiconductor device, the device including: a first substrate; a first metal layer disposed over the first substrate; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors each include single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 200 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm, where the fourth metal layer provides a global power distribution, and where processing of the device includes use of a carrier wafer.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
85.
3D memory semiconductor devices and structures with memory-line pillars
A 3D memory device, the device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; a plurality of memory-line pillars, where each memory-line pillar of the plurality of memory-line pillars is directly connected to a plurality of the source or the drain, where the plurality of memory-line pillars are vertically oriented, and where the at least one memory transistor is self-aligned to an overlaying another the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the memory controller circuit includes a row buffer, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
86.
3D semiconductor devices and structures with metal layers
A semiconductor device, the semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 240 nm alignment error; where the fifth metal layer includes global power delivery; and a via disposed through the second level, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
G03F 9/00 - Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
87.
3D semiconductor device, structure and methods with connectivity structures
A 3D device, the device including: at least one first level including logic circuits; at least one second level bonded to the first level, where the at least one second level includes a plurality of transistors; connectivity structures, where the connectivity structures include a plurality of transmission lines, where the plurality of transmission lines are designed to conduct radio frequencies (“RF”) signals, and where the bonded includes oxide to oxide bond regions and metal to metal bond regions; and a plurality of vias disposed through the at least one second level, where at least a majority of the plurality of vias have a diameter of less than 5 micrometers.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
88.
3D semiconductor device, structure and methods with connectivity structures
A 3D semiconductor device including: a first level including a single crystal layer, and a memory control circuit which includes at least one temperature sensor circuit and first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors—which may include a metal gate—disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; a memory array including word-lines and at least four memory mini arrays (each mini array includes at least four rows by four columns of memory cells), each memory cell includes at least one second transistor or at least one third transistor; and a connection path from fourth metal to third metal, the path includes a via disposed through the memory array.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
89.
3D semiconductor device and structure with single-crystal layers
A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; a first oxide layer disposed over the second metal layer; a second oxide layer disposed over the first oxide layer; and a second level including at least one array of memory cells and second transistors, where each of the memory cells includes at least one of the second transistors, where the second level overlays the first level, where at least one of the second transistors includes at least two independent gates, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components
3D semiconductor device including: a first level including first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the first single-crystal transistors; a first metal layer disposed atop the first single-crystal transistors; a second metal layer disposed atop the first metal layer; a second level disposed atop the second metal layer includes second transistors and a memory array of first memory cells; a third level including second memory cells which include some third transistors, which themselves include a metal gate and is disposed above the second level; a third metal layer disposed above the third level; a fourth metal layer disposed above the third metal layer; a connective path from the third metal layer to the second metal layer with a thru second level via of a diameter less than 800 nm which also passes thru the memory array, memory control circuits for wear leveling.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
91.
3D semiconductor devices and structures with electronic circuit units
A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and is overlaying the first level; at least four electronic circuit units (ECUs); and a redundancy circuit, where each of the ECUs includes a first circuit which includes a portion of the first transistors, where each of the ECUs includes a second circuit, the second circuit including a portion of the second transistors, where each of the at least four ECUs includes a first vertical bus, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where each of the at least four ECUs includes at least one processor and at least one memory array, where the second level is bonded to the first level, and the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.
H01L 23/528 - Layout of the interconnection structure
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 69/00 - Erasable-and-programmable ROM [EPROM] devices not provided for in groups , e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
A 3D semiconductor device, the device including: a first level including first single crystal transistors; a second level including second transistors; memory periphery circuits; and memory cells, where the first level is overlaid by the second level, where the first level includes a transferred layer and a bonded layer, where the second level is bonded to the first level, where the bonded second level includes oxide to oxide bonds, where the bonded second level includes metal to metal bonds, where the first level includes a preponderance of the memory periphery circuits, where the second level includes a preponderance of the memory cells, where the preponderance of the memory periphery circuits are connected to the preponderance of the memory cells using a portion of the metal to metal bonds, and where the memory periphery circuits include at least one Look up Table (“LUT”) circuit.
A 3D semiconductor device including: a first level including a single crystal layer, a memory control circuit which includes a plurality of first transistors; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors which include a metal gate are disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; and a memory array including word-lines, the memory array includes at least four memory mini arrays, each including at least four rows by at least four columns of memory cells, where each of the memory cells includes at least one of the second transistors or at least one of the third transistors, the memory control circuit includes at least one Look Up Table circuit (“LUT”).
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/528 - Layout of the interconnection structure
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
94.
3D memory devices and structures with metal layers
A semiconductor device including: a first level including first memory arrays, a plurality of first transistors, and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes second memory arrays; a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, where the second filled holes are aligned to the first filled holes with a more than 1 nm but less than 40 nm alignment error, and where the third level includes decoder circuits.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
95.
3D semiconductor device and structure with metal layers
A semiconductor device including: a first silicon layer including a first single crystal silicon layer; first transistors with a single crystal channel and overlaid by a first metal layer; overlaid by a second metal layer; overlaid by a third metal layer; a second level with second transistors and including a metal gate, and then disposed over the third metal layer; the second level is overlaid by a third level with third transistors; and then overlaid by a fourth metal layer; fourth overlaid by a fifth metal layer; parts of the second transistors are made with Atomic Layer Deposition (“ALD”); the fifth metal layer average thickness is greater than the third metal layer average thickness by at least 50%; at least one element within at least one of the second transistors has been processed independently of the third transistors.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including at least one electromagnetic wave receiver, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the integrated circuits include at least one memory circuit, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 23/528 - Layout of the interconnection structure
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
97.
3D semiconductor device and structure with metal layers and memory cells
3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; second metal layer overlaying first metal layer; a second level including second transistors, first memory cells (each including at least one second transistor) and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells; third metal layer disposed above third level; fourth metal layer includes global power distribution grid, has a thickness at least twice the second metal layer, disposed above third metal layer; fourth level includes single-crystal silicon, atop fourth metal layer.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
G11C 11/404 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
G11C 11/4097 - Bit-line organisation, e.g. bit-line layout, folded bit lines
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 69/00 - Erasable-and-programmable ROM [EPROM] devices not provided for in groups , e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
98.
3D memory semiconductor devices and structures with bit-line pillars
A 3D memory device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of memory-line pillars, where each memory-line pillar of the plurality of memory-line pillars is directly connected to a plurality of the source or the drain, where the plurality of memory-line pillars are vertically oriented, where the channel is horizontally-oriented and a plurality are connected to a body pillar, where the body pillar is at least temporary connected to a negative bias, the at least one memory transistor is self-aligned to an overlaying another memory transistor, both being processed following a same lithography step; a control level including a memory controller circuit and is hybrid bonded to the first structure.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
99.
3D semiconductor device and structure with bonding
A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components
100.
Multilevel semiconductor device and structure with image sensors and wafer bonding
An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level with an oxide to oxide bond; a plurality of pixel control circuits; a plurality of memory circuits; and a third level disposed underneath the first level, where the third level includes a plurality of third transistors.
patents
