Missing Link Electronics, Inc.

United States of America

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IPC Class
H04L 12/54 - Store-and-forward switching systems 5
H04L 12/70 - Packet switching systems 4
G06F 17/50 - Computer-aided design 3
H03M 3/00 - Conversion of analogue values to or from differential modulation 3
H03M 7/30 - CompressionExpansionSuppression of unnecessary data, e.g. redundancy reduction 3
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Found results for  patents

1.

Tightly-Coupled, Loosely Connected Heterogeneous Packet Based Transport

      
Application Number 18199241
Status Pending
Filing Date 2023-05-18
First Publication Date 2023-11-30
Owner MISSING LINK ELECTRONICS, INC. (USA)
Inventor
  • Schubert, Nils Endric
  • Epping, David
  • Braun, Andreas
  • Langenbach, Ulrich

Abstract

Tightly-coupled, loosely connected distributed systems can be implemented more energy efficient and optimized for computational overhead via multi-protocol heterogeneous packet-based transport. When receiving a plurality of packets from a root complex where contents of each packet from the plurality of packets organized in accordance with a first protocol, a sequence number is added to each packet and a packet type is identified. Every packet in the first plurality of packets is encapsulated into at least one packet organized in accordance with a second protocol to form a second plurality of packets organized in accordance with the second protocol. All the packets from the second plurality of packets can be handled via Direct Memory Access. A write-only communication scheme can be implemented using doorbell and command registers for more efficient data reading and writing in distributed systems.

IPC Classes  ?

  • H04L 49/552 - Prevention, detection or correction of errors by ensuring the integrity of packets received through redundant connections
  • H04L 49/9057 - Arrangements for supporting packet reassembly or resequencing
  • H04L 49/25 - Routing or path finding in a switch fabric
  • H04L 45/44 - Distributed routing
  • H04L 47/24 - Traffic characterised by specific attributes, e.g. priority or QoS
  • H04L 47/34 - Flow controlCongestion control ensuring sequence integrity, e.g. using sequence numbers
  • H04L 47/10 - Flow controlCongestion control
  • H04L 47/30 - Flow controlCongestion control in combination with information about buffer occupancy at either end or at transit nodes
  • H04L 12/54 - Store-and-forward switching systems

2.

Deterministic real time multi protocol heterogeneous packet based transport

      
Application Number 17744176
Grant Number 11695708
Status In Force
Filing Date 2022-05-13
First Publication Date 2022-09-29
Grant Date 2023-07-04
Owner Missing Link Electronics, Inc. (USA)
Inventor
  • Schubert, Nils Endric
  • Epping, David
  • Braun, Andreas
  • Langenbach, Ulrich

Abstract

Deterministic real-time multi-protocol heterogeneous packet-based transport is achieved by traffic shaping. When receiving a plurality of packets from a root complex where contents of each packet from the plurality of packets organized in accordance with a first protocol, a sequence number is added to each packet and a packet type is identified. Every packet in the first plurality of packets is encapsulated into at least one packet organized in accordance with a second protocol to form a second plurality of packets organized in accordance with the second protocol. All the packets from the second plurality of packets pass traffic scheduling or traffic shaping prior being sent via a plurality of connections to avoid burstiness and to achieve bounded transport latency in the plurality of connections, thereby providing deterministic real-time behavior in distributed systems.

IPC Classes  ?

  • H04L 12/28 - Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
  • H04L 49/552 - Prevention, detection or correction of errors by ensuring the integrity of packets received through redundant connections
  • H04L 49/9057 - Arrangements for supporting packet reassembly or resequencing
  • H04L 49/25 - Routing or path finding in a switch fabric
  • H04L 45/44 - Distributed routing
  • H04L 47/24 - Traffic characterised by specific attributes, e.g. priority or QoS
  • H04L 47/34 - Flow controlCongestion control ensuring sequence integrity, e.g. using sequence numbers
  • H04L 47/10 - Flow controlCongestion control
  • H04L 47/30 - Flow controlCongestion control in combination with information about buffer occupancy at either end or at transit nodes
  • H04L 12/54 - Store-and-forward switching systems
  • H04L 12/70 - Packet switching systems

3.

Real-time multi-protocol heterogeneous packet-based transport

      
Application Number 17018962
Grant Number 11356388
Status In Force
Filing Date 2020-09-11
First Publication Date 2020-12-31
Grant Date 2022-06-07
Owner MISSING LINK ELECTRONICS, INC. (USA)
Inventor
  • Schubert, Nils Endric
  • Epping, David
  • Braun, Andreas
  • Langenblach, Ulrich

Abstract

Deadlocks in a multi-protocol heterogeneous packet-based transport system are avoided while maintaining real-time aspects. When receiving a plurality of packets from a root complex where contents of each packet from the plurality of packets organized in accordance with a first protocol, a sequence number is added to each packet and a packet type is identified. Every packet in the first plurality of packets is encapsulated into at least one packet organized in accordance with a second protocol to form a second plurality of packets organized in accordance with the second protocol. All the packets from the second plurality of packets are sent via a plurality of connections so that each connection from the plurality of connections only transports packets from the second plurality of packets that encapsulate packets from the first plurality that have a same packet type.

IPC Classes  ?

  • H04L 12/28 - Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
  • H04L 49/552 - Prevention, detection or correction of errors by ensuring the integrity of packets received through redundant connections
  • H04L 49/9057 - Arrangements for supporting packet reassembly or resequencing
  • H04L 49/25 - Routing or path finding in a switch fabric
  • H04L 45/44 - Distributed routing
  • H04L 47/24 - Traffic characterised by specific attributes, e.g. priority or QoS
  • H04L 47/34 - Flow controlCongestion control ensuring sequence integrity, e.g. using sequence numbers
  • H04L 47/10 - Flow controlCongestion control
  • H04L 47/30 - Flow controlCongestion control in combination with information about buffer occupancy at either end or at transit nodes
  • H04L 12/54 - Store-and-forward switching systems
  • H04L 12/70 - Packet switching systems

4.

Heterogeneous packet-based transport

      
Application Number 16892177
Grant Number 10848442
Status In Force
Filing Date 2020-06-03
First Publication Date 2020-09-17
Grant Date 2020-11-24
Owner Missing Link Electronics, Inc. (USA)
Inventor
  • Schubert, Nils Endric
  • Epping, David
  • Braun, Andreas
  • Langenblach, Ulrich

Abstract

For secure transport, when receiving a plurality of packets from a root complex where contents of each packet from the plurality of packets organized in accordance with a first protocol, a sequence number is added to each packet and a packet type is identified. Every packet in the first plurality of packets is encrypted and encapsulated into at least one packet organized in accordance with a second protocol to form a second plurality of packets organized in accordance with the second protocol. All the packets from the second plurality of packets are sent via a plurality of connections so that each connection from the plurality of connections only transports packets from the second plurality of packets that encapsulate packets from the first plurality that have a same packet type.

IPC Classes  ?

  • H04J 3/22 - Time-division multiplex systems in which the sources have different rates or codes
  • H04L 12/939 - Provisions for redundant switching, e.g. using parallel switching planes
  • H04L 12/861 - Packet buffering or queuing arrangements; Queue scheduling
  • H04L 12/947 - Address processing within a device, e.g. using internal ID or tags for routing within a switch
  • H04L 12/721 - Routing procedures, e.g. shortest path routing, source routing, link state routing or distance vector routing
  • H04L 12/851 - Traffic type related actions, e.g. QoS or priority
  • H04L 12/54 - Store-and-forward switching systems
  • H04L 12/801 - Flow control or congestion control
  • H04L 12/835 - Bitrate adaptation in active flows using buffer capacity information at the endpoints or transit nodes
  • H04L 12/70 - Packet switching systems

5.

Heterogeneous packet-based transport

      
Application Number 16055864
Grant Number 10708199
Status In Force
Filing Date 2018-08-06
First Publication Date 2019-02-21
Grant Date 2020-07-07
Owner Missing Link Electronics, Inc. (USA)
Inventor
  • Schubert, Nils Endric
  • Epping, David
  • Braun, Andreas
  • Langenbach, Ulrich

Abstract

Deadlocks in a heterogeneous packet-based transport system are avoided. When receiving a plurality of packets from a root complex where contents of each packet from the plurality of packets organized in accordance with a first protocol, a sequence number is added to each packet and a packet type is identified. Every packet in the first plurality of packets is encapsulated into at least one packet organized in accordance with a second protocol to form a second plurality of packets organized in accordance with the second protocol. All the packets from the second plurality of packets are sent via a plurality of connections so that each connection from the plurality of connections only transports packets from the second plurality of packets that encapsulate packets from the first plurality that have a same packet type.

IPC Classes  ?

  • H04J 3/22 - Time-division multiplex systems in which the sources have different rates or codes
  • H04L 12/939 - Provisions for redundant switching, e.g. using parallel switching planes
  • H04L 12/861 - Packet buffering or queuing arrangements; Queue scheduling
  • H04L 12/947 - Address processing within a device, e.g. using internal ID or tags for routing within a switch
  • H04L 12/721 - Routing procedures, e.g. shortest path routing, source routing, link state routing or distance vector routing
  • H04L 12/851 - Traffic type related actions, e.g. QoS or priority
  • H04L 12/54 - Store-and-forward switching systems
  • H04L 12/801 - Flow control or congestion control
  • H04L 12/835 - Bitrate adaptation in active flows using buffer capacity information at the endpoints or transit nodes
  • H04L 12/70 - Packet switching systems

6.

HETEROGENEOUS PACKET-BASED TRANSPORT

      
Application Number US2018045438
Publication Number 2019/036217
Status In Force
Filing Date 2018-08-06
Publication Date 2019-02-21
Owner MISSING LINK ELECTRONICS, INC. (USA)
Inventor
  • Schubert, Nils Endric
  • Epping, David
  • Braun, Andreas
  • Langenblach, Ulrich

Abstract

Deadlocks in a heterogeneous packet-based transport system are avoided. When receiving a plurality of packets from a root complex where contents of each packet from the plurality of packets organized in accordance with a first protocol, a sequence number is added to each packet and a packet type is identified. Every packet in the first plurality of packets is encapsulated into at least one packet organized in accordance with a second protocol to form a second plurality of packets organized in accordance with the second protocol. All the packets from the second plurality of packets are sent via a plurality of connections so that each connection from the plurality of connections only transports packets from the second plurality of packets that encapsulate packets from the first plurality that have a same packet type.

IPC Classes  ?

  • H04L 12/56 - Packet switching systems
  • H04L 12/801 - Flow control or congestion control
  • H04L 12/861 - Packet buffering or queuing arrangements; Queue scheduling
  • H04L 29/06 - Communication control; Communication processing characterised by a protocol

7.

Automation for configurable mixed-signal systems

      
Application Number 14419643
Grant Number 10509880
Status In Force
Filing Date 2013-08-16
First Publication Date 2015-08-20
Grant Date 2019-12-17
Owner Missing Link Electronics, Inc. (USA)
Inventor
  • Schubert, Nils Endric
  • Brock, Johannes
  • Grumbein, Christian

Abstract

Configuration information is generated for a configurable mixed-signal system. Analog requirements for operating the configurable mixed-signal system are gathered. A simulation model of a delta-sigma modulator is received. A simulation based on the simulation model of the delta-sigma modulator is performed to obtain parameter settings for the delta-sigma modulator. The obtained parameter settings are used to build at least a portion of a description of the configurable mixed-signal system. The description of the configurable mixed signal system is synchronized to receive configuration information.

IPC Classes  ?

  • G06F 17/50 - Computer-aided design
  • H03M 3/00 - Conversion of analogue values to or from differential modulation
  • H03M 7/32 - Conversion to or from delta modulation, i.e. one-bit differential modulation

8.

Configurable mixed-signal systems

      
Application Number 14419642
Grant Number 09209828
Status In Force
Filing Date 2013-08-16
First Publication Date 2015-06-25
Grant Date 2015-12-08
Owner Missing Link Electronics, Inc. (USA)
Inventor
  • Schubert, Nils Endric
  • Brock, Johannes
  • Grumbein, Christian

Abstract

An electronic system includes a configurable processing device. The configurable processing device includes a processor that performs digital processing, a first input that receives digital signal, a first output that sends digital signal and a converter that converts between analog and digital signals. The converter includes a delta-sigma modulator.

IPC Classes  ?

  • H03M 3/00 - Conversion of analogue values to or from differential modulation
  • G06F 17/50 - Computer-aided design
  • H03M 7/30 - CompressionExpansionSuppression of unnecessary data, e.g. redundancy reduction

9.

Partitioning systems operating in multiple domains

      
Application Number 14373023
Grant Number 10140049
Status In Force
Filing Date 2013-02-23
First Publication Date 2014-12-25
Grant Date 2018-11-27
Owner Missing Link Electronics, Inc. (USA)
Inventor
  • Schubert, Nils Endric
  • Eckstein, Felix

Abstract

Within a partitioned system, a first system partition operates in a safety domain in which predictable operation of the first system partition is necessary to protect the system or operators of the system from harm. A second system partition operates in a user domain in which information supplied by the second system partition is not sufficiently reliable to be used by the first system partition within the safety domain. A mediator controller is connected between the first system partition and the second system partition. The mediator controller receives the information supplied by the first system partition. The mediator controller monitors and supervises use of the information by the second system partition in order maintain requirements of the safety domain to protect the system or operators of the system from harm.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F 21/53 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by executing in a restricted environment, e.g. sandbox or secure virtual machine
  • G06F 21/55 - Detecting local intrusion or implementing counter-measures
  • H04L 29/08 - Transmission control procedure, e.g. data link level control procedure
  • H04L 29/06 - Communication control; Communication processing characterised by a protocol

10.

CONFIGURABLE MIXED-SIGNAL SYSTEMS

      
Application Number US2013055466
Publication Number 2014/031496
Status In Force
Filing Date 2013-08-16
Publication Date 2014-02-27
Owner MISSING LINK ELECTRONICS, INC. (USA)
Inventor
  • Schubert, Nils Endric
  • Brock, Johannes
  • Grumbein, Christian

Abstract

An electronic system includes a configurable processing device. The configurable processing device includes a processor that performs digital processing, a first input that receives digital signal, a first output that sends digital signal and a converter that converts between analog and digital signals. The converter includes a delta-sigma modulator.

IPC Classes  ?

  • H03M 3/02 - Delta modulation, i.e. one-bit differential modulation
  • H03M 7/30 - CompressionExpansionSuppression of unnecessary data, e.g. redundancy reduction

11.

DESIGN AUTOMATION FOR CONFIGURABLE MIXED-SIGNAL SYSTEMS

      
Application Number US2013055471
Publication Number 2014/031497
Status In Force
Filing Date 2013-08-16
Publication Date 2014-02-27
Owner MISSING LINK ELECTRONICS, INC. (USA)
Inventor
  • Schubert, Nils Endric
  • Brock, Johannes
  • Grumbein, Christian

Abstract

Configuration information is generated for a configurable mixed-signal system. Analog requirements for operating the configurable mixed-signal system are gathered. A simulation model of a delta-sigma modulator is received. A simulation based on the simulation model of the delta-sigma modulator is performed to obtain parameter settings for the delta-sigma modulator. The obtained parameter settings are used to build at least a portion of a description of the configurable mixed-signal system. The description of the configurable mixed signal system is synchronized to receive configuration information.

IPC Classes  ?

  • G06F 17/50 - Computer-aided design
  • H03M 7/30 - CompressionExpansionSuppression of unnecessary data, e.g. redundancy reduction
  • H03M 3/00 - Conversion of analogue values to or from differential modulation

12.

PARTITIONING SYSTEMS OPERATING IN MULTIPLE DOMAINS

      
Application Number US2013027528
Publication Number 2013/126852
Status In Force
Filing Date 2013-02-23
Publication Date 2013-08-29
Owner MISSING LINK ELECTRONICS, INC. (USA)
Inventor
  • Schubert, Nils, Endric
  • Eckstein, Felix

Abstract

Within a partitioned system, a first system partition operates in a safety domain in which predictable operation of the first system partition is necessary to protect the system or operators of the system from harm. A second system partition operates in a user domain in which information supplied by the second system partition is not sufficiently reliable to be used by the first system partition within the safety domain. A mediator controller is connected between the first system partition and the second system partition. The mediator controller receives the information supplied by the first system partition. The mediator controller monitors and supervises use of the information by the second system partition in order maintain requirements of the safety domain to protect the system or operators of the system from harm.

IPC Classes  ?