09 - Scientific and electric apparatus and instruments
Goods & Services
Downloadable and recorded computer software for use in
programming, reading, writing, verifying, and executing
internal and external memories of microcontrollers and
microprocessors; downloadable and recorded computer software
for bootloader and firmware uploading, configuration, and
management; downloadable and recorded computer software for
in-system programming of ARM-based microcontrollers and
microprocessors; downloadable and recorded software
development tools for embedded systems; downloadable and
recorded computer software for data transfer between host
computers and microcontroller or microprocessor-based
devices; downloadable and recorded instruction manuals sold
as a unit with all the foregoing software.
2.
DEVICE, SYSTEM AND METHODS FOR A TEMPERATURE COMPENSATED CURRENT REFERENCE
An apparatus may include a current mirror circuit, a cascode circuit, and a current generator circuit. The current generator circuit may produce a Proportional-to-Absolute-Temperature (PTAT) current and a Complementary-to-Absolute-Temperature (CTAT) current. The PTAT current and the CTAT current may be based on a first impedance and a second impedance. A combination of the PTAT current and the CTAT current may serve as a current reference. The values of the first impedance and the second impedance may be chosen to reduce the first-order temperature variation in the current reference. The inversion coefficient of the current generation devices may be modified to reduce the second-order temperature variation in the current reference.
A data storage system includes, a memory device including a virtual block, non-transitory computer readable media storing instructions thereon, and at least one processor. The instructions, when executed by the at least one processor, cause the at least one processor to: measure a program temperature associated with the virtual block; measure a read temperature associated with the virtual block; determine, based at least in part on the measured program temperature and the measured read temperature, a cross-temperature condition; and based on the determined cross-temperature condition, determine an adjusted voltage. The adjusted voltage includes one or more of: an adjusted pass through voltage, an adjusted bit line bias voltage, or an adjusted source line voltage.
A system and method for an automated interfacing system for docking a mobility aid with target platforms are disclosed. The method may include detecting, by a mobility aid equipped with a plurality of antennas, a presence of a target platform equipped with an antenna. The method may also include establishing a connection between the mobility aid and the target platform. The method may further include determining a relative position and an orientation between the mobility aid and the target platform. The method may be to generating a docking route to the target platform based on the determined relative position and orientation.
A High-Electron-Mobility-Transistor comprising an upper insulating layer formed over a second buffer layer formed over a second barrier layer formed over a first buffer layer formed over a first barrier layer formed over a first doped structure and formed over a substrate. A second doped structure formed within the second barrier layer. A first gate electrode connected to the first doped structure. A second gate electrode connected to the second doped structure. A drain terminal formed at a first side of the first gate electrode. A source terminal formed at a second side of the first gate electrode.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
A method performed by a semi-autonomous or autonomous robot comprising retrieving a sensor pack from a deployment location near a first equipment to be monitored, the sensor pack including a processor, a non-transitory computer readable memory, a battery, a data port, and at least one sensor; deploying the sensor pack to the first equipment; retrieving the sensor pack from the first equipment; charging the battery of the sensor pack; downloading sensor data from the sensor pack; and sending downloaded sensor data from the sensor pack to a processor remote from the deployment location.
G01D 21/00 - Measuring or testing not otherwise provided for
B25J 5/00 - Manipulators mounted on wheels or on carriages
B25J 19/00 - Accessories fitted to manipulators, e.g. for monitoring, for viewingSafety devices combined with or specially adapted for use in connection with manipulators
Systems and methods are provided for receiving, decoding, encoding, and transmitting signals for an NFC Type A device using a configurable logic block (CLB) to receive a data signal, generate a start signal indicating that a start bit has been detected, generate a data high signal indicating that a logic high value has been detected, generate a data sample signal indicating a sampling time for the receive data signal, generate an end of data signal indicating that an end of the receive data signal has been detected, and generate a transmit data signal. The systems and methods may include instructions executed by a microprocessor to use the CLB-generated signals to process the receive data signal and to transmit data.
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
G06K 7/10 - Methods or arrangements for sensing record carriers by electromagnetic radiation, e.g. optical sensingMethods or arrangements for sensing record carriers by corpuscular radiation
H04B 5/20 - Near-field transmission systems, e.g. inductive or capacitive transmission systems characterised by the transmission techniqueNear-field transmission systems, e.g. inductive or capacitive transmission systems characterised by the transmission medium
A system, and method for automatically updating configuration or software information on a device without a connection to a central server are disclosed. A first device may include a memory of the first device to store a first configuration. The first device may also include a timer to indicate an age of the first configuration stored in the memory. The first device may further include a control circuit of the first device. The control circuit may be configured to determine, based on the age of the first configuration, that the first device has golden unit status and broadcast a status that the first device is a golden unit. The control circuit may additionally be configured to establish a communication channel between the first device and a second device. The control circuit may further be configured to transfer the first configuration from the first device to the second device.
An apparatus may have a detector (30) configured to fit substantially within a utility box (20) installed in a cavity (15) of a ceiling (10) or a wall in a room, a wiring assembly (40) configured to couple the detector to a power source, and an attachment assembly (50) configured to attach the detector to the utility box, wherein the detector may be recessed within the utility box when attached to the utility box.
An apparatus and method are disclosed for error correction in Reed-Solomon (RS) code decoders. The apparatus may include a receiver configured to receive flow control unit (FLIT) blocks from a transmitter, wherein the FLIT blocks are encoded using Reed-Solomon codes with predefined burst error characteristics for transmission across one or more lanes. A FLIT block processing unit organizes and processes the FLIT blocks for decoding. An error locator polynomial computation module identifies error locations by generating an error locator polynomial based on the FLIT blocks, determining a symmetrical error pattern from the predefined burst error characteristics, defining a constrained polynomial root search space based on the symmetrical error pattern, and determining roots of the error locator polynomial within the constrained search space to identify error locations. An error magnitude computation module determines error magnitudes corresponding to the identified error locations using a direct computation method.
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
11.
ELECTRONIC OBJECT INSIDE WASHING MACHINE DRUM DETECTION SYSTEM
A system and method for detecting electronic objects in a washing machine are provided. The system may include a washing machine drum to hold laundry items, a metal detector sensor positioned to monitor objects entering the drum, a decision-making circuit to process signals from the metal detector sensor and identify electronic objects based on detected electromagnetic characteristics, and an alert circuit to notify a user upon detection of an electronic object.
G01V 3/10 - Electric or magnetic prospecting or detectingMeasuring magnetic field characteristics of the earth, e.g. declination or deviation operating with magnetic or electric fields produced or modified by objects or geological structures or by detecting devices using induction coils
D06F 34/05 - Signal transfer or data transmission arrangements for wireless communication between components, e.g. for remote monitoring or control
D06F 34/14 - Arrangements for detecting or measuring specific parameters
D06F 34/28 - Arrangements for program selection, e.g. control panels thereforArrangements for indicating program parameters, e.g. the selected program or its progress
D06F 103/00 - Parameters monitored or detected for the control of domestic laundry washing machines, washer-dryers or laundry dryers
D06F 105/58 - Indications or alarms to the control system or to the user
12.
SYSTEM AND METHOD FOR DETECTING DEVIATIONS IN HARDWARE TIMERS
Systems and methods are disclosed for detecting deviations in hardware timer operations. A system may include a first timer driven by a first clock source to produce a first timer value, while a second timer may be driven by a second, independent clock source to produce a second timer value. A deviation logic hardware block may compute a complement of the first timer value, calculate a difference between the complemented value and the second timer value, and compare the difference to a deviation limit to determine whether a deviation has occurred.
A system, apparatus, and method for charging an unmanned aerial vehicle using rail electrified at ground-level are disclosed. The apparatus may include a power management circuit interface. The apparatus may also include a navigation circuit interface. The apparatus may further include a control circuit. The control circuit may be to navigate an unmanned aerial vehicle (UAV) to a rail based on information received via the navigation circuit interface. The rail may be configured to be electrified at ground-level. The control circuit may also be to instruct the UAV to couple a charging contact on the UAV with a charging contact coupled to the rail. The control circuit may additionally be to coordinate a charging operation between the UAV and the rail via the power management circuit interface. The control circuit may further be to instruct the UAV to disengage the charging contact on completion of the charging operation.
A method is provided comprising communicating with a semi-autonomous or autonomous robot to coordinate retrieval of a sensor pack from a location proximate the first equipment; retrieving sensor data from the sensor pack; inputting the data from the sensor pack to a machine learning model; decoding a response from the machine learning model to identify a specific intervention; and dispatching the semi-autonomous or autonomous robot to the first equipment to perform an intervention.
An apparatus may include a current mirror circuit, a cascode circuit and a current generator circuit. The current generator circuit may produce a Proportional-to-Absolute Temperature (PTAT) current and a Complementary-to-Absolute Temperature (CTAT) current. The PTAT current and the CTAT current may be based on a first impedance and a second impedance. A combination of the PTAT current and the CTAT current may be a current reference. The values of the first impedance and the second impedance may be chosen to reduce the first-order temperature coefficient of the current reference and the current reference may be a first-order temperature-compensated current reference.
G05F 3/22 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations wherein the transistors are of the bipolar type only
G05F 3/24 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations wherein the transistors are of the field-effect type only
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03K 3/011 - Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
A Schottky barrier diode (SBD) includes a volume of semiconductor material, a plurality of laterally spaced pockets of doped material, and a silicon layer. The volume of semiconductor material presents opposite first and second ends. The plurality of laterally spaced pockets of doped material extend into the volume of semiconductor material adjacent the first end. The silicon layer is located adjacent the first end between the pockets of doped material.
A Schottky barrier diode (SBD) comprises a volume of semiconductor material presenting opposite first and second ends, a plurality of laterally spaced pockets of doped material extending into the volume of semiconductor material adjacent the first end, a Schottky layer located adjacent the first end between the pockets of doped material of doped material, and a silicide layer located adjacent each pocket of doped material. The Schottky and silicide layers include dissimilar metals.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 64/64 - Electrodes comprising a Schottky barrier to a semiconductor
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
18.
ELECTRONIC OBJECT INSIDE WASHING MACHINE DRUM DETECTION SYSTEM
A system and method for detecting electronic objects in a washing machine are provided. The system may include a washing machine drum to hold laundry items, a metal detector sensor positioned to monitor objects entering the drum, a decision-making circuit to process signals from the metal detector sensor and identify electronic objects based on detected electromagnetic characteristics, and an alert circuit to notify a user upon detection of an electronic object.
Disclosed herein are apparatus, system, method, and computer-readable medium aspects for error correction in a PCI Express (PCIe) Forward Error Correction (FEC) system. An example method may include receiving an FEC block comprising interleaved Reed-Solomon (RS) codewords, decoding the FEC block using a standard decoder to correct up to three successive RS symbol errors, and if the standard decoder fails, attempting error correction using one or more parallel decoders, comprising at least a 4-burst decoder to correct a single burst error spanning four RS symbols. The method may include selecting a corrected FEC block from an output of one of the standard decoder and the one or more parallel decoders based on successful error correction. The one or more parallel decoders can further comprise a 5-burst decoder and a 6-burst decoder.
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H03M 13/17 - Burst error correction, e.g. error trapping, Fire codes
20.
HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR MANUFACTURING SAME
A High-Electron-Mobility-Transistor comprising an upper insulating layer formed over a second buffer layer formed over a second barrier layer formed over a first buffer layer formed over a first barrier layer formed over a first doped structure and formed over a substrate. A second doped structure formed within the second barrier layer. A first gate electrode connected to the first doped structure. A second gate electrode connected to the second doped structure. A drain terminal formed at a first side of the first gate electrode. A source terminal formed at a second side of the first gate electrode.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
21.
DEVICE, SYSTEM AND METHODS FOR A TEMPERATURE-COMPENSATED CURRENT REFERENCE
An apparatus may include a current mirror circuit, a cascode circuit, and a current generator circuit. The current generator circuit may produce a Proportional-to-Absolute-Temperature (PTAT) current and a Complementary-to-Absolute-Temperature (CTAT) current. The PTAT current and the CTAT current may be based on a first impedance and a second impedance. A combination of the PTAT current and the CTAT current may serve as a current reference. The values of the first impedance and the second impedance may be chosen to reduce the first-order temperature variation in the current reference. The inversion coefficient of the current generation devices may be modified to reduce the second-order temperature variation in the current reference.
G05F 3/24 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations wherein the transistors are of the field-effect type only
G05F 3/30 - Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities
22.
TRANSFERRING CONFIGURATION INFORMATION FROM A FIRST DEVICE TO A SECOND DEVICE BASED ON THE STATUS OF THE FIRST DEVICE
A system, and method for automatically updating configuration or software information on a device without a connection to a central server are disclosed. A first device may include a memory of the first device to store a first configuration. The first device may also include a timer to indicate an age of the first configuration stored in the memory. The first device may further include a control circuit of the first device. The control circuit may be configured to determine, based on the age of the first configuration, that the first device has golden unit status and broadcast a status that the first device is a golden unit. The control circuit may additionally be configured to establish a communication channel between the first device and a second device. The control circuit may further be configured to transfer the first configuration from the first device to the second device.
A method may include receiving signaling at a system basis chip implementing a transceiver of a 10SPE PHY; changing, at the system basis chip, the signaling from first voltage levels incompatible with a voltage domain of a microcontroller (MCU) implementing a controller of the 10SPE PHY to second voltage levels compatible with the voltage domain of the MCU; and communicating the changed signaling to the MCU.
Disclosed herein are apparatus, system, method, and computer-readable medium aspects for error correction in a PCI Express (PCIe) Forward Error Correction (FEC) system. An example method may include receiving an FEC block comprising interleaved Reed-Solomon (RS) codewords, decoding the FEC block using a standard decoder to correct up to three successive RS symbol errors, and if the standard decoder fails, attempting error correction using one or more parallel decoders, comprising at least a 4-burst decoder to correct a single burst error spanning four RS symbols. The method may include selecting a corrected FEC block from an output of one of the standard decoder and the one or more parallel decoders based on successful error correction. The one or more parallel decoders can further comprise a 5-burst decoder and a 6-burst decoder.
An apparatus and method are disclosed for error correction in Reed-Solomon (RS) code decoders. The apparatus may include a receiver configured to receive flow control unit (FLIT) blocks from a transmitter, wherein the FLIT blocks are encoded using Reed-Solomon codes with predefined burst error characteristics for transmission across one or more lanes. A FLIT block processing unit organizes and processes the FLIT blocks for decoding. An error locator polynomial computation module identifies error locations by generating an error locator polynomial based on the FLIT blocks, determining a symmetrical error pattern from the predefined burst error characteristics, defining a constrained polynomial root search space based on the symmetrical error pattern, and determining roots of the error locator polynomial within the constrained search space to identify error locations. An error magnitude computation module determines error magnitudes corresponding to the identified error locations using a direct computation method.
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
A Schottky barrier diode (SBD) comprises a volume of semiconductor material presenting opposite first and second ends, a plurality of laterally spaced pockets of doped material extending into the volume of semiconductor material adjacent the first end, a Schottky layer located adjacent the first end between the pockets of doped material of doped material, and a silicide layer located adjacent each pocket of doped material. The Schottky and silicide layers include dissimilar metals
A Schottky barrier diode (SBD) includes a volume of semiconductor material, a plurality of laterally spaced pockets of doped material, and a silicon layer. The volume of semiconductor material presents opposite first and second ends. The plurality of laterally spaced pockets of doped material extend into the volume of semiconductor material adjacent the first end. The silicon layer is located adjacent the first end between the pockets of doped material.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/64 - Electrodes comprising a Schottky barrier to a semiconductor
28.
SINGLE AND DUAL-EDGE TRIGGERED PHASE ERROR DETECTION
An example apparatus includes a sampling clock divider, a phase detector and a digital discriminator. The sampling clock divider generates a divided reference clock and a divided feedback clock by dividing a reference clock and a feedback clock, respectively using a sampling rate. The phase detector receives the divided reference clock and the divided feedback clock and sets status signal. The digital discriminator to receive samples of the status signal at the sampling rate and generate a locked status signal indicative of a locked status of a clock tracking circuit at least partially based on the samples of the status signal. Another apparatus may comprise a phase detector, a sampling logic circuit, a decimator, an interpolator, a multiplexer, and a digital discriminator.
H03L 7/091 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/095 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
An apparatus includes a control circuit to connect to an audio device of a safety system. The safety system is to detect a hazardous condition. The audio device is to alert a user of the hazardous condition. The safety system is to include a sensor to sense the hazardous condition. The apparatus includes an interface to connect the control circuit to the audio device. The control circuit is to determine whether to clean a housing of the sensor and, based on a determination to clean the housing of sensor, cause the audio device to vibrate or issue sound waves at an inaudible frequency.
B08B 7/02 - Cleaning by methods not provided for in a single other subclass or a single group in this subclass by distortion, beating, or vibration of the surface to be cleaned
B08B 5/02 - Cleaning by the force of jets, e.g. blowing-out cavities
A semiconductor device including a volume of semiconductor material, an integrated metal-oxide semiconductor field-effect transistor (MOSFET), and an integrated Schottky barrier diode (SBD). The volume of semiconductor material presents laterally spaced first and second sides and a trench. The trench extends from the first end and is spaced between the sides. The MOSFET includes a split gate comprising a first gate section located within the trench and a laterally spaced apart second gate section located within the trench. The SBD is located within the trench. The SBD includes a Schottky metal.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
An apparatus may have a detector configured to fit substantially within a utility box installed in a cavity of a ceiling or a wall in a room, a wiring assembly configured to couple the detector to a power source, and an attachment assembly configured to attach the detector to the utility box, wherein the detector may be recessed within the utility box when attached to the utility box.
A trench MOSFET with a trench bottom oxide thickness that is equal to or greater than a trench sidewall oxide thickness, and a method of making the same. A trench, including a sidewall and a bottom, is created in a semiconductor material. A first bottom thickness of a gate oxide is deposited on the bottom, and a first sidewall thickness of the gate oxide is deposited on the sidewall. The first sidewall thickness is removed, leaving the first bottom thickness. A second sidewall thickness is grown on the sidewall of the trench, and a second bottom thickness is grown on top of the first bottom thickness. The first and second bottom thicknesses of the gate oxide form a total bottom thickness that is at least equal to the second sidewall thickness, and may be between one (1) and two (2) times greater than the second sidewall thickness.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
A data storage device with adjustable power credit allocation, and a method of providing adjustable power credit allocation in a data storage device. The device includes a non-volatile memory media and a controller. Relevant operating conditions are quantified, including a number of program/erase cycles completed by the memory media and a temperature of the controller. Recommended power credit numbers are determined for relevant commands, including read, write, and erase, based on the quantified operating conditions. The power credit allocation for the data storage device is adjusted based on the determined recommended power credit numbers. More or fewer program/erase cycles may result in, respectively, raising or lowering the power credit allocation. Higher or lower temperatures may result in, respectively, lowering or raising the power credit allocation. The controller may adjust the power credit allocation based on the plurality of recommended power credit numbers using a look-up table or using a formula.
Systems and methods are provided for receiving, decoding, encoding, and transmitting signals for an NFC Type A device using a configurable logic block (CLB) to receive a data signal, generate a start signal indicating that a start bit has been detected, generate a data high signal indicating that a logic high value has been detected, generate a data sample signal indicating a sampling time for the receive data signal, generate an end of data signal indicating that an end of the receive data signal has been detected, and generate a transmit data signal. The systems and methods may include instructions executed by a microprocessor to use the CLB-generated signals to process the receive data signal and to transmit data.
H04B 5/20 - Near-field transmission systems, e.g. inductive or capacitive transmission systems characterised by the transmission techniqueNear-field transmission systems, e.g. inductive or capacitive transmission systems characterised by the transmission medium
H04B 5/70 - Near-field transmission systems, e.g. inductive or capacitive transmission systems specially adapted for specific purposes
35.
Device and Method for Robotic Predictive Maintenance
A method performed by a semi-autonomous or autonomous robot comprising retrieving a sensor pack from a deployment location near a first equipment to be monitored, the sensor pack including a processor, a non-transitory computer readable memory, a battery, a data port, and at least one sensor; deploying the sensor pack to the first equipment; retrieving the sensor pack from the first equipment; charging the battery of the sensor pack; downloading sensor data from the sensor pack; and sending downloaded sensor data from the sensor pack to a processor remote from the deployment location.
B62D 57/032 - Vehicles characterised by having other propulsion or other ground-engaging means than wheels or endless track, alone or in addition to wheels or endless track with ground-engaging propulsion means, e.g. walking members with alternately or sequentially lifted supporting base and legVehicles characterised by having other propulsion or other ground-engaging means than wheels or endless track, alone or in addition to wheels or endless track with ground-engaging propulsion means, e.g. walking members with alternately or sequentially lifted feet or skid
36.
Device and Method for Robotic Predictive Maintenance, Diagnostics, and Component Replacement
A method is provided comprising communicating with a semi-autonomous or autonomous robot to coordinate retrieval of a sensor pack from a location proximate the first equipment; retrieving sensor data from the sensor pack; inputting the data from the sensor pack to a machine learning model; decoding a response from the machine learning model to identify a specific intervention; and dispatching the semi-autonomous or autonomous robot to the first equipment to perform an intervention.
G05D 1/689 - Pointing payloads towards fixed or moving targets
G05B 13/02 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric
G05D 105/80 - Specific applications of the controlled vehicles for information gathering, e.g. for academic research
A semiconductor device including a volume of semiconductor material, an integrated metal-oxide semiconductor field-effect transistor (MOSFET), and an integrated Schottky barrier diode (SBD). The volume of semiconductor material presents laterally spaced first and second sides and a trench extending from the first end and being spaced between the sides. The MOSFET includes a split gate comprising a first gate section located adjacent the first end and a laterally spaced apart second gate section located adjacent the first end, and a gate oxide underlying the first and second gate sections. The SBD is located within the trench. The SBD includes a Schottky metal.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
A trench MOSFET with a trench bottom oxide thickness that is equal to or greater than a trench sidewall oxide thickness, and a method of making the same. A trench, including a sidewall and a bottom, is created in a semiconductor material. A first bottom thickness of a gate oxide is deposited on the bottom, and a first sidewall thickness of the gate oxide is deposited on the sidewall. The first sidewall thickness is removed, leaving the first bottom thickness. A second sidewall thickness is grown on the sidewall of the trench, and a second bottom thickness is grown on top of the first bottom thickness. The first and second bottom thicknesses of the gate oxide form a total bottom thickness that is at least equal to the second sidewall thickness, and may be between one (1) and two (2) times greater than the second sidewall thickness.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
A data storage device with adjustable power credit allocation, and a method of providing adjustable power credit allocation in a data storage device. The device includes a non-volatile memory media and a controller. Relevant operating conditions are quantified, including a number of program/erase cycles completed by the memory media and a temperature of the controller. Recommended power credit numbers are determined for relevant commands, including read, write, and erase, based on the quantified operating conditions. The power credit allocation for the data storage device is adjusted based on the determined recommended power credit numbers. More or fewer program/erase cycles may result in, respectively, raising or lowering the power credit allocation. Higher or lower temperatures may result in, respectively, lowering or raising the power credit allocation. The controller may adjust the power credit allocation based on the plurality of recommended power credit numbers using a look-up table or using a formula.
A semiconductor device including a volume of semiconductor material, an integrated metal-oxide semiconductor field-effect transistor (MOSFET), and an integrated Schottky barrier diode (SBD). The volume of semiconductor material presents laterally spaced first and second sides and a trench extending from the first end and being spaced between the sides. The MOSFET includes a split gate comprising a first gate section located adjacent the first end and a laterally spaced apart second gate section located adjacent the first end, and a gate oxide underlying the first and second gate sections. The SBD is located within the trench. The SBD includes a Schottky metal.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
41.
SEMICONDUCTOR DEVICE HAVING INTEGRATED PLANAR MOSFETS AND AN INTEGRATED TRENCH SCHOTTKY BARRIER DIODE
A semiconductor device comprising a volume of semiconductor material including a first end, a second end spaced vertically from the first end, a first side, and a second side spaced laterally from the first side; a first integrated planar MOSFET located at the first side of the volume of semiconductor material; a second integrated planar MOSFET located at the second side of the volume of semiconductor material; and a trench located at the first end of the volume of semiconductor material between the first and second integrated planar MOSFETs. An integrated trench Schottky barrier diode comprising a Schottky metal is located within the trench. Methods for making the semiconductor device are also disclosed.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
A microcontroller having error injection circuitry is provided. The microcontroller may include one or more operational components, and an error injection circuity operatively coupled to the one or more operational components. The error injection circuitry may autonomously inject one or more errors into the one or more operational components, and guard one or more error channels associated with the one or more operational components during the injection of the one or more errors.
G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 11/277 - Tester hardware, i.e. output processing circuits with comparison between actual response and known fault-free response
43.
INPUT CIRCUITRY FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
Numerous embodiments of input circuitry for an analog neural memory in a deep learning artificial neural network are disclosed. In one example, an input block for providing an input to a vector-by-matrix multiplication array in a neural memory system, the vector-by-matrix multiplication array comprising non-volatile memory cells arranged in rows and columns, comprises a digital-to-analog converter; a voltage-to-current converter to generate a current responsive to an output of the digital-to-analog converter; and a current to voltage logarithmic converter for generating a voltage that is a function of a logarithm of the current.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
44.
MICROCONTROLLER WITH ERROR INJECTION CIRCUITRY AND METHOD OF USING SAME
A microcontroller having error injection circuitry is provided. The microcontroller may include one or more operational components, and an error injection circuity operatively coupled to the one or more operational components. The error injection circuitry may autonomously inject one or more errors into the one or more operational components, and guard one or more error channels associated with the one or more operational components during the injection of the one or more errors.
Examples include managing address space in a register bank of a system basis chip. An apparatus includes a bus slave and a system basis chip including a register bank, an access controller to confine reach of the bus slave to a select set of addresses of the register bank, and an address space manager to set the select set of addresses of the register bank.
One or more examples of systems, methods and devices are disclosed for provisioning a headless WiFi device. A method may include: inferring a channel identifier of a desired WiFi router access point, establishing a communication link with a provisioning WiFi device utilizing the channel identifier, and establishing a communication link with the WiFi router access point utilizing a channel identifier provided by the provisioning WiFi device.
Disclosed herein are apparatus, system, method, and computer-readable medium aspects for limiting re-rush current in a power supply system. An example method may include detecting an AC power dropout event, activating a battery backup unit (BBU) to supply energy, charging a bulk capacitor of a power factor correction stage within a power supply unit during the AC power dropout event using energy stored in the BBU, and resuming power conversion in the power supply system in response to restoration of AC power with limited or no re-rush current.
G06F 1/30 - Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
H02J 9/06 - Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
An apparatus may include a physical layer device, a detection circuitry and a power control circuitry. The physical layer device provides one or more functions of a physical layer to interface with a shared physical transmission medium. The detection circuitry detects an indication of power control signaling on the shared physical transmission medium, and detects an indication of Ethernet signaling on the shared physical transmission medium. The indication of power control signaling is different than the indication of Ethernet signaling. The power control circuitry manages a power state of the apparatus at least partially responsive to an output of the detection circuitry.
Disclosed herein are apparatus, system, method, and computer-readable medium aspects for limiting re-rush current in a power supply system. An example method may include detecting an AC power dropout event, activating a battery backup unit (BBU) to supply energy, charging a bulk capacitor of a power factor correction stage within a power supply unit during the AC power dropout event using energy stored in the BBU, and resuming power conversion in the power supply system in response to restoration of AC power with limited or no re-rush current.
H02J 9/06 - Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over
50.
SYSTEM AND METHOD TO PROVISION STORAGE USING NON-CONTIGUOUS STORAGE SPACE
Systems and methods to chain smaller non-contiguous free chunks in non-volatile memory to form a logical storage volume which is greater than any of the constituent free chunks. These comprise: identifying a plurality of free chunks of available storage in a storage array; identifying a start block offset and a number of blocks of respective ones of the plurality of free chunks; creating a logical volume by chaining the plurality of free chunks, wherein blocks are provisioned in the logical volume beginning at a first free chunk start block offset for a first free chunk number of blocks, continuing to provision blocks in the logical volume at a second free chunk start block offset for a second free chunk number of blocks, and continuing to provision blocks in the logical volume until the plurality of free chunks are provisioned in the logical volume.
Systems and methods to chain smaller non-contiguous free chunks in non-volatile memory to form a logical storage volume which is greater than any of the constituent free chunks. These comprise: identifying a plurality of free chunks of available storage in a storage array; identifying a start block offset and a number of blocks of respective ones of the plurality of free chunks; creating a logical volume by chaining the plurality of free chunks, wherein blocks are provisioned in the logical volume beginning at a first free chunk start block offset for a first free chunk number of blocks, continuing to provision blocks in the logical volume at a second free chunk start block offset for a second free chunk number of blocks, and continuing to provision blocks in the logical volume until the plurality of free chunks are provisioned in the logical volume.
A computer-implemented method for increasing reliability of a NAND flash device, the method comprising performing, via a flash controller, the operations of determining a read error rate of a virtual block included in the NAND flash device; determining, based at least in part on the read error rate, that garbage collection should be performed on the virtual block; and performing, based on the determination that garbage collection should be performed, the garbage collection on the virtual block.
A method for making a metal-insulator-metal (MIM) capacitors by etching a dielectric layer to form a via or contact hole, a tub, and a trench in the dielectric layer; depositing conformal metal in the via or contact hole, the tub, and the trench, wherein deposited conformal metal forms a via or contact in the via or contact hole; depositing a bottom electrode metal in the tub to form a bottom electrode of a metal-to-metal (MIM) capacitor; removing bottom electrode metal from the bottom electrode to form a dish-shape upper surface; depositing an insulator material on the bottom electrode to form an insulator layer of the MIM capacitor; and depositing a top electrode metal on the insulator layer to form a top electrode of the MIM capacitor.
A wireless communication device includes a communication element, non-transitory computer-readable storage media including instructions stored thereon, and at least one processor. The instructions, when executed by the at least one processor, cause the at least one processor to: transmit, by the communication element, a first signal; during a pre-defined time period following the transmission of the first signal, detect, by the communication element, a second signal; responsive to detecting the second signal, perform, during the pre-defined time period, a measurement; and determine path loss based on the measurement.
A computer-implemented method for increasing reliability of a HAND flash device, the method comprising performing, via a flash controller, the operations of determining a read error rate of a virtual block included in the NAND flash device; determining, based at least in part on the read error rate, that garbage collection should be performed on the virtual block; and performing, based on the determination that garbage collection should be performed, the garbage collection on the virtual block.
A microcontroller is provided comprising a processor, a data bus interface, a random access memory (RAM) including a plurality of pages, and a non-transitory computer readable memory including instructions, that when executed on the processor, after the microcontroller writes data to a first page of the plurality of pages, send a first interrupt to a host CPU external to the microcontroller; and process a second interrupt triggered by the host CPU, the second interrupt indicating a write by the CPU to the second page of the plurality of pages.
A diode comprises a semiconductor substrate, an n-well formed in the semiconductor substrate, a p-well formed in the semiconductor substrate that is spaced apart from the n-well, a first isolation region formed in the n-well, a first electrode formed in direct contact with the n-well and formed of a metal material, a first heavily doped region formed in the n-well and having a dopant concentration greater than a dopant concentration of the n-well, a second electrode formed in direct contact with the first heavily doped region, a second isolation region formed in the semiconductor substrate and between the n-well and the p-well, a second heavily doped region formed in the p-well and having a dopant concentration greater than a dopant concentration of the p-well, and a third electrode formed in direct contact with the second heavily doped region.
A wireless communication device includes a communication element, non-transitory computer-readable storage media including instructions stored thereon, and at least one processor. The instructions, when executed by the at least one processor, cause the at least one processor to: transmit, by the communication element, a first signal; during a pre-defined time period following the transmission of the first signal, detect, by the communication element, a second signal; responsive to detecting the second signal, perform, during the pre-defined time period, a measurement; and determine path loss based on the measurement.
A microcontroller is provided comprising a processor, a data bus interface, a random access memory (RAM) including a plurality of pages, and a non-transitory computer readable memory including instructions, that when executed on the processor, after the microcontroller writes data to a first page of the plurality of pages, send a first interrupt to a host CPU external to the microcontroller; and process a second interrupt triggered by the host CPU, the second interrupt indicating a write by the CPU to the second page of the plurality of pages.
A metal-oxide semiconductor field-effect transistor (MOSFET) including a volume of semiconductor material, a split gate, a gate oxide, and a doped material in the volume of semiconductor material. The volume of semiconductor material presents laterally spaced first and second sides and a trench spaced between the sides. The split gate presents laterally spaced apart first and second gate sections. The trench is located between the first and second gate sections. The gate oxide underlies the first and second gate sections and at least partially fills the trench. The doped material is in contact with the gate oxide.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
A method of programming a memory cell having a floating gate by applying a first program pulse to the memory cell to place electrons on the floating gate, wherein the first program pulse comprises a program voltage that includes a preliminary voltage level in a first portion of the first program pulse and a first voltage level in a second portion of the first program pulse, wherein the first voltage level is greater than the preliminary voltage level. The first voltage level is applied immediately successive to the preliminary voltage level. Then, applying successive program pulses to the memory cell to place additional electrons on the floating gate, wherein the successive program pulses include the program voltage, and wherein the program voltage increases in voltage level for each one of the successive program pulses relative to a previous one of the successive program pulses or the first program pulse.
Disclosed is a method of panel level packaging of one or more devices. The method comprises: providing a carrier with one or more cooling fins; placing a filler material between at least two of the one or more cooling fins; providing one or more components on the carrier; and removing the filler material. Also disclosed is a panel level packaged device, comprising one or more of a photonic integrated circuit and an electronic integrated circuit; and a carrier, having a mounting side onto which the photonic integrated circuit and/or the electronic integrated circuit are mounted. The carrier is configured with cooling protrusions on a side, opposite to the mounting side.
A metal-oxide semiconductor field-effect transistor (MOSFET) including a volume of semiconductor material, a split gate, a gate oxide, and a doped material in the volume of semiconductor material. The volume of semiconductor material presents laterally spaced first and second sides and a trench spaced between the sides. The split gate presents laterally spaced apart first and second gate sections. The trench is located between the first and second gate sections. The gate oxide underlies the first and second gate sections and at least partially fills the trench. The doped material is in contact with the gate oxide.
Disclosed herein are aspects for detecting and responding to over-current conditions in a solid-state circuit breaker (SSCB) system. An example aspect for a solid-state circuit breaker system includes a shunt resistor (205) to generate a voltage proportional to a current flowing through a circuit, a plurality of fault detection units (203), an OR gate (206) to receive timer output signals from the plurality of fault detection units (203) and generate a fault detection signal, and an SR latch (207) having a set input to receive the fault detection signal from the OR gate (206), the SR latch (207) configured to provide a control signal to a gate driver of a solid-state switch based on the fault detection signal. Each fault detection unit can include a digital-to analog (DAC) converter to set a threshold voltage, a comparator (204) to compare voltages, and a timer to validate a fault condition and generate the timer output signals.
H02H 1/00 - Details of emergency protective circuit arrangements
H02H 3/093 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current with timing means
H02H 3/05 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection Details with means for increasing reliability, e.g. redundancy arrangements
H02H 3/00 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
65.
PUMPING CONTROLLER FOR A PLURALITY OF CHARGE PUMP UNITS
In one example, a system comprises a plurality of charge pump units connected in parallel to receive an input voltage and to generate an output voltage greater than the input voltage; and a pumping controller to provide a pumping signal to a first charge pump unit of the plurality of charge pump units and to provide sequentially delayed versions of the pumping signal to the other charge pump units of the plurality of charge pump units, the pumping controller comprising a plurality of circuit blocks, each of the plurality of circuit blocks comprising a delay circuit and a latch.
Disclosed is a method of panel level packaging of one or more devices. The method comprises: providing a carrier with one or more cooling fins; placing a filler material between at least two of the one or more cooling fins; providing one or more components on the carrier; and removing the filler material. Also disclosed is a panel level packaged device, comprising one or more of a photonic integrated circuit and an electronic integrated circuit; and a carrier, having a mounting side onto which the photonic integrated circuit and/or the electronic integrated circuit are mounted. The carrier is configured with cooling protrusions on a side, opposite to the mounting side.
Disclosed is a method of panel level packaging of one or more devices. The method comprises: providing a carrier, forming at least one optical waveguide on the carrier, selectively removing the at least one optical waveguide to obtain one or more opening areas, and mounting one or more components to the carrier within the one or more opening areas. Also disclosed is a panel level packaged device, comprising one or more of a photonic integrated circuit and an electronic integrated circuit; and a carrier, having a mounting side with at least one patterned optical waveguide. The photonic integrated circuit and/or the electronic integrated circuit are mounted into one or more opening areas of the at least one patterned optical waveguide.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/62 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having no potential barriers
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
68.
CONNECTIVITY FRAMEWORK HAVING UNIFIED STACK AND MESSAGING PROTOCOL FOR EMBEDDED SECURE CONNECTIVITY
An apparatus comprises a computing device including one or more processors, multiple peripheral communication devices of different communication protocol types operably connected to the one or more processors, and a memory to store processor-executable instructions comprising an application layer protocol stack. The processor-executable instructions are such that, when executed by the one or more processors, cause the one or more processors to perform operations for respective ones of messages to be communicated to and from the computing device via respective ones of the multiple peripheral communication devices. The operations comprise communicating the respective ones of messages via the respective ones of the multiple peripheral communication devices according to a unified messaging protocol that is common to the multiple peripheral communication devices.
H04L 67/12 - Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
H04L 69/08 - Protocols for interworkingProtocol conversion
H04L 69/18 - Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
An apparatus may include a physical layer (PHY), a reconciliation sublayer (RS), a Media Access Control layer (MAC), and a logic circuit acting as a Central Segment Controller or Local Node Manager. The PHY may interface with a shared transmission medium of a network. The RS may support Physical Layer Collision Avoidance (PLCA), and the circuit may send a request to register a node with a network, and derive a node identifier for use by the PLCA RS to determine transmit opportunities, wherein the node identifier is at least partially derived from the node's position in a table of registered nodes in the network received in response to the registration request.
H04W 84/18 - Self-organising networks, e.g. ad hoc networks or sensor networks
H04L 41/22 - Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks comprising specially adapted graphical user interfaces [GUI]
H04L 45/28 - Routing or path finding of packets in data switching networks using route fault recovery
A diode comprises a semiconductor substrate, an n-well formed in the semiconductor substrate, a p-well formed in the semiconductor substrate that is spaced apart from the n-well, a first isolation region formed in the n-well, a first electrode formed in direct contact with the n-well and formed of a metal material, a first heavily doped region formed in the n-well and having a dopant concentration greater than a dopant concentration of the n-well, a second electrode formed in direct contact with the first heavily doped region, a second isolation region formed in the semiconductor substrate and between the n-well and the p-well, a second heavily doped region formed in the p-well and having a dopant concentration greater than a dopant concentration of the p-well, and a third electrode formed in direct contact with the second heavily doped region.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
A system and method for a polymer with a low dielectric constant (130a-f) applied in targeted areas of a semiconductor using additive manufacturing and a second polymer having high thermal conductivity (140) encasing the entire semiconductor are disclosed. The method may include applying, using an additive manufacturing technique, a first polymer to a first area of a semiconductor die. The first polymer may include a first filler having a dielectric constant of 3.3 or less. The method may also include applying a second polymer over the first polymer and encapsulating the semiconductor die. The second polymer may be different from the first polymer.
Disclosed is a method of panel level packaging of one or more devices. The method comprises: providing a carrier, forming at least one optical waveguide on the carrier, selectively removing the at least one optical waveguide to obtain one or more opening areas, and mounting one or more components to the carrier within the one or more opening areas. Also disclosed is a panel level packaged device, comprising one or more of a photonic integrated circuit and an electronic integrated circuit; and a carrier, having a mounting side with at least one patterned optical waveguide. The photonic integrated circuit and/or the electronic integrated circuit are mounted into one or more opening areas of the at least one patterned optical waveguide.
G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/42 - Coupling light guides with opto-electronic elements
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
A method of programming a memory cell having a floating gate by applying a first program pulse to the memory cell to place electrons on the floating gate, wherein the first program pulse comprises a program voltage that includes a preliminary voltage level in a first portion of the first program pulse and a first voltage level in a second portion of the first program pulse, wherein the first voltage level is greater than the preliminary voltage level. The first voltage level is applied immediately successive to the preliminary voltage level. Then, applying successive program pulses to the memory cell to place additional electrons on the floating gate, wherein the successive program pulses include the program voltage, and wherein the program voltage increases in voltage level for each one of the successive program pulses relative to a previous one of the successive program pulses or the first program pulse.
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
74.
HYBRID OVER-CURRENT DETECTION METHOD FOR SOLID-STATE CIRCUIT BREAKER (SSCB)
Disclosed herein are aspects for detecting and responding to over-current conditions in a solid-state circuit breaker (SSCB) system. An example aspect for a solid-state circuit breaker system includes a shunt resistor to generate a voltage proportional to a current flowing through a circuit, a plurality of fault detection units, an OR gate to receive timer output signals from the plurality of fault detection units and generate a fault detection signal, and an SR latch having a set input to receive the fault detection signal from the OR gate, the SR latch configured to provide a control signal to a gate driver of a solid-state switch based on the fault detection signal. Each fault detection unit can include a digital-to analog converter to set a threshold voltage, a comparator to compare voltages, and a timer to validate a fault condition and generate the timer output signals.
G01R 31/327 - Testing of circuit interrupters, switches or circuit-breakers
G01R 15/14 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks
G01R 15/20 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
75.
BATTERY MANAGEMENT SYSTEM (BMS) ANALOG FRONT-END (AFE) AND ACTIVE CELL BALANCING ARCHITECTURE
A centralized control unit for actively balancing a multi-cell battery pack is provided. The centralized control unit may include an analog-to-digital converter (ADC) to monitor and digitize voltage readings of the battery cells in the multi-cell battery pack, a microcontroller unit (MCU) to process the digitized voltage readings from the ADC, analyze a state of the battery cells, and execute one or more balancing algorithms, and a DC-DC converter to enable redistribution of energy to maintain balance across the battery cells.
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
G01R 31/3842 - Arrangements for monitoring battery or accumulator variables, e.g. SoC combining voltage and current measurements
H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
76.
ADDRESSING AND ROUTING FOR DEVICES USING CONNECTIVITY FRAMEWORK FOR EMBEDDED CONNECTIVITY
An apparatus comprising a computing device including one or more processors, multiple peripheral communication devices, and a memory to store processor-executable instructions. The one or more processors are to perform operations of a gateway node comprising receiving a message from a first end node via a first one of the peripheral devices, the message including a source identifier comprising a first end node identifier assigned to the first end node and a destination identifier comprising a second end node identifier assigned to a second end node; consulting a routing table at least partially responsive to receiving the message; and forwarding the message to the second end node via a second one of the peripheral devices based on an entry in the routing table, the entry including an interface identifier stored in association with the second end node identifier, the interface identifier corresponding to the second one of the peripheral devices.
H04L 67/12 - Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
H04L 69/08 - Protocols for interworkingProtocol conversion
H04L 69/18 - Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
A method is provided for forming a thin film resistor (TFR) and a thin film MIM capacitor (TFMIMCAP) in an integrated circuit (IC) device, with using a sacrificial oxide hardmask. A method comprises: forming an etch stop layer over an integrated circuit (IC) structure; forming a thin film layer over the dielectric etch stop layer; annealing the thin film layer; and forming first and second thin film elements in the thin film layer comprising: photomasking the thin film layer with a photomask; etching thin film layer through the photomask to define the first and second thin film elements; and etch byproducts comprising polymer. An integrated circuit device has a nitride insulator/capacitance layer above and adjacent a thin film element having an above thickness magnitude and an adjacent thickness magnitude within 50 Å of one another.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
Numerous examples are disclosed of systems and methods for operating one or more arrays of resistive random access memory (RRAM) cells. In one example, a system comprises an array of resistive random access memory (RRAM) units arranged in rows and columns; and a sense amplifier for determining a differential value stored in a first RRAM unit and a second RRAM unit in the array, wherein the first RRAM unit comprises a first select transistor coupled to a first set of one or more RRAM cells and the second RRAM unit comprises a second select transistor coupled to a second set of one or more RRAM cells.
An integrated circuit apparatus includes a transistor and a varactor. The transistor includes a transistor source and a transistor drain formed in a transistor well area of a semiconductor substrate, a transistor gate oxide formed over the substrate, and a transistor gate formed over the transistor gate oxide. The varactor is located laterally offset from the transistor and includes a pair of varactor source/drain regions formed in a varactor well area of the semiconductor substrate, a varactor gate insulator formed over the substrate, and a varactor gate formed over the varactor gate insulator, wherein the varactor gate is formed from a different material than the transistor gate.
H10D 1/64 - Variable-capacitance diodes, e.g. varactors
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
A vertical power metal oxide semiconductor field effect transistor includes a volume of semiconductor material, a channel, a source, a drain, and a gate. The volume of semiconductor material presents opposite vertically spaced first and second ends and an outer side perimeter adjacent the first end. The channel extends through the volume of semiconductor material from the first source to the drain. The source is located adjacent the first end. The gate at least substantially surrounds the outer perimeter of the volume of semiconductor material.
An apparatus including a planar metal oxide semiconductor field-effect transistor and a trench Schottky barrier diode that are physically and functionally integrated into a single, continuous structure, and a method of making such an apparatus. The integrated, trench Schottky barrier diode is located over a junction field-effect transistor neck region which is adjacent to the planar metal oxide semiconductor field-effect transistor. The Schottky barrier diode and the planar metal oxide semiconductor field-effect transistor may be located in a single, continuous volume of semiconductor material. The planar metal oxide semiconductor field-effect transistor may include first and second transistor sides spaced on opposite sides of the junction field-effect transistor neck region, such that the trench Schottky barrier diode may be located between the first and second transistor sides.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
82.
LATERAL JUNCTION FIELD EFFECT TRANSISTOR HAVING A VERTICAL CHANNEL AND METHODS FOR MAKING THE SAME
A lateral junction field-effect transistor including a volume of semiconductor material including a first end, a second end spaced vertically from the first end, a first side, and a second side spaced laterally from the first side. A source and a drain are located at the first end of the volume of semiconductor material. Laterally spaced apart first and second gates are also located at the first end of the volume of semiconductor material. The source is positioned between the first and second gates.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
83.
SEMICONDUCTOR PACKAGING USING A LOW DIELECTRIC CONSTANT POLYMER IN TARGETED AREAS IN CONJUNCTION WITH A HEAT-TRANSFER ENHANCED POLYMER
A system and method for a polymer with a low dielectric constant applied in targeted areas of a semiconductor using additive manufacturing and a second polymer having high thermal conductivity encasing the entire semiconductor are disclosed. The method may include applying, using an additive manufacturing technique, a first polymer to a first area of a semiconductor die. The first polymer may include a first filler having a dielectric constant of 3.3 or less. The method may also include applying a second polymer over the first polymer and encapsulating the semiconductor die. The second polymer may be different from the first polymer.
A system and method for a drift reset circuit for updating the input offset voltage in an ionization smoke detector are disclosed. The method may include monitoring an ionization chamber of a smoke detector for an alert. The method may also include periodically powering on a drift reset circuit to update an input offset voltage of an operational amplifier. The method may additionally include outputting the input offset voltage to the operational amplifier. The method may further include powering off the drift reset circuit.
A centralized control unit for actively balancing a multi-cell battery pack is provided. The centralized control unit may include an analog-to-digital converter (ADC) to monitor and digitize voltage readings of the battery cells in the multi-cell battery pack, a microcontroller unit (MCU) to process the digitized voltage readings from the ADC, analyze a state of the battery cells, and execute one or more balancing algorithms, and a DC-DC converter to enable redistribution of energy to maintain balance across the battery cells.
In one example, a method comprises generating a first voltage; generating a second voltage; prior to a read operation, charging a first node and a third node to the first voltage and charging a second node and a fourth node to the second voltage, wherein a first capacitor couples the first node and the second node and a second capacitor couples the third node and the fourth node; and during the read operation, discharging the first node through a reference memory cell and discharging the third node through a selected memory cell, wherein the second node tracks the first node through the first capacitor and the fourth node tracks the second node through the second capacitor.
An integrated circuit apparatus includes a transistor and a varactor. The transistor includes a transistor source and a transistor drain formed in a transistor well area of a semiconductor substrate, a transistor gate oxide formed over the substrate, and a transistor gate formed over the transistor gate oxide. The varactor is located laterally offset from the transistor and includes a pair of varactor source/drain regions formed in a varactor well area of the semiconductor substrate, a varactor gate insulator formed over the substrate, and a varactor gate formed over the varactor gate insulator, wherein the varactor gate is formed from a different material than the transistor gate.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
A junction field-effect transistor that is normally off rather than normally on, and a method of making such a device. The junction field-effect transistor includes a volume of semiconductor material, a first gate located at a first side of the semiconductor material, a second gate located at a second side opposite and spaced apart from the first gate, a Schottky barrier diode, and a drain. The Schottky barrier diode is located at a first end of the semiconductor material between the first and second gates, and replaces a conventional source. The drain is located at the second end, opposite the diode, and a region of the semiconductor material between the diode and the drain provides a channel. The Schottky barrier diode conducts in a forward mode (i.e., the device is on) only when the anode-to-cathode voltage exceeds the metal-to-semiconductor barrier potential, which means the device is normally off.
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 64/64 - Electrodes comprising a Schottky barrier to a semiconductor
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
A device has a CMOS metal stack of metal layers oriented substantially horizontally, and an inductor coil oriented substantially vertically in the CMOS metal stack and comprising at least two metal layers of the CMOS metal stack. A device has a semiconductor chip comprising a substrate and an integrated circuit, a metal stack of metal layers, a planar spiral inductor comprising at least two metal layers of the metal stack, wherein the semiconductor chip defines a semiconductor plane having a semiconductor plane normal vector and the planar spiral inductor defines an inductor plane having a inductor plane normal vector, wherein an angle between the semiconductor plane normal vector and the inductor plane normal vector is between 1 and 90 degrees.
H01F 29/02 - Variable transformers or inductances not covered by group with tappings on coil or windingVariable transformers or inductances not covered by group with provision for rearrangement or interconnection of windings
H01F 21/12 - Variable inductances or transformers of the signal type discontinuously variable, e.g. tapped
H10D 1/68 - Capacitors having no potential barriers
H10D 86/80 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors
A device has a CMOS metal stack of metal layers oriented substantially horizontally, and an inductor coil oriented substantially vertically in the CMOS metal stack and comprising at least two metal layers of the CMOS metal stack. A device has a semiconductor chip comprising a substrate and an integrated circuit, a metal stack of metal layers, wherein the metal stack is connected to the semiconductor chip, a planar spiral inductor comprising at least two metal layers of the metal stack, and a magnetic core in the planar spiral inductor, wherein the magnetic core has magnetic material, wherein the semiconductor chip defines a semiconductor plane having a semiconductor plane normal vector and the planar spiral inductor defines an inductor plane having an inductor plane normal vector, wherein an angle between the semiconductor plane normal vector and the inductor plane normal vector is between 1 and 90 degrees.
H10D 1/68 - Capacitors having no potential barriers
H10D 86/80 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors
A device has a CMOS metal stack of metal layers oriented substantially horizontally in the CMOS metal stack, and a differential inductor coil oriented substantially vertically in the CMOS metal stack and comprising at least two metal layers of the CMOS metal stack. A device having a semiconductor chip having a substrate and an integrated circuit, a metal stack of a plurality of metal layers, wherein the metal stack is connected to the semiconductor chip, and a planar spiral differential inductor comprising at least two metal layers of the metal stack, wherein the semiconductor chip defines a semiconductor plane having a semiconductor plane normal vector and the planar spiral differential inductor defines a differential inductor plane having a differential inductor plane normal vector, wherein an angle between the semiconductor plane normal vector and the differential inductor plane normal vector is between 1 and 90 degrees.
H01F 29/02 - Variable transformers or inductances not covered by group with tappings on coil or windingVariable transformers or inductances not covered by group with provision for rearrangement or interconnection of windings
H01F 3/04 - Cores, yokes or armatures made from strips or ribbons
H01F 21/12 - Variable inductances or transformers of the signal type discontinuously variable, e.g. tapped
H10D 1/68 - Capacitors having no potential barriers
H10D 86/80 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors
A device has a semiconductor chip comprising a substrate and an integrated circuit, a metal stack of metal layers connected to the semiconductor chip, and a planar spiral inductor comprising at least two metal layers of the metal stack, wherein the semiconductor chip defines a semiconductor plane having a semiconductor plane normal vector and the planar spiral inductor defines a inductor plane having an inductor plane normal vector, wherein an angle between the semiconductor plane normal vector and the inductor plane normal vector is between 1 and 90 degrees, a sensing membrane when interacting with an ionized fluid is operable to attract ions, wherein the sensing membrane is operable to electrically communicate with the planar spiral inductor; and a fluid property measurement circuit operable to measure a quality factor or inductance of the planar spiral inductor and output a fluid property signal.
G01N 27/74 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating magnetic variables of fluids
H10D 80/20 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising capacitors, power FETs or Schottky diodes
93.
ION SENSING WITH THREE-DIMENSIONAL VERTICAL INDUCTORS WITH MAGNETIC CORE
A device has a semiconductor chip with a substrate and an integrated circuit, a metal stack connected to the semiconductor chip, a planar spiral inductor having a magnetic core and comprising at least two metal layers of the metal stack, wherein the semiconductor chip defines a semiconductor plane having a semiconductor plane normal vector and the planar spiral inductor defines an inductor plane having an inductor plane normal vector, wherein an angle between the semiconductor plane normal vector and the inductor plane normal vector is between 1 and 90 degrees; a sensing membrane operable to attract ions when interacting with an ionized fluid, wherein the sensing membrane is operable to electrically communicate with the planar spiral inductor; and a fluid property measurement circuit operable to measure a quality factor or inductance of the planar spiral inductor or a charge on the magnetic core and output a fluid property signal.
G01N 27/02 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance
G01N 27/22 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating capacitance
94.
HYPER-INTEGRATED DATA DEVICES WITH RADIATION TOLERANCE
Methods to form a three-dimensional semiconductor package comprising a customized ultra-bandwidth elements (CUBE) die coat shielding particles with an electrically insulating coating, disperse the coated shielding particles in a base material to form a mold structure; and position the mold structure proximate the three-dimensional semiconductor package to shield the package from radiation. Devices comprising: a three-dimensional semiconductor package; and a mold structure proximate the three-dimensional semiconductor package, the mold structure comprising: a base material; and shielding particles comprising an electrically insulating coating, wherein the shielding particles are dispersed in the base material.
In one example, a method comprises generating a first voltage; generating a second voltage; prior to a read operation, charging a first node and a third node to the first voltage and charging a second node and a fourth node to the second voltage, wherein a first capacitor couples the first node and the second node and a second capacitor couples the third node and the fourth node; and during the read operation, discharging the first node through a reference memory cell and discharging the third node through a selected memory cell, wherein the second node tracks the first node through the first capacitor and the fourth node tracks the second node through the second capacitor.
A device has a semiconductor chip with a substrate and an integrated circuit, a metal stack connected to the semiconductor chip, a planar spiral inductor having a magnetic core and comprising at least two metal layers of the metal stack, wherein the semiconductor chip defines a semiconductor plane having a semiconductor plane normal vector and the planar spiral inductor defines an inductor plane having an inductor plane normal vector, wherein an angle between the semiconductor plane normal vector and the inductor plane normal vector is between 1 and 90 degrees; a sensing membrane operable to attract ions when interacting with an ionized fluid, wherein the sensing membrane is operable to electrically communicate with the planar spiral inductor; and a fluid property measurement circuit operable to measure a quality factor or inductance of the planar spiral inductor or a charge on the magnetic core and output a fluid property signal.
G01N 27/22 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating capacitance
97.
DETERMINING AN OPERATIONAL LIMIT FOR A TRANSISTOR DEVICE WITH AGING RECOVERY
Systems and methods for determining an operational limit for a transistor are disclosed. The method may include receiving a set of input parameters related to a transistor and performing an age-dependent analysis based on the input parameters. The age-dependent analysis may include performing a non-aging simulation of the transistor by simulating a non-aging operation of the transistor and performing a plurality of aging simulations of the transistor based on aging conditions specified by the input parameters, a different value of at least one operational parameter of the transistor, and an aging recovery effect of the transistor as a function of a usage parameter of the transistor. The analysis may further include comparing respective results of the aging simulations with a result of the non-aging simulation. The method may include determining an operational limit for the transistor based at least on a result of the age-dependent analysis of the transistor.
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
Systems and methods for determining an operational limit for a transistor are disclosed. The method may include receiving a set of input parameters related to a transistor and performing an analysis of the transistor based on the set of input parameters. The analysis may include performing a simulation of the transistor under time dependent dielectric breakdown conditions by simulating an operation of the transistor and performing a series of lifetime simulations of the transistor. The series of lifetime simulations may include a simulation of an operation of the transistor based on conditions specified by the input parameters and a different value of at least one operational parameter of the transistor. The analysis may further include comparing respective results of the series of lifetime simulations with a target lifetime of the transistor. The method may include determining an operational limit for the transistor based on a result of the analysis.
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
A system and method for a drift reset circuit for updating the input offset voltage in an ionization smoke detector are disclosed. The method may include monitoring an ionization chamber of a smoke detector for an alert. The method may also include periodically powering on a drift reset circuit to update an input offset voltage of an operational amplifier. The method may additionally include outputting the input offset voltage to the operational amplifier. The method may further include powering off the drift reset circuit.
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
G01N 27/64 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating the ionisation of gases, e.g. aerosolsInvestigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electric discharges, e.g. emission of cathode using wave or particle radiation to ionise a gas, e.g. in an ionisation chamber
A device has a semiconductor chip comprising a substrate and an integrated circuit, a metal stack of metal layers connected to the semiconductor chip, and a planar spiral differential inductor comprising at least two metal layers of the metal stack, wherein the semiconductor chip defines a semiconductor plane having a semiconductor plane normal vector and the planar spiral differential inductor defines an inductor plane having an inductor plane normal vector, wherein an angle between the semiconductor plane normal vector and the inductor plane normal vector is between 1 and 90 degrees; a sensing membrane operable to become electrically charged when interacting with an ionized fluid, wherein the sensing membrane is operable to electrically communicate with the planar spiral differential inductor; and a fluid property measurement circuit operable to measure a quality factor or inductance of the planar spiral differential inductor and output a fluid property signal.
G01N 27/74 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating magnetic variables of fluids
H10D 80/20 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising capacitors, power FETs or Schottky diodes
