Systems and methods herein are for one or more processing units of a subnet manager (SM) to communicate configuration information with at least one subnet management agent (SMA) that is associated with at least one switch and with a host machine, the configuration information to enable the at least one switch to configure a forwarding table based in part on a mapping of at least one virtual network address to physical network addresses of two or more physical ports of the host machine, and the configuration information to enable the host machine to communicate with other host machines using the at least one switch and the at least one virtual network address.
H04L 61/103 - Mapping addresses of different types across network layers, e.g. resolution of network layer into physical layer addresses or address resolution protocol [ARP]
H04L 101/668 - Internet protocol [IP] address subnets
In one embodiment, a system includes clock circuitry to generate a local clock signal, the clock circuitry including an oscillator, clock synchronization circuitry to adjust the local clock signal based on a remote clock, and a processor to train a machine learning model to predict a frequency or a frequency adjustment for applying to the local clock signal during clock holdover.
Technologies for optimizing the spreading of traffic across multiple local output ports while considering both local load and end-to-end (E2E) load are described. One device has multiple outgoing ports and a network adapter that determines, for a first flow of packets, a first end-to-end (E2E) congestion rate of at least some of the outgoing ports. The network adapter determines a port state of at least some of the outgoing ports. The network adapter receives a first packet associated with the first flow of packets. The network adapter determines, using a first desired rate for the first flow, the first E2E congestion rates, and the port states, i) a first time at which the first packet is to be transmitted and ii) a first outgoing port on which the first packet is to be transmitted. The first packet is sent on the first outgoing port at the first time.
A network interface device includes packet processing circuity to capture a network packet transmitted by a software application running on a computing device and capture, at time of transmission of the network packet, a value of a physical clock as a receive timestamp for subscriber entities of the computing device. The circuitry associates the receive timestamp with a first packet copy of the network packet and inserts the first packet copy to a first receive pipeline of a first subscriber entity. The circuitry associates the receive timestamp with a second packet copy of the network packet and inserts the second packet copy to a second receive pipeline of a second subscriber entity.
Systems and methods herein are for a network having at least one host processor of a host node to discover peer nodes in the network. The at least one host processor can communicate a group identifier (ID) with further nodes in the network, where the group ID is based in part on a secret. A subset of the nodes can identify as part of a community within the network based in part on the group ID. The at least one host processor can use a key, which may be also based in part on the secret, with at least one node of the subset of the nodes to validate the host node and the at least one node as the peer nodes within the network based in part on being associated with the key.
Apparatuses, systems, and techniques to monitor incoming data flows from a plurality of network sources and identify a data flow from any of the plurality of sources that exceeds a threshold value. In at least one embodiment, the data flow from any of the plurality of sources that exceeds the threshold value are rate-limited while the data flow from any of the plurality of sources that do not exceed the threshold value are passed through without any rate limiting.
A system and method for restricting traffic in a computer network, the method may include extracting a routing path of a packet, and determining whether to allow or block the packet based on the routing path.
Systems and methods are described for quantum information retrieval. An example system may include a quantum cloning unit, a photon number splitting (PNS) unit, and a variable-strength measurement unit to enhance the accuracy and reliability of quantum state estimations without introducing substantial decoherence. The quantum cloning unit may be used to generate approximate clones of a qubit. If the information is encoded in a multi-photon state resulting in a multi-photon state qubit, then the photon number splitting (PNS) unit may be used to intercept the multi-photon state and reflect a single photon from the multi-photon state, which may then be subjected to quantum cloning. These qubits and qubit clones may then be subjected to variable-strength measurements, which provides detailed analysis with minor disturbance to quantum properties such as superposition and entanglement.
H04B 10/077 - Arrangements for monitoring or testing transmission systemsArrangements for fault measurement of transmission systems using an in-service signal using a supervisory or additional signal
H04B 10/85 - Protection from unauthorised access, e.g. eavesdrop protection
Embodiments of the present disclosure are directed to sampling telemetric values of computing devices in an efficient manner. Generally speaking, embodiments described herein are directed to sampling counters and gauges of computing devices in a network, data center, etc. in a way that reduces redundant and non-informative signals, while being adaptive when sampling with high granularity desirable. According to one embodiment, counters can be correlated with each other, sharing residual information, and therefore, sampling only a subset of them, or a “representative” can be sufficient in representing a current state. When there is a notable change in the representative, the telemetry sampling procedure can increase its granularity and sample not only the representative but also the underlying group of telemetric values.
A computing system includes a memory and a table remap circuit. The table remap circuit is to modify a size of a table comprising table elements stored in the memory, while the table is available for access by one or more users, by (i) defining a first interim table and a second interim table, (ii) iteratively transferring table elements from the first interim table to the second interim table, (iii) in response to a request from a user to write a table element in the table, writing the table element in the first interim table or in the second interim table in accordance with a selection criterion, and (iv) remapping the table to the second interim table.
Systems and methods herein are for network communications, where at least one processor can include or be associated with a data path module and a packet steering module, where the data path module can receive communications that may be associated with different communication protocols and can determine an elephant flow based in part on a size indication associated with the communications, and where the packet steering module can receive information that may be associated with the elephant flow and can enforce at least one rule to steer incoming packets for different receive queues associated with respective ones of the communication protocols.
Systems and methods are described for secure communication to facilitate encrypted transmission of data between a transmitting device (encoder) and a receiving device (decoder), leveraging quandle algebra. An example system includes an encoder, a decoder, and a communication channel. The encoder may generate a ciphertext (c) based on a message (x), an encoding variable (y), and a public encryption key (e), wherein, c=xy. The cipher text (c) is then transmitted, via the communication channel, to the decoder. The decoder may receive the ciphertext (c) via the communication channel and generate a deciphered form (x′) of the message (x) based on the ciphertext (c), the encoding variable (y), and a private encryption key (f), wherein, x′=cy, and and are binary operations that satisfy axioms of a quandle and/or a rack.
A device for holding a plurality of ferrules securely against a respective plurality of receptacles, which may include: a frame including: a transverse portion arranged in a transverse direction, a first longitudinal portion projecting from a first edge of the transverse portion and a second longitudinal portion projecting from a second edge of the transverse portion opposite to the first edge of the transverse portion, wherein the first and the second longitudinal portions project from the respective edges of the transverse portion in a longitudinal direction that is substantially perpendicular to the transverse direction; and a holder coupled between the first and second longitudinal portions of the frame, the holder being configured to hold, with respect to the frame, a plurality of ferrules arranged longitudinally parallel to each other and being distanced from each other in the transverse direction.
The technology disclosed herein enables selective clearing of memory regions upon a context switch. An example method includes the operations of: determining an identifier of a current execution context associated with a memory region; determining an identifier of a previous execution context specified by metadata associated with the memory region; responsive to determining that the identifier of the current execution context does not match the identifier of the previous execution context, associating the memory region with the current execution context; and clearing at least a part of the memory region.
G06F 21/53 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by executing in a restricted environment, e.g. sandbox or secure virtual machine
15.
REMOTE DIRECT MEMORY ACCESS OPERATIONS WITH INTEGRATED DATA ARRIVAL INDICATION
Disclosed are apparatuses, systems, and techniques that improve efficiency and decrease latency of remote direct memory access (RDMA) operations. The techniques include but are not limited to unified RDMA operations that are recognizable by various communicating devices, such as network controllers and target memory devices, as requests to establish, set, and/or update arrival indicators in the target memory devices responsive to arrival of one or more portions of the data being communicated.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
In one embodiment, a system includes a hardware clock to maintain a clock time, and a network device including a network interface to receive a first time-synchronization message from a clock synchronization leader as part of a two-way time synchronization protocol, and a hardware accelerator to identify the first time-synchronization message, cause generation and sending of a second time-synchronization message to the clock synchronization leader in response to identifying the first time synchronization message, and provide timing information associated with the first time-synchronization message and the second time-synchronization message to time-synchronization software running on a host device to synchronize the hardware clock to the clock synchronization leader.
A system includes at least one processing node to perform one or more compute processes as part of a distributed workload to generate an output. The at least one processing node is configured with a derived seed value that is generated from a base seed value. The system further includes a rounding circuit to perform rounding operations for the at least one processing node according to the derived seed value.
G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow
G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
18.
Load Balancing Between Network Devices Using Queue Sharing
A system includes one or more processors, and multiple network devices to connect the one or more processors to a network. The one or more processors are to issue work requests to the multiple network devices, by posting work descriptors on one or more shared queues that are each accessible to the multiple network devices. The network devices are to pull the work descriptors from the one or more shared queues, and to execute the work requests responsively to the work descriptors.
In one embodiment, a network device includes a network interface to share time synchronization packets with at least one remote device over a network, a hardware clock to maintain a clock time, and packet processing circuitry to process the time synchronization packets according to a two-way time synchronization protocol in order to cause clock synchronization between the hardware clock and at least one clock of the at least one remote device.
In one embodiment, a system includes a peripheral device, which includes an interface to receive from a virtual machine (VM) running on a host device, over a communication data bus, a request for timing data derived from a time measurement dialogue, the host device maintaining a master clock time, a hardware clock to maintain a peripheral device clock time, and processing circuitry to transform the master clock time to a frame of reference of the VM, and provide to the VM, over the communication data bus, the timing data based on the peripheral device clock time, and the master clock time transformed to the frame of reference of the VM.
In one embodiment, a network device includes parser configuration registers, hardware parsers coupled to receive data of a header section of a packet and including flexible hardware parsers to parse the data of the header section based on parser configurations loaded into the parser configuration registers, and a controller to selectively load the parser configurations associated with different protocols into the parser configuration registers such that a next parser configuration is loaded into the parser configuration registers based on a next protocol found while parsing a previous header of the header section.
In one embodiment, a network device includes an interface to receive packets over a network, a parser engine to receive data of a header section of a packet, and parse at least one first part of the header section yielding first parsed data, and a steering engine to receive the first parsed data, generate a parsing information for use in parsing at least one second part of the header section, and provide the parsing information to the parser engine, wherein: the parser engine is to parse the at least one second part of the header section based on the parsing information yielding second parsed data, and the steering engine is to perform an action based on the second parsed data.
An apparatus includes a serial bus and a serial bus interface circuit. The serial bus is to connect to at least one device. The serial bus interface circuit is to receive a sequence of serial-bus-interface read instructions from a processor, to forward the serial-bus-interface read instructions over the serial bus to the at least one device, to buffer data elements, which are received over the serial bus from the at least one device in response to the serial-bus-interface read instructions, and to make the buffered data elements available to the processor.
A network resiliency controller may monitor a port status for a network interface controller. A software defined datapath may be used to virtualize different ports of the network interface controller and direct traffic to a given port. If it is determined that a port failure is imminent or has occurred, one or more selectors may modify a port associated with the network interface controller. The network resiliency controller may identify the port switching, determine a new connection has been established with a new port, and then modify one or more traffic rules for routing traffic along the new port.
H04L 41/0663 - Performing the actions predefined by failover planning, e.g. switching to standby network elements
H04L 41/0604 - Management of faults, events, alarms or notifications using filtering, e.g. reduction of information by using priority, element types, position or time
Apparatuses and associated methods of manufacturing are described that provide a cage receptacle assembly configured to receive a cable connector. The cage receptacle assembly includes a cage body defining a first end and a second end. The cage body includes a top cage member attached to a bottom cage member via two side portions, and the top cage member defines an opening. The cage receptacle assembly defines a heat dissipation unit disposed within the opening of the top cage member, allowing heat to be transferred from the cable connector to an external environment of the cage receptacle assembly.
Technologies for spreading packets of transport flows across multiple network paths are described. A network controller includes a transport layer and a network layer. The transport layer includes a flow scheduler to schedule a transport flow from one of a plurality of transport flows. The network layer includes multipath logic to receive packets from the transport flow and select which path of a plurality of paths to a destination to use for the packets based on path congestion weights corresponding to the plurality of paths.
Systems and methods herein are for at least one circuit that can determine that a network reference associated with a first network hardware is subject to a network performance degradation in a network, can cause suspension of traffic flow associated with the network reference, can save configuration for at least the network reference at a node associated with the first network hardware, and can cause the configuration to be deployed in a second network hardware so that the network reference that was previously in the first network hardware is provided from the second network hardware to resume the traffic flow.
H04L 41/0816 - Configuration setting characterised by the conditions triggering a change of settings the condition being an adaptation, e.g. in response to network events
28.
Efficient parallelized computation of a Benes network configuration
A configurable switching network includes an optical Benes network having N input ports and N output ports, and multiple processors. The optical Benes network includes multiple 2-by-2 photonic switches interconnected by optical links, and is reducible in a plurality of nested subnetworks associated with respective nesting levels. The multiple processors are to: (i) receive a permutation defining requested interconnections between the N optical input ports and N optical output ports of the optical Benes network, (ii) determine a setting of the 2-by-2 photonic switches that implements the received permutation, including determining sub-settings for two or more subnetworks of a given nesting level in parallel, and (iii) configure the multiple 2-by-2 photonic switches of the optical Benes network in accordance with the determined setting.
Technologies for payload direct memory storing (PDMS) for out-of-order delivery of packets in remote direct memory access (RDMA) are described. A responder device includes an RDMA transport layer that can receive packets out of order and allow direct data placement of packet data in order. The responder device receives a first packet with a first packet number and first location information. The responder device stores first packet data to a first location according to the first location information. The responder device also receives a second packet and stores second packet data to a second location according to the second location information. A second packet number indicates that the first packet is received out of order. The first and second packet data are stored in order. The responder device can provide an indication that a message has arrived in response to determining that all packets of the message have arrived.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 15/167 - Interprocessor communication using a common memory, e.g. mailbox
A method includes receiving a set of codewords of a Forward Error Correction (FEC) code, each codeword including a plurality of code symbols. A temporal distribution of erroneous code symbols is estimated over the set of codewords. A long-term Block Error Rate (BLER) associated with the set of codewords is estimated based on the temporal distribution of the erroneous code symbols.
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/25 - Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
A device, communication system, and method are provided. In one example, a system for routing traffic is described that includes a plurality of ports to facilitate communication over a network. The system also includes a controller to selectively activate or deactivate ports of the system based on queue depths and additional information to improve power efficiency of the system.
In one embodiment, a network device includes a network interface to receive packets over a packet data network, packet processing circuitry to manage a multiplex network receive queue, and including a policer to provide queue fairness for a plurality of network flows competing for access to the multiplex network receive queue, and including meters to label the received packets, and selectively operate in (a) a two-level mode with two-levels of the meters, and (b) a single-level mode with a single one of the meters, and queueing logic to add some of the received packets to the multiplex network receive queue and drop others of the received packets responsively to labelling of the packets by the meters.
Systems and methods herein are for determining a poisoning in a machine learning (ML) model, which may be a pre-trained ML model that is subject to finetuning by a third-party. The system and method herein obtain first observations associated with the pre-trained ML model and may determine a distribution or classification of the first observations with respect to second observations obtained during the finetuning of the pre-trained ML model at different periods. Further, the determining of the poisoned ML model may be based in part on the distribution or classification being different than a predetermined threshold or being outside a predetermined threshold range.
Apparatuses, systems, and techniques to collect network intelligence related to a particular node in a network is passed to an immediate upstream neighbor in the network. The upstream neighbor analyzes the received network intelligence and automatically scales a telemetry streaming pipeline up or down to accommodate telemetry communication with the downstream neighbor in the network.
H04L 41/0896 - Bandwidth or capacity management, i.e. automatically increasing or decreasing capacities
H04L 41/16 - Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks using machine learning or artificial intelligence
35.
LIVE MIGRATION FOR CONFIDENTIAL COMPUTE ENVIRONMENTS
Systems and methods are directed toward migration operations, such as live migration operations, associated with confidential computing environments. Responsive to a request to migrate data, a secure hypervisor may establish a secure communication channel to a network interface controller to pass one or more keys for accessing securely stored data. The secure hypervisor may generate a descriptor associated with a memory location of the data and then pass the descriptor to the network interface controller. As a result, encryption/decryption operations may be offloaded to the network interface controller, which may use the descriptor and key to migrate the data from a source location to a destination location.
Technologies for creating an optimized and accelerated network pipeline using a network pipeline abstraction layer (NPAL) are described. A DPU includes DPU hardware and memory that stores DPU software with the NPAL that supports multiple network protocols and network functions in a network pipeline. The network pipeline includes a set of tables and logic organized in a specific order to be accelerated by an acceleration hardware engine of the DPU. The acceleration hardware engine processes network traffic data using the network pipeline.
Methods, systems, and machine-readable mediums to encode at least one vector associated with a log using a neural network. In at least one embodiment, a neural network is trained, at least in part, by obtaining first, second, and third encoded vectors by encoding a first vector associated with a first log sequence, a second vector associated with a second log sequence similar to the first log sequence, and a third vector associated with a third log sequence dissimilar from the first log sequence; and selecting at least one model weight that increases a likelihood that the first encoded vector is closer to the second encoded vector than the third encoded vector.
Methods, systems, and machine-readable mediums to encode at least one vector associated with a log using a neural network. In at least one embodiment, a processor is to encode at least one log message using at least one neural network trained, at least in part, by: obtaining a similarity score associated with a first vector and a second vector, the first vector to be associated with one or more first log messages, and the second vector to be associated with one or more second log messages; generating at least one similarity value indicating similarity between the first vector and the second vector; and determining a metric indicating similarity between the similarity score and the at least one similarity value.
Technologies for creating an optimized and accelerated network pipeline using an emulated network pipeline abstraction layer (NPAL) of an emulated data processing unit (DPU), including an emulated processing device and an emulated acceleration hardware engine, are described. The emulated NPAL supports multiple network protocols and network functions in an emulated network pipeline. The emulated network pipeline includes a set of tables and logic organized in a specific order to be accelerated by the emulated acceleration hardware engine. The emulated acceleration hardware engine can process network traffic data using the emulated network pipeline.
Technologies for creating an optimized and accelerated network pipeline using a network pipeline abstraction layer (NPAL) for split interfaces are described. A DPU includes a physical port configured to couple to a breakout cable that physically couples to a set of a plurality of devices, DPU hardware, and a memory operatively coupled to the DPU hardware. The NPAL supports a plurality of logical split ports, each logical split port corresponding to one of the plurality of devices, wherein the network pipeline comprises a set of tables and logic organized in a specific order to be accelerated by the acceleration hardware engine. The acceleration hardware engine is to process the network traffic data using the network pipeline.
Technologies for creating an optimized and accelerated network pipeline using a virtual switch and a network pipeline abstraction layer (NPAL) for fast link recovery are described. The virtual switch can monitor a link availability of each of a plurality of links to a destination, the plurality of links being specified in an initial group of identifiers. The virtual switch can detect a link failure of a first link of the plurality of links. The NPAL can remove a first link identifier, associated with the first link, from the initial group of link identifiers to obtain a modified group of link identifiers. The NPAL can cause a routing table in the NPAL to be updated to remove the first link identifier. The acceleration hardware engine can process network traffic data using the network pipeline and distribute the network traffic data to only the remaining links of the plurality of links.
Technologies for creating an optimized and accelerated network pipeline using a network pipeline abstraction layer (NPAL) for policy-based routing (PBR) over Service Function Chaining (SFC) are described. A DPU includes acceleration hardware engine to provide a single accelerated data plane. A processing device can generate a first virtual bridge and a second virtual bridge, the first virtual bridge to be controlled by a first network service hosted on the DPU and having a set of one or more network rules, and the second virtual bridge having a policy-based routing policy (PBR policy). The processing device can add the virtual port between the first virtual bridge and the second virtual bridge. The acceleration hardware engine, in the single accelerated data plane, can route network traffic data using the PBR policy and process the network traffic data using the set of one or more network rules.
Technologies for configuring flexible hardware-accelerated rules in a Service Function Chaining (SFC) architecture are described. A DPU includes an acceleration hardware engine to provide a single accelerated data plane, and a processing device that generates a first virtual bridge and a second virtual bridge. The first virtual bridge is controlled by a first network service hosted on the DPU and has a first set of one or more network rules. The second virtual bridge has a second set of one or more user-defined network rules. The processing device generates a combined set of network rules based on the first set of one or more network rules and the second set of one or more user-defined network rules. The acceleration hardware engine processes network traffic data in the single accelerated data plane using the combined set of network rules.
Technologies for configuring multiple virtual bridges and interface mappings in a Service Function Chaining (SFC) architecture are described. A DPU can include memory to store a configuration file specifying the virtual bridges and interface mappings, and a processing device operatively coupled to the memory. The processing device, according to the configuration file, generates a first virtual bridge and a second virtual bridge. The first virtual bridge is controlled by a first network service hosted on the DPU, and the second virtual bridge is controlled by a user-defined logic. The processing device adds add one or more host interfaces to the second virtual bridge, a first service interface to the first virtual bridge to operatively couple to the first network service, and one or more virtual ports between the first virtual bridge and the second virtual bridge.
VERTICAL-CAVITY SURFACE-EMITTING LASER WITH HIGH SIDE-MODE SUPPRESSION RATIO AND HIGH POLARIZATION-MODE SUPPRESSION RATIO AND A METHOD OF MANUFACTURING THE SAME
Some embodiments of the present disclosure are directed to a laser design that provides side-mode suppression that is separately configurable from polarization-mode suppression, such that each may be independently optimized to simultaneously provide a high side-mode suppression ratio and a high polarization-mode suppression ratio. For example, a laser (e.g., a VCSEL) may include an active region configured to emit light, an aperture defining an optical axis, a first element positioned along the optical axis on a first side of the active region, and a second element positioned along the optical axis on a second side of the active region opposite the first side of the active region. The first element may be configured to increase a side-mode suppression ratio of the laser, and the second element may be configured to increase a polarization-mode suppression ratio of the laser.
H01S 5/068 - Stabilisation of laser output parameters
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
Methods, systems, and machine-readable mediums to perform a neural network to encode log data. In at least one embodiment, a processor comprising one or more circuits to encode at least one log message, at least in part, by encoding a first type of information in the at least one log message to obtain a first encoding, encoding a second type of information in the at least one log message to obtain a second encoding, and obtaining a resultant encoding at least in part by combing at least the first and second encodings.
Methods, systems, and machine-readable mediums to perform a neural network to classify one or more logs. In at least one embodiment, a processor comprising one or more circuits to classify one or more log entries to obtain one or more classified log entries, obtain combined information at least in part by combing at least the one or more classified log entries and telemetry information, and use at least one machine learning process to classify the combined information.
G06F 18/2411 - Classification techniques relating to the classification model, e.g. parametric or non-parametric approaches based on the proximity to a decision surface, e.g. support vector machines
G06F 18/2433 - Single-class perspective, e.g. one-against-all classificationNovelty detectionOutlier detection
48.
Load balancing between network devices based on communication load
A system includes multiple network devices and one or more processors. The network devices are to connect to a network. The one or more processors are to exchange communication traffic over the network via the multiple network devices, to estimate multiple communication loads experienced respectively by the multiple network devices, and to distribute subsequent communication traffic among the multiple network devices, responsively to the multiple estimated communication loads.
Systems and methods herein are for at least one circuit that can be associated with a host controller and that can enable a network element to perform a test of packet processing flow in a network, where instructions can be performed for different match-action tables in an order so that first instructions of the different match-action tables can generate test packets for the packet processing flow, second instructions can provide rules associated with the packet processing flow, and third instructions can perform verification of the test based on the rules under the test and using the test packets.
Data transceivers including a transmitter configured with a digital filter, and a receiver configured with an equalizer, are equipped with logic to measure a combined pulse response to a symbol generated by the transmitter at an output of the equalizer, adjust the combined pulse response by an impulse response of the digital filter to generate an adjusted pulse response, and modify the digital filter with one or more floating taps based on the adjusted pulse response.
In one embodiment, a device includes a processing unit to find at least one value of at least one filter parameter using Bayesian Optimization, and provide the at least one value of the at least one filter parameter to a filter to generate an adjustment to cause clock circuitry to adjust a local clock signal or local clock based on an error signal and the at least one value of the at least one filter parameter, and a memory to store data used by the processing unit.
Apparatuses and associated methods of manufacturing are described that provide a cage receptacle assembly configured to receive a cable connector. An illustrative cage receptacle assembly is described to include a cage body, a first heat dissipation unit disposed proximate to a bottom side of the cage body and configured to remove heat from the bottom side of the cage body, and a second heat dissipation unit disposed proximate to a top side of the cage body and configured to remove heat from the top side of the cage body.
An example electronic module includes a multi-chip module (MCM) substrate comprising a central portion configured to receive a main die; a plurality of MCM sockets positioned about a peripheral portion of the MCM substrate; and a plurality of mezzanine packages coupled to respective MCM sockets of the plurality of MCM sockets. The plurality of MCM sockets and the MCM substrate are configured to enable communication of digital data between the main die and respective mezzanine packages of the plurality of mezzanine packages. The plurality of mezzanine packages includes at least one co-packaged copper (CPC) package; and at least one co-packaged optics (CPO) package.
A network device includes packet processing circuitry, one or more hardware peripherals, a Baseboard Management Controller (BMC) and a Central Processing Unit (CPU). The packet processing circuitry is to communicate packets over a network. The BMC is to control the hardware peripherals. The CPU is to perform control-plane operations for communicating the packets by the packet processing circuitry. Each of the CPU and the BMC is to modify states of the hardware peripherals, and to synchronize the other of the BMC and the CPU with the modified state of the hardware peripherals.
An interconnect device is provided. In one example, an interconnect device includes circuits capable of receiving a request via an ingress port; in response to receiving the request, identifying one or more egress ports associated with the ingress port; activating the one or more egress ports associated with the ingress port; receiving data via the ingress port; processing the received data to identify an egress port associated with a destination of the data; and scheduling the data to be forwarded from the egress port associated with the destination of the data.
Apparatuses, systems, and techniques to detect a Denial of Service (DoS) attack on a target device by an entity. In at least one embodiment, the detection is followed by an event message to prevent the entity from sending further communications to the target device.
In one embodiments, a system includes a network device including a host interface to receive time synchronization messages generated by software executed by a processing unit of a host device, a hardware clock to maintain a clock time, scheduler circuitry to manage periodic transmission of the time synchronization messages according to the clock time and schedule data provided by the software, and a network interface to transmit the time synchronization messages to at least one clock synchronization follower according to the schedule data and the clock time.
A system for connecting cage-side connectors to PCB-side connectors. The system enables OSFP and QSFP pluggable modules to be connected to breakouts on PCBs within a networking device. The system includes one or more cage-side connectors connected via one or more cables to one or more PCB-side connectors. Keyed PCB-side connectors and unique lengths of cables ensure proper connections to headers on a PCB.
Systems and devices for network data collection and processing are provided. An example system includes a first networked device and a centralized computing device communicably coupled with the at least one networked device. The first networked device operates to generate event-driven data entries associated with the first networked device and generate first data packets including the event-driven data entries and/or manipulated outputs generated based on manipulations to the event-driven data entries. The centralized computing device receives the first data packets from the first networked device and determines configuration updates based on the first data packets. The configuration updates are generated locally by the centralized computing device, and the centralized computing device transmits the one or more configuration updates to the first networked device.
H04L 41/082 - Configuration setting characterised by the conditions triggering a change of settings the condition being updates or upgrades of network functionality
60.
SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR MACHINE LEARNING FOR DATACENTER APPLICATIONS
Methods, systems, devices, and computer program products for machine learning in datacenter applications are provided. An example method includes receiving, by a centralized computing device, data packets from a networked device communicably coupled with the centralized computing device. The networked device is associated with performance of at least a first machine learning based task, and each of the data packets include data entries generated by the networked device based on data traffic associated with the at least one networked device and/or one or more modifications thereto. The method further includes generating updated operational parameters associated with the first machine learning based task based on the data entries forming the plurality of data packets where the updated operational parameters are generated locally by the centralized computing device. The method also includes transmitting, by the centralized computing device, the updated operational parameters to the networked device.
A system can include a ring waveguide, a ring waveguide heater operatively coupled to the ring waveguide, and an interferometer including a first arm waveguide and a second arm waveguide. The first arm waveguide is positioned to be heated by the ring waveguide heater and to not be optically coupled to the ring waveguide, and the second arm waveguide is positioned to be optically coupled to the ring waveguide.
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour
G02F 1/225 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure
62.
SYSTEM AND METHOD FOR COOLING INTERCONNECT MODULES
Assemblies, systems, and methods are provided for dissipating heat from a receptacle assembly for holding a transceiver and attaching to a PCB. The receptacle assembly has a body defining a first end, a second end, a top surface extending between the first end and the second end, and a bottom surface extending between the first end and the second end opposite the top surface. A thermal dissipation device is disposed on the bottom surface, and the thermal dissipation device is configured to dissipate heat from the receptacle assembly to an external environment via the bottom surface. The thermal dissipation device may include at least one conductive element and at least one dissipation element and may interact with other cooling features of the PCB.
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
H01R 25/00 - Coupling parts adapted for simultaneous co-operation with two or more identical counterparts, e.g. for distributing energy to two or more circuits
An interconnect device is provided. In one example, an interconnect device includes ports and circuits to receive measurements from two or more switching devices; determine, based on the measurements, a relative power consumption of each switching device from the two or more switching devices; generate, based on the relative power consumption of each switching device from the two or more switching devices, respective power instructions for each switching device from the two or more switching devices; and distribute the respective power instructions to each switching device from the two or more switching devices.
Rekeying operations can be performed without significantly impacting the execution of software that relies on those keys. In one embodiment, a hardware-based solution connects to a memory controller in a way that hides the rekeying from the software, where the hardware keeps track of which memory addresses in a memory space correspond to new keys. Rekeying can be performed for memory addresses in order, such as from bottom to top addresses in a region table, and a rekeying address can be used to keep track the rekeying process, such that addresses below the rekeying address in the table are to use the new keys and addresses above the rekeying address are to use the current or old key, with the address corresponding to the rekeying address using the prior key for reads and the new key for writes. Keys can then be updated frequently without significant downtime or software modifications.
Systems and methods are described for implementing quantum key distribution (QKD) in a data center environment. An example quantum transmitter includes an on-chip semiconductor laser as a light source to generate photons, quantum state preparation circuitry configured to receive a sequence of bits, map each bit to a quantum state and a measurement basis, and encode the quantum state of each bit onto a corresponding photon to generate a qubit, and a quantum channel interface configured to transmit the qubit to a quantum receiver via a quantum communication channel. An example quantum receiver includes a quantum channel interface to receive qubits, a silicon-based single photon avalanche diode (SPAD) as a photon detector for qubit detection, and quantum state measurement circuitry that is configured to decode the state of each qubit based on a selected measurement basis.
Assemblies and methods of manufacturing are provided for a liquid cooled network-interface controller (NIC) assembly configured to receive and operably engage a transceiver module. An example liquid cooled NIC assembly includes a PCB, a first thermally conductive member supported by the PCB, and a second thermally conductive member supported by the first thermally conductive member. The first thermally conductive member is thermally isolated from the second thermally conductive member. A liquid cooling unit may thermally engage the first thermally conductive member and the second thermally conductive member. The first thermally conductive member and the second thermally conductive member are configured to conduct heat toward the liquid cooling unit, such that the liquid cooling unit may dissipate heat from the first thermally conductive member and the second thermally conductive member.
A system and method for managing congestion in a computer communication network is disclosed. The system comprises a plurality of Network Interface Controllers (NICs) that connect multiple hosts to the network, the NICs supporting a configurable Congestion Control (CC) scheme selected from among multiple available CC schemes. One or more processors coupled to the network are configured to automatically select, based on time-series data indicative of one or more performance measures of the network over time, respective CC schemes and/or CC parameters for one or more of the NICs. The one or more processors provision the selected CC schemes and/or parameters to the NICs and iteratively repeat the selection and provisioning steps in response to updated performance measures so as to optimize network performance.
H04L 47/12 - Avoiding congestionRecovering from congestion
H04L 41/22 - Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks comprising specially adapted graphical user interfaces [GUI]
H04L 43/08 - Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
Systems and methods herein are for a semiconductor product having at least one channel and at least one nozzle formed on or within a surface thereof, where the at least one channel can allow flow of a liquid therethrough, where the at least one nozzle can allow ejection of the liquid to the surface or to an area above the surface, where an enclosure retains the liquid, to provide at least part of a cooling of the semiconductor product having heat absorbed to the liquid from device activity in the semiconductor product.
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
H01L 23/427 - Cooling by change of state, e.g. use of heat pipes
69.
Maximum Compare-and-Swap Remote Direct Memory Operation (RDMO)
A system includes a first network device and a second network device. The first network device is to send over a network a command that (i) specifies a memory location, a compare value and a swap value and (ii) instructs that the swap value be written into the memory location only if the compare value is larger than a current value in the memory location. The second network device is to receive the command over the network, and to execute the command by reading the current value from the memory location, comparing the current value to the compare value, and, upon finding that the compare value is larger than the current value, writing the swap value to the memory location in place of the current value.
H04L 67/1097 - Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
A system includes a first network device and a second network device. The first network device is to send over a network a command that (i) specifies a key for accessing a hash table in a memory and (ii) instructs that a value be read or written at a location in the hash table corresponding to the key. The second network device is to receive the command over the network, and to execute the command by calculating the location in the hash table based on the key, and reading or writing the value at the location.
A system includes a first network device and a second network device. The first network device is to connect a host to a network, and to send over the network a command that requests logging of one or more software transactions conducted in the host. The second network device is to receive the command over the network, and to execute the command by logging the one or more software transactions.
Systems, methods, and computer program products are described for a redundant external laser source in optical systems (e.g., CPO systems). An example system may include a plurality of ELS units, a RELS unit, an optical switch, and a plurality of optical couplers, and a control unit. The control circuit may be configured to detect an operational failure of a first ELS unit. In response to detecting such a failure, the control circuit may configure the RELS unit to replace the first ELS unit and, using the optical switch, substitute the first ELS unit with the RELS unit. Such a configuration ensures continuous system performance by dynamically replacing failing ELS units with redundant ELS units, thereby reducing downtime and enhancing the reliability of the optical communication system.
Modules, systems, and methods for cooling optics and copper packages are described herein. Some embodiments of the present invention may be directed to cooling systems for cooling electronic modules (e.g., network switches) that include optics and copper packages. An electronic module may include a substrate having a first surface defining a central portion and a peripheral portion. A main die (e.g., an ASIC) may be positioned on the central portion of the first surface, and a plurality of optical modules may be positioned on the peripheral portion of the first surface (e.g., around the main die). A cooling system may include a cold plate thermally coupled to the main die that includes a fluid inlet and a fluid outlet for receiving and releasing a cooling fluid. The cooling system may also include multiple cooling conduits, each thermally coupling the cold plate to an optical module.
In one embodiment, a system includes prefetcher engines to predict next memory access addresses of a memory from which to load data to a cache during execution of a software application, and load the data from the predicted next memory access addresses to the cache during execution of the software application, and a processor to assign cache replacement precedence values to cache lines based on the prefetcher engines that loaded the cache lines, and evict the cache lines from the cache based on the cache replacement precedence values of the cache lines.
G06F 12/08 - Addressing or allocationRelocation in hierarchically structured memory systems, e.g. virtual memory systems
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
G06F 12/126 - Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
75.
Reducing set of policies with two or more hyper-dimensions
In one embodiment, a system includes a processor to reduce a number of cache replacement precedence value policies available for selection by a machine learning agent, each cache replacement precedence value policy including an array of predefined cache replacement precedence values for corresponding different combinations of (a) prefetcher engines that loaded cache lines, and (b) event-types of events that have been performed on the cache lines, and a memory to store data used by the processor.
G06F 12/08 - Addressing or allocationRelocation in hierarchically structured memory systems, e.g. virtual memory systems
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
G06F 12/126 - Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
76.
Environmental-based parameters optimization of clock
In one embodiment, a device includes clock circuitry including an oscillator to generate a local clock signal having a clock frequency, and a hardware clock to maintain a local clock responsively to the clock signal, at least one sensor to measure at least one value of at least one environmental parameter, processing circuitry to find at least one value of at least one filter parameter based on the at least one value of the at least one environmental parameter, and a filter to receive an error signal between a remote clock and the local clock, and filter the error signal and generate an adjustment to cause the clock circuitry to adjust the local clock signal or the local clock based on the at least one value of the at least one filter parameter.
A system includes a first network device and a second network device. The first network device is to send over a network a command that specifies a value and instructs that the value be appended to a set of values in a memory. The second network device is to receive the command over the network, and to execute the command by appending the value to the set of values.
H04L 67/1097 - Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
Assemblies and methods of manufacturing are provided for a liquid cooled network-interface controller (NIC) assembly configured to receive and operably engage a transceiver module. An example liquid cooled NIC assembly includes a PCB, a first thermally conductive member supported by the PCB, and a second thermally conductive member supported by the first thermally conductive member. The first thermally conductive member is thermally isolated from the second thermally conductive member. A liquid cooling unit may thermally engage the first thermally conductive member and the second thermally conductive member. The first thermally conductive member and the second thermally conductive member are configured to conduct heat toward the liquid cooling unit, such that the liquid cooling unit may dissipate heat from the first thermally conductive member and the second thermally conductive member.
A network adapter including a host interface, a network interface, packet processing circuitry, and Translation-as-a-Service (TaaS) circuitry. The host interface is to communicate with a host over a peripheral bus. The network interface is to send and receive packets to and from a network for the host. The packet processing circuitry is to process the packets. The TaaS circuitry is integrated in the network adapter and is to (i) receive from a requesting device a request to translate an input address into a requested address in a requested address space, (ii) translate the input address into the one or more requested addresses, and (iii) return the one or more requested addresses to the requesting device.
G06F 12/1072 - Decentralised address translation, e.g. in distributed shared memory systems
H04L 67/1097 - Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
A system includes one or more processors to trace one or more packets transmitted by an application distributed among a plurality of computing nodes. The one or more processors are to generate tracing data based at least in part on tracing the one or more packets. The tracing data includes temporal information associated with transmission of the one or more packets. The one or more processors are to manage a data allocation associated with the application based on the tracing data.
Some embodiments of the present disclosure are directed to wafer alignment in multiple dies. For example, a receptacle wafer and a photonic wafer may be prepared containing a plurality of individual dies. Further, these two wafers may be aligned, wafer bonded, and cut into the individual dies. Additionally, or alternatively, these individual dies may be ready to be attached to a substrate and require no further alignment. The method of the present disclosure may be (i) cost effective since a single, passive receptacle wafer alignment results in multiple dies, (ii) repeatable (e.g., less variance in production) since it utilizes silicon lithography alignment features and scalable silicon WOW assembly, and (iii) improve optical performance since the thin receptacle wafer has a lower height resulting in a shorter optical path.
Some embodiments of the present disclosure are directed to optical connectors and methods of assembling the same. For example, the present disclosure provides for a “semi-detachable” connector. A mechanical receptacle may be actively aligned to the photonic integrated circuit die, allowing for full testing of the device and for a simplified assembly process. At a later step in the assembly process, the connector may be placed on the receptacle (passively—already tested) and the connector may be adhered to the receptacle. The present disclosure may result in a simplified assembly, and a smaller device size that fits inside an octal small form factor pluggable (OSFP) transceiver.
Systems and methods are described herein for drop port assisted resonance detection for ring assisted Mach-Zehnder Interferometers (RAMZI). An example system comprises a ring assisted Mach-Zehnder Interferometer (RAMZI) that includes a Mach-Zehnder Interferometer (MZI) and a ring resonator, a drop port operatively coupled to the ring resonator, and a control circuit operatively coupled to the drop port and the RAMZI. The drop port is configured to capture an optical signal indicative of an output power spectrum of the ring resonator, and the control circuit is configured to tune the RAMZI for spectral alignment between the MZI and the ring resonator based on at least the optical signal.
G01B 11/27 - Measuring arrangements characterised by the use of optical techniques for measuring angles or tapersMeasuring arrangements characterised by the use of optical techniques for testing the alignment of axes for testing the alignment of axes
A computer system includes a processor and a Duplicate Write Circuit (DWC). The DWC is to hold a definition that specifies an address range and a plurality of additional address ranges, and to receive, from the processor, a write command that specifies a write-data and a write-address. When the write-address falls outside the address range, the DWC is to generate a write cycle that writes the write-data to the address. When the write-address falls in the address range, the DWC is to generate (i) the write cycle that writes the write-data to the address, and (ii) a sequence of additional write cycles that write the write-data to corresponding addresses in the additional address ranges.
Some embodiments of the present disclosure are directed to an optical waveguide for co-packaged optics packages. For example, a module may include a substrate having a substrate optical waveguide, an interposer disposed on a surface of the substrate, where the interposer comprises an interposer optical waveguide, and where the interposer is configured to optically align the interposer optical waveguide with the substrate optical waveguide, a main die disposed on a surface of the interposer, and a photonic IC disposed on the surface of the interposer and configured to be in optical communication with the interposer optical waveguide. Additionally, or alternatively, the substrate optical waveguide may be configured to convey optical signals between the substrate and the interposer. Further, the interposer optical waveguide may be configured to convey optical signals between the surface of the substrate and the interposer.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
G02B 6/42 - Coupling light guides with opto-electronic elements
H01L 23/00 - Details of semiconductor or other solid state devices
A receiver including a first component to receive a signal including a sequence of symbols and generate an equalized signal with an estimated sequence of symbols corresponding to the signal. The receiver further includes a second component to generate, based on the equalized signal, a decision including a sequence of one or more bits that represent each symbol of the estimated sequence of symbols. The second component of the receiver further generates a confidence level corresponding to the decision, wherein the confidence level is based on a comparison of a first probability that the equalized signal comprises two or more errors and a second probability that the equalized signal comprises zero errors.
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
Systems, devices, and methods are provided. In one example, a system is described that includes circuits to receive a plurality of numbers at a first computing system, perform an operation on the plurality of numbers to generate a number, and use the generated number to perform stochastic rounding of a floating point number to generate a stochastically rounded floating point number.
G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow
G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
88.
ELECTRONIC DEVICE INCLUDING LIQUID COOLANT CONDUIT WITH HELICAL PORTION
An electronic device, which may include an electronic component, a cooling body in thermal contact with the electronic component, a conduit coupled to the cooling body to deliver a coolant to or from the cooling body, the conduit comprising a coiled portion, and a coupler coupled to the coiled portion of the conduit, the coupler being removably couplable to a coolant infrastructure coupler.
In one embodiment, a system includes a network device application-specific integrated circuit (ASIC), which includes a microcontroller to provide a command to a hardware accelerator to perform a job including gathering telemetry data from at least one hardware unit and write the gathered telemetry data to a memory, and the hardware accelerator to gather the telemetry data from the at least one hardware unit and write the gathered telemetry data to the memory based on the command.
G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
H04Q 9/00 - Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
A system for transmitting data is described, among other things. An illustrative system is disclosed to include one or more circuits to perform receive-side scaling (RSS) by receiving a packet, identifying one or more bits in the packet, and forwarding the packet to a receiving queue based on the identified one or more bits in the packet.
A device, systems, and method are described which provide low memory determination of an nth percentile. The device, systems, and method include receiving user input indicating a percentile (n) to be approximated for a measurement. The device, systems, and method further include initializing an nth-percentile estimator to an initial value and using a control loop to update the nth-percentile estimator until n% of samples are lower than the nth-percentile estimator and 100%-n% of samples are higher than the nth-percentile estimator, wherein for each value in a set of data, the nth-percentile estimator is updated based on whether each value is higher or lower than the nth-percentile estimator.
In one embodiment, a responder device includes a network interface to receive packets of a stream of packets transmitted from a requester device with packet sequence numbers, and packet processing circuitry to collect information about the packet sequence numbers of the packets that have been received from the requester device, generate a selective acknowledgement including an indication of the packet sequence numbers of at least one packet of the packets that has been received and at least one other packet of the packets that has not been received by the responder device from the requester device, wherein the at least one packet that has been received by the responder device includes at least one of the packets received out-of-order according to the packet sequence numbers, and send the selective acknowledgement to the requester device via the network interface.
A network device includes a hardware-implemented packet processing pipeline includes: multiple pipeline stages, and a processor. The hardware-implemented packet processing pipeline is to process packets exchanged with a packet network. The processor is to execute sideband tasks for the packet processing pipeline. At least one of the pipeline stages is to trigger the processor to execute a sideband task by posting a Completion-Queue Element (CQE) on a Completion Queue (CQ) accessible to the processor.
A system for predicting and/or capturing data relating to anomalies in a networking device is provided. In one example, a networking device receives telemetry data, stores the telemetry data in a cyclic buffer, detects an anomaly, and outputs the telemetry data from the cyclic buffer. The telemetry data from the cyclic buffer may be used for training a prediction model. In another example, a trained prediction model analyzes telemetry data sampled at a first rate, predicts a future anomaly, and in response to the prediction of the future anomaly, triggers sampling of the telemetry at a second rate, faster than the first rate.
H04L 67/12 - Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
H04L 67/147 - Signalling methods or messages providing extensions to protocols defined by standardisation
In one embodiment, a sender node includes packet processing circuitry to associate, at layer 2 or 3 of Open Systems Interconnection (OSI) model, path identifiers and per-path packet sequence numbers with packets, wherein the path identifiers identify paths from the sender node to receiver nodes, and an interface to send the packets with the associated packet sequence numbers and path identifiers to the receiver nodes.
Technologies for spreading a burst of data across multiple network paths in remote direct memory access (RDMA) over converged Ethernet (ROCE) and InfiniBand are described. A RDMA adapter receives, from a requestor device over a local interface, a request to send data of a transport flow directed to a target device over a network interface, and one or more parameters being related to a multipath selection by the network controller. The RDMA adapter sends a first burst of data of the transport flow via a first network path to the target device. The RDMA adapter identifies, using the one or more parameters, a second network path to the target device. The RDMA adapter sends the second burst of data to the target device on the second network path.
A peripheral device includes a bus interface and circuitry. The bus interface is to exchange bus transactions over a peripheral bus that permits out-of-order transfer of at least some of the bus transactions. The circuitry is to generate a plurality of streams of the bus transactions, to select, from among the plurality of streams, one or more streams for which transaction ordering is required, to enforce the transaction ordering among the bus transactions of the selected streams, and to send the bus transactions via the bus interface to the peripheral bus.
Approaches presented herein provide for the reduction of unwanted electrical reflections caused by impedance mismatches at an input of an optical modulator device, such as at the interface between a (radio frequency) signal source and an electro-absorption modulated laser (EML). Reflections can be reduced though use of one or more electrical filters, such as resistor-capacitor (RC) filters, that can be placed at the input of the EML device to reduce reflections through impedance matching at that location, while maintaining the efficiency and bandwidth of the modulator for high bandwidth transmission. Such a filter can be used with a single ended or differential EML device, and can be integrated on an EML chip or added as discrete components on a chip carrier on which the EML chip is supported.
Systems, computer program products, and methods are described for efficient link-down management. An example transmitter detects an impending link-down event at the transmitter. Once detected, the transmitter encodes the link-down event within a control block. The encoded control block is then transmitted via a physical layer of the communication network to a receiver. Once the control block is transmitted, the transmitter then initiates the link-down event. An example receiver receives the control block via a physical layer of the communication network from a transmitter. Then, the receiver extracts, from the control block, an operational code (opcode) identifying an impending link-down event at the transmitter. In response, the receiver retrieves, from a database, a responsive action corresponding to the link-down event based on the extracted opcode and subsequently executes the responsive action.
Systems and methods are described for in-band spectral cross-talk monitoring. An example system includes a built-in self-test (BIST) and logic circuitry and a processor. The processor is operatively coupled to the BIST and logic circuitry, a first micro ring modulator (MRM) associated with a first data packet (FD), and a second MRM associated with a second data packet (SD). The processor is configured to: receive, from the first MRM, a complement of the first data packet (FD) that comprises second MRM spectral cross-talk data; receive, from a second MRM, a complement of the second data packet (SD); and determine, using the BIST and logic circuitry, a spectral ordering of the FD and the SD based on at least the second MRM spectral cross-talk data and the SD to address shifting in the initial mapping of the positional order of the MRMs and the spectral order of the data packets.
H04B 10/073 - Arrangements for monitoring or testing transmission systemsArrangements for fault measurement of transmission systems using an out-of-service signal
H04B 10/80 - Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups , e.g. optical power feeding or optical transmission through water
