A hybrid photonic circuit with one or more nonlinear photonic elements. The photonic circuit includes one or more photonic logic gate and one or more nonlinear photonic elements coupled to the one or more photonic logic gate. The one or more photonic logic gates receives one or more photonic input signals and generate one or more photonic intermediate output signals based at least in part on the one or more photonic input signals. The one or more nonlinear photonic elements receive the one or more photonic intermediate output signals and generate one or more photonic output signals through application of a nonlinear transfer function of the one or more nonlinear photonic elements to one or more amplitudes of the one or more photonic intermediate output signals.
A photonic circuit configured to operate as a universal photonic gate. The photonic circuit includes at least a first photonic gate and a first nonlinear photonic circuit coupled to the first photonic gate. The first photonic gate receives one or more photonic input signals and generates, based at least in part on the one or more photonic input signals, one or more first photonic intermediate output signals. The first nonlinear photonic circuit receives the one or more first photonic intermediate output signals and generates one or more first photonic output signals by applying a first nonlinear transfer function of the first nonlinear photonic circuit to the one or more first photonic intermediate output signals. A logical function of the photonic circuit depends on phase shifts applied by phase shifters of the first photonic gate and an amplitude value of a bias signal input into the first photonic gate.
A photonic circuit operating as a photonic register includes a first set of cascading photonic gates coupled to a second set of cascading photonic gates. The first set of cascading photonic gates generates, at a first output, a first intermediate output signal based on a first photonic input signal and a second photonic input signal, and generates, at a second output, a second intermediate output signal based on the second intermediate output signal and the second photonic input signal. The second set of cascading photonic gates generates, at a first output, a first photonic output signal based on the first intermediate output signal and a second photonic output signal that was generated at a second output. The second set of cascading photonic gates generates, at the second output, the second photonic output signal based on the first intermediate output signal and the first photonic output signal.
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
H03K 3/42 - Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
A photonic counter circuit presented herein includes a first photonic circuit coupled to a second photonic circuit. A first input of the first photonic circuit is coupled to an output of the first photonic circuit, and a second input of the first photonic circuit receives a photonic clock signal. The first photonic circuit generates a first photonic output bit signal based in part on the photonic clock signal. A first input of the second photonic gate is coupled to an output of the second photonic gate. A second input of the second photonic gate is coupled to the output of the first photonic gate and receives the first photonic output bit signal. The second photonic circuit generates a second photonic output bit signal based in part on the first photonic output bit signal.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
A photonic circuit that operates as a photonic flip-flop includes a first photonic gate coupled to a second photonic gate. A first input of the first photonic gate receives a first photonic input signal. A second input of the first photonic gate is coupled to an output of the second photonic gate and receives a second photonic output signal generated by the second photonic gate. The first photonic gate generates a first photonic output signal based on the first photonic input signal and the second photonic output signal. A first input of the second photonic gate receives a second photonic input signal. A second input of the second photonic gate is coupled to an output of the first photonic gate and receives the first photonic output signal. The second photonic gate generates the second photonic output signal based on the second photonic input signal and the first photonic output signal.
A photonic processor with multiple layers of feedback. At least one of a first set of photonic adders in the photonic processor includes a feedback path feeding a first feedback signal from a carry output to an input of the at least one first photonic adder. The at least one first photonic adder generates a photonic sum based in part on the first feedback signal. At least one of a second set of photonic adders in the photonic processor includes a feedback path feeding a second feedback signal from a carry output to an input of the least one second photonic adder. The at least one second photonic adder generates an updated version of a photonic input signal based in part on the second feedback signal and the photonic sum. A feedback interface feeds the updated version of the photonic input signal back to an input of the photonic processor.
G06E 1/04 - Devices for processing exclusively digital data operating upon the order or content of the data handled for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
A photonic circuit with at least one nonlinear amplitude thresholder for correcting errors produced by linear photonic logic. One or more photonic input gates of the photonic circuit receive one or more input signals and generate one or more photonic signals based on the one or more photonic input signals. A first set of one or more photonic gates of the photonic circuit generates one or more intermediate photonic signals based on the one or more photonic signals. The at least one nonlinear amplitude thresholder generates at least one photonic thresholding signal based on the one or more intermediate photonic signals, the at least one nonlinear amplitude thresholder operating in a first operating regime, second operating regime, and/or third operating regime. A second set of one or more photonic gates of the photonic circuit generates one or more photonic output signals based on the at least one photonic thresholding signal.
G02F 1/365 - Non-linear optics in an optical waveguide structure
G02F 1/225 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure
A photonic circuit for generating an ultrafast clock for a photonic processor. The photonic circuit includes a beam splitter, a phase shifter, a first photonic combiner coupled to the beam splitter and the phase shifter, and a second photonic combiner coupled to the beam splitter and the first photonic combiner. The beam splitter splits a received photonic seed clock signal into a first photonic seed clock signal and a second photonic seed clock signal. The phase shifter shifts a phase of a received photonic signal to generate a phase-shifted version of the photonic signal. The first photonic combiner combines the second photonic seed clock signal with the phase-shifted version of the photonic signal to generate a first combined photonic signal. The second photonic combiner combines a delayed and attenuated version of the first photonic seed clock signal with the first combined photonic signal to generate a photonic clock signal.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
H01S 3/00 - Lasers, i.e. devices using stimulated emission of electromagnetic radiation in the infrared, visible or ultraviolet wave range
H03K 3/86 - Generating pulses by means of delay lines and not covered by the preceding subgroups
9.
CASCADABLE PHOTONIC CIRCUIT WITH SEMICONDUCTOR OPTICAL AMPLIFIER BASED AMPLITUDE THRESHOLDER
A photonic circuit with at least one semiconductor optical amplifier-based amplitude thresholder for correcting bit errors. The photonic circuit further includes a first cascaded series of one or more photonic components and a second cascaded series of one or more photonic components that is coupled to the at least one amplitude thresholder. The first cascaded series of one or more photonic components generates one or more intermediate photonic output signals based on one or more received photonic input signals. The at least one amplitude thresholder generates one or more thresholding photonic signals based on a first of the one or more photonic output signals. The second cascaded series of one or more photonic components generates one or more photonic output signals based at least in part on a second of the one or more intermediate photonic output signals and the one or more thresholding photonic signals.
A photonic circuit with a semiconductor optical amplifier-based amplitude thresholder for correcting bit errors produced by a passive photonic logic. In addition to the amplitude thresholder, the photonic circuit further includes a plurality of photonic inputs receiving photonic input signals, a first cascaded series of photonic components coupled to the photonic inputs, and a second cascaded series of photonic components coupled to the amplitude thresholder. The first cascaded series of photonic components generates a plurality of intermediate photonic output signals based on the photonic input signals. The amplitude thresholder generates a saturated photonic signal based on a first of the plurality of intermediate photonic output signals when the amplitude thresholder operates in a single nonlinear region. The second cascaded series of photonic components generates a photonic output signal based at least in part on a second of the plurality of intermediate photonic output signals and the saturated photonic signal.
Embodiments of the present disclosure are directed to an efficient design of a photonic circuit by an emulator circuit that optimizes coefficients of an S-matrix representation model of the photonic circuit. The emulator circuit comprises a first optimizer circuit, a comparator circuit, and a second optimizer circuit. The first optimizer circuit determines target coefficients of a target S-matrix representation model of the photonic circuit, based on photonic input signals and target photonic output signals of the target S-matrix representation model. The comparator circuit compares the target coefficients with device coefficients of an S-matrix representation model of the photonic circuit. The second optimizer circuit iteratively updates the device coefficients based on the comparison to determine final device coefficients. The photonic circuit is defined in accordance with the determined final device coefficients.
Embodiments are directed to designing area and power-efficient photonic super-gates. A first modeling circuit of an emulator circuit generates a physical model for a photonic circuit having a plurality of cascaded photonic gates, based on a set of photonic input signals and a set of one or more photonic output signals that are defined in accordance with a truth table of the photonic circuit. Based on the physical model, a first optimizer circuit of the emulator circuit estimates initial parameters of a target model for the photonic circuit. A second modeling circuit of the emulator circuit generates, based on the initial parameters, a set of parameters of the target model. A second optimizer circuit of the emulator circuit executes a design algorithm on the set of parameters of the target model to instantiate a photonic super-gate that emulates operations of the photonic circuit.
Embodiments of the present disclosure are directed to an integrated circuit with photonic bit-corrector circuits. The integrated circuit includes a photonic circuit, a photonic bit-corrector circuit, a photodetector array coupled to the photonic bit-corrector circuit, and an electronic circuit coupled to the photodetector array. The photonic circuit includes a plurality of cascaded photonic gates configured to generate a first photonic output signal for a set of photonic input signals applied to the photonic circuit. The photonic bit-corrector circuit is configured to generate a second photonic output signal for the set of photonic input signals applied to the photonic bit-corrector circuit. The photodetector array is configured to generate an electrical signal based on the second photonic output signal. The electronic circuit is configured to compare the electrical signal with a label signal and output a corrected version of the first photonic output signal based on the comparison.
Embodiments of the present disclosure are directed to an integrated circuit with photonic bit-corrector circuits. The integrated circuit includes a photonic circuit, a photonic bit-corrector circuit, a photodetector array coupled to the photonic bit-corrector circuit, and an electronic circuit coupled to the photodetector array. The photonic circuit includes a plurality of cascaded photonic gates configured to generate a first photonic output signal for a set of photonic inputs applied to the photonic circuit. The photonic bit-corrector circuit is configured to generate a second photonic output signal for the set of photonic input signals applied to the photonic bit-corrector circuit. The photodetector array is configured to generate an electrical signal based on the second photonic output signal. The electronic circuit is configured to compare the electrical signal with a label signal and output a corrected version of the first photonic output signal based on the comparison.
H03K 19/14 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
G06E 1/00 - Devices for processing exclusively digital data
H03K 19/003 - Modifications for increasing the reliability
G06N 3/067 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using optical means
Embodiments of the present disclosure are directed to an integrated circuit with a photonic processor and an electrical analog memory. The integrated circuit further includes an array of photonic intensity modulators coupled to the photonic processor via a first set of optical connections, and an array of photodetectors coupled to the photonic processor via a second set of optical connections. The electrical analog memory is directly coupled to the array of photodetectors and the array of photonic intensity modulators.
Embodiments of the present disclosure are directed to an integrated circuit with a photonic processor and an electrical analog memory. The integrated circuit further includes an array of photonic intensity modulators coupled to the photonic processor via a first set of optical connections, and an array of photodetectors coupled to the photonic processor via a second set of optical connections. The electrical analog memory is directly coupled to the array of photodetectors and the array of photonic intensity modulators.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
Embodiments of the present disclosure are directed to an integrated circuit with photonic bit-corrector circuits. The integrated circuit includes a photonic circuit, a photonic bit-corrector circuit, a photodetector array coupled to the photonic bit-corrector circuit, and an electronic circuit coupled to the photodetector array. The photonic circuit includes a plurality of cascaded photonic gates configured to generate a first photonic output signal for a set of photonic input signals applied to the photonic circuit. The photonic bit-corrector circuit is configured to generate a second photonic output signal for the set of photonic input signals applied to the photonic bit-corrector circuit. The photodetector array is configured to generate an electrical signal based on the second photonic output signal. The electronic circuit is configured to compare the electrical signal with a label signal and output a corrected version of the first photonic output signal based on the comparison.
Embodiments of the present disclosure are directed to a photonic implementation of a processor for message generation for digital currency (e.g., bitcoin) transactions. The processor includes an input photonic circuit and a message generation photonic circuit coupled to the input photonic circuit via a first set of optical connections. The input photonic circuit receives input data of a first size and splits the received input data into a plurality of input messages of a second size. The message generation photonic circuit receives the plurality of input messages from the input photonic circuit via the first set of optical connections, and generates a plurality of output messages of the second size based at least in part on the plurality of input messages.
G06E 3/00 - Devices not provided for in group , e.g. for processing analogue or hybrid data
G06Q 20/36 - Payment architectures, schemes or protocols characterised by the use of specific devices using electronic wallets or electronic money safes
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
19.
PHOTONIC IMPLEMENTATION OF MESSAGE GENERATION FOR DIGITAL CURRENCY TRANSACTIONS
Embodiments of the present disclosure are directed to a photonic implementation of a processor for message generation for digital currency (e.g., bitcoin) transactions. The processor includes an input photonic circuit and a message generation photonic circuit coupled to the input photonic circuit via a first set of optical connections. The input photonic circuit receives input data of a first size and splits the received input data into a plurality of input messages of a second size. The message generation photonic circuit receives the plurality of input messages from the input photonic circuit via the first set of optical connections, and generates a plurality of output messages of the second size based at least in part on the plurality of input messages.
H03K 19/14 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
G06Q 20/06 - Private payment circuits, e.g. involving electronic currency used only among participants of a common payment scheme
20.
Photonic implementation of keys update and hash generation for digital currency transactions
Embodiments of the present disclosure are directed to a photonic implementation of a processor for keys update and hash generation for digital currency (e.g., bitcoin) transactions. The processor includes a first photonic circuit and a second photonic circuit coupled to the first photonic circuit via a set of optical connections. The first photonic circuit is configured to generate a plurality of new messages based at least in part on a plurality of input messages. During a plurality of operational cycles, the second photonic circuit is configured to receive, from the first photonic circuit via the set of optical connections, the plurality of new messages, and update a plurality of keys based at least in part on the received plurality of new messages. The second photonic circuit is further configured to generate at least one hash value based on the plurality of keys generated after the plurality of operational cycles.
G06E 3/00 - Devices not provided for in group , e.g. for processing analogue or hybrid data
G06Q 20/36 - Payment architectures, schemes or protocols characterised by the use of specific devices using electronic wallets or electronic money safes
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
21.
PHOTONIC IMPLEMENTATION OF KEYS UPDATE AND HASH GENERATION FOR DIGITAL CURRENCY TRANSACTIONS
Embodiments of the present disclosure are directed to a photonic implementation of a processor for keys update and hash generation for digital currency (e.g., bitcoin) transactions. The processor includes a first photonic circuit and a second photonic circuit coupled to the first photonic circuit via a set of optical connections. The first photonic circuit is configured to generate a plurality of new messages based at least in part on a plurality of input messages. During a plurality of operational cycles, the second photonic circuit is configured to receive, from the first photonic circuit via the set of optical connections, the plurality of new messages, and update a plurality of keys based at least in part on the received plurality of new messages. The second photonic circuit is further configured to generate at least one hash value based on the plurality of keys generated after the plurality of operational cycles.
H03K 19/14 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
G06Q 20/06 - Private payment circuits, e.g. involving electronic currency used only among participants of a common payment scheme
patents
