Hft Solutions, LLC

United States of America

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H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal 11
G06F 1/08 - Clock generators with changeable or programmable clock frequency 6
G06F 30/34 - Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] 6
H04J 3/06 - Synchronising arrangements 6
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation 5
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Found results for  patents

1.

Field programmable gate array with external phase-locked loop

      
Application Number 18067332
Grant Number 12113539
Status In Force
Filing Date 2022-12-16
First Publication Date 2024-10-08
Grant Date 2024-10-08
Owner HFT Solutions, LLC (USA)
Inventor Badizadegan, Nima

Abstract

The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

IPC Classes  ?

  • H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • G06F 1/08 - Clock generators with changeable or programmable clock frequency
  • G06F 30/34 - Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
  • H04J 3/06 - Synchronising arrangements

2.

Field programmable gate array with internal phase-locked loop

      
Application Number 17723130
Grant Number 12107587
Status In Force
Filing Date 2022-04-18
First Publication Date 2024-10-01
Grant Date 2024-10-01
Owner HFT Solutions, LLC (USA)
Inventor Badizadegan, Nima

Abstract

The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

IPC Classes  ?

  • H03L 7/08 - Details of the phase-locked loop
  • G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
  • H03K 19/17736 - Structural details of routing resources
  • H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • H03M 9/00 - Parallel/series conversion or vice versa
  • H04B 1/40 - Circuits

3.

Field programmable gate array with external phase-locked loop

      
Application Number 17723145
Grant Number 11575381
Status In Force
Filing Date 2022-04-18
First Publication Date 2023-02-07
Grant Date 2023-02-07
Owner HFT Solutions, LLC (USA)
Inventor Badizadegan, Nima

Abstract

The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

IPC Classes  ?

  • H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • G06F 1/08 - Clock generators with changeable or programmable clock frequency
  • G06F 30/34 - Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
  • H04J 3/06 - Synchronising arrangements

4.

Field programmable gate array with external phase-locked loop

      
Application Number 17405188
Grant Number 11502694
Status In Force
Filing Date 2021-08-18
First Publication Date 2022-11-15
Grant Date 2022-11-15
Owner HFT Solutions, LLC (USA)
Inventor Badizadegan, Nima

Abstract

The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

IPC Classes  ?

  • H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • G06F 30/34 - Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
  • G06F 1/08 - Clock generators with changeable or programmable clock frequency
  • H04J 3/06 - Synchronising arrangements

5.

Field programmable gate array with internal phase-locked loop

      
Application Number 17236577
Grant Number 11329655
Status In Force
Filing Date 2021-04-21
First Publication Date 2022-05-10
Grant Date 2022-05-10
Owner HFT Solutions, LLC (USA)
Inventor Badizadegan, Nima

Abstract

The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

IPC Classes  ?

  • H03L 7/08 - Details of the phase-locked loop
  • H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • H03M 9/00 - Parallel/series conversion or vice versa
  • H03K 19/17736 - Structural details of routing resources
  • G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
  • H04B 1/40 - Circuits

6.

Field programmable gate array with external phase-locked loop

      
Application Number 17248304
Grant Number 11128305
Status In Force
Filing Date 2021-01-19
First Publication Date 2021-09-21
Grant Date 2021-09-21
Owner HFT SOLUTIONS, LLC (USA)
Inventor Badizadegan, Nima

Abstract

The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

IPC Classes  ?

  • H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • H04J 3/06 - Synchronising arrangements
  • G06F 30/34 - Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
  • G06F 1/08 - Clock generators with changeable or programmable clock frequency

7.

Field programmable gate array with internal phase-locked loop

      
Application Number 16937309
Grant Number 11018678
Status In Force
Filing Date 2020-07-23
First Publication Date 2021-05-25
Grant Date 2021-05-25
Owner HFT SOLUTIONS, LLC (USA)
Inventor Badizadegan, Nima

Abstract

The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

IPC Classes  ?

  • H03L 7/08 - Details of the phase-locked loop
  • H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • H03K 19/17736 - Structural details of routing resources
  • H04B 1/40 - Circuits
  • H03M 9/00 - Parallel/series conversion or vice versa
  • G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation

8.

Field programmable gate array with external phase-locked loop

      
Application Number 16937314
Grant Number 10931286
Status In Force
Filing Date 2020-07-23
First Publication Date 2021-02-23
Grant Date 2021-02-23
Owner HFT SOLUTIONS, LLC (USA)
Inventor Badizadegan, Nima

Abstract

The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

IPC Classes  ?

  • H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • G06F 1/08 - Clock generators with changeable or programmable clock frequency
  • G06F 30/34 - Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
  • H04J 3/06 - Synchronising arrangements

9.

Field programmable gate array with external phase-locked loop

      
Application Number 16672076
Grant Number 10826502
Status In Force
Filing Date 2019-11-01
First Publication Date 2020-11-03
Grant Date 2020-11-03
Owner HFT SOLUTIONS, LLC (USA)
Inventor Badizadegan, Nima

Abstract

The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

IPC Classes  ?

  • H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • G06F 1/08 - Clock generators with changeable or programmable clock frequency
  • G06F 30/34 - Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
  • H04J 3/06 - Synchronising arrangements

10.

Field programmable gate array with internal phase-locked loop

      
Application Number 16670702
Grant Number 10771069
Status In Force
Filing Date 2019-10-31
First Publication Date 2020-09-08
Grant Date 2020-09-08
Owner HFT SOLUTIONS, LLC (USA)
Inventor Badizadegan, Nima

Abstract

The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

IPC Classes  ?

  • H03L 7/08 - Details of the phase-locked loop
  • H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
  • H04B 1/40 - Circuits
  • H03M 9/00 - Parallel/series conversion or vice versa
  • H03K 19/17736 - Structural details of routing resources

11.

Field programmable gate array with internal phase-locked loop

      
Application Number 16888218
Grant Number 10763865
Status In Force
Filing Date 2020-05-29
First Publication Date 2020-09-01
Grant Date 2020-09-01
Owner HFT SOLUTIONS, LLC (USA)
Inventor Badizadegan, Nima

Abstract

The present invention relates to a field programmable gate array system that provides phase control with minimal latency.

IPC Classes  ?

  • H04L 7/08 - Speed or phase control by synchronisation signals the synchronisation signals recurring cyclically
  • H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
  • H03M 9/00 - Parallel/series conversion or vice versa
  • H04B 1/40 - Circuits
  • H03K 19/17736 - Structural details of routing resources