The present invention relates to a single photon avalanche diodes-based time-of-flight sensor (100). The single photon avalanche diodes (SPADs) based time-of-flight (ToF) sensor (100) includes an Nx N single photon avalanche diode (SPAD) photodetector (101), a front-end (FE) unit (103), a pulse shaping (PS) unit (105), a pulse store unit (107), a peak detection unit (109), a digital logic unit (111), a timing processing circuitry unit (113), and memory elements unit (115). Due to integration of multiple units in single photon avalanche diodes (SPADs) based time-of-flight (ToF) sensor (100), the single photon avalanche diodes-based time-of-flight (ToF) sensor (100) accurately measures distance by adequate, suitable, and efficient elimination of background light.
The invention relates to a CIS technology that uses impulsive metrics and non-linear/higher order statistics to substantially reduce the random telegraph signal (RTS) noise. The CMOS image sensor includes a 4T active pixel pinned photodiode (301), a row select transistor (202), a low noise column level amplifier (203), a thermal noise filter (204), a maxima detector (205) and a minima detector (206), a simple and hold reset switch (207), a simple and hold signal switch (208), an analog to digital convertor (209). The maxima and the minima values obtained from the maxima detector (205) and the minima detector (206) provides a median value. Further, the dual capacitor used in the maxima detector (205) and minima detector (206) gets charged and discharged simultaneously during the reset phase and the signal phase. Due to this, there is a substantial reduction of the RTS noise components.
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
3.
High dynamic range CMOS image sensor having multi-step voltage gain enhancement for low light vision
A method and a system are disclosed for pixel-embedded signal amplification of a CMOS image sensor using multi-step voltage-gain enhancement. It involves activating a row of the CMOS image sensor by resetting switches SRST 202, SH1 201 and SH2 209 to charge nodes PD1, PD2, SD1, and SD2 to a pre-set voltage potential and VRST 203. The CMOS sensor switches OFF SRST 202, SH1 201 and SH2 209 for integration of the charges at PD1 for producing a corresponding photo-generated signal. This signal is sampled by transferring to a gate of source follower SF1, to produce an amplified signal. It further involves double-sampling the amplified signal for removing any pixel-offset variation to produce a resultant signal. The said method is repeated for second row of CMOS image sensor for implementing additional gain on the resultant voltage signal, and the same is finally converted to digital bits to obtain an output signal of with enhanced gain.
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
H04N 25/778 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
4.
High dynamic range CMOS image sensor by pixel-embedded signal amplification and method thereof
A method and a system are described for improving a dynamic range of a CMOS image sensor by pixel-embedded signal amplification. An electromagnetic radiation is incident for a predetermined duration on a pixel array including a plurality of photodiodes. The photodiodes release electrons in form of an input electronic signal and the released input signal is temporarily stored in a storage node. The said input signal is then transferred to a gate of an in-pixel amplifier, which is configured to dynamically alternate between modes of capacitance and switched biasing, using a single in-pixel switch. Then, the in-pixel amplifier is modulated while in capacitance mode for a voltage build-up and this augment gain of the input signal. Thereafter, the in-pixel amplifier alternates to a switched biasing mode for suppression of noise signals. Finally, a resultant electronic signal is generated with a high gain after processing and suppression of the noise signals.
H04N 5/363 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise
H04N 5/378 - Readout circuits, e.g. correlated double sampling [CDS] circuits, output amplifiers or A/D converters
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H04N 25/65 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/778 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
patents