B01D 53/04 - Separation of gases or vapoursRecovering vapours of volatile solvents from gasesChemical or biological purification of waste gases, e.g. engine exhaust gases, smoke, fumes, flue gases or aerosols by adsorption, e.g. preparative gas chromatography with stationary adsorbents
Semiconductor devices and methods of forming the same include a bottom transistor having a bottom gate. A top transistor has a top gate above the bottom gate and is separated from the bottom transistor by a dielectric layer. A conductive via extends through the top gate and the dielectric layer to contact the bottom transistor. A dielectric liner between the conductive via and the top gate electrically insulates the top gate from the conductive via.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A semiconductor structure (2000) includes a first transistor including a first set of one or more channels (110), a second transistor vertically stacked over the first transistor, the second transistor including a second set of one or more channels (138), the second set of channels of the second transistor being horizontally offset from the first set of channels of the first transistor. The semiconductor structure also includes a power plane (164) at a first side of the semiconductor structure, and a contact (170) extending from the first side of the semiconductor structure, through the power plane, to a source/drain region (144) of the second transistor.
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
A semiconductor structure including a first stack of semiconducting layers, a second stack of semiconducting layers, wherein the first stack of semiconducting layers has at least one fewer layer than the second stack of semiconducting layers, and a backside channel plug directly beneath the first stack of semiconducting layers.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
Semiconductor devices include a bottom layer and a top layer. The bottom layer includes a pair of first channel regions being separated by a first dielectric bar, a pair of second channel regions being separated by a second dielectric bar, and a gate structure having an integral backside contact between the first channel regions and the second channel regions. The top layer includes third channel regions, over and laterally offset with respect to the first channel regions, and fourth channel regions, over and laterally offset with respect to the second channel regions.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
6.
STACKED TRANSISTOR STRUCTURES WITH ALIGNED CELL BOUNDARIES AND SHIFTED CHANNELS
A semiconductor structure includes a first transistor and a second transistor vertically stacked over the first transistor. The first transistor and the second transistor have horizontally aligned cell boundaries (801). A first set of one or more channels (110) of the first transistor are horizontally offset from a second set of one or more channels (142) of the second transistor within the horizontally aligned cell boundaries.
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
A microelectronic structure including an underlying device. An interconnect located on the underlying device. Interconnect includes a first Mx metal line and a second Mx metal line. The first Mx metal line is located adjacent to the second Mx metal line. A jumper connects the first Mx metal line to the second Mx metal line and the first Mx metal line extends higher than the jumper.
Memory recall for neural networks, including: receiving one or more inputs for a neural network; determining if an entry corresponding to the one or more inputs is stored in a memory lookup table for the neural network, wherein the memory lookup table comprises a plurality of entries each associating a respective neural network input with a corresponding output generated by a version of the neural network; responsive to the entry being stored in the memory lookup table, providing the corresponding output for the entry; and responsive to the entry not being stored in the memory lookup table, providing an output by processing the one or more inputs by the neural network to generate the output.
A semiconductor device is provided and includes a first transistor including a first source/drain (S/D) region (112), a second transistor stacked over the first transistor and including a second S/D region (114), a first backside power rail (BPR, 120) disposed below the first transistor, a second BPR (130) disposed below the first BPR, a via (140) by which the second S/D region and the first BPR are connected and metallization (150). The metallization (150) passes through and is insulated from the first BPR (120). The first S/D region (112) and the second BPR (130) are connected by the metallization (150).
A microelectronic structure that includes a stack nanosheet transistor comprising a lower nanosheet transistor and an upper nanosheet transistor. The lower nanosheet transistor includes a lower source/drain and the upper nanosheet transistor includes an upper source/drain. An airgap located between the upper source/drain and the lower source/drain. The airgap is vertically aligned with the upper source/drain and the lower source/drain. A first layer located between the airgap and the lower source/drain.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A computer-implemented method automatically enhancing model robustness and accuracy associated with a specified artificial intelligence (AI) model. The method may include automatically identifying model information associated with each of the AI models in the AI-based computer system, wherein automatically identifying the model information further comprises identifying a status of model results for the AI models. The method may also include automatically identifying the one or more subsystems related to the specified AI model. The method may further include, based on the identification of the related one or more subsystems, automatically identifying one or more important subsystems to the specified AI model. The method may also include, based on the one or more important subsystems, automatically revising the status of a model result of the specified AI model according to model revision rules. The method may also include generate a system status interpretability report for the specified AI model.
Scheduling tasks for concurrent execution in parallel is provided. Metrics corresponding to execution of tasks in a plurality of stages of a distributed application are received from a set of worker nodes. An analysis of the metrics corresponding to the execution of the tasks in the plurality of stages of the distributed application is performed using a prediction model. An optimal per-stage task execution parallelism level for each respective stage of the plurality of stages is determined using the prediction model based on the analysis of the metrics. The tasks are scheduled to execute on the set of worker nodes based on the optimal per-stage task execution parallelism level determined for each respective stage of the plurality of stages to improve at least one of runtime of the distributed application and resource utilization by the distributed application.
A method of testing fiber optic communication lanes includes sending a plurality of test parameters by a first end unit of a testing tool to a second end unit of the testing tool through at least one communication lane of a plurality of communication lanes that extend from a first cable endpoint to a second cable endpoint through at least one fiber optic cable. The first cable endpoint is connected to the first end unit and the second cable endpoint is connected to the second end unit, and the plurality of test parameters comprises wavelengths of a plurality of test signals. The method further includes sending the plurality of test signals by the first end unit to the second end unit through the plurality of communication lanes, and receiving test results through the at least one communication lane of the plurality of communication lanes.
H04B 10/077 - Arrangements for monitoring or testing transmission systemsArrangements for fault measurement of transmission systems using an in-service signal using a supervisory or additional signal
H04B 10/079 - Arrangements for monitoring or testing transmission systemsArrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
Disclosed embodiments provide methods, systems, and computer program products for implementing intelligent congestion control of data transfers in Fibre Channel (FC) communication paths based on an associated priority of workloads running on respective virtual machines (VMs). In a disclosed embodiment, a host server comprises a Virtual IO Server (VIOS) with Nport ID Virtualization (NPIV) technology to manage the multiple VMs; receives Fabric Performance Impact Notification (FPIN) congestion event notifications and transmits the FPIN congestion event notifications to the VMs with a respective throttle factor configured for respective VMs. Disclosed embodiments throttle IO operations of the VMs based on a priority of the VMs to implement intelligent congestion control, and restore IO operations of the VMs in a VM group order based on a reverse VM priority when the congestion event is cleared.
G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines
H04L 41/40 - Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks using virtualisation of network functions or resources, e.g. SDN or NFV entities
H04L 47/129 - Avoiding congestionRecovering from congestion at the destination endpoint, e.g. reservation of terminal resources or buffer space
15.
SHARING A MEDIA ITEM TO A VIDEO CONFERENCE SESSION
Described are techniques for sharing a media item to a video conference session. The techniques include receiving an instruction to share the media item to one or more other user devices participating in the video conference session. The techniques further include capturing an independent data feed for the media item that is separate from a video conference data feed. The techniques further include sending the independent data feed to the one or more other user devices using a messaging protocol that identifies the independent data feed for the media item as being separate from the video conference data feed. The identifying of the independent data feed as being separate from the video conference data feed enables the one or more other user devices to provide the independent data feed in an application window that is independent of a video conference application window of the video conference session.
A method, system, and computer program product detect and react to neural signals. The method includes monitoring the neural signals, which are collected from a user by a neural-computer interface (NCI) device. The method further includes detecting, based on the monitoring, an inhibitory signal in the neural signals and determining, in response to the detecting, that the inhibitory signal is aligned with an emotionally salient signal. Additionally, the method includes generating a notification in response to the determining that the inhibitory signal is aligned with the emotionally salient signal. The notification is displayed at an output device.
Systems and techniques for snooping input/output (I/O) events in a computing system are described. An example technique includes obtaining a configuration comprising a plurality of snoop space profiles, each snoop space profile indicating a respective range of memory addresses that map to a respective completion queue. The technique also includes monitoring input/output (I/O) traffic exchanged across a communication interface between an I/O adapter and a processor in a computing system, based on the configuration. The technique further includes performing one or more actions to assist processing of the I/O traffic, based in part on the monitoring.
Embodiments of the invention provide a computer-implemented method that includes executing a multi-leg neural network (NN) having a first-NN-leg and a second-NN-leg. The first-NN-leg includes first- NN-leg layers. A first layer of the first-NN-leg layers is at a first depth location in the first NN-leg that corresponds with a first depth location in the second-NN-leg. A second layer of the first-NN-leg layers is at a second depth location in the first-NN-leg that corresponds with a second depth location in the second-NN- leg. Information of the first layer of the first-NN-leg layers is sourced from the first depth location in the second-NN-leg. Information of the second layer of the first-NN-leg layers is sourced from the second depth location in the second-NN-leg.
The embodiments herein describe configuring a data device that enables communication between a host and a shared network adapter. The data device can include data connections between the host and the shared network adapter. The data device can have both control queues in a control plane and data queues in a data plane. The control queues can be activated first in order to issue control commands to configure the data plane in the shared network adapter.
Embodiments of the present disclosure provide methods, systems, and computer program products for implementing user interface (UI) Task Automations. Disclosed embodiments include receiving an automation structure and inputs and outputs of the structure to create a task automation, and providing multi-modal interfaces to process one or more teaching demonstrations for the task automation, where the teaching demonstrations identify automation processing parameters and operations for the task automation. Interactive contextual guidance are generated to record conditional execution of one or more actions or expressions based on states of one or more UI elements of the teaching demonstrations. Disclosed embodiments include recording, based on the conditional execution of one or more actions or expressions, the teaching demonstrations, synthesizing a UI task automation program of the task automation from the teaching demonstrations, and presenting the UI task automation program for validation.
Method and apparatus for deep learning. A first input and a second input are accessed. A first embedding for the first input is generated using a binding network. A second embedding for the second input is generated using the binding network. The first and second embeddings are aggregated to generate a combined embedding. A transformation function is applied to the combined embedding to generate a transformed combined embedding. The transformed combined embedding is processed, using an unbinding network, to extract a first transformed embedding for the first input and a second transformed embedding for the second input. An inference function is applied to the first transformed embedding to generate a first output. The inference function is applied to the second transformed embedding to generate a second output.
A computer-implemented method, according to one approach, includes: sending one or more instructions to apply an initial influencing factor to smart materials of a 4D object. Moreover, the 4D object is configured to deliver one or more microparticles from a start location to a target location along a delivery path in response to the initial influencing factor being applied to the smart materials. One or more instructions to monitor movement of the 4D object along the delivery path in response to applying the initial influencing factor to the smart materials are also sent. In response to determining the 4D object has deviated from the delivery path, one or more instructions to use one or more machine learning models to dynamically weight the initial influencing factor applied to the smart materials are further sent.
G05B 13/04 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric involving the use of models or simulators
G06N 3/04 - Architecture, e.g. interconnection topology
23.
DEVELOPING 4-DIMENSIONAL (4D) OBJECTS CONFIGURED TO TRANSPORT MICROPARTICLES TO TARGET LOCATIONS
A computer-implemented method, according to one approach, includes: receiving a request to deliver one or more microparticles from a start location to a target location along a delivery path. Available characteristic data corresponding to the request to deliver the one or more microparticles is also obtained. The characteristic data corresponds to 4D objects capable of delivering microparticles, the one or more microparticles, the delivery path, and one or more ambient environments along the delivery path. Furthermore, one or more machine learning models are used to analyze the available characteristic data and determine a 4D object that is configured to deliver the one or more microparticles to the target location in response to an influencing factor being applied to the 4D object.
A method, computer system, and a computer program product are provided. A neural network that includes multiple heads is trained. At least one auxiliary head of the multiple heads is identified. After completion of initial epochs of the training, a respective inverse gradient layer between the at least one auxiliary head and a feature extractor of the neural network is applied. Additional epochs of the training with the neural network and the inverse gradient layer are performed.
A phase-change memory (PCM) device (10) includes an electrically insulating material (11) and a PCM cell (12-16), which is embedded in the electrically insulating material (11). The PCM cell (12-16) includes a phase-change material layer (or PCM layer, for short), e.g., a layer including a germanium-antimony-tellurium alloy. The PCM layer (14) has a top surface, a bottom surface, and a side surface linking the top surface and the bottom surface. The PCM cell (12-16) further includes an outer electrode (12), which contacts the side surface of the PCM layer (14). That is, the outer electrode (12) laterally caps the PCM layer (14). The PCM cell (12-16) further includes a heater (15) extending at least partially through the PCM layer (14), transversely to the top surface and the bottom surface of the PCM layer (14), to contact the PCM layer (14).
The invention is notably directed to a physical reservoir for a magnetic reservoir computing apparatus. The physical reservoir includes a ferromagnetic film, which comprises a two-dimensional arrangement of point deformations. The point deformations are dimensioned to act as pinning sites for magnetic domains of the ferromagnetic film. The invention further concerns a magnetic reservoir computing apparatus comprising such a physical reservoir, as well as methods of operating and fabricating such a reservoir computing apparatus. The proposed approach results in a low-power-consumption physical reservoir, which is easy to fabricate.
G06G 7/00 - Devices in which the computing operation is performed by varying electric or magnetic quantities
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
27.
CONTINUOUS ADJUSTMENT OF LIGHTING THROUGH VIDEO STREAM
According to one embodiment, a method, computer system, and computer program product for continuous lighting adjustment through a video stream is provided. The embodiment may include identifying a lighting system. The embodiment may also include determining a lighting goal. The embodiment may further include analyzing a scene in a video stream, wherein one or more lighting features of the video stream are illuminated by the lighting system. The embodiment may also include comparing at least one lighting feature of the scene to the lighting goal. While the lighting goal is not met, the embodiment may include adjusting a lighting system according to the lighting goal, and repeating the analyzing and comparing until the lighting goal is met.
H05B 47/125 - Controlling the light source in response to determined parameters by determining the presence or movement of objects or living beings by using cameras
G06V 10/00 - Arrangements for image or video recognition or understanding
G06V 10/60 - Extraction of image or video features relating to illumination properties, e.g. using a reflectance or lighting model
Computer-implemented methods for performing enhanced resolution time-domain reflectometry are provided. Aspects include obtaining a plurality of waveforms by transmitting a first pulse on a transmission line, transmitting a second pulse on the transmission line, where the second pulse is transmitted after the first pulse by a delay, and capturing and measuring reflections of the transmitted pulses, wherein the delay corresponding to each of the plurality of waveforms is different. Aspects also include identifying a discontinuity of the transmission line based at least in part on the plurality of waveforms. Based on a determination that the transmission line includes the discontinuity, aspects include calculating third derivative curves for each of the plurality of waveforms and calculating a length of the discontinuity of the transmission line based on the third derivative curves. Aspects also include creating a notification indicating a location and the length of the discontinuity of the transmission line.
A sensing structure (101) is provided and includes a tubular element (110) through which a fluid is flowable along a single path, an array of sensors (120 1-5) disposed along a length of the tubular element whereby the fluid is flowable through each of the sensors and sensing circuitry electrically connected with each of the sensors and configured to measure a reactance of each of the sensors and to determine whether any reactance is indicative of a presence of a biological cell in the fluid flowing through the corresponding sensors.
B01L 3/00 - Containers or dishes for laboratory use, e.g. laboratory glasswareDroppers
G01N 33/487 - Physical analysis of biological material of liquid biological material
G01N 27/02 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance
G01N 27/22 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating capacitance
G01N 15/12 - Investigating individual particles by measuring electrical or magnetic effects by observing changes in resistance or impedance across apertures when traversed by individual particles, e.g. by using the Coulter principle
30.
MULTI-PART TRANSACTION INTEGRITY PROTECTION AND ENCRYPTION
Multi-part transaction integrity protection and encryption is disclosed, including generating, by a first device, a first message authentication code (MAC) for authenticating a plurality of packets of a transaction, the plurality of packets including at least a first packet received from a second device over a data link and a second packet generated by the first device in response to receiving the first packet, wherein the first MAC is generated using data included in the plurality of packets; and sending, by the first device to the second device, the second packet and the first MAC over the data link.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
31.
EDGE DEVICE FACILITY TO SELECTIVELY LOCATE MISSING CHAT MESSAGES
Selective locating of missing chat messages for an edge device is provided. The process includes sending a locate chat message request from a user's edge device to at least one other edge device of at least one other participant in a chat with the user via an end-to-end encryption messaging system. The locate chat message request identifies at least one search parameter for at least one missing chat message of the chat on the edge device. The process further includes, based on sending the locate chat message request, receiving at the edge device from the at least one other edge device, the at least one missing chat message of the chat identified via the at least one search parameter.
An example system includes a processor to receive state bundles including full state bundles and delta bundles with dependencies corresponding to updates received via a transport layer from a lower layer in a multi-layer edge architecture. The processor can conflate the state bundles to generate ready to be processed bundles. The processor can then process the ready to be processed bundles.
A phase-change memory cell includes an insulating layer; a first electrode embedded in the insulating layer, wherein an outer end of the first electrode is locally flush with an outer surface of the insulating layer; a second electrode, larger than the first electrode, and spaced from the first electrode; a compositionally homogenous crystalline phase change material layer; and a highly oriented seed layer. A crystal structure of the homogenous phase change material layer is correlated with a crystal structure of the highly oriented seed layer. The compositionally homogenous phase change material layer and the highly oriented seed layer are located at least partially between the first and second electrodes.
A thermal interface material (TIM) that includes a thermally reworkable polysiloxane with thermally reversible cycloadduct functionalities on at least one polysiloxane chain is disclosed. A TIM that includes a polysiloxane blended with a crosslinking network having thermally reversible cycloadduct functionalities is disclosed as well. A method of providing a TIM that includes a thermally reversible polymer network, a semiconductor package containing the TIM, and a computing device including the semiconductor package are also disclosed. The thermally reworkable polymer network of the provided TIM includes at least one polysiloxane chain and thermally reversible cycloadduct functionalities.
C08G 77/48 - Macromolecular compounds obtained by reactions forming in the main chain of the macromolecule a linkage containing silicon, with or without sulfur, nitrogen, oxygen, or carbon in which at least two but not all the silicon atoms are connected by linkages other than oxygen atoms
B29C 73/16 - Auto-repairing or self-sealing arrangements or agents
A thermal interface material (TIM) that includes a hydroxy-terminated polysiloxane blended with a catalyst generator is disclosed. When the catalyst generator is activated by a thermal stimulus, it catalyzes cleavage of silicon-oxygen bonds in the hydroxy-terminated polysiloxane. A semiconductor package and a computing device containing the TIM are also disclosed. Additionally, a method of providing a TIM, as well as a semiconductor package containing the TIM are disclosed. Providing the TIM includes blending a hydroxy-terminated polysiloxane with a catalyst generator that cleaves silicon-oxygen bonds when activated by a thermal stimulus.
A method for accelerated video editing that includes providing a video, segmenting, using a segmentation module, the video into a number of clips, and automatically computing, for each clip of the number of clips, corresponding metadata representing at least one attribute of the clip based on an analysis of contents of each clip of the plurality of clips. A profile script is generated based on the corresponding metadata, the profile script is generated to include one or more editing actions to be performed on a section of the video that corresponds to at least one identified clip from the number of clips. An editing tool is used to automatically edit the video based on the profile script to generate an edited video.
G11B 27/28 - IndexingAddressingTiming or synchronisingMeasuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording
37.
THREE-DIMENSIONAL PRINTING WITH PHOTOSENSITIVE RESIN
A system for three-dimensional (3D) printing. The system includes: a printing head for printing a material including a photosensitive resin; a first ultraviolet (UV) light source; and, a controller configured to direct the printing head to print a layer of the material, calculate an appropriate strength of UV radiation in a first UV beam to solidify the layer, and direct the first UV light source to project the first UV beam at the appropriate strength to the layer, wherein the printing head includes a semitransparent nozzle configured to allow the first UV beam to be transmitted through the semitransparent nozzle.
A data-analysis-based process of controlling a floating solar array location is provided. The process includes providing data analysis-based control of location of the floating solar array on water within a geographical area. The floating solar array has a propulsion system coupled to the floating solar array to facilitate relocating of the floating solar array. The control is configured to identify, using one or more machine learning prediction models, a region of a plurality of regions of the geographical area which meets, for a forecasted time period, a predefined criteria for harvesting energy from the floating solar array. Further, the control is configured to initiate, using the propulsion system, dynamic relocating of the floating solar array to the identified region of the geographical area to facilitate solar energy harvesting from the floating solar array for the forecasted time period.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
A field effect transistor (FET) device(102). The FET device(102) includes a semiconductor channel(102-C). Additionally, the FET device (102)includes a first gate dielectric in contact with the semiconductor channel(102-C). Further, the FET device(102) includes a metal-insulator-metal (MIM) structure. The MIM structure includes a liner(216-L) comprising a first metal, an insulator, and a second metal. The first metal is in contact with the first gate dielectric. Additionally, the insulator is in contact with the first metal and the second metal. Further, the FET device includes a floating gate(106A-FG). The floating gate(106A-FG) includes the first metal and an extension. Additionally, the extension is disposed to one side of the MIM structure, and includes a surface (106-X)for sensing a sample in contact with the surface(106-X).
G01N 27/414 - Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
G01N 27/26 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variablesInvestigating or analysing materials by the use of electric, electrochemical, or magnetic means by using electrolysis or electrophoresis
H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
40.
CHIRAL SPIN-CURRENT SUPPLY STRUCTURE FOR MTJ-BASED MEMORY
A memory structure including a chiral spin-current supply structure is provided. The chiral spin-current supply structure includes an inner core composed of a spin-collector material, a spin-conducting insulating layer surrounding the inner core, and a charge-current conducting spin-orbit spin-current generating layer surrounding the spin-conducting insulating layer. A magnetic tunnel junction structure is in contact with a horizontal surface of the inner core of the chiral spin-current supply structure.
Spin-orbit torque magnetoresistive random access memory (SOT MRAM) devices are provided. Each of the SOT MRAM devices integrates a SOT layer and an interconnect layer at a same metal level using a topological conductor (i.e., a topological metal or a topological semimetal) as both the interconnect layer and the SOT layer. The SOT MRAM devices further include a magnetic tunnel junction (MTJ) structure contacting the SOT layer, and a contact structure contacting the MTJ structure.
According to one embodiment, a method, computer system, and computer program product for adjusting an audible area of an avatar's voice is provided. The present invention may include receiving, at a microphone, a source audio; creating a received audio; calculating, by a generative model, a voice propagation distance of a user based on the source audio, the received audio, and a templated text sentence describing a category of a mixed reality environment experienced by the user; drawing a virtual circle within the mixed reality environment centered on a user avatar representing the user and with a radius equal to the voice propagation distance; and transmitting the source audio to one or more participants within the mixed-reality environment represented by one or more participant avatars located within the virtual circle.
A method includes: receiving, by a processor set, context data from one or more Internet of Things (IoT) sensors; identifying, by the processor set, one or more objects in a frame of a video stream, thereby determining identified objects; classifying, by the processor set, the identified objects, thereby determining classified objects; prioritizing, by the processor set, the classified objects using the context data, thereby determining prioritized objects; selecting, by the processor set, an object from the prioritized objects; enhancing, by the processor set, the frame of the video stream based on the selected object; and rendering, by the processor set, the enhanced frame on a display of a visual enhancement device.
An AI platform is used for developing a combination therapy for a patient afflicted with a tumor that has produced clones. The combination therapy, which includes at least two perturbations, is capable of targeting clones (including subclones) that have escaped therapeutic intervention due to resistance and/or evolution. The AI platform is trained with perturbation data obtained from at least one cell line that has similar characteristics to a clone of interest. The trained AI platform predicts how the clone of interest will respond to perturbations and ranks the perturbation responses from highest to lowest. At least one cell line may be an existing cell line from a well-established database or synthetic cell line generated by the AI platform. The AI platform may include one or more of a machine learning platform, deep learning platform, artificial neural network (ANN), convolution neural network (CNN), and generative adversarial network (GAN).
Described are techniques for determining a quiesce timeout for a containerized workload used to identify a storage unit for the containerized workload. The techniques include determining an Input/Output (I/O) rate associated with a containerized workload that executes in a container environment, where the containerized workload interfaces with a storage system to store the data. The techniques further include determining a quiesce timeout for the containerized workload that is based at least in part on the I/O rate of data associated with the containerized workload and an amount of memory allocated for buffering the data during performance of a backup operation without incurring an I/O overflow. The techniques further include determining storage unit specifications that enable performance of the backup operation within the quiesce timeout and evaluating storage units available to the container environment to identify a storage unit for the containerized workload based on the storage unit specifications.
An approached is disclosed that selectively replaces physical objects with virtual objects viewable in augmented reality. Selective replacement is based on user location and corresponding preferences mapped to location clusters. AI systems learn user preferences for location clusters and derive object preferences for users depending on location. Preferences and priorities for objects within each location cluster are derived using location data, purchase histories, IoT data, social media, communication data and other data sources. AI systems implement algorithms to predict levels of engagement between users and objects of a particular location cluster and as objects around the user are predicted to be uninteresting to the user, uninteresting objects may be replaced within AR environments using AR image overlay techniques with new objects having an interest rating above a threshold level. Replacement objects are purchasable through the AR interface, whereby users select objects to purchase and initiate delivery.
An apparatus for tin whisker isolation and detection includes a substrate having a plurality of pads for connecting to an electronic component placed on the substrate, and a shield placed on a surface of the substrate. The shield includes a plurality of cavities aligned over the plurality of pads. A plurality of sensing components each associated with one of the plurality of cavities are configured for sensing an electrically conductive growth from a corresponding pad of the plurality of pads. A plurality of circuit connections are each configured to connect one of the sensing components to detection circuitry. The detection circuitry is configured to receive one or more sensing signals from one or more of the sensing components and detect an electrically conductive growth from the corresponding pad based on the one or more sensing signals.
A semiconductor structure with self-aligned backside trench epitaxy includes a channel fin extending vertically from a bottom source/ drain region of a field effect transistor. The bottom source/drain region includes a trench epitaxy later located underneath a bottommost surface of the channel fin. A high-k metal gate stack is disposed along sidewalls of the channel fin. The high-k metal gate is separated from the bottom source/drain region by a bottom spacer. A top source/drain region is located above a topmost surface of the channel fin. The top source/drain region is separated from the high-k metal gate by a top spacer. The semiconductor structure further includes a backside metal contact within a backside interlayer dielectric. The backside metal contact is electrically connected to, and vertically aligned with, the bottom source/drain region.
A computer-implemented method, according to one approach, includes identifying machines involved in performance of a manufacturing process at a manufacturing location, and identifying a workflow sequence of execution of the machines. Conditions associated with remote operators using virtual reality (VR) devices to remotely control the machines to perform the workflow sequence of execution at the manufacturing location are received. The method further includes determining, for each of the VR devices, an extent of a VR collaborative environment to display. The extents are determined based on the conditions, thereby reducing latency in performance of the workflow sequence of execution at the manufacturing location. The method further includes outputting the extents to the VR devices.
G05B 19/427 - Teaching successive positions by tracking the position of a joystick or handle to control the positioning servo of the tool head, leader-follower control
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
A magnetoresistive device (102) is disclosed that includes a crystalline bottom electrode layer (126) on a semiconductor substrate (104), a crystalline metal layer (124) above the crystalline bottom electrode layer, a conductive oxide layer (122) above the crystalline metal layer, and a magnetic tunnel junction (MTJ) structure (108, 116, 120) above the conductive oxide layer. The conductive oxide layer (122) has a relatively low resistance and can be formed by an annealing process which causes a reaction of an insulating oxide layer (114) deposited on an amorphous reactive material layer (112).
Described is an integrated circuit device comprising one or more interconnects. Each interconnect of the one or more interconnects can be structured as a stack of layers including distinct topological layers, where each of the distinct topological layers can be a layer of topological material. Any two successive layers of the distinct topological layers can be separated by one or more interfaces, each forming a boundary between two consecutive layers of the stack, where the two consecutive layers can be engineered to preserve topologically protected surface states of each of the any two successive layers of the distinct topological layers.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
The present disclosure includes systems and methods for reducing rewrite overhead in a sequential access storage system. The method may comprise writing a data set to a sequential access medium using a magnetic head, wherein the data set comprises a plurality of encoded data blocks, classifying each of the plurality of encoded data blocks on the sequential access medium into one of at least three classes of write quality, and rewriting the encoded data blocks in a rewrite area of the sequential access medium based at least in part on the write quality class. In some embodiments, the at least three classes of write quality may comprise a hard rewrite class for which rewrites are necessary to prevent data loss, a soft rewrite class for which rewrites are desirable but not necessary, and a no rewrite class for which no rewrite is needed or desired.
Photonic content-addressable memories (CAMs) and applications thereof are provided. The CAM includes a photonic cross-bar array comprising a plurality of row and column waveguides, and a plurality of photonic filter devices. Each filter device is selectively programmable in first and second states representing respective stored bit values that filters out light according to the programming. An encoder for encoding a plurality of input bit-strings into optical signals such that bit values in different bit-strings are encoded using optical signals in different pairs of optical states, and to simultaneously supply the optical signals corresponding to each bit-position in the bit-strings to a respective row waveguide of the array. The CAM further comprises a detector for detecting light in any of said optical states in each column waveguide, thereby identifying any mismatch between each input bit-string and bit values stored in the filter devices coupling light to that waveguide.
G11C 15/00 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
54.
CONTEXTUAL VIRTUAL REALITY RENDERING AND ADOPTING BIOMARKER ANALYSIS
According to one embodiment, a method, computer system, and computer program product for biometric mixed-reality emotional modification is provided. The present invention may include collecting, by a plurality of biosensors, biometric information on a user during a mixed-reality session, wherein the biometric information comprises biomarkers; identifying, by one or more machine learning models, a mental state of the user based on the biometric information; and responsive to determining that the mental state does not match an intended emotion associated with a mixed-reality experience, modifying the mixed-reality experience with one or more virtual content elements.
A semiconductor structure includes a front-end-of-line level including a plurality of field effect transistors electrically connected to a back-end-of-line interconnect level. The back-end-of-line interconnect level is located on a first side of the front-end-of-line level. A backside power rail is embedded within a backside interlayer dielectric located on a second side of the front-end-of-line level opposing the first side of the front-end-of-line level. The backside power rail is electrically connected to at least one field effect transistor of the plurality of field effect transistors. At least one backside field effect transistor is formed on a first semiconductor layer disposed, at least in part, above a passive device region. A first side of the passive device region is in contact with the first semiconductor layer and a second side of the passive device region, opposing the first side, is in contact with the back-end-of-line interconnect level.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 23/528 - Layout of the interconnection structure
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
56.
BUILD ENVIRONMENT FOR SOFTWARE DEVELOPMENT, SECURITY, AND OPERATIONS
Aspects of the present disclosure relate generally to software development environments and, more particularly, to systems, computer program products, and methods of automating software development, security, and operations (DevSecOps). For example, a computer- implemented method includes receiving, by a processor, a plurality of infrastructure as code files specifying a configuration of a runtime environment for a deployable image of source code in a continuous integration and continuous delivery pipeline for a cloud platform; generating, by the processor, compliance code for at least one file of the plurality of infrastructure as code files; building, by the processor, the deployable image of the source code in the continuous integration and continuous delivery pipeline according to the configuration specified by the plurality of infrastructure as code files and the compliance code; and deploying, by the processor, an instance of the image in the runtime environment.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 21/54 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by adding security routines or objects to programs
57.
HETEROGENEOUS GATE ALL AROUND DIELECTRIC THICKNESS
A semiconductor includes a first GAA FET (303) and second GAA FET (305). The second GAA FET includes a first gate dielectric (391) and second gate dielectric (472) within its gate structure. The first GAA FET includes just the first gate dielectric within its gate structure. The gate dielectric structure of the first GAA FET provides for a nominal or a lesser effective gate dielectric or gate dielectric resistance relative to an effective gate dielectric structure of the second GAA FET. The first GAA FET further includes a first gate conductor (392) within its gate structure and the second GAA FET further includes the first gate conductor and a second gate conductor (395) within its gate structure. The first gate conductor and the second gate conductor are separated by the second gate dielectric.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
A semiconductor structure includes a first field-effect transistor having a first back side source/drain contact, a second back side source/drain contact, and a first power line and a first signal line each connected to the first back side source/drain contact and the second back side source/drain contact, respectively. The semiconductor structure further includes a second field-effect transistor vertically stacked above the first field-effect transistor. The second field-effect transistor having a first front side source/drain contact, a second front side source/drain contact, and a first power line and a first signal line each connected to the first front side source/drain contact and the second front side source/drain contact, respectively.
H01L 23/528 - Layout of the interconnection structure
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
59.
SELF-ALIGNED PATTERNED PROJECTION LINER FOR SIDEWALL ELECTRODE PCM
A memory device (380) and method of forming a projection liner (175) under a mushroom phase change memory device with sidewall electrode (145A, 145B, 145C) process scheme to provide self-aligned patterning of resistive projection liner during sidewall electrode formation.
A system and method for flushing the electrolyte out of an electrolyte flushable battery apparatus during a thermal runaway event. At least one condition of the electrolyte flushable battery apparatus is monitored to detect a potential thermal runaway event based on the at least one condition exceeding a threshold value. In response the inlet valve and outlet valves on the battery apparatus are opened. A flushing liquid is flushed or pumped through the battery apparatus where the flushing liquid enters the apparatus through the inlet valve and leaves the apparatus through the outlet valve. The flushing liquid is then stored in a reservoir.
H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
A microelectronic structure comprises a first stacked device structure comprising a first upper device and a first lower device, a second stacked device structure comprising a second upper device and a second lower device, and an isolation pillar structure (236) located between the first and second stacked device structures. The isolation pillar structure has an upper section contacting the first and second upper devices and a lower section contacting the first and second lower devices. The upper section of the isolation pillar structure has a first width and the lower section of the isolation pillar structure has a second width different than the first width.
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
Described are techniques for multi-tenant security. The techniques include detecting malicious activity on a compromised application in a multi-tenant host. The techniques further include automatically performing a live migration of each tenant of the multi-tenant host to a respective single-tenant host. The techniques further include mitigating the malicious activity on the compromised application that is migrated to a single-tenant host, and automatically performing another live migration of each benign tenant to a new multi-tenant host.
An example operation may include one or more of storing a batch scoring engine and an application programming interface (API) for the batch scoring engine, receiving a trigger to perform a batch prediction process, reading input data from a source data store and executing, via the batch scoring engine, one or more predictive models on the input data to generate a predictive output and metadata associated with the predictive output, storing the predictive output and the metadata in a target data store, and updating the API with a location of the predictive output within the target data store and a location of the metadata within the target data store
A computer-implemented method of clustering anomalies detected in a computerized system. The proposed method makes use of an unsupervised cognitive model, executed based on input datasets to obtain clusters of anomalies. The method accesses input datasets, which correspond to detected anomalies of the computerized system. These anomalies span respective time windows. Each input dataset comprises a set of timeseries of key performance indicators. The key performance indicators of each input dataset extend over a respective time window. That is, each anomaly corresponds to a respective time window. This model includes a first stage, which includes an encoder designed to learn fixed-size representations of input datasets, and a second stage, which is a clustering stage. The model is executed based on the input datasets accessed, the first stage learning fixed-size representations of the input datasets and the second stage clustering the learned representations.
G06F 18/23213 - Non-hierarchical techniques using statistics or function optimisation, e.g. modelling of probability density functions with fixed number of clusters, e.g. K-means clustering
65.
STACKED FIELD EFFECT TRANSISTOR CELL WITH HYBRID CROSS-COUPLE CONTACT
Embodiments are disclosed for a complementary metal oxide semiconductor (CMOS) device. The CMOS device includes a hybrid cross-couple contact. The hybrid cross-couple contact includes a frontside contact to a gate of the CMOS device. The frontside contact is disposed on a frontside of the CMOS device. The hybrid cross-couple contact includes a source contact to a source of the CMOS device. The source contact is disposed on a backside of the CMOS device. The hybrid cross-couple contact includes a drain contact to a drain of the CMOS device. The drain contact is disposed on a backside of the CMOS device.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H10B 10/00 - Static random access memory [SRAM] devices
A video file is detected by a computer system. The video file that is to be provided to one or more client devices. The video file contains a video stream that includes a plurality of video images. A first video image of the plurality of video images is reconstructed based on a first machine learning technique. The first machine learning technique is based on one or more video images that occur temporally before the first video image in the video stream. A reconstruction status of the first video image of the plurality of video images is identified based on the video file and based on a second machine learning technique. An altered video file is generated in response to the reconstruction status and based on the video file.
A microelectronic structure including a plurality of lower transistors and a plurality of upper transistors, where channels of the upper transistors are staggered from channels of the lower transistors. A lower dielectric pillar located beneath an upper transistor, where the dielectric pillar separates bottom transistors.
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
A method for preparing a trained crossbar array of a neural network is provided. The method includes feeding an input portion of a predetermined truth table into a computer simulation of a crossbar array, and generating analog output values for the input portion of the truth table based on simulated weights. The method further includes calculating a loss value from each of the analog output values and expected values for an output portion of the truth table, and adjusting the simulated weights based on the calculated loss values. The method further includes refeeding the input portion of the predetermined truth table into the computer simulation and recalculating the output values using the adjusted simulated weights until the analog output values produce the expected values for the output portion of the truth table within a predefined margin of error.
A network comprises a plurality of oscillators. The network is configured to control the phase of the plurality of oscillators by thermal coupling through a thermal link.
The method performs at the orchestration interface at which update information, including changes to tasks of a workflow, is received from a task manager system (TMS), where the workflow includes a set of tasks, inputs to the tasks, and outputs from the tasks. The inputs and outputs determine runtime dependencies between the tasks. Based on the update information received, the orchestration interface populates a topology of nodes and edges as a directed acyclic graph (DAG) that maps nodes to tasks and edges to runtime dependencies between tasks, based on node inputs and outputs. The orchestration interface instructs the execution of the tasks and handling dependencies by interacting with a task execution system (TES) and by traversing the DAG, the orchestration interface identifies tasks that depend on completed tasks as per the runtime dependencies and instructs the TES to execute the dependent tasks identified.
An apparatus 100 used for analysis of a fluid-based system includes a main chamber 102 consisting of an optically transparent high strength material that ensures transmission of infrared and ultraviolet wavelengths and is capable of withstanding high pressures. The apparatus also includes first and second fluid tight endcaps 106, 108 attached to first and second ends of the main chamber, wherein the first endcap permits entry of a fluid into the main chamber and the second endcap permits the fluid to exit the main chamber. The apparatus further includes a fixed filter guide rail located inside the main chamber and attached to one of the end caps, and a filter 118 located inside the main chamber and configured to removably attach to the fixed filter guide rail, wherein the filter is capable of capturing residue or contaminants in the fluid.
G01N 21/29 - ColourSpectral properties, i.e. comparison of effect of material on the light at two or more different wavelengths or wavelength bands using visual detection
G01N 21/85 - Investigating moving fluids or granular solids
G01N 21/94 - Investigating contamination, e.g. dust
According to the embodiment of the present invention, a semiconductor device includes a first source/drain and a second source/drain. A first source/drain contact includes a first portion and a second portion. The first portion of the first source/drain contact is located directly atop the first source/drain. The second portion of the first source/drain contact extends vertically past the first source/drain. The first source/drain is in direct contact with three different sides of a first section of the second portion of the first source/drain contact.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Described are techniques for font attribute detection. The techniques include receiving a document having different font attributes amongst a plurality of words respectively comprised of at least one character. The techniques further include generating a dense image document from the document by setting the plurality of words to a predefined size, removing blank spaces from the document, and altering an order of characters relative to the document. The techniques further include determining characteristics of the characters in the dense image document and aggregating the characteristics for at least one word. The techniques further include annotating the at least one word with a font attribute based on the aggregated characteristics.
The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. The method includes detecting a region, such as an individual processor, of a processor chip exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life. The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltage spikes back to within some pre-specified range. The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
H02H 3/20 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess voltage
G05F 1/571 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overvoltage detector
75.
SEMICONDUCTOR DEVICE WITH RESONANT TUNNELING DIODE AND FIELD EFFECT TRANSISTOR
Systems, devices and/or methods provided herein relate to a device that can facilitate generation of a pulse to affect a qubit and to a method that can facilitate fabrication of a semiconductor device. The semiconductor device comprises an RTD (270) and an FET (280) co-integrated in a common layer (290) extending along a substrate (210). A method for fabricating the semiconductor device comprises applying, at a substrate layer, a template structure comprising an opening, a cavity and a seed structure (223) comprising a seed material and a seed surface, and sequentially growing along the substrate a plurality of diode layers (271-277) of an RTD (270) and a plurality of transistor layers (281-283) of an FET (280) within the cavity of the template structure from the seed surface, wherein the RTD and FET are co-integrated along the substrate.
H01L 21/8252 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
A system and method to tie a removable component to a host device. A first pairing key is stored into a security module on a host device such as a server rack. A removable component is inserted into the server rack for the first time. In response to this first insertion the first pairing key is burned into the removable component using a plurality of physically modifiable internal components. The server rack/security module receives a request form the removable component to operate on the server rack, the request includes a burned in pairing key. The security module compares the received pairing key with the first pairing key and permits operation of the removable component in response to a match between the received pairing key and the first pairing key.
G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules
G06F 21/71 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
A system and method of securely controlling a device from another device. The user of the device attempts to modify the device in some way. In response to the attempted modification a request is generated and sent to a controlling device. The request includes information related to the desired modification. The controlling device analyzes the request and a determination on how to respond to the request is made. This response is encrypted at the controlling device and transmitted to the device. The device then decrypts the response and implements the indicated response to the request. The encryption and decryption keys are burned into the corresponding devices such that information needed to decrypt the response is not transmitted to the device.
H04L 67/125 - Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks involving control of end-device applications over a network
H04M 1/72463 - User interfaces specially adapted for cordless or mobile telephones with means for adapting the functionality of the device according to specific conditions to restrict the functionality of the device
G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules
A method can include obtaining device data for a set of electronic devices. The device data can indicate power utilized by the set of electronic devices. The method can include obtaining a capacity of a backup power source. The method can include obtaining priority data regarding an allocation of power to the set of electronic devices. The method can include obtaining a set of environmental conditions. The method can include calculating, based at least in part on the set of environmental conditions and the device data, a projected electrical load on the backup power source. The method can include determining that one or more thresholds are exceeded. The determining can comprise identifying that the projected electrical load exceeds the capacity. The method can include modifying, in response to the determining and according to the priority data, power supplied to the set of electronic devices from the backup power source.
Embodiments for providing enhanced endpoint multicast emulation in a computing environment. One or more multicast operations may be executed on an overlay network using endpoint multicast emulation by using an overlay layer or a virtual extensible LAN ("VXLAN") layer to maintain control over one or more multicast groups.
Performing a mutual exclusion data class analysis is provided. A data class group of a plurality of data class groups that a matching data class is a member of is identified. The matching data class matches data in a plurality of rows of a column in a data asset. Data classes included in the data class group that the matching data class is a member of are identified. A mutual exclusion data class is filtered from the data class group to form a filtered data class group for the column. The filtered data class group is run against the column of the data asset decreasing processing time and resource utilization of a computer.
Embodiments for identifying an optimal cloud computing environment for a computing task is disclosed. Embodiments comprises receiving a computing task to be executed in a cloud computing environment, wherein the computing task requires a set of cloud computing environment parameter values of the cloud computing environment, pre-selecting a set of candidate cloud computing environments, each of which meets the set of cloud computing environment parameter values, ranking the candidate cloud computing environments using reward-based ranking parameter values of the candidate cloud computing environments as an additional selection constraint, and selecting the highest ranking cloud computing environment as the optimal cloud computing environment for the computing task. Furthermore, embodiments comprise executing the computing task in the optimal cloud computing environment, monitoring execution when executing the computing task, and updating parameter values of the reward-based ranking for the selected optimal cloud computing environment.
A computer-implemented method, a computer program product, and a computer system for building a knowledge graph. A computer system converts user inputs as to a partial topology of a knowledge graph that a user wants to build into one or more initial nodes corresponding to respective natural language descriptions. A computer system interprets the respective natural language descriptions using natural language processing to match the one or more initial nodes against reference data. A computer system, based on matched reference data, obtains a valid topology of nodes and edges, wherein the nodes and edges are mapped onto the matched reference data. A computer system, based on the valid topology, generates a data flow linking to the matched reference data via associations of the nodes and edges and the matched reference data. A computer system builds an executable knowledge graph from the data flow.
A method including: receiving multiple time series of data, each time series representing a health-related temporal impact of a historical set of elements on an adverse health-related condition; automatically deconvolving the health-related temporal impact, to determine an individual contribution of each element of each of the historical sets to the health-related temporal impact of the respective historical set, wherein the deconvolving is performed respectively of an additive impact and/or a multiplicative impact of elements; receiving a selection of a new set of elements which is different from any one of the historical sets; and based on the determined individual contributions, automatically predicting a temporal impact of the new set of elements, wherein the new set consists of elements selected from said group but which do not jointly constitute any one of the historical sets.
G06Q 10/04 - Forecasting or optimisation specially adapted for administrative or management purposes, e.g. linear programming or "cutting stock problem"
84.
UNIFIED FRAMEWORK FOR MULTIGRID NEURAL NETWORK ARCHITECTURE
A method including: receiving, as input, an image; providing a neural network structure including a plurality of multilayer multi-scale neural networks, wherein the plurality of multilayer multi-scale neural networks are arranged sequentially, by laterally connecting corresponding scale-level layers between each two adjoining multilayer multi-scale neural networks in the sequence; and at a training stage, training the neural network structure on a training dataset, to obtain a trained machine learning model configured to perform a computer vision task which includes outputting at least one of: (i) a classification of the image into one class of a set of two or more classes, (ii) a segmentation of a least one object in the image, and (iii) a detection of at least one object in the image.
A computer-implemented method is provided for offline reinforcement learning with a dataset. The method includes training a neural network which inputs a state-action pair and outputs a respective Q function for each of a reward and one or more safety constraints, respectively. The neural network has a linear output layer and remaining non-linear layers being represented by a feature mapping function. The training includes obtaining the feature mapping function by constructing Q-functions based on the dataset according to an offline reinforcement algorithm. The training further includes tuning, using the feature mapping function, a weight between the reward and the one or more safety constraints, wherein during the obtaining and the tuning steps, an estimate of a Q-function is provided by subtracting an uncertainty from an expected value of the Q-function. The uncertainty is a function to map the state-action pair to an error size.
32322X coupling spacer is present, Me is iron and X is tantalum or tungsten. The coupling spacer is formed by providing a material stack including at least a precursor paramagnetic hexagonal metal phase material forming multilayered structure that includes alternating layers of magnetic metal, Me, and metal, X, and then thermally soaking the material stack.
A semiconductor structure is provided that includes a first FET device stacked over a second FET device, wherein the first FET device contains a first functional gate structure containing a first work function metal and the second FET device contains a second functional gate structure containing a second work function metal. In the structure, the first work function metal is absent from an area including the second work function metal, and vice versa. Thus, no shared work functional metal is present in the semiconductor structure.
Handler wafers and methods of handling a wafer include positioning a handler, which is attached to a wafer by a bonding layer that comprises a debonding layer, an optical enhancement layer, and an anti-reflection layer. The handler is debonded from the wafer using a laser that emits laser energy at a wavelength that is absorbed by the debonding layer and that is confined to the debonding layer by the optical enhancement layer, such that the material of the debonding layer ablates when exposed to the laser energy to release the wafer.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
C09J 5/06 - Adhesive processes in generalAdhesive processes not provided for elsewhere, e.g. relating to primers involving heating of the applied adhesive
In a present invention embodiment, time series data is received including information pertaining to a corresponding attribute of monitored activity on a processing device. An upper bound of the time series data is determined based on a weighted combination of a prior upper bound and a current value derived from the time series data. Greater weight is provided to greater values in the time series data based on an exponent applied to the prior upper bound and the current value and an effect of older values in the time series data decays over time based on a smoothing factor applied to exponential values of the prior upper bound and the current value. The upper bound is applied to a profile of an entity, and abnormal activity on the processing device is detected based on a comparison of the upper bound to a corresponding bound of the profile.
A Computer-implemented Method And A Computer System For Identifying Persistent Anomalies For Failure Prediction. The Computer System Receives A Time Series Data Stream. The Computer System Received A Predetermined Number N And A Predetermined Number M Which Is A Fraction Of N. The Computer System Segments The Time Series Data Stream Into N Consecutive Sliding Windows. The Computer System Performs Supervised Persistent Anomaly Detection To Determine Whether Anomalies Across The N Consecutive Sliding Windows Are Persistent, By Using A Binary Classification Model. The Computer System Performs Unsupervised Persistent Anomaly Detection To Determine Whether The Anomalies Across The N Consecutive Sliding Windows Are Persistent. The Computer System Combines Results Of The Supervised Persistent Anomaly Detection And Results Of The Unsupervised Persistent Anomaly Detection To Determine Persistent Anomalies.
Live migration of a virtual machine (VM) includes establishing multipath connections between the VM and functions of host interface on a source host. The multipath connections include a passthrough path and a software-virtualized (or emulated) path provided by a hypervisor of the source host. A failover of the passthrough path to the emulated path is executed, and a state of the emulated path is thereafter saved. On a host interface of a destination host, functions corresponding to those of the source host are exposed. The VM is then migrated from the source host to the destination host. The VM resumes host interface communication with the host interface of the destination host from the saved state via an emulated path provided by a hypervisor of the destination host. After resuming communication, a passthrough path of communication between the VM and the host interface of the destination host is established.
Inadvertent data swaps can be prevented by measuring volume of transactions in distributed computing environment to determine locations for potential data swaps; and managing a correlation between a thread identification (ID) and transaction header (ID) for transactions in the distributed computing environment. In some embodiments, the prevention of data swaps can further include performing a data transmission interruption to avoid data swaps at the locations for potential data swaps. When the thread identification (ID) and transaction header (ID) do not match the potential for data swaps can be high.
Information extraction systems and computer-implemented methods for producing a searchable representation of information contained in a corpus of documents by generating a document structure graph for each document, the graph indicating a structural hierarchy of document items in that document based on a predefined hierarchy of predetermined item-types, and linking document items to a parent document item in the structural hierarchy, for each document, generating a knowledge graph including first nodes, representing document items in the corpus and second nodes representing language items identified in those document items, interconnecting the first nodes and second nodes by edges representing a defined relation between items represented by the nodes interconnected by that edge, storing the knowledge graph in a knowledge graph database, and producing the searchable representation by traversing edges of the graph in response to input search queries.
Techniques regarding augmenting one or more training datasets for training one or more AI models are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise training augmentation component that can generate an augmented training dataset for training an artificial intelligence model by extracting a simplified source code sample from a source code sample comprised within a training dataset.
Automatic measurement of semantic textual similarity of conversations, by: receiving two conversation texts, each comprising a sequence of utterances; encoding each of the sequences of utterances into a corresponding sequence of semantic representations; computing a minimal edit distance between the sequences of semantic representations; and, based on the computation of the minimal edit distance, performing at least one of: quantifying a semantic similarity between the two conversation texts, and outputting an alignment of the two sequences of utterances with each other.
Encrypting data blocks by receiving blocks of compressed data, determining a size, in bytes, of the compressed data, appending a trailer to the compressed data, the trailer associated with the size in bytes of the compressed data, encrypting the compressed data and trailer, yielding encrypted data, where a header of the encrypted data comprises a number of complete encrypted data blocks, and providing the encrypted data to a user.
The invention is notably directed to a sensor system (100) for performing distributed sensing and classification of sensor data. The sensor system (100) comprises a set of distributed sensor nodes (111) for sensing the sensor data. The sensor system (100) is configured to encode the sensor data of each sensor node of a set of distributed sensor nodes (111) for sensing the sensor data as high-dimensional vectors (V1,V2,......VS) and to transmit the high-dimensional vectors (V1,V2,......VS) over a respective link between the respective sensor node and a receiver system (130). The sensor system (100) is further configured to superpose the high-dimensional vectors (V1,V2,......VS) of the sensor data from the set of sensor nodes (111) by physical superposition, thereby generating a superposed high-dimensional vector and to classify the superposed high-dimensional vectors (V1,V2,......VS) at the receiver system (130).
G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
An apparatus for providing data storage protection, the apparatus comprising: a data storage library(10) including a deep slot cell(100) configured to house a plurality of tape cartridges, wherein the deep slot cell comprises :a front side of the deep slot cell configured to allow insertion and removal of a locking tape cartridge of the plurality of tape cartridges by a robotic mechanism(20);a depth side of the deep slot cell configured with an opening to engage a locking mechanism(730) that prevents a biasing spring mechanism of the deep slot cell from automatically advancing a rear-most tape cartridge of the plurality of tape cartridges forward toward the front side of the deep slot cell; and a front air gap(736) at the front side of the deep slot cell that prevents the robotic mechanism from reaching a front-most tape cartridge of the plurality of tape cartridges after the robotic mechanism removes the locking tape cartridge from the deep slot cell.
Semiconductor structures are disclosed which comprise semiconductor devices having buried power rails. In one example, a semiconductor structure comprises a plurality of semiconductor devices. Each of the semiconductor devices is isolated from an adjacent semiconductor device by a dielectric layer. The semiconductor structure further comprises a first diffusion break extending across the plurality of semiconductor devices, a second diffusion break extending across the plurality of semiconductor devices and a plurality of gates extending across the plurality of semiconductor devices. The gates are disposed between the first diffusion break and the second diffusion break. Each semiconductor device comprises a power rail extending between the first diffusion break and the second diffusion break under the plurality of gates.
An example operation may include one or more of receiving a blockchain transaction that comprises a state reference to an unspent transaction output (UTXO), determining whether the UTXO is included within a first subset of transactions on a blockchain ledger based on a zero-knowledge (ZK) proof included in the state reference, determining whether the UTXO is included within a second subset of transactions on the blockchain ledger based on a hash value included in the state reference, and in response to a determination that the UTXO is not included in either of the first and second subsets of transactions, committing the blockchain transaction including the state reference to the blockchain ledger via a blockchain peer.
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