A 24-transistor D flip-flop circuit operates in a sampling mode when a clock signal has a first voltage state, and a holding mode when the clock signal has a second voltage state. The flip-flop circuit includes an internal control node coupled to a reference voltage node by way of a transistor controllable to couple the internal control node to the reference voltage node when the clock signal has the second voltage state. The flip-flop has very low power dissipation as it includes a 4-transistor change-sense component to detect changes in input data. The change-sense component is coupled in series with the transistor and receives an indication of an input voltage state of the flip-flop circuit and an indication of an output voltage state of the flip-flop circuit, and inhibits toggling of the internal control node if the indicated input voltage state and the indicated output voltage state are the same.
H03K 3/289 - Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable of the primary-secondary type
Tx is the total power supplied to the power transmitter. The method also involves detecting the presence of a foreign object in response to the estimated transmitter energy loss.
H04B 5/00 - Near-field transmission systems, e.g. inductive or capacitive transmission systems
H04W 52/24 - TPC being performed according to specific parameters using SIR [Signal to Interference Ratio] or other wireless path parameters
H02J 5/00 - Circuit arrangements for transfer of electric power between ac networks and dc networks
H02J 17/00 - Systems for supplying or distributing electric power by electromagnetic waves
H02J 7/02 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from AC mains by converters
There is disclosed a metal-insulator-metal, MIM, capacitor. The MIM capacitor comprises a MIM stack formed within an interconnect metal layer. The interconnect metal layer is utilized as an electrical connection to a metal layer of the MIM stack.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers
H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
4.
METHOD AND APPARATUS FOR DETERMINING IGNITION TIMING CONTROL IN AN INTERNAL COMBUSTION ENGINE
A control methodology and apparatus for an engine suitable for use in capacitor discharge ignition systems for internal combustion engines or brushless DC motors is provided, which make use of a simple logic block to determine for instance an ignition timing advance angle or duty cycle signal based on actual engine speed versus engine control parameter data stored in a table, which is a read-only memory, preferably configurable. To minimise memory space, a small number of values of engine control parameter versus engine speed are stored in the table and the logic block determines the required engine control signal for a measured value of engine speed by an interpolation process, preferably linear interpolation.
The invention provides a storage element with monitoring circuit (10), comprising a data input interface (DIN), a data output interface (DOUT), a clock signal input interface (CLK), a storage fault indicator interface (SF), a monitored state information storage element (Q0) having a clock input terminal coupled to the clock signal input interface (CLK), a data input terminal coupled to the data input interface (DIN) and a data output terminal, a previous state information storage element (Q2) having a clock input terminal coupled to the clock signal input interface (CLK), and a data input terminal coupled to the data output terminal of the monitored state information storage element (Q0), the previous state information storage element (Q2) being configured to record the previous state (d2) of the monitored state information storage element (Q0), a state change indication unit (CIU) having a clock input terminal coupled to the clock signal input interface (CLK), the state change indication unit (CIU) being configured to generate a state change indication signal (x0) indicative of whether the monitored state information storage element (Q0) shall have performed a state change by observing the data (d) at the data input interface (DIN) and the data output terminal, and a state change confirmation unit (CCU) coupled to the state change indication unit (CIU), the state change confirmation unit (CCU) being configured to generate a storage fault indicator (SF) by observing the data output terminal of the monitored state information storage element (Q0) and the data output (d2) of the previous state information storage element (Q2) and checking whether the result of this observation is in line with the state change indicator (x0). The invention further provides a method for monitoring storage elements or the involved clock (sub-) trees.
A communication system comprises a plurality of software partitions operably coupled to one another via at least one hardware module, wherein each of the plurality of software partitions comprises memory allocated to store data for use solely by the respective software partition, wherein the hardware module is arranged to copy data from a first memory location of a first software partition to second memory location of a second software partition wherein the second memory location is selected by the second software partition.
The present invention provides a monitor, especially a wake up monitor, for monitoring an integrated circuit, the monitor comprising a first monitoring unit configured to monitor at least one input of the integrated circuit, a second monitoring unit configured to monitor at least one output of the integrated circuit, a measurement unit configured to measure the time elapsed between an event on the at least one input and a reaction to the event on the at least one output and configured to output an alert signal if the elapsed time exceeds a predetermined first time limit. The present invention furthermore discloses an integrated circuit and a method for monitoring an integrated circuit.
A method and apparatus of validating a test pattern for at-speed testing of at least one integrated circuit, IC, design. The method comprises calculating at least one weighted rise activity, WRA, value for at least one region of the IC design based at least partly on rising gate transitions within the at least one region of the IC design when the test pattern is applied thereto, calculating at least one weighted fall activity, WFA, value for the at least one region of the IC design based at least partly on fall gate transitions within the at least one region of the IC design when the test pattern is applied thereto, and validating the test pattern based at least partly on the WRA value and the WFA value.
The present invention relates to a bandwidth estimation circuit for estimating and predicting the bandwidth of a computer system, the bandwidth estimation circuit comprising: a memory unit which is configured to store multiple predetermined bandwidth envelopes, wherein each one of the predetermined bandwidth envelopes is assigned to a feature of a code of an application program; a bandwidth measurement unit which is configured to online measure the bandwidth of a data transaction based on the code; a selection unit coupled either to the memory unit and the bandwidth measurement unit and configured to find the nearest bandwidth envelopes in the memory unit for the measured bandwidth; a calculation unit which is configured to calculate a ratio between the selected bandwidth envelopes, to construct a new bandwidth envelope by applying an interpolation function based on the calculated ratio and to calculate an estimated bandwidth by applying the new bandwidth envelope. The present invention also relates to a computer system, a method for estimating and predicting the bandwidth and a computer readable program product.
LOW-VOLTAGE DIFFERENTIAL SIGNALING (DIFFERENTIAL SIGNALING) DRIVER CIRCUIT AND METHOD OF ENABLING AND DISABLING A DIFFERENTIAL SIGNALING DRIVER CIRCUIT
A Low-Voltage Differential Signaling (differential signaling) driver circuit (10) comprising enable circuitry for enabling and disabling the differential signaling driver circuit (10) in accordance with an control signal is described. The differential signaling driver circuit (10) comprises: a differential output (12, 13) connected or connectable to a differential signaling receiver circuit via a differential transmission line; current control circuitry (14) for driving a signal current through the differential output (12, 13) in accordance with a driver signal; feedback circuitry (16) for driving the current control circuitry (14) to counteract a difference between a common mode voltage of the differential output (12, 13) and a reference voltage from a reference voltage provider; and the enable circuitry (18). The feedback circuitry (16) comprises a common mode node (20) for providing the common mode voltage (Vcm), a reference input (22) connected or connectable to the reference voltage provider, and a feedback input (24). The enable circuitry (18) is arranged to connect the feedback input (24) to the common mode node (20) when the differential signaling driver circuit (10) is in an enabled state and to the reference voltage provider when the differential signaling driver circuit (10) is in a disabled state. A method of enabling (5.1) and disabling (5.2) a Low-Voltage Differential Signaling (differential signaling) driver circuit (10) is also proposed.
H03K 19/003 - Modifications for increasing the reliability
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
An apparatus for debugging operational code of a target program comprises a memory storing the operational code and a set of instructions representing a debugger program for debugging the operational code. A microprocessor is configured to execute the operational code and the debugger program. The debugger program can inject a jump to a breakpoint handling routine into the operational code and let a compiler program create code pieces for the breakpoint handling routine..
A power efficient direct Tire Pressure Monitoring System, TPMS, for providing a non-continuous tire pressure monitoring of a tire of a vehicle, such as a automobile vehicle, the TPMS comprising: - a processing unit having at least a first operating mode and a second operating mode; - a timing unit; - an acceleration measuring unit; - a comparing unit; - a pressure measuring unit; - a transmitting unit; and, - a power supplying unit for supplying power to the processing unit in the first and second operating modes wherein the latter mode is less power consuming than the former mode, wherein the processing unit is adapted to: - enter the second operating mode after an acceleration threshold and an operating clock frequency have been set; and, - enter the first operating mode responsive to a first trigger signal. A tire, a vehicle and a method are also claimed.
An ESD protection circuit (100) and device structure (200) comprises five transistors (101, 102, 103, 104 and 105), two PNP and three NPN. The five transistors are coupled together so that a first NPN and PNP pair (101, 102) constitute a first silicon controlled rectifier, SCR. The NPN transistor 102 of the first SCR and a third transistor (103) of NPN type are coupled so that they constitute a Darlington pair. A further NPN and PNP pair (104, 105) are coupled together to form a second SCR with the collector of the PNP transistor of the first SCR being coupled with the emitter of the PNP transistor (104) of the second SCR. The circuit is particularly suitable for high voltage triggering applications and two or more devices may be cascaded in series in order to further increase the triggering voltage.
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
14.
DATA PROCESSING DEVICE AND METHOD OF CONDUCTING A LOGIC TEST IN A DATA PROCESSING DEVICE
A data processing device (10), comprising a processing unit (12) and a test control unit (16) connected to the processing unit (12), is described. The processing unit (12) and the test control unit (16) are arranged to: start a logic test of the processing unit (2.2); detect a test abort event (2.3); and, in response to the test abort event, perform an event response action (2.5-2.8) which comprises aborting the logic test (2.5) and booting the processing unit (2.7, 2.8), said booting including executing an event handling routine (2.8). The event response action may comprise setting a reset vector to an address of the event handling routine (2.7). System availability may thus be improved. In particular, the delay between capturing an asynchronous signal and responding to it may be reduced. The test abort event may, for example, be an asynchronous event having certain pre-defined characteristics. A method (2.1-2.8) of operating a data processing device is also described.
A current-to-voltage converter (101) receives a current which varies with temperature according to a selected one of two or more temperature coefficient factors and converts it to a temperature-dependent voltage which may be used as a control signal to varactor in a voltage controlled oscillator, VCO, (109) in order to compensate for temperature-induced frequency drift in the VCO. A feedback arrangement (501, 502) with hysteresis is provided for controlling the selection of the temperature coefficient factor and operates by comparing the temperature-dependent voltage with a reference voltage. The reference voltage may be pre-set and equivalent to a known operating temperature. A switching signal is generated when Vout approaches the reference voltage and in response a control module generates a selection signal for selecting a different temperature coefficient factor. The invention provides multi-slope voltage and current generation in a continuous way and with a wide dynamic range and is particularly useful for controlling VCO's used in short range FMCW radar systems.
The present invention comprises a method and apparatus for controlling an IGBT device. The method comprises, upon receipt of a first and at least one further IGBT control signals, the first IGBT control signal indicating a required change in operating state of the IGBT device, controlling an IGBT driver module for the IGBT device to change an operating state of the IGBT device by applying a first logical state modulation at an input of an IGBT coupling channel, and applying at least one further modulation to the logical state at the input of the IGBT coupling channel in accordance with the at least one further IGBT control signal within a time period from the first logical state modulation, the time period being less than a state change reaction period ∆t for the at least one IGBT device.
G05F 3/16 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
A vibration gyroscope circuitry (VCIRC) connectable to a vibrating MEMS gyroscope (VMEMS). The circuitry comprises drive circuitry (DRIVE) arranged to drive, when the circuitry is connected, the vibration MEMS gyroscope (VMEMS) and a measurement unit (DMU) which provides a drive measurement voltage signal (DMV) forming a measure of a displacement of a mass along a drive axis. A sense circuitry (SENSE) is arranged to process a sense measurement signal of the vibration MEMS gyroscope (VMEMS) forming a measure for a displacement of the mass along a sense axis. A digital sample clock generator (SCG) is arranged to generate a sample clock signal (SCLK) from an input signal (FDxy) derivable from a drive measurement voltage signal (DMV). The sample clock generator (SCG) comprises an oscillator (HFOSC) arranged to generate a master clock (MOSC), and a counter unit (OSCCNTR) arranged to count master clock periods during one period of the input signal. The clock generator also comprises a number count monitor (NCM) arranged to determine during how many input signal periods the number count stays constant, and to compare the number of constant periods (Ncp) with a critical number of constant periods (Ncp_crit). A frequency shifter (FSH) will trigger the oscillator to shift the master clock frequency whenever the number count monitor (NCM) has determined that the number of constant periods (Ncp) exceeds the critical number of constant periods (Ncp_crit).
An ignition control device having an Electronic Fuel Injection (EFI) mode and a Capacitive Discharge ignition (CDI) mode is described. The ignition control device comprises: an output for providing an output voltage (V0UT), connected or connectable to a load, the load being a fuel injection actuator of an EFI system or an ignition capacitor of a CDI system; and a driver unit connected to the output, for driving the output voltage from a low level (V0UTI) to a high level (VOUTO) and from the high level to the low level in dependence on an input signal (On/Off), each transition of the output voltage from the low level to the high level having a low-to-high transition time which is longer for the CDI mode than for the EFI mode.
F02D 43/00 - Conjoint electrical control of two or more functions, e.g. ignition, fuel-air mixture, recirculation, supercharging or exhaust-gas treatment
F02P 3/06 - Other electric spark ignition installations characterised by the type of ignition power generation storage having capacitive energy storage
APPARATUS AND METHOD FOR EXTERNAL ACCESS TO CORE RESOURCES OF A PROCESSOR, SEMICONDUCTOR SYSTEMS DEVELOPMENT TOOL COMPRISING THE APPARATUS, AND COMPUTER PROGRAM PRODUCT AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM ASSOCIATED WITH THE METHOD
There is disclosed an apparatus for external access to core resources (211,212) of a processor (2) comprising a processing core (21), a shared memory (22), and a multiple paths Direct Memory Access, DMA, controller (23). Access to core critical resources can be performed while the core is executing an application program. The proposed apparatus comprises a Manager module (13) which is operable to setup the DMA controller to copy the assigned core resources via allocated DMA channel into a safe memory region. Further, an Observer module (14) is operable to read the transferred data and make the correlation on the host apparatus side. This allows accessing data used by the core via the DMA controller into, e.g., a run-time debugger accessible region.
A controller (20; 21; 22) used to control a flyback switching mode power supply (10; 11; 12). The flyback switching mode power supply (10; 11; 12) is constructed to charge a capacitor (C), and includes a rectifying device (RD), a series arrangement of a switch (SW1) and a primary winding (L1) of a transformer (T) for receiving an input voltage (Vin), and a secondary winding (L2) of the transformer (T) for charging the capacitor (C) via the rectifying device (RD) to an output voltage (Vout). The controller (20; 21; 22) is configured to sense the output voltage (Vout) and to turn on the switch (SW1) when the change of the output voltage (Vout) over time becomes smaller than a predetermined threshold (dth). By using the controller (20; 21; 22) to sense and use the output voltage (Vout) across the capacitor (C) to turn on the switch (SW1), a controlled flyback switching mode power supply (10; 11; 12) that makes use of voltage control is realized.
H02M 3/28 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
H02M 3/24 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
H02M 3/22 - Conversion of DC power input into DC power output with intermediate conversion into AC
The invention provides a bond wire arrangement comprising a signal bond wire (1) for operably connecting a first electronic device (6) to a second electronic device (8), and a control bond wire (2) being arranged alongside the signal bond wire at a distance so as to have a magnetic coupling with the signal bond wire (1), and having a first end (11) coupled to ground, and a second end (12) coupled to ground via a resistive element (14). The proposed solution allows the control of the Q factor (losses) of wire bond inductors during assembly phase, which will save time and reduce overall design cycle as compared to known methods.
An FFT device (10) for performing a Fast Fourier Transform (FFT) of an operand vector of length N is described. The FFT device (10) comprises a control unit (18), a coefficient unit (14), and a transformation unit (26, 27). The control unit (18) controls a sequence of transformation rounds, the transformation rounds including two or more FFT rounds and further including or not including a window round. The control unit (18) also maintains configuration data indicating for each of said transformation rounds whether the respective transformation round is an FFT round, a window-FFT round, or a window round. The coefficient unit (14) provides transformation data. The transformation unit (26, 27) is arranged to receive, for each of said transformation rounds, transformation data (8.4; 8.6, 8.10) from the coefficient unit (14), the transformation data depending on whether the respective transformation round is an FFT round (8.10, 8.1 1 ), a window-FFT round (8.6— 8.9), or a window round (8.4— 8.7) as indicated by the configuration data, and to perform the respective linear transformation on the basis of the transformation data. A method for performing a Fast Fourier Transform is described as well.
The invention provides a processing system, comprising a memory comprising a processor call stack; a stack space usage register configured to determine the stack space usage of the processor call stack and to store a usage parameter indicative of the determined stack space usage; a first threshold register configured to store a pre-determinable first stack level threshold; and a first comparator configured to compare the usage parameter with the first stack level threshold and to output a first interrupt blocking signal, if the usage parameter exceeds the first stack level threshold, the first interrupt blocking signal being configured to block the decoding of interrupt signals input to the processing system and having interrupt priorities lower than or equal to or just lower than a first interrupt priority threshold. The invention further provides a method for stack management, especially in a processing system.
The FFT device comprises: a control unit arranged to control a sequence of transformation rounds, the transformation rounds including two or more FFT rounds, wherein the FFT rounds include a window-FFT round or the transformation rounds further include a window round, wherein each transformation round is arranged to be carried out in a sequence of N/M successive operations, each operation transforming a subvector of length M of said operand vector into a corresponding transformed subvector of length M; and a coefficient unit for providing transformation data; and a transformation unit arranged to receive, for each of said transformation rounds, transformation data from the coefficient unit, the transformation data depending on whether the respective transformation round is an FFT round, a window-FFT round or said window round and to perform the respective linear transformation on the basis of the transformation data.
A unit (10; 11; 12; 13) used to control a segment liquid crystal display (15; 16). The segment liquid crystal display (15; 16) includes at least a backplane electrode (20) and at least a front plane electrode (25) both associated with a same segment of the segment liquid crystal display (15; 16). The unit (10; 11; 12; 13) includes a controller (30; 40; 50) in order to generate a pulse-width- modulated control signal (35) that has two voltage levels and a variable duty cycle. The unit (10; 1; 12; 13) further includes an integrator (60; 61) to integrate the pulse-width-modulated control signal (35) and to provide an integrated control signal (90) which has more than two discrete voltage levels corresponding to different variable duty cycle values. An output of the unit (10; 11; 2; 13) supplies the integrated control signal (90) to the at least a backplane electrode (20) or to the at least a front plane electrode (25) so that visibility of the same segment in the segment liquid crystal display (15; 16) can be controlled. By having a pulse-width-modulated control signal (35) with only two voltage levels and different duty cycle values generated by the controller (30; 40; 50), and by having the integrator (60; 61) integrating said pulse-width-modulated control signal (35), more than two different discrete voltage levels are generated to control the at least a backplane electrode (20) or at least a front plane electrode (25) without the need to use an application specific segment liquid crystal interface in the unit (10; 11; 12; 13), thereby abating the cost of implementation of the unit (10; 11; 12; 13).
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
G02F 1/133 - Constructional arrangementsOperation of liquid crystal cellsCircuit arrangements
26.
SIGNAL PROCESSING UNIT AND METHOD FOR SEARCHING FOR PEAKS IN A TWO-DIMENSIONAL MATRIX
A signal processing unit and a method for searching for peaks in a two-dimensional matrix of numbers are described. The matrix is analyzed row by row and then column by column. Analyzing a row comprises, for each element of the row, tagging the element in response to determining that the element is a local maximum of the row Analyzing a column comprises determining a bit field associated with the column by determining, for each element of the column, a corresponding bit field element Determining the bit field element comprises: if the element of the column has not been tagged, setting the bit field element to a predefined first value, and, if the element of the column has been tagged, determining whether the element is a local maximum and, in this case, setting the bit field element to a predefined second value different from the first value and, otherwise, setting the bit field element to the first value.
A switching module comprising at least one current sense component. The at least one current sense component is arranged to generate a first phase sense current based at least partly on a received output signal of the at least one differential amplifier when the first cross-coupling component is configured to operably couple the differential inputs of the at least one differential amplifier to the output node of the at least one power switching device and the current sense feedback node with a first polarity, generate a second phase sense current based at least partly on a received output signal of the at least one differential amplifier when the first cross-coupling component is configured to operably couple the differential inputs of the at least one differential amplifier to the output node of the at least one power switching device and the current sense feedback node with a second polarity, and output a combined sense current based at least partly on a combination of the first phase sense current and the second phase sense current.
The present invention relates to an insulated gate bipolar transistor, IGBT (200), driver module (605) for driving at least one gate (202) of at least one IGBT device (200), and method therefor. The IGBT driver module (605) comprises at least one series capacitance (210) operably coupled between a driver component (630, 640) of the IGBT driver module (605) and the at least one gate (202) of the at least one IGBT device (200). The IGBT driver module (605) further comprises at least one series capacitance charge adjustment component (205) controllable to determine a gate voltage error (ΔGerr) at the at least one gate (202) of the at least one IGBT device (200) and dynamically adjust a charge of the at least one series capacitance (210) based at least partly on the determined gate voltage error (ΔGerr).
H03K 17/14 - Modifications for compensating variations of physical values, e.g. of temperature
H03K 17/06 - Modifications for ensuring a fully conducting state
H03K 17/0412 - Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
This invention relates to a RF and mm-wave frequency power detector used for the power detection of the transferred signal in high frequency transmitter, receiver and/or transceiver. This invention increases the sensitivity of the power detector even for a very high frequency application. It also extends the dynamic range and improves accuracy due to the suppress of the process, voltage, temperature variations. The peak detector circuit comprises a first output (vsigB) coupled to ground by a first load at terminal common emitter of a first and second switching device. A second output (vrefB) is coupled to ground by a second load at terminal common emitter of a third and fourth switching device. A third output (vsigT) is coupled to a supply voltage node by a third load at terminal common collector of the first and second switching device. A fourth output (vrefT) is coupled to the supply voltage node by a fourth load at terminal common collector of the third and fourth switching device. The first, second, third, and fourth switching devices have respective control terminals which are biased with a common bias voltage (vb). The first, second, third and fourth load are selected so that R1=R2=αf*R3=αf R4, with R1, R2, R3, R4 a resistance of said first, second, third and fourth load, respectively, and αf a common-base current gain of the switching devices.
An ESD protection device comprising an SCR -type circuit (300) including a PNP transistor (101) and NPN transistor (106) incorporates a Zener diode (108) which permits the circuit to operate at comparatively low trigger voltage thresholds. Zener diode breakdown voltage is controlled by doping levels in a doped area (308) of an N-type well (307). One or more diodes (105) connected in series between the SCR circuit and the input/output terminal of the device advantageously raises the snapback voltage of the SCR circuit. The use of nitride spacers (314a, 314b) between doped regions (310, 313, 315) instead of gate oxide technology significantly reduces unwanted leakage currents.
H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action
31.
VOLTAGE SUPPLY CIRCUIT WITH AN AUXILIARY VOLTAGE SUPPLY UNIT AND METHOD FOR STARTING UP ELECTRONIC CIRCUITRY
A voltage supply circuit for an electronic circuit includes a switch configured to selectively connect a supply input of the electronic circuit with a main supply voltage source. An auxiliary voltage supply unit has an auxiliary voltage output coupled to the supply input of the electronic circuit. The auxiliary voltage supply unit is configured to at least temporarily output an auxiliary voltage to the supply input. The auxiliary voltage has a voltage level lower than a voltage level of a main supply voltage supplied by the main supply voltage source.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G05F 1/569 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
32.
METHOD AND APPARATUS FOR DETECTING AND MANAGING OVERCURRENT EVENTS
A method of detecting overcurrent events within at least one electronic device, and an overcurrent detection module therefor. The method comprises receiving at least one current requirement indication from at least one electronic device, determining at least one overcurrent value based at least partly on the received at least one current requirement indication, receiving at least one indication of at least one input current flow for the at least one electronic device, and determining that an overcurrent event is occurring if the indicated at least one input current flow for the at least one electronic device exceeds the determined at least one overcurrent value.
An electronic device, typically a microcontroller 100, which is divided into a multiplicity of power domains 102 comprising one or more intelligent peripherals 103, is provided with an on-board power management module (105) for switching power to one or more domains for pre-determined time periods and in a predetermined sequence. The values of the predetermined time periods and sequence may be pre-programmed by the design engineer or user of the device 100. In one example, power is switched to domains in a round robin fashion. An optional interrupt capability permits selective application of power to a dormant intelligent peripheral requesting it at the expense of others and based on a priority scheme. Consumption of current supplied to power domains may be monitored by a power watchdog 108 or alternatively via a dedicated power monitor associated with each intelligent peripheral. The invention helps to reduce device power consumption without any associated reduction in processing performance.
A layered network (10; 11; 12) to provide offload of data in a communication processor (100; 110; 120). The layered network (10; 11; 12) includes a first set (S1) of network elements at a first layer (L1) and a second set (S2) of one or more network elements at a second layer (L2). The network elements of the first set (S1) are configured for processing incoming data and the network elements of the second set (S2) of one or more network elements at the second layer (L2) are configured to process intermediate data received from the first set (S1) of network elements. The network elements of a particular subset (Si1) of the network elements of the first set (Si1) of network elements are connected to only a particular network element (Ei2) of the second set (S2) to transfer the incoming data processed by the network elements of the particular subset (Si1) to the particular network element (Ei2) of the second set (S2). The layered network (10; 11; 12) further includes a powering controller (25) configured to, during offload of the data, put a particular network element (Ei2) of the second set (S2) at the second layer (L2) in an on state only if at least a particular network element (Ei1) of the particular subset (Si1) of the network elements of the first set (S1) at the first layer (L1) is in an on state and at least one of the network elements of the first set (S1) is in an off state. The powering controller (25) is configured to discriminate between chains of network elements formed by at least network elements of the first set (S1) and network elements of the second set (S2) and to have a chain in an on state if a first network element of the chain at a highest layer hierarchy is in an on state.
Calibration circuit (10) and a method for calibrating an RC circuit of an integrated circuit (70) for calibrating a high-pass filter (11, 16), wherein the calibration circuit comprises: a filter arrangement (11, 16) comprising at least one tuneable filter (11) configured to filter an input signal (V1) having a predetermined frequency wherein the tunable filter (11) comprises at least two tuneable resistor elements (22, 23); a saturation detector (12) configured to detect saturation and non-saturation of the tuneable filter (11) by comparing a comparison voltage (V4) with the signal voltage of the filtered input signal (V2); a calibration control logic (13) configured to provide an incrementing counter signal (CI) and a decrementing counter signal (CD); wherein the calibration circuit (10) is further configured to set the comparison voltage (V4) to a first threshold voltage (Vth); to provide iteratively an incrementing counter signal (CI) to the filter (11) until saturation is detected; after saturation is detected, reducing the comparison voltage (V4) to a predetermined second threshold voltage (Vth/2) which is a predetermined value lower than the first threshold voltage (Vth); to provide then iteratively a decrementing counter signal (CD) to the filter (11) until non-saturation is detected. This invention further provides an integrated circuit, in particular a receiver circuit, a radar system and a calibration method.
H03H 7/12 - Bandpass or bandstop filters with adjustable bandwidth and fixed centre frequency
36.
CAN FD END-OF-FRAME DETECTOR, CAN BIT STREAM PROCESSING DEVICE, METHOD FOR DETECTING THE END OF A CAN FD FRAME, AND METHOD OF OPERATING A CAN BIT STREAM PROCESSOR
A method for detecting an end-of-frame of a CAN FD frame in an input bit stream (30) is described. The CAN FD frame comprises one or more portions provided at a normal bit rate and one or more portions provided at a high bit rate, the one or more portions provided at the normal bit rate including an end-of-frame field consisting of a succession of seven or more recessive bits. The method comprises: providing a recessive bit count; defining a stretched bit transmission time (T_STR) longer than the bit transmission time associated with the high data rate; stretching the bit transmission time of each dominant bit succeeding a recessive bit in the input bit stream (30) to the stretched bit transmission time, thus generating a conditioned input bit stream (46); sampling the conditioned input bit stream (30) at a bit counter rate, thus generating a sampled bit stream; resetting the recessive bit count in response to each dominant bit in the sampled bit stream; and incrementing the recessive bit count in response to each recessive bit in the sampled bit stream. A CAN FD end-of-frame detector, a CAN bit stream processing device, and a method of operating a CAN bit stream processor are described as well.
H04L 12/413 - Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
B60R 16/023 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided forArrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for transmission of signals between vehicle parts or subsystems
There is provided an energy consumption meter device (1 ) comprising the processor (8) arranged to receive input data from the sampling unit. The processor calculates at a calculation step [n] an energy contribution value using ΔΕ using a sampled voltage value and a sampled current value. The processor will calculate an energy value E[n] using a reminder value which was calculated at a previous calculation step [n-1 ]. The processor will then calculate a relative delay Td' using the threshold value, the reminder value and the energy value, and generate an output pulse at an output time tpulse which is delayed for the relative delay Td' with respect to the calculation time step[n]. By delaying the output pulse with a value which is a closest proximity of Td, the cycle-by- cycle jitter is less or equal to the clock frequency of the timer tclk.
A script-driven head-up display controller comprising an image warping unit and an image projection unit wherein the image warping unit is coupled to the image projection unit and is adapted to: - receive a line-based warping descriptor comprising first information associated with a distortion caused by a non-flat display; and, - in response to the reception of the line-based warping descriptor, the image warping unit is further adapted to, based on the line-based warping descriptor: - fetch one or more lines of the source image; and, - output to the image projection unit at least one output line of the output image associated with an electronic image warping of one or more pixels of the one or more input lines, and wherein the line-based warping descriptor further comprises second information associated with buffer management instructions calculated off-line.
Apparatus (110) for configuring network equipment or devices (101a-101n) during runtime is particularly applicable to network equipment based on QorIQ (trade mark) communication platforms for DPAA (Data Path Acceleration Architecture) optimization purposes and provides a way maintaining an optimal configuration which can change over time according to real traffic conditions. The invention may be implemented with any kind of adaptation algorithm for targeting different DPAA features. A flow characteristic function is determined from collected traffic statistics for a multiplicity of traffic flows classified by a common property such as protocol or destination or source. Flow properties are characterised over time, past present and future prediction and in relation to other existing flows based on assigned priorities. A computed flow characteristic function represents the basis for all adaptation algorithms which may be implemented in order to optimise the various DPAA features. In contrast with conventional methods which adapt traffic to system constraints, the apparatus of the present invention itself continuously adapts to traffic dynamics in order to maintain an optimal configuration over an extended period of time.
G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
A method of performing register allocation for at least one program code module. The method comprises constructing a restriction graph for program variables within at least one program instruction, and determining whether the constructed restriction graph is colourable. The method further comprises, if it is determined that the constructed restriction graph is not colourable, determining whether at least one alternative form of the at least one program instruction is available, and modifying the at least one program instruction to comprise an alternative form if it is determined that at least one alternative form is available.
G06F 9/06 - Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
41.
ELECTRONIC DEVICE HAVING MULTIPLEXED INPUT/OUTPUT TERMINALS
An electronic device (200) has terminals (202) for interfacing internal signals to other electronic devices. Each terminal is electrically coupled to a terminal driver (203) and a terminal control circuit (212) for receiving a terminal configuration defining the properties and multiplexing of the terminal. The actual configuration of the terminal driver is set according to the terminal configuration. The device has at least one terminal checker (204,204') arranged for comparing the actual configuration to at least one check configuration, the check configuration defining a configuration of the terminal driver that is either allowed or not allowed, and for, when said comparing indicates a not allowed configuration, setting the actual configuration to a default configuration. Advantageously safe operation of the device in a system is achieved by monitoring the configuration of the multiplexed terminals, and switching to a default configuration when in error.
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
The invention relates to a method of resetting a processor, the method comprising the receiving of a reset signal indicating that one or more parts (51, 52) of said processor need to be reset, and forwarding of said reset signal to said parts (51, 52) to be reset. The forwarding of the reset signal is delayed for a period of time for at least one of the parts (51) to be reset. The clock frequency of at least one of the parts to be reset is gradually decreased during said period of time. In this way the total activity of the processor device is gradually decreased so as to avoid an on- chip voltage overshoot, which could cause a total reset of all the parts of the processor.
The use of a netlist (108) or other database containing topological information of an electrical circuit (101) comprising a multiplicity of components (103, 110) which are to undergo safe operating area (SOA) checking, permits a relationship between recorded SOA errors to be established. Knowing how such errors may be interdependent can assist designers in deciding which errors should be rectified first. The relationship between the recorded errors relating to two connected components may be modified by a confidence factor based on elapsed time between the occurrence of the two recorded errors.
A power field effect transistor (200), a power field effect transistor device and a method of manufacturing a power field effect transistor are provided. During the manufacturing of the power field effect transistor (200), a body drive stage to manufacture the body region (128) of the power field effect transistor (200) is shortened to obtain a relatively low on resistance for the power field effect transistor (200). Before the implanting stage of the dopants of the body region (128), a pre body drive stage is introduced. During the pre body drive stage and the body drive stage sidewalls of a polysilicon layer (112) of the power field effect transistor (200) are oxidized to obtain a power field effect transistor (200) which has at the sidewalls an oxidized polysilicon layer (150) that is thick enough to prevent a premature current injection from the gate (112) to the source regions (122) of the power field effect transistor (200).
A semiconductor device (100) comprises a first contact layer (102), a first drift layer (106) adjacent the first contact layer (102), a buried body layer (108) adjacent the first drift layer (106) and a second contact layer (112). A first vertical trench (114) and a second vertical trench (116) are provided, the first and second vertical trenches (114, 116, 118, 120) being spaced with respect to each other and extending from the second contact layer (112) to substantially beyond the buried body layer (108). A second drift layer (110) is also provided and sandwiched between the buried body layer (108) and the second contact layer (112).
An embodiment of a microwave power generation module includes an amplifier arrangement, an impedance matching element, and a resonant element. The amplifier arrangement includes a transistor with a transistor input and a transistor output. The impedance matching element is formed from a planar conductive structure. The planar conductive structure has a proximal end and a distal end, and the proximal end is electrically coupled to the transistor output. The resonant element has a proximal end electrically coupled to the distal end of the planar conductive structure, and the resonant element is configured to radiate electromagnetic energy having a microwave frequency in a range of 800 megahertz (MHz) to 300 gigahertz (GHz). A combination of the impedance matching element and the resonant element is configured to perform an impedance transformation between an impedance of the transistor and an impedance of an air cavity.
There is provided a method of estimating a bit error rate in a transport channel of a wireless communication system. The method comprises the receiving a signal from a remote transmitter of the wireless communication system via a physical channel, the signal comprising data and noise forming a plurality of soft bits. The method further comprises the counting, during a period of time, a number of erroneous bits being those soft bits which have an amplitude below -2A or above +2A with A being the average amplitude of the soft bits received. Next, the number of erroneous bits is divided by a number of total bits received during said period of time in order to obtain the bit error rate. This method provides a way to estimate the BER value without knowing the exact shape of the noise distribution. In an embodiment a selection is made between two estimation algorithms.
A spread-spectrum clock generation circuit comprises at least one comparison element; at least one charge storage device arranged to couple an output of the at least one comparison element to an input of the at least one comparison element and arranged to set a first oscillation frequency of the spread-spectrum clock generation circuit; and a switched charge storage arrangement additionally arranged to couple an output of the at least one comparison element to an input of the at least one comparison element and arranged to set a second oscillation frequency of the spread-spectrum clock generation circuit.
H03K 25/02 - Pulse counters with step-by-step integration and static storageAnalogous frequency dividers comprising charge storage, e.g. capacitor without polarisation hysteresis
H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
H03L 5/00 - Automatic control of voltage, current, or power
A transceiver circuit for operating in a controller area network (CAN), having a CAN bus network and a control unit, that supports a flexible data rate (CAN FD), is described. The transceiver circuit comprises: a transmit CAN path and a receive CAN path; an input node on the transmit CAN path; a detection module operably coupled to the input node on the transmit CAN path and arranged to receive an input frame from the control unit before the input frame is transmitted on the CAN bus network and determine whether the input frame on the transmit CAN path comprises a CAN FD frame; and at least one switching module, operably coupled to the detection module and coupleable to the CAN bus network, where the at least one switching module is operable to impart a first voltage value on the CAN bus network in response to the input frame being determined as comprising a CAN FD frame.
An electronic control unit (100) suitable for a motorcycle (101) provides diagnostic support, tachometer drive and warning lamp drive all multiplexed onto one pin (102) and driven by a single driver circuit (117). In a diagnostics mode, the pin is connected to diagnostic equipment (106). When a diagnostic test has been completed, a tachometer drive signal is output on the pin, the drive signal having a duty cycle set high enough to illuminate the warning lamp (103) if a fault condition is detected by on-board sensors (112, 113). By combining multiple functions onto a single pin with a single driver circuit, the cost of implementing an engine control unit may be reduced compared with existing arrangements which require separate pins and drivers for each function.
B62J 99/00 - Subject matter not provided for in other groups of this subclass
B60R 16/023 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided forArrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for transmission of signals between vehicle parts or subsystems
51.
METHOD OF DESIGNING AN INTEGRATED CIRCUIT AND COMPUTER PROGRAM PRODUCT
A method of designing an integrated circuit is described. The integrated circuit comprises a plurality of circuit components, including one or more functional components and one or more tile shapes. A pcell instance may be defined to specify a functional component along with one or more tile shapes. The tile shapes are thus associated with the functional component. A netlist may be arranged to specify interconnections between the functional components of the integrated circuit as well as electrical interactions between the tile shapes and functional components. A computer program product for carrying out the method is also described.
A data processing device (10) comprises a protection key unit (44), a dummy key unit (24), and a control unit (50). The protection key unit (44) provides a protection key. The dummy key unit (24) provides a dummy key. The dummy key unit (24) has a set of two or more allowed dummy key values associated with it and is configurable by a user or a host device (8) to set the dummy key to any value selected from said set of allowed dummy key values. The control unit (50) is connected to the dummy key unit (24) and to the protection key unit (44) and arranged to set the protection key to the value of the dummy key in response to a tamper detection signal (fatal_sec_vio) indicating a tamper event. The value of the dummy key may notably be different from zero. A method of protecting a data processing device (10) against tampering is also described.
The invention provides an apparatus and method for checking the integrity of visual display information and has particular application to checking images displayed in an automotive vehicle, such images containing safety critical information. The image intensity is checked only to an extent commensurate with a human being able to interpret its correct meaning. Hence, images which are defective in some way yet still recognisable by the human eye are not classified as failures. In one embodiment, a part of the image containing safety critical information is segmented into smaller areas and the luminance of pixels in each segmented area is compared with a threshold brightness level and a threshold darkness level. A histogram for each area is generated and compared with a reference.
Apparatus suitable for detecting a fault in a processor 101 comprises a monitor 100 which receives input and output signals 102, 103 from the processor and generates a hash index key which is used to access entries in a hash table 203. The entries may include actions such as setting a timer 201 so that the response of an output to a change of state of an input may be confirmed as valid within a specified time interval.
A charge pump circuit (202) comprises a first bipolar transistor device (288) and a second bipolar switching device (286) arranged in a differential pair configuration. A first terminal of each of the first and second bipolar switching devices (288, 286) are coupled to a supply (291). A second like terminal of each of the first and second bipolar switching devices (288, 286) are coupled together and to ground potential (226) via a pulsed current source (290). A field effect switching device (201) is also provided and the first terminal of the first bipolar switching device (288) is coupled to the voltage supply (216) via the field effect switching device (201).
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
A system on chip (10) comprises a responder unit (14) comprising a set of responder elements (15) and an access control unit (18) associated with an authorization list (38) and the responder unit (14). An entry of the authorization list (38) defines a set of access requirements in relation to an address space identifying at least part of the responder unit (14). The access control unit (18) is arranged to: receive a request for access (34) to a target responder element (15') among the responder elements (15) of the responder unit (14), determine the corresponding set of access requirements for the received access request from the authorization list (38), and evaluate the request for access (34) with respect to the determined set of access requirements and generate a first request evaluation result (56). A protection unit (36) associated with the responder unit (14) is arranged to: provide a group assignment (40) assigning a group (G1, G2, G3,...) to each of the responder elements (15) of the responder unit (14), provide a group authorization list (42), an entry of the group authorization list (42) defining a set of group access requirements for the group assigned, receive the request for access (34) to the target responder element (15'), determine the group assigned to the target responder element (15') from the group assignment (40) and further determine the set of group access requirements from the group authorization list (42) for the group assigned. The system-on-chip also evaluates the request with respect to the determined set of group access requirements and generates a second request evaluation result (58). Interaction with the target responder element (15') is controlled in response to the first and/or second evaluation result (56, 58).
Apparatus (103) suitable for determining the resistance and inductance of an electric motor (101) estimates the phase shift between a voltage applied to the motor and motor current. Estimation of the phase shift employs a heterodyne technique. The measured motor current is conditioned prior to heterodyning in a mixer 203 in order to reduce the effects of nonlinearities introduced by a voltage source inverter (102) which supplies the motor (101) with a voltage. A value for impedance may be calculated as a ratio of a voltage applied to the motor and the motor current. The resistance and inductance may then be calculated from the impedance and phase shift calculations. In cases where the voltage applied to the motor cannot be directly measured but only the voltage supply to the voltage source inverter 102 is known, a value for impedance may be determined based on a ratio of a reconstructed voltage signal having a phase angle equal to that of the motor current and the motor current.
A communication apparatus for preventing the broadcasting of unauthorised messages on a broadcast bus network, the communication apparatus comprising: - a first memory adapted to store first information; - a second memory adapted to store second information; - a monitoring unit adapted to: - monitor the bus for processing messages being broadcasted on the bus, and - output a third information and fourth information - a comparing unit adapted to compare the first information with the third information and the second information with the fourth information; and, - a message destroyer adapted to: when: - the first information matches with the third information, and - the second information does not match with the fourth information, causing the body of the current message to be altered while the current message is being broadcasted on the bus.
A method and a computer program product for disassembling a mixed machine code are described. The machine code is provided as a sequence of code items including one or more instructions and one or more data items. The method comprises: storing the sequence of code items in accordance with a corresponding sequence of addresses; executing the machine code, thereby generating an execution trace; and partitioning the sequence of addresses into instruction address blocks and data address blocks on the basis of control data, the control data comprising at least the execution trace.
G06F 9/06 - Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
60.
METHOD AND APPARATUS FOR CONTROLLING AN OPERATING MODE OF A PROCESSING MODULE
A method of controlling an operating mode of at least one processing module. The method comprises receiving an indication of the execution of at least one background task by the at least one processing module, aggregating an execution duration for the at least one background task on the at least one processing module, and configuring a lower power mode for the at least one processing module when the at least one background task is allocated to the at least one processing module for execution thereon if the aggregated execution duration for the at least one background task exceeds a threshold duration within an evaluation period.
G06F 9/06 - Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
G06F 9/44 - Arrangements for executing specific programs
A radio signal decoder (100) is provided. The radio signal decoder (100) comprises a receiver configured to receive a digitized radio signal (122), the radio signal having modulated subcarrier frequencies encoding digital information, a first set of the subcarrier frequencies having a first subcarrier spacing (PUSCH; PUCCH; SRS ), a second set of the subcarrier frequencies having a second subcarrier spacing (RACH), a first transformer (130, FFT) configured to transform the digitized radio signal from a time domain into a frequency domain, the transformer being configured with the first subcarrier spacing, an a first decoder (140, PUSCH; PUCCH; SRS ) configured to reconstruct digital information from the output of the first transformer, and an inverse transformer (220, IFFT) configured to receive as input at least a part of the output (132) of the first transformer representing a frequency range overlapping the second set of subcarrier frequencies, and to transform the input from the frequency domain back to the time domain, the first inverse transformer being configured with the first subcarrier spacing, a second transformer (160, FFT) configured to transform the output of inverse transformer from the time domain to a frequency domain, the second transformer being configured with the second subcarrier spacing, a second decoder (170, 180, ZC) reconstructing digital information from the output of the second transformer.
A gate drive circuit (10a) to drive a gate terminal (G) of a power transistor (12a). The gate drive circuit (10a) includes a first capacitor (C1), a first switch (SW1), a measurement circuit (5) and a reference source (6) to generate a reference voltage (Vref). The first capacitor (C1) has a first terminal (T11) electrically coupled to the gate terminal (G) of the power transistor (12a). The first switch (SW1) is arranged between a second terminal (T21) of the first capacitor (C1) and a first predetermined voltage (Vp1). The measurement circuit (5) is used to measure a differential voltage across the first capacitor (C1). The gate drive circuit (10a) is configured to pre-charge the first capacitor (C1) to obtain a second predetermined voltage (Vp2) across the first capacitor (C1). The gate drive circuit (10a) is further configured to arrange the first switch (SW1) in an on state to turn on the power transistor (12a) and to electrically couple the first predetermined voltage (Vp1) to the second terminal (T21) of the first capacitor (C1). The first capacitor (C1) is initially pre-charged at the second predetermined voltage (Vp2). The measurement circuit (5) is configured to arrange the first switch (SW1) in an off state when the differential voltage across the first capacitor (C1) has changed with respect to the second predetermined voltage (Vp2) by the reference voltage (Vref). By using the measurement circuit (5) to measure the differential voltage across the first capacitor (C1) and to turn off the first switch (SW1) when the differential voltage across the first capacitor (C1) has changed with respect to the second predetermined voltage (Vp2) by the reference voltage (Vref), an accurate control of the charge change in the first capacitor (C1) is provided. The charge change proportional to the reference voltage (Vref) is a measure of an amount of charge that is transferred to the gate terminal (G) of the power device (12a) to turn on the power device (12a).
H03K 17/06 - Modifications for ensuring a fully conducting state
H03K 17/689 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit
63.
OSCILLATOR CIRCUIT AND METHOD OF GENERATING A CLOCK SIGNAL
An oscillator circuit (201) of the type comprising a flip-flop (219) for generating a clock signal (222) and two comparators (213, 216) for comparing a reference voltage with the voltage across a first capacitor which is charged during a first cycle of the clock signal and the voltage across a second capacitor which is charged during a second cycle of a clock signal provides a means for removing the effects of any offset in either comparator. This is achieved by reversing the inputs of the comparators (213, 216) for each cycle of the output frequency. Thus an offset in a comparator which would increase the clock period on one cycle will reduce the period of the next cycle by the same amount (due to the fact that any offset drift tends to evolve slowly compared with the output clock frequency). As a net result, the period of time over two clock periods will stay constant regardless of any offset drift in a comparator.
Interfacing between radio units (RE, REC) in a base station (200) in a mobile communication system uses a common public radio interface CPRI (210) for streaming IQ data samples and control data arranged in lanes. A separate serial interface sRIO (220) is now additionally used for transferring selected control data arranged in packets to a controller (203), the selected control data being streamed between other radio units via the common public radio interface. In the radio unit (202), the selected control data are arranged in packets to be transmitted via the serial interface, and, vice versa, the selected control data arranged in packets received via the serial interface are arranged in lanes to be streamed. Advantageously the control data of the streaming CPRI interface is seamlessly transferred to the controller (203) via the packet based serial interface.
H04L 29/10 - Communication control; Communication processing characterised by an interface, e.g. the interface between the data link level and the physical level
H04L 29/08 - Transmission control procedure, e.g. data link level control procedure
65.
METHOD AND DEVICE FOR DATA STREAMING IN A MOBILE COMMUNICATION SYSTEM
Interfacing between radio units (RE, REC) in a base station (200) in a mobile communication system uses a common public radio interface CPRI (210,211,212) for streaming IQ data samples arranged in lanes. A separate serial interface sRIO (220) is now additionally used for transferring selected data samples arranged in packets, the selected samples corresponding to selected lanes streamed between other radio units via the common public radio interface. In the radio unit, the selected data samples are arranged in packets to be transmitted via the serial interface, and, vice versa, the selected data samples arranged in packets received via the serial interface are arranged in lanes. A system timer coupled to the CPRI generates a timebase for controlling the sRIO interface in order to have it synchronized. Advantageously the data sample transfer capacity of the streaming CPRI interface is extended using the packet based serial interface.
H04L 29/10 - Communication control; Communication processing characterised by an interface, e.g. the interface between the data link level and the physical level
H04L 29/08 - Transmission control procedure, e.g. data link level control procedure
An on-board trimming circuit suitable for trimming an accelerometer (100) provides offset trim (112, 113) and gain trim (116, 115) modules for determining correct trim codes for subsequent programming into the trimming circuit. The correct trim codes may be determined by comparing sensor outputs (107,108,109) which have been adjusted by successive trim codes, with a reference voltage in a comparator (117) until the comparator toggles or by using a successive approximation technique. The reference voltage is supplied form a tap (130) of a feedback resistance divider circuit (128) which forms a part of an on-board voltage reference generator (126) which may be used to provide a full scale reference for an analog to digital converter which converts a sensor output voltage into a digital signal. Using reference voltages supplied from such a feedback circuit significantly lessens the impact of any offsets inherent in the voltage reference generator (126) on the trimming process.
G01P 21/00 - Testing or calibrating of apparatus or devices covered by the other groups of this subclass
G01L 25/00 - Testing or calibrating of apparatus for measuring force, torque, work, mechanical power, or mechanical efficiency
G01D 3/036 - Measuring arrangements with provision for the special purposes referred to in the subgroups of this group mitigating undesired influences, e.g. temperature, pressure on measuring arrangements themselves
67.
EMITTER FOLLOWER BUFFER WITH REVERSE-BIAS PROTECTION
The invention relates to a buffer circuit for a receiver device comprising a transconductance stage (105) and an output stage coupled in parallel to output stages of other channels of the device. The output of the transconductance stage (105) is connected to a base of a bipolar transistor (110) in the output stage. A switch (112) is connected between the base of the bipolar transistor (110) and the emitter of the bipolar transistor (110). A controller (120) is arranged to switch the buffer circuit from a switch-off mode to a switch-on mode and back. In switch-off mode the switch (112) is switched on, so as to connect the base and the emitter of the bipolar transistor (110).
H03F 3/50 - Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower
68.
A GATE DRIVE CIRCUIT AND A METHOD FOR SETTING UP A GATE DRIVE CIRCUIT
A gate drive circuit (10a) used to drive a power transistor (12a). The gate drive circuit includes a first switch (SW1) and a first capacitor (C1). A first terminal (T11) of the first capacitor (C1) is electrically coupled to the first switch (SW1). The first switch (SW1) is electrically coupled between the first terminal (T11) and a voltage supply (HV) of the power transistor (12a). A second terminal (T12) of the first capacitor (C1) is electrically coupled to the reference potential (GND). The gate drive circuit (10a) further includes a first voltage limiter (VL) in parallel with the first capacitor (C1). The first voltage limiter (VL) limits a voltage across the first capacitor (C1) to a first predetermined voltage. The gate drive circuit (10a) further includes a second capacitor (C2), a pre-charging circuit (PC) arranged between the first terminal (T11) of the first capacitor (C1) and a first terminal (T21) of the second capacitor (C2). The gate drive circuit (10a) further includes a third capacitor (C3) with a first terminal (T31) electrically coupled to a second terminal (T22) of the second capacitor (C2) and a second terminal (T32) electrically coupled to a gate terminal (G) of the power transistor (12a). Additionally the gate drive circuit (10a) includes a second switch (SW2) arranged between the first terminal (T11) of the first capacitor (C1) and the second terminal (T22) of the second capacitor (C2), a third switch (SW3) arranged between the first terminal (T31) of the third capacitor (C3) and the reference potential (GND) and a fourth switch (SW4) arranged between the second terminal (T32) of the third capacitor (C3) and the reference potential (GND). During a setup of the gate drive circuit (10a) after applying the voltage supply (HV), the gate drive circuit (10a) is configured to arrange the first switch (SW1) in an on state to electrically couple the supply voltage (HV) to the first terminal (T11). The first capacitor (C1) is in this way charged to obtain the first predetermined voltage across the first capacitor (C1). The gate drive circuit (10a) is further configured to configure the pre-charging circuit to pre-charge the second capacitor (C2) to obtain a second predetermined voltage across the second capacitor (C2). The gate drive circuit (10a) is also configured to pre-charge the third capacitor (C3) to obtain a third predetermined voltage across the third capacitor (C3). The gate drive circuit (10a) is configured to be powered by the voltage across the first capacitor (C1). By charging the first capacitor (C1) and by pre-charging the second and third capacitors (C2, C3), the gate drive circuit (10a) is setup, powered up and and ready to be used to drive the gate terminal (G) of the power transistor (12a).
An integrated matching circuits for a high frequency amplifier transistor (12) having an input terminal (G), an output terminal (D) and a reference terminal (S). The reference terminal (S) is coupled to a reference potential (GND). The integrated matching circuit comprises an inductive element (IND1), and a capacitive element (CAP1) arranged in a series arrangement with the inductive element (IND1). The series arrangement has a first terminal end (TE1) connected to the input terminal (G) or to the output terminal (D) and a second terminal end (TE2) connected to the reference terminal (S). The first terminal end (TE1) and the second terminal end (TE2) are arranged at a same lateral side (LS) of the integrated matching circuit to obtain a geometry with the first terminal end (TE1) adjacent to the input terminal (G) or to the output terminal (D) and the second terminal end (TE2) adjacent to the reference terminal (S). The integrated matching circuit is arranged such that a plurality of the series arrangement is placed in parallel along a line extending along an input contact terminal (GT) or an output contact terminal (DT) of the high frequency amplifier transistor (12). The plurality of the series arrangement is connected together at the same first terminal end (TE1) and at the same second terminal end (TE2) of each of the series arrangement. The first terminal end (TE1) of each of the series arrangement is connected together to the input contact terminal (GT) or to the output contact terminal DT). The second terminal end (TE2) of each of the series arrangement is connected together to a reference contact terminal (ST) of the high frequency amplifier transistor (12).
A high frequency amplifier comprising a high frequency amplifier transistor (12) integrated in a first die (DIE1) of a first semiconductor technology and a matching circuit. The high frequency amplifier transistor (12) has an input terminal (G), an output terminal (D) and a reference terminal (S). The reference terminal (S) is coupled to a reference potential (GND). The matching circuit comprises at least a first inductive bondwire (BW1), a second inductive bondwire (BW2) and a capacitive element (CAP;CAP1;CAP2) arranged in series with said inductive bondwires (BW1,BW2). The capacitive element (CAP;CAP1;CAP2) is integrated in a second die (DIE2) of a second semiconductor technology different from the first semiconductor technology. The second semiconductor technology comprises an isolating substrate for conductively isolating the capacitive element (CAP;CAP1;CAP2) from a support (PKG) attached at a first side (AS) to the second die (DIE2). The capacitive element (CAP;CAP1;CAP2) comprises a first plate (P1) electrically coupled to a first bondpad (BD1) of the second die (DIE2) and a second plate (P2) electrically coupled to a second bondpad (BD2) of the second die (DIE2), The first bondpad (BD1) is connected to the input terminal (G) or to the output terminal (D) by means of the first inductive bondwire element (BW1). The second bondpad (BD2) is connected to the reference terminal (S) by means of the second inductive bondwire element (BW2). The first and second bondpads (BD1,BD2) are arranged at a second side (OS) of the second die (DIE2) opposite to the first side (AS). By having only series elements integrated in the second die (DIE2), ground vias connecting the passive elements to a ground pad or ground connection of the package (PKG) underneath the second die (DIE2) are avoided and better and thicker isolating substrates may be used to integrate high quality passive elements in the second die (DIE2).
A buck converter and method of operating a buck converter are proposed. The buck converter (10) has an output node (12) and a ground node (14), wherein a load (8) is connected or connectable between the output node (12) and the ground node (14) and the buck converter (10) is arranged to drive an output current I_out through the output node (12), thereby generating an output voltage V_out in the output node (12). The buck converter (10) comprises: a current control unit (16, 18, 20, 22) arranged to control the output current I_out in dependence on a control voltage V_ctl provided at a control node (24); and a voltage control unit (26, 58, 60) arranged to provide the control voltage V_ctl. The voltage control unit comprises: an integrator unit (28) arranged to control the control voltage V_ctl in dependence on a time integral of a difference between the output voltage and the reference voltage; at least one of an overshoot detector (48) arranged to detect an overshoot of the output voltage V_out, and an undershoot detector (46) arranged to detect an undershoot of the output voltage V_out; and a current source (58) connected to the control node (24) and arranged to pull a current of amplitude I_pull from the control node (24) in response to the overshoot detector (48) detecting an overshoot of the output voltage V_out, or arranged to push a current of amplitude I_push to the control node (24) in response to the undershoot detector (46) detecting an undershoot of the output voltage V_out, or both.
A diagnostic apparatus (100) comprises a diagnostic data buffer (112) constituting a volatile memory, and a non-volatile memory (120) capable of receiving data from the buffer (112). A data buffer controller (102) is also provided and is operably coupled to the buffer (112) and has an event alert input and a data channel monitoring input for receiving diagnostic data. The buffer (112) receives, when the state of a buffer status memory (116) indicates that the buffer (112) is in an unprotected state, at least part of the diagnostic data received by the controller (102) via the data channel monitoring input to the buffer (112) and the controller (102) sets the state of the buffer status memory (116) to indicate the protected state in response to receipt of an event alert received via the event alert input. A controller (124) monitors the buffer status memory (116) and copies a portion of the buffer (112) to the non-volatile memory (120) in response to the buffer status memory (116) being set to be indicative of the protected state.
An operation scheduler adapted to schedule in an asynchronous contention-based system, the execution of operations and sequence of operations, wherein: - the first FIFO queue is adapted to store one trigger message and/or one operation request, - the message router is coupled to the first FIFO queue and is adapted to route instructions to the second FIFO queue or the memory and locate in the memory unit the instructions of a suspended operation associated with a trigger message and authorise execution of the suspended operation; - the arbitration unit is coupled to the second FIFO queue and to the memory, and is adapted to schedule the execution of instructions associated with a standalone non-preemptable operation during a period of time within which at least one operation of the first sequence is being suspended.
A method of operating a data processing system comprises: processing data words and switching between contexts; assigning a context signature Sig(W, C) to any pair (W, C) formed of a data word W and a context C. The data words and contexts include a first data word W1, a first context C1, and a second context C2 different from the first context C1 and the context signature Sig(W1, C1) of the first data word W1 and the first context C1 differs from the context signature Sig(W1, C2) of the first data word W1 and the second context C2; reading, within a current context CC, a data record from a memory unit (14), the data record comprising a payload data word WR and a protection signature; providing, as a verification signature, the context signature Sig(WR, CC) of the payload data word WR and the current context CC; checking the verification signature against the protection signature; and generating an error signal if the verification signature differs from the protection signature (S5). A data processing device (10) capable of context switching and comprising a signature unit (22) for providing context-dependent signatures is also described.
A device and a method for executing a program, and a method for storing a program are described. The method of executing a program includes a sequence of instruction cycles, wherein each instruction cycle comprises: updating the program counter value (1.1); reading (1.2) a data word (w) from a memory location identified by the updated program counter value, wherein the data word (w) comprises an instruction (π) and a protection signature (χ); determining (1.3) a verification signature (χ) by applying a signature function (Γ-->χ) associated with the program counter value to the instruction (Γ); executing (1.6) the instruction (Γ) if the verification signature and the protection signature (χ) are consistent with each other; and initiating (1.5) an error action if they are inconsistent with each other. A method for storing a program on a data carrier is also described.
A carrier aggregation controller 100 for providing an aggregated baseband signal from a plurality of baseband signals is provided. The controller comprises an accumulating memory 170, a selector 160 and a time domain transformer 180. The selector 160 is configured to add at least a first list of frequency domain samples obtained for the first baseband signal to first consecutive locations in the accumulating memory centered at a first preset location associated with the first baseband signal, and a second list of frequency domain samples obtained for the second baseband signal to second consecutive locations in the accumulating memory centered at a second preset location associated with the second baseband signal. The time domain transformer 180 is configured to apply at least an inverse discrete Fourier transform to the frequency domain samples accumulated in the accumulating memory, obtaining the aggregated baseband signal.
An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.
The invention provides an apparatus and method which allows identification of the system (202,204) which provided images (502,503) for each pixel of a touchscreen display (101) which displays merged images of arbitrary shapes supplied from a plurality of systems. It further allows routing of user inputs to the appropriate system for further processing. Colour keying may be used to superimpose one image (401) onto another (405).The invention finds particular application in the automotive field where images produced by an infotainment system may be merged with those produced by a mobile phone onto the in-vehicle display screen.
A data processing device (10) and a method for performing a round of an N point Fast Fourier Transform are described. The round comprises computing N output operands on the basis of N input operands by applying a set of N/P radix-P butterflies to the N input operands, wherein P is greater or equal two and the input operands are representable as N / (M*P)^2 input operand matrices (M1, M2), wherein M is greater or equal one, each input operand matrix is a square matrix with M*P lines and M*P columns, and each column of each input operand matrix contains the input operands for M of said butterflies, wherein the processing device comprises an input operand memory unit and an input buffer and is arranged to compute, for each of said input operand matrices, a corresponding output operand matrix by: reading the respective input operand matrix from the input operand memory unit and buffering it as a whole in the input buffer; and for each column of the respective buffered input operand matrix, computing the corresponding column of the output operand matrix by applying the respective M butterflies to the respective column.
A processor device (400) processes data samples of a radio signal in a mobile communication system. A fast flow process is executed for all samples and a batch process (150,450) is executed at intervals on a subset of the samples. The device has a processor (430,431) for executing the flow process via a local buffer memory (325), a memory interface (340) to a system memory (345), and a memory controller (420) for controlling storing of the data samples in the buffer memory. The processor establishes whether data samples in the local buffer memory are part of the subset, and if not, invalidates them after executing the flow process. The memory controller provides free memory space in the local buffer by transferring data samples which are not invalidated from the local buffer memory to the system memory, and by invalidating processed samples. Advantageously the local buffer may be relatively small, while the amount of data transferred to the system memory is limited.
A signal processing device comprising at least one control unit arranged to receive at least one pack-insert instruction, decode the received at least one pack-insert instruction, and output at least one pack-insert control signal in accordance with the received pack-insert instruction. The signal processing device further comprising at least one pack-insert component arranged to receive at least a first data block to be inserted into a sequence of data blocks to be output to at least one destination register, receive a plurality of further data blocks to be packed within the sequence of data blocks to be output to the at least one destination register, arrange the at least first data block and the plurality of further data blocks into a sequence of data blocks based at least partly on the at least one pack-insert control signal, and output the sequence of data blocks.
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
82.
SIGNAL PROCESSING DEVICE AND METHOD OF PERFORMING A BIT-EXPAND OPERATION
A signal processing device comprising at least one control unit arranged to receive at least one bit-expand instruction, decode the received at least one bit-expand instruction, and output at least one control signal in accordance with the received at least one bit-expand instruction. The signal processing device further comprising at least one execution unit component arranged to receive at least one source register value comprising at least one data bit to be expanded, extract at least one data bit from the at least one source register value located at an offset position according to the at least one control signal, expand the at least one extracted data bit into at least one multi-bit data type, and output the at least one multi-bit data type to at least one destination register.
G06F 9/06 - Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
A phase detector (32) for generating a phase difference signal (UP, DOWN) indicative of a phase difference between a first bi-level signal of frequency F1 (Fref) and a second bi-level signal of frequency F2 (Ffb) is proposed. The phase detector may comprise a first detector input (16) for receiving the first bi-level signal, a second detector input (17) for receiving the second bi-level signal, a first flip-flop (4), a second flip-flop (5), a NAND gate (7), a first overphase detection unit (41), and a second overphase detection unit (42). An output of the first overphase detection unit (41) may be connected to a direct input (D) of the second flip-flop (5) and may be arranged to output the level "1" in response to F1 ≤ F2 and the level "0" in response to F1 > F2. An output of the second overphase detection unit (42) may be connected to a direct input (D) of the first flip-flop (4) and may be arranged to output the level "1" in response to F2 ≤ F1 and the level "0" in response to F2 > F1. A sawtooth characteristic of the phase difference signal (UP, DOWN) may thus be avoided. A phase-locked loop comprising the phase detector (32) is also described.
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/107 - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
H03D 13/00 - Circuits for comparing the phase or frequency of two mutually-independent oscillations
84.
METHOD OF GENERATING A TARGET LAYOUT ON THE BASIS OF A SOURCE LAYOUT
A method of generating a target layout of an Integrated circuit Is proposed. The method comprises: providing a source layout comprising one or more source pcells, each source pcell comprising one or more shapes, each shape having a contour composed of edges; providing a set of connectivity constraints for connecting each shape of each source pcell to none, one, or more other components of the integrated circuit: providing a set of target design constraints; for each shape of each source pcell, determining a corresponding target shape, the target shape having a contour composed of edges with defined lengths; for each shape of each source pcell, inserting none, one, or more edges into the contour of the shape, or into the contour of the corresponding target shape, so as to allow for a one-to-one mapping between the edges of the shape of the source pcell and the edges of the corresponding target shape: for each edge of each shape of each source pcell, determining a corresponding edge of the corresponding target shape; for each edge of each shape of each source pcell, defining an edge length constraint for constraining the edge to have the length of the corresponding edge of the corresponding target shape, thus generating a set of edge length constraints; applying a legalization procedure to the source layout on the basis of the set of connectivity constraints, the set of target design constraints, and the set of edge length constraints.
A NETWORK RECEIVER FOR A NETWORK USING DISTRIBUTED CLOCK SYNCHRONIZATION AND A METHOD OF ADJUSTING A FREQUENCY OF AN INTERNAL CLOCK OF THE NETWORK RECEIVER
A network receiver NR, 300 for a network NW, 390 using distributed clock synchronization and a method of adjusting a frequency of an internal clock of the network receiver are provided. The network receiver NR, 300 receives from the network NW, 390 a input signal 304 and has an internal clock CLK, 306 for generating a clock signal 305. The network receiver NR, 300 further comprises a clock bit comparator CBC, 312 and an adjustment signal generator ASG, 322. The clock bit comparator CBC, 312 compares lengths of a first time period lapsed while receiving at least five consecutive bits of the signal 304 and of an internal clock time interval representing the same number of bits as a number of bits of the first time period. The adjustment signal generator ASG, 322 generates a frequency adjustment signal 332 for controlling a frequency of the internal clock CLK, 306 in dependence of a result of the comparison of the lengths to reduce a difference between the lengths.
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
86.
VOLTAGE REGULATOR, APPLICATION-SPECIFIC INTEGRATED CIRCUIT AND METHOD FOR PROVIDING A LOAD WITH A REGULATED VOLTAGE
A voltage regulator (200) for digital loads (203) combines a closed loop regulation circuit (207,210) with an open loop topology. A (closed loop) transistor (210) and a bank of (open loop) transistors (218, 220, 221 ) share the same voltage source VDD and gate control current. Each of the bank of transistors is sized to match different current load requirements and one or more may be switched in or out as appropriate when the digital load transitions from one operating mode to another. The regulator has good DC load regulation and unconditional stability regardless of output capacitance.
A network receiver NR, 300 for a network NW, 390 using distributed clock synchronization and a method of sampling at a network receiver a signal are provided. The network receiver NR, 300 receives from the network NW, 390 an input signal 304 which is sampled by a data sampler DS, 308 of the network receiver at sampling moments. Sampling moments have a relative position in time within a period of time of a single bit. The network receiver NR, 300 further comprises a clock bit comparator CBC, 312 and a sampling moment adaptor SMA, 322. The clock bit comparator CBC, 312 compares lengths of a first time period lapsed while receiving at least five consecutive bits of the signal 304 and of an internal clock time interval representing the same number of bits as a number of bits of the first time period. The sampling moment adaptor SMA, 322 adapts the relative position of the sampling moment in dependence of a result of the comparison of the lengths to reduce a difference between the lengths.
A cell monitoring apparatus (118) comprises a memory (220) to store input state data representing initial parameters for estimating parameters of a rechargeable cell and a processor operably coupled to the memory and supporting an estimator unit (212) to receive the input state data. The processor and the memory are arranged to execute code representing a linear time-invariant state transition model and a non-linear observation model are provided to model the rechargeable cell using at least a non-linear open circuit voltage, an internal resistance, a time-invariant distortion voltage across a reactive component block, and a distortion current component constituting an error of measurement of current flowing through the reactive component block. The estimator unit (212) performs extended Kalman filtering in respect of the state transition model and the observation model using the input state data in order to generate output state data. The processor is arranged to evaluate a criterion associated with at least part of the output state data and to generate a control signal in response to evaluation of the criterion.
G01R 31/36 - Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
A receiver system and method for receiver testing Abstract A receiver system (100) which may be implemented in an integrated circuit device (101) and suitable for use in automotive radar systems (201) such as collision avoidance systems, includes self test circuitry whereby a local oscillator test signal is generated by an on-board frequency multiplier (126) and mixed in a down-conversion mixer (106) with an RF test signal. The RF test signal is generated on the device (101) by up-conversion of an externally generated low-frequency test signal with the local oscillator test signal. Baseband components may also be checked using test signals of suitable frequency divided down from the local oscillator test signal by a programmable frequency divider (130). This self test arrangement obviates any need for applying externally generated RF test signals to the IC device.
Interfacing according to a common public radio interface in a base station in a mobile communication system is described. A radio controller REC may have a first version (CPRI V4), and the radio unit RE a second version (CPRI V5). Only the second version provides a data format for transferring legacy data samples for GSM. The interfacing comprises a conversion process for rate-converting the legacy data samples. First a predetermined number of the legacy data samples is converted (44) to frequency samples in a frequency domain, then the frequency samples are zero padded (45) to extend the frequency range according to a related sample rate of a 4G data format and then converted into a number of data samples of the related sample rate. The related sample rate is a multiplication of S/K times a basic frame rate of the 4G data format, S samples being allocated to K frames, K and S being integers and K being 8 or less. Advantageously large buffers for allocating a large number of legacy samples to 4G frames are avoided.
A method (100) is provided for detecting a race condition of a parallel task when accessing a shared resource (403) in a multi-core processing system. The method requires that a core (401) requires only a read access to the data set of another core (402), thereby ensuring better decoupling of the tasks. In an initialisation phase (101), initial values of global variables are assigned, in an activation phase (102), each core determines if the other core has written new values to the variables and if so, detects a race condition. Initial values are restored for each variable in a deactivation phase (103).
A microcontroller unit (MCU) having a functional state, a reset state, and one or more assertable fault sources is described. Each fault source has its own fault source assertion count and its own fault source assertion limit; the MCU is arranged to perform the following sequence of operations in a cyclic manner: if one or more of the fault sources are asserted, pass from the functional state to the reset state and increase the respective fault source assertion counts by one increment; if one or more of the fault source assertion counts exceeds the respective fault source assertion limit, disable the respective fault source; and pass from the reset state to the functional state. A method of operating an MCU is also disclosed.
A signal processing device comprising at least one timestamp generation component arranged to generate at least one local timestamp value, and to provide the at least one local timestamp value to at least one data link layer module for timestamping of data packets. The signal processing device further comprising at least one debug module arranged to receive the at least one local timestamp value and to timestamp debug information based at least partly on the at least one local timestamp value.
A memory controller (10) used to verify authenticity of data (DATA) stored in a first memory unit (15). The memory controller (10) includes a secure memory unit (20) which stores a pre-stored value (PV) representative for the authenticity of the data (DATA) to be written in the first memory unit (15). The memory controller (10) further includes a processing system (25). The processing system (25) is configured to calculate a calculated value (CV) which is representative for the data (DATA) in the first memory unit (15) after a write cycle (WC). The calculation of the calculated value (CV) is triggered by the write cycle (WC). The processing system (25) further compares the calculated value (CV) with the pre-stored value (PV) in order to verify whether the data (DATA) stored in the first memory unit (15) after the write cycle (WC) has been altered in accordance with the authenticity. By comparing the calculated value (CV) with the pre-stored value (PV) authenticity of the data (DATA) stored in the first memory unit (15) after the write cycle (WC) is verified, thus preventing the memory controller (10) to continue operating in case the data (DATA) written to the first memory unit (15) is not anymore authentic.
G06F 21/78 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
G06F 21/30 - Authentication, i.e. establishing the identity or authorisation of security principals
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
An electronic device (410) is for controlling motor drive circuits for driving a multi-phase motor (460) in a force assisted system. Each motor drive circuit (420,420',420") selectively permitting current to flow into or out of a respective phase of the multi-phase motor connected to the motor drive circuit in response to being driven by respective control signals. A motor control circuit (414) generates the control signals. A fault processor (415) detects at least one fault condition causing a fault current in a first motor drive circuit. In the event of the fault condition being detected, at least one alternative control signal is generated for at least one motor drive circuit for permitting at least one compensation current to flow for reducing a faulty force due to the fault current.
A safety system comprising: - a safety apparatus adapted to be mounted at the rear of a bicycle and comprising a processor, a motion sensor, a threat sensing device and a user alert device, all coupled to the processor, wherein the processor is adapted to: - control the driver alert device based on a threat position value and/or the threat speed value; - control the user alert device based on at least one of a motion-based value, an ambient light- based value, the threat position value and the threat speed value. It is also claimed the safety apparatus and a collaborative safety system comprising a plurality of safety systems, each being coupled to a communication device through which the processor is further adapted to control the driver alert device and/or the user alert device of the others of the plurality in response to the sensing of a threat.
A low drop-out voltage regulator (100), an integrated circuit, a sensor and a method of providing a regulated voltage are provided. The low drop-out voltage regulator (100) comprises a regulated voltage driver (106, VD) for providing the regulated voltage (Vreg) in response to a control voltage (Vc), a feedback-loop circuit (112, FC) for generating the control signal (104, Vc) such that the regulated voltage driving circuit (106, VD) provides the regulated voltage (Vreg), and a pull-up circuit (108, PC) for pulling up the regulated voltage (Vreg) to a supply voltage (Vsup) when a difference between the supply voltage (Vsup) and the control voltage (Vc) is smaller than a predetermined threshold value. In the feedback-loop circuit (112, FC) a first feedback voltage (Vf1) or a second feedback voltage (Vf2) is generated, respectively, on basis of a first ratio and a second ratio between the feedback voltage and the regulated voltage (Vreg). The second feedback voltage (Vf2) is generated instead of the first feedback voltage (Vf1) when the regulated voltage (Vreg) is pulled-up to the supply voltage (Vsup).
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
A device (100) is for securely accessing data in a memory via an addressing unit (120) which provides a memory interface (124) for interfacing to a memory (140), a core interface (121 ) for interfacing to a core processor (130) and a first and second security interface (123,122). The device comprises a security processor HSM (102) for performing at least one security operation on the data and a remapping unit MMAP (101 ). The remapping unit enables the security processor to be accessed by the core processor via the first security interface and to access the memory device via the second security interface according to a remapping structure for making accessible processed data based on memory data. Advantageously the device provides a clear view on encrypted memory data without requiring system memory for storing the clear data.
A memory including a plurality of word line drivers and two charge pumps. During an initialization mode, a first charge pump provides a supply voltage to a first set of word line drivers and a second charge pump provides a voltage to a second set of word line drivers. During a normal read operation, the second charge pump supplies a supply voltage to the word line driver used for the read operation. During a normal mode write operation, the first charge pump supplies a supply voltage to the word line driver being used for the write operation.
A voltage metering module for metering a voltage signal. The voltage metering module comprises at least one analogue to digital converter, ADC, component arranged to receive at an input thereof a voltage signal and to generate a digital signal representative of the received voltage signal. The at least one ADC component comprises at least one sampling network controllable to sample the received voltage signal for conversion to a digital signal representative of the received voltage signal, at least one compensation network operably coupled in parallel with the sampling network and controllable to sample the received voltage signal such that an input current of the compensation network at least partially compensates for a component of an input current of the sampling network. Figure 8 to accompany abstract.
G01R 31/36 - Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
patents
