A memory device according to embodiments of the present disclosure comprises a first semiconductor structure, a second semiconductor structure on the first semiconductor structure, a first bonding insulation layer between the first semiconductor structure and the second semiconductor structure, a second bonding insulation layer between the first bonding insulation layer and the second semiconductor structure, a pad structure connected to the first semiconductor structure through the first bonding insulation layer, and a contact plug connected to the pad structure, extending in a direction perpendicular to an upper surface of the pad structure to be connected to the second semiconductor structure, and having a width less than a width of the upper surface of the pad structure.
Disclosed are a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a plurality of memory cells, wherein each memory cell of said plurality of memory cells includes a memory layer; a selector layer disposed over the memory layer to select the memory layer, the selector layer including an amorphous silicon layer including a dopant containing a group-13 element and a group-15 element of a periodic table; and a barrier layer containing boron (B) disposed over or below the selector layer.
A memory device according to embodiments of the present disclosure may comprise a word line buried in a substrate and extending in a first direction, a bit line contact disposed between word lines, contacting an active area of the substrate, and having at least a portion of a side surface concave toward a center in a second direction perpendicular to the first direction, and a gate capping layer including a first capping portion contacting an upper surface of the word line and a second capping portion positioned on the first capping portion, overlapping with at least a portion of the side surface of the bit line contact in the second direction, and having a width different from a width of the first capping portion.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
4.
FERROELECTRIC MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
A ferroelectric memory device includes interlayer insulating layers and gate lines alternately stacked, a data storage layer vertically passing through the interlayer insulating layers and the gate lines and having a cylindrical shape, and a channel layer formed in an area enclosed by the data storage layer. The data storage layer includes a first ferroelectric layer abutting on the channel layer, a second ferroelectric layer abutting on the interlayer insulating layers and the gate lines, and an interface layer formed between the first and the second ferroelectric layers.
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
5.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
Disclosed is a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a plurality of first conductive lines extending in a first direction; a plurality of second conductive lines disposed over the first conductive lines and extending in a second direction intersecting with the first direction; and a plurality of memory cells respectively overlapping with intersection areas between the first conductive lines and the second conductive lines, wherein each of the memory cells includes a selector pattern and a Magnetic Tunnel Junction (MTJ) pattern which is disposed in an upper portion or a lower portion of the selector pattern, and wherein each of the second conductive lines is disposed between the MTJ patterns.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
An image processing device is disclosed. The image processing device includes an error calculator configured to calculate, for a first group of pixels, a first error of a first test phase difference based on a difference between the first test phase difference calculated based on the first group of pixels and a value corresponding to a lens position; a weight determiner communicatively coupled to the error calculator to receive the first error from the error calculator and configured to determine a first group of weights corresponding to the first group of pixels based on the first error; and a weight applicator communicatively coupled to the weight determiner to receive the first group of weights from the weight determiner and configured to apply the first group of weights to pixel data of the first group pixels.
An image sensing device for generating image data is disclosed. A clamp control circuit included in the image sensing device includes a sensing circuit configured to sense a voltage level of a pixel signal to output a sensing signal; and a clamping circuit coupled to a column line, and configured to control a voltage level of a clamp voltage control signal in response to a voltage level of the sensing signal, and control a level of a clamp voltage in response to a clamp enable signal, the clamp voltage controlled based on a voltage level of the clamp voltage control signal and provided to the column line.
Semiconductor devices, controllers, and their operating methods are disclosed. In an embodiment, a controller includes an internal command generator configured to generate overwrite operation setting information in response to a data permanent erase request to perform an overwrite operation on a data storage area corresponding to the data permanent erase request; an overwrite data generator configured to generate a plurality of unit addresses corresponding to the data storage area based on the overwrite operation setting information, and to generate a plurality of pieces of overwrite data to be written to the data storage area corresponding to the plurality of unit addresses, respectively; and a storage area controller configured to control the data storage area to store the plurality of pieces of overwrite data corresponding to the plurality of unit addresses, respectively.
Methods and systems for improving performance of a decoder in a memory device are described. An example method includes receiving a noisy codeword, generating, based on the noisy codeword, a first log likelihood ratio (LLR) sequence that uses symmetric LLR metrics, and performing, on a second LLR sequence, a decoding iteration to generate a decoded data sequence. Upon determining that a checksum of the decoded data sequence satisfies a condition, the method further includes generating, based on the decoded data sequence, an intermediate sequence, incrementing at least one of multiple counters based on comparing corresponding bits of the intermediate sequence and the noisy codeword, and updating, based on the multiple counters, the second LLR sequence, which is used to perform another decoding iteration. An example system implements the above-described method using one or more processors.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/09 - Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
10.
ASYMMETRIC HARD READ CHANNEL ESTIMATION IN MEMORY DEVICES
Methods and systems for improving performance of a decoder in a memory device are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, and determining, based on the noisy codeword, a ones count and a checksum. The method further includes determining, based on the ones count and the checksum, an asymmetric ratio, a first log-likelihood ratio (LLR) value indicative of a bit being zero-valued, and a second LLR value indicative of the bit being one-valued. Then, the method includes generating an LLR sequence by applying the first LLR value and the second LLR value to each element of the noisy codeword, and performing a hard decoding operation on the LLR sequence to generate a candidate version of the transmitted codeword. An example system implements the above-described method using one or more processors.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/39 - Sequence estimation, i.e using statistical methods for the reconstruction of the original codes
A reset request is set in advance to be transmitted to a host device through a hardware configuration of a controller when an unrecoverable error occurs in a storage device. Therefore, it is possible to provide a storage device capable of quickly and stably receiving a hardware reset signal from a host device and performing a fast recovery operation, and an operating method thereof.
A memory device according to embodiments of the present disclosure includes a stack structure including conductive layers alternately stacked with interlayer insulating layers in a third direction, and an anti-bending structure overlapping the stack structure in a third direction. The anti-bending structure includes an auxiliary layer and impurity regions within the auxiliary layer and including an impurity injected into the auxiliary layer.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
13.
MEMORY APPARATUS AND OPERATION METHOD OF MEMORY APPARATUS
A memory apparatus includes: a cell array comprising a plurality of memory cells, and an access circuit that performs a read operation on a memory cell among the plurality of memory cells. Such an access circuit determines data stored in the memory cell and selectively applies a reverse pulse to the memory cell based on the determined data of the memory cell.
A memory device includes a first core die including first to N-th channels and a second core die including (N+1)-th to 2N-th channels. A channel among the first to N-th channels of the first core die and a channel among the (N+1)-th to 2N-th channels of the second core die input and output data by receiving a write command in common and a read command in common.
A ramp generator, capable of generating a ramp signal from an image sensor, includes a current controller, a bias voltage generator, and a ramp signal generator. The current controller adjusts a value of a reference current applied to a first node based on a plurality of control signals, and it adjusts a value of a current applied to a second node based on some control signals from among the plurality of control signals. The bias voltage generator generates a bias voltage based on a current mirrored according to the first node and the second node. The ramp signal generator generates a ramp signal based on the bias voltage.
A semiconductor device, and more particularly, a storage device includes a memory device including a plurality of memory cells corresponding to a plurality of threshold voltage distributions and capable of improving the success rate of a read operation; and a memory controller determining an optimal read voltage, which is used for a read operation of target memory cells corresponding to a first threshold voltage distribution among the plurality of threshold voltage distributions, based on an average threshold voltage of the first threshold voltage distribution, a standard deviation of the first threshold voltage distribution, and a number of error-correctable bits during an error correction operation of data read from the target memory cells.
An image signal processor includes a defective pixel detector configured to detect a defective pixel from among similar characteristic pixels, the similar characteristic pixels representing pixels having a characteristic same as a characteristic of a target pixel included in a target kernel, a pattern determiner configured to determine a pattern of the target kernel based on pixel data of pixels included in the target kernel when the defective pixel is present, and a pixel interpolator configured to interpolate, when the defective pixel is positioned in a texture area of the pattern, the target pixel based on pixel data of pixels positioned in the texture area among dissimilar characteristic pixels and pixel data of pixels positioned in the texture area among the similar characteristic pixels, the dissimilar characteristic pixels representing pixels having a characteristic different from the characteristic of the target pixel.
G06V 10/74 - Image or video pattern matchingProximity measures in feature spaces
H04N 25/683 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to defects by defect estimation performed on the scene signal, e.g. real time or on the fly detection
18.
MEMORY APPARATUS AND OPERATION METHOD OF MEMORY APPARATUS
A memory apparatus includes a first switch and a second switch configured to electrically connect or disconnect a first voltage line and a bit line in response to a first driving signal and a second driving signal; a third switch and a fourth switch configured to electrically connect or disconnect a second voltage line and a word line in response to a third driving signal and a fourth driving signal; a memory cell electrically connected between the bit line and the word line; and a signal level control circuit configured to differentially control turn-on degrees of the third and fourth switches when a forward enable signal is enabled, and differentially control turn-on degrees of the first and second switches when a reverse enable signal is enabled.
G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
19.
MEMORY APPARATUS, MEMORY SYSTEM, AND OPERATION METHOD OF MEMORY SYSTEM
A memory system includes: a memory apparatus including a plurality of memory cells; and a controller that controls a curing operation to be performed on a first memory cell among the plurality of memory cells when the number of access operations performed on the first memory cell exceeds a preset number of times.
A semiconductor memory device for storing data is disclosed. The semiconductor memory device includes at least one cell region including a plurality of memory cells connected between a plurality of wordlines and a plurality of bitlines, wherein a precharge operation is performed on the plurality of memory cells during a precharge operation period; at least one source-voltage supply circuit configured to supply a second voltage having a lower level than a first voltage based on a second voltage activation signal; at least one wordline driving circuit configured to operate based on the second voltage, and drive the plurality of wordlines according to a main wordline driving signal; and a defect detection circuit configured to detect a level change of the second voltage during the precharge operation period, and output a defect flag signal indicating whether the at least one wordline driving circuit is defective.
An image signal processor for performing image conversion is disclosed. The image signal processor includes a kernel generator configured to generate a target kernel including a pair of adjacent target pixels; a texture determiner configured to determine whether the target kernel corresponds to a flat region or a dark region by analyzing a texture of the target kernel; a threshold setting circuit configured to determine a threshold based on a result of the determination of the texture determiner; a defective pixel determiner configured to determine, based on pixel data of reference pixels having a same attribute as the pair of target pixels, whether each of the target pixels is defective pixel; and a defective pixel corrector configured to correct one of the pair of target pixels when the target pixels are determined as defective pixels.
H04N 25/683 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to defects by defect estimation performed on the scene signal, e.g. real time or on the fly detection
A storage device receives a write command requesting to write write data from a host, determines a first time point at which a memory starts performing a target operation different from an operation of storing the write data, and, after determining the first time point, suspends transmission of a ready-to-transfer request for the write command from a second time point as a time point earlier than the first time point.
A memory device includes a contact, and a plurality of support structures disposed around the contact, wherein each of the support structures is formed utilizing a plurality of overlapping holes. The support structures include an insulating layer disposed within the overlapping holes. The support structures are formed by expanding and overlapping a plurality of first openings.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
A semiconductor system including a control device including a first area and a second area. The first area includes an internal interface area disposed in a first direction and the second area comprising an internal input and output line disposed in a second direction. The control device includes a memory device stacked on the second area and configured to input and output data. The internal interface area intersecting with the internal input and output line. The control device and the memory device are configured to input and output the data to and from the internal interface area through the internal input and output line.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
A memory device includes a cell array and control circuitry. The cell array includes a plurality of cell strings coupled to a word line and a drain select line. The control circuitry is configured to apply a program voltage to the word line during a program time period, and control the drain select line to avoid programming data in plural memory cells included in the plurality of cell strings during a partial time length in the program time period.
Systems and methods for improving performance of a memory device, which includes a bit-flipping (BF) decoder, are described. The disclosed embodiments improve the performance of the memory device by selecting parameters for the BF decoder that are optimized for current conditions of the memory device An example method includes performing a first number of decoding iterations on a received codeword, tracking the number of bit errors during the decoding, and determining, based thereon, an asymmetric ratio associated with the codeword. The method further includes determining, based on the asymmetric ratio and a checksum associated with the codeword, a current set of parameters for configuring the BF decoder, and performing a second number of decoding iterations on the codeword to generate data that was encoded. An example system includes the BF decoder and a memory controller that are configured to perform the above-described method.
A semiconductor memory device and a method of operating the semiconductor memory device are provided. The semiconductor memory device includes a memory cell array including a plurality of memory blocks; a peripheral circuit performing a program operation or a read operation on a selected memory block from among the plurality of memory blocks; a temperature measurement circuit performing a temperature measurement operation to measure a first temperature during the program operation and a second temperature during the read operation; and a block read counter deriving a read count increment of the selected memory block based on the first temperature and the second temperature and updating a read count value of the selected memory block based on the read count value and the derived read count increment.
A semiconductor device includes a first conductive line including an upper portion of a carbon-based thin layer; a variable resistance layer disposed over the first conductive line; a selector layer disposed over the variable resistance layer, with a carbon-based thin layer disposed thereon; and a second conductive line disposed over the selector layer.
A system includes a central processing unit; a first processing device; and a second processing device, and the first processing device (i) reads original data from the first memory, (ii) reads pre-processing information from the first base address register, (iii) executes a pre-processing operation on the original data using the pre-processing information to generate result data, and (iv) transmits the result data to second processing device without detouring via an external processor.
09 - Scientific and electric apparatus and instruments
Goods & Services
(Based on 44(e)) Data processing accelerators; Data processing accelerators, namely memories for artificial intelligence and machine learning; Data processing accelerators, namely, memories for data processing equipment for use with artificial intelligence and machine learning; Data processing accelerators, namely, memories for data processing equipment for use with artificial intelligence and machine learning, for wholesale market (Based on Intent to Use) Artificial intelligence accelerators for data processing, namely, memories for data processing equipment for use with artificial intelligence and machine learning; Artificial intelligence inference accelerators, namely, memories for data processing equipment for use with artificial intelligence and machine learning
31.
STACKED PNM DEVICE, AND CDC TRAINING METHOD AND NORMAL OPERATION METHOD OF STACKED PNM DEVICE
SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION (Republic of Korea)
Inventor
Yoon, Byung Kuk
Song, Choung Ki
Kim, Jae Joon
Han, Sang Hyeok
Abstract
A stacked Processing Near Memory (PNM) device, in order to achieve smooth clock domain crossing (CDC) between a stacked memory chip and a logic chip and to minimize a consumption of die area, can train a delay time of an asynchronous path for each bank of the memory chip and optimally control an output timing of received data for each bank in each corresponding FIFO in consideration of the delay time of each bank as a result of the training. The stacked PNM device may perform a CDC training method and a normal operation method.
A duty cycle monitoring circuit includes a duty cycle reduction circuit, a duty cycle detection circuit, and a latch circuit. The duty cycle reduction circuit reduces duty cycles of a first clock signal and a second clock signal to generate a first input signal and a second input signal. The duty cycle detection circuit detects duty cycles of the first input signal and a second input signal to generate a first output signal and a second output signal. The latch circuit generates a duty detection signal based on the first output signal and the second output signal.
SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION (Republic of Korea)
Inventor
Yoon, Byung Kuk
Song, Choung Ki
Kim, Jae Joon
Han, Sang Hyeok
Abstract
A hybrid bonding structure includes a local transmission line and a global transmission line each connecting a memory chip to a logic chip. During a read operation, data is directly transmitted from the memory chip to the logic chip through the local transmission line. During a write operation, data is transmitted from the logic chip to the memory chip through the global transmission line. A control signal is transmitted from the logic chip to the memory chip through the global transmission line. Accordingly, a plurality of banks implemented in the memory chip can be simultaneously controlled and a plurality of Processor Element s (Pes) implemented in the logic chip may operate as a single core. The hybrid bonding structure may be used to implement a machine learning accelerator.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
34.
COMPARATOR AND SEMICONDUCTOR APPARATUS USING THE SAME
A comparator includes an amplification circuit and a latch circuit. The amplification circuit generates a first amplification signal and a second amplification signal based on a clock signal, an input signal, and a reference voltage. The latch circuit generates a first output signal and a second output signal based on the clock signal, the first amplified signal, and the second amplified signal.
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
35.
SEMICONDUCTOR SYSTEM FOR PERFORMING SOFT-LANDING OPERATION
Disclosed is a semiconductor system for performing a soft-landing operation that sequentially reduces the level of a word line. A semiconductor device includes a first driving element configured to drive a word line to a voltage level of a driving signal based on a word line selection signal, a second driving element configured to drive the word line based on the word line selection signal, and a third driving element configured to drive the word line based on a discharge signal.
A data storage device includes a volatile memory and a nonvolatile memory, and a caching function is provided by storing a cache line including compressed user data and tag data in the volatile memory. Therefore, increases in the number of accesses and addition of a storage region using the volatile memory for caching functions are prevented, resulting in a data storage device with improved caching operation performance.
A storage device comprising a memory device including a plurality of storage spaces respectively corresponding to a plurality of physical addresses, and a controller configured to receive at least one of K logical addresses for a write operation, store the at least one of K logical addresses in an buffer, search for and select, from among the at least one of K logical addresses stored in the buffer, a target logical address of a location including an N-bit value, obtained by applying a preset conversion rule to an N-bit value included in the location corresponding to a target physical address, and generate, when the target logical address is searched for, compressed mapping information by mapping, to the target logical address, a target compressed physical address generated by removing, from the target physical address, the N-bit value in the location corresponding to the target physical address.
An operating method of a memory device, in a program operation, applies a first program pass voltage to program non-selected word lines of first word lines and second word lines, the first and second word lines coupled to first memory cells and second memory cells of a string, respectively, and applies a second program pass voltage to a first intermediate dummy word line coupled to a first intermediate dummy memory cell, among the first intermediate dummy memory cell and a second intermediate dummy memory cell coupled between the first memory cells and the second memory cells in the string.
A semiconductor memory device and a method of operating the semiconductor memory device are provided. The semiconductor memory device includes a memory cell array including a plurality of memory blocks, a peripheral circuit configured to perform a program operation, a read operation, or an erase operation on the plurality of memory blocks, and a control logic configured to set a level of a drain select line operating voltage or a level of a source select line operating voltage corresponding to each memory block based on a number of erase-write (EW) cycles or a number of read operations for each memory block, and control the peripheral circuit to perform the program operation, the read operation, or the erase operation based on the set drain select line operating voltage or the set source select line operating voltage.
A semiconductor device may comprise a first electrode, a second electrode on the first electrode, a resistance change layer between the first electrode and the second electrode, an oxygen reservoir layer disposed between the resistance change layer and the second electrode and including yttria-stabilized zirconia (YSZ), and a porous material layer, contacting the oxygen reservoir layer and including a pore, and positioned on the resistance change layer.
A method for fabricating an electronic device includes forming a material layer suitable for forming an etched layer over a first substrate; forming a hard mask layer over a second substrate; bonding the first substrate and the second substrate with each other in such a manner that the material layer and the hard mask layer face each other; removing the second substrate from an upper portion of the hard mask layer; and forming an etched layer pattern by performing an etching process with the hard mask layer used as an etching barrier.
A fuse circuit of a semiconductor memory device includes: a plurality of fuse blocks. Each of the fuse blocks includes a first fuse set and a second fuse set, and is configured to output, in response to an access column address, a fuse hit signal indicating whether the access column address is programmed. The second fuse set is of a different type from the first fuse set.
The present disclosure provides a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a channel layer including a plurality of channel pillars that pass through a gate stack and a channel connection portion that extends from each of the plurality of channel pillars to overlap with the gate stack, a memory layer including a vertical portion between the plurality of channel pillars and the gate stack and a horizontal portion that extends from the vertical portion between the gate stack and the channel connection portion, and a doped semiconductor layer contacting the channel connection portion and overlapping with the channel connection portion.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Techniques for scan testing integrated circuits that process sensitive data while protecting such data from unauthorized access. A second scan register is provided in parallel to a primary scan register, the second scan register functionally replicating the primary scan register. The primary and replica scan registers are scan loadable (i.e., can be loaded with scan data) but are non-scannable (i.e., not scan readable). Instead of data captured by the first and second scan registers being scanned out for external observation, contents of the first and second scan registers are compared, and the comparison result is captured by a third scan register that operates as a regular scannable (or scan readable) register. The values of the third scan register scanned out for observation reflect the test results, and data in the first and second scan registers are not scanned out and cannot be observed.
A memory device includes a plurality of stacked slice chips. The plurality of slice chips are electrically connected to each other through a plurality of through-vias, and when one of the plurality of slice chips is chip-killed, the operation of the plurality of slice chips is determined by correcting a slice ID in each of the plurality of slice chips. In addition, among the slice chips that are not chip-killed among the plurality of slice chips, a slice chip at a lowest layer and a slice chip at a highest layer are determined to operate.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
An image sensing device is provided to include a substrate in which a first pixel region, a second pixel region, and a non-pixel region between the first and second pixel regions are defined; an insulating layer disposed on the substrate; a first grid structure disposed on the insulating layer and in the non-pixel region; a second grid structure disposed on a lateral surface of the first grid structure and including an organic material; and a first color filter disposed over the insulating layer of the first pixel region and configured to transmit light in a first color and absorb light in other colors, and a second color filter disposed over the insulating layer of the second pixel region and configured to transmit light in a second color different from the first color and absorb light in the first color and other colors.
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
A semiconductor device comprising a gate structure disposed on a substrate, a first spacer disposed on the substrate and disposed on two opposite sides of the gate structure, a second spacer disposed on the substrate, outside the first spacer, a semiconductor layer disposed on the substrate and contacting an outer surface of the second spacer, and a third spacer covering an upper surface of the gate structure, a side surface of the second spacer, and an upper surface of the semiconductor layer.
According to embodiments of the present disclosure, a memory device may include a substrate including a cell area where memory cells are disposed and an extended area outside the cell area; a first gate electrode layer buried in the substrate and extending from the cell area to the extended area in a set direction, an upper surface of the first gate electrode layer in the cell area being located at substantially the same level as the upper surface of the first gate electrode layer in the extended area; a second gate electrode layer disposed on the first gate electrode layer, and extending from the cell area to the extended area in the set direction; and a word line contact located in the extended area, and extending into the second gate electrode layer in a vertical direction, vertical to the set direction.
A semiconductor device may include: channel pillars arranged in a first direction and a second direction intersecting the first direction and having a first interval in the first direction and a second interval in the second direction, the first interval being smaller than the second interval; a select line surrounding the channel pillars arranged in the first direction and extending in the first direction; word lines stacked above the select line; and local bit lines penetrating through the word lines and connected to the channel pillars.
A memory device and a method of operating the memory device are provided. The memory device may include a plurality of memory blocks, an operating voltage generating circuit configured to generate and apply an operating voltage to global word lines, a plurality of pass transistor units respectively corresponding to the plurality of memory blocks, respectively configured to couple local word lines of the plurality of memory blocks to the global word lines, and a well bias applying circuit configured to apply a well bias having a negative level to a well of a plurality of pass transistors included in each of the plurality of pass transistor units.
A method of testing a memory device includes testing for a physical defect of memory devices formed on a wafer, determining a region of the wafer where the memory devices are located when a test result for the physical defect is a pass, inputting first operation conditions to memory devices located in a first region and inputting second operation conditions to memory devices located in a second region, and simultaneously testing the memory devices input with the first operation conditions and the memory devices input with the second conditions under various conditions.
A semiconductor memory device includes a memory block including at least one programmed page and at least one erased page; and a control circuit configured to generate characteristic information for the memory block. The characteristic information includes information related to reliability of the memory block. The semiconductor memory device also includes a peripheral circuit configured to control an operation of the memory block based on the characteristic information. In another example, a semiconductor memory device includes: a memory block including at least one programmed page and at least one erased page; a control circuit configured to generate a block closed ratio (BCR) indicating a ratio of the at least one programmed page in the memory block to a total number of pages in the memory block; and a peripheral circuit configured to control an operation of the memory block based on the block closed ratio (BCR).
A semiconductor memory device includes a first channel structure which is adjacent to an insulating structure and penetrates a plurality of conductive layers, a second channel structure which is spaced apart from the insulating structure and penetrates the plurality of conductive layers, a first impurity region included in an end portion of the first channel structure, and a second impurity region included in an end portion of the second channel structure. A doping concentration of an impurity in the first impurity region is different from a doping concentration of an impurity in the second impurity region.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
Techniques to boost reliability of a storage device may include performing an in-memory garbage collection operation to transfer data from a source memory block to a target memory block inside a memory device without using a memory controller. The in-memory garbage collection operation may cause soft errors in the source memory block to be converted into hard errors in the target memory block. In response to a test read of the target memory block, it may be determined that the target memory block has a failed bit count (FBC) greater than a FBC threshold by taking into account a degradation of a soft error decoder correction capability caused by the hard errors from the in-memory garbage collection operation. An external garbage collection operation may be performed on the target memory block to reclaim the target memory block.
A method of forming an SOI substrate including a hydrogen thermal treatment performed on a pretreated sacrificial wafer, under high temperature. A stopper layer and a semiconductor layer may be sequentially formed on a first surface of the sacrificial wafer on which the hydrogen (H2) thermal treatment was performed. The stopper layer and the semiconductor layer may be formed by an epitaxial growth process using a mixed precursor including a monosilane (MS) source and a dichlorosilane (DCS) source.
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
A memory includes a bit line, first to Nth cell groups (N≥2), each with multiple memory cells connected to the bit line, and first to Nth current supply circuits supplying currents to the bit line. The first current supply circuit's current is determined by sensing the bit line current when input voltages are supplied to the first cell group. A kth current supply circuit's current (2≤k≤N) is determined by sensing the bit line current when input voltages are supplied to the first to kth cell groups, with the first to k−1th current supply circuits activated.
G11C 7/16 - Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
A manufacturing method of a semiconductor package including forming a through-electrode in a substrate including a first surface and a second surface opposite to each other, forming a front conductive bump on the first surface of the substrate, reflowing the front conductive bump, and planarizing an upper portion of the front conductive bump after reflowing the front conductive bump.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
58.
MEMORY SYSTEM FOR PERFORMING POST PACKAGE REPAIR AND AN OPERATION METHOD THEREOF
A memory system includes at least one memory device and a controller. The controller includes an input path for transferring a data input/output (I/O) request input from an external device to the at least one memory device and an output path for transferring a response corresponding to the data I/O request. The controller is configured to selectively couple the output path to the input path for a post package repair (PPR) operation.
A storage device comprises a memory device with a storage region, a compression operation unit that generates compression data by performing a first compression operation on write data, and a control operation unit that divides the storage region into multiple storage spaces, selects N selection storage spaces, controls the compression operation unit, and stores first and second data in (N-K+1) selection storage spaces when the sum of the size of the first data, which is a compressed portion of the write data at a first timing, and the size of the second data, which is an uncompressed portion of the write data at the first timing, is equal to or smaller than a storage size corresponding to (N-K+1) selection storage spaces at the first timing when the execution rate of the first compression operation reaches a first execution rate.
A memory device includes a substrate including first and second connection regions arranged in a first horizontal direction; an electrode structure including word lines vertically stacked on the substrate and dummy word lines vertically stacked on the word lines; drain select lines disposed in a drain select line layer on the electrode structure, and extending parallel to each other in the first horizontal direction; drain contacts connected to the drain select lines, respectively, in the first connection region; and dummy contacts extending vertically through the drain select lines in the second connection region, and connected to the dummy word lines, respectively, The dummy contacts are disposed in a plurality of rows, arranged in a second horizontal direction that is perpendicular to the first horizontal direction, and dummy contacts connected in common to one of the dummy word lines are disposed in a single row.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
A semiconductor package includes a wiring structure, a first bump, and a semiconductor chip. The wiring structure includes a first electrode and has a first surface and a second surface that faces away from the first surface. The second surface of the wiring structure includes a recessed area that overlaps the first electrode. The first bump includes a first conductive pillar on the first surface of the wiring structure and a first solder layer on the first conductive pillar. The first bump contacts the first electrode. The first electrode includes a first section and a second section. The first section of the first electrode is disposed between the first surface of the wiring structure and the second surface of the wiring structure. The second section of the first electrode has a lower surface that is included in the first surface of the wiring structure. The horizontal width of the first conductive pillar is less than the horizontal width of the first electrode. A semiconductor chip is disposed above the second surface of the wiring structure.
Embodiments of the present disclosure provide a chip stack package including a first semiconductor chip having a front bump on a first surface, a second semiconductor chip stacked on a second surface of the first semiconductor chip opposite the first surface, a carrier bump bonded to the front bump, a mold member surrounding the first semiconductor chip, the second semiconductor chip, and the carrier bump, and an external connection bump disposed on the carrier bump.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
63.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
The semiconductor device includes a first channel structure; a first air layer surrounding a side surface of the first channel structure; a first bitline contacting the side surface of the first channel structure; a first wordline contacting a lower portion of the first channel structure; a storage node having one end contacting an upper portion of the first channel structure; a second channel structure contacting an upper portion of the storage node; a second air layer surrounding a side surface of the second channel structure; a second bitline contacting the side surface of the second channel structure; and a second wordline contacting an upper portion of the second channel structure. The first bitline extends in a direction perpendicular to a direction in which the first channel structure extends. The second wordline extends in a direction perpendicular to a direction in which the second channel structure extends.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
A chip stack package includes a first semiconductor chip having a first test bump on a first surface and a second semiconductor chip stacked on a second surface of the first semiconductor chip opposite the first surface. The chip stack package also includes a second test bump bonded to the first test bump. The chip stack package further includes a mold member surrounding the first semiconductor chip, the second semiconductor chip, and the second test bump. The chip stack package additionally includes a test pad disposed on the mold member and connected to the second test bump.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
65.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a first bitline extending in a first direction, a first wordline extending in a second direction crossing the first direction, a first active region contacting the first bitline, a back-gate extending parallel to the first wordline, and a storage transistor contacting the first active region. The first active region is disposed between the first wordline and the back-gate, and includes a vertical portion extending in a third direction crossing the first and second directions and a horizontal portion that contacts one end of the vertical portion and the first bitline.
A semiconductor device includes a pull-up source voltage generation circuit configured to drive a pull-up voltage to a normal voltage during a normal period and to drive the pull-source voltage to a test voltage during a test period. The semiconductor device also includes a pull-down source voltage generation circuit configured to drive a pull-down voltage to a ground voltage during the normal period and to drive the pull-down source voltage to a bit line pre-charge voltage during the test period. The semiconductor device further includes an equalization control signal driver configured to receive the pull-up source voltage and the pull-down source voltage to drive an equalization control signal for equalizing voltage levels of an internal bit line pair of a bit line sense amplifier.
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
Semiconductor devices and methods for fabricating semiconductor devices are disclosed. In some implementations, a semiconductor device may include a first electrode layer; a second electrode layer disposed over the first electrode layer and spaced apart from the first electrode layer; and a selector layer disposed between the first electrode layer and the second electrode layer and including an insulating material that contains at least a dopant and carbon, wherein a carbon concentration at a first portion of the selector layer adjacent to the second electrode layer is higher than a carbon concentration at a second portion of the selector layer adjacent to the first electrode layer.
A memory system and a data processing system including the memory system may manage a plurality of memory devices. For example, the data processing system may categorize and analyze error information from the memory devices, acquire characteristic data from the memory devices and set operation modes of the memory devices based on the characteristic data, allocate the memory devices to a host workload, detect a defective memory device among the memory devices and efficiently recover the defective memory device.
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
G06F 11/16 - Error detection or correction of the data by redundancy in hardware
A semiconductor device includes a peripheral circuit structure, a memory cell array disposed over the peripheral circuit structure, and a bonding structure disposed between the peripheral circuit structure and the memory cell array. The memory cell array includes a first stack structure including first interlayer insulating layers and first conductive patterns disposed alternately with each other in a first direction over the bonding structure, second conductive patterns separated from each other in a horizontal direction between the first stack structure and the bonding structure, each of the second conductive patterns comprising electrode portions spaced apart from in the first direction and a connection portion extending in the first direction to couple the electrode portions, a vertical channel passing through the first stack structure and the electrode portions of each of the second conductive patterns, and a separation insulating layer disposed between the second conductive patterns.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
A method and memory system for decoding data read from a storage of a memory system. The method reads the data stored in the storage of the memory system with read voltages spanning a range of voltage threshold distributions and including voltages within each of the voltage threshold distributions. The method further divides the range into bins spanning the range; generates initial log likelihood ratio values for each bin and generating a bin sequence bn of bin positions; and adjusts values of the initial log likelihood ratio values for each bin to provide adjusted log likelihood ratio values for each bin prior to a final decoding of the data read from the storage.
A memory apparatus includes an instruction memory and a plurality of micro control units. The instruction memory outputs a plurality of instruction codes at a predetermined time interval in accordance with a plurality of address signals and a plurality of divided clock signals. The plurality of micro control units are coupled to each of a plurality of memory regions, provide each of the plurality of address signals to the instruction memory in accordance with each of the plurality of divided clock signals, and perform operations in accordance with corresponding instruction codes among the plurality of instruction codes.
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
72.
STORAGE DEVICE CONTROLLING INPUT ORDER OF COMMANDS AND METHOD FOR OPERATING THE STORAGE DEVICE
A storage device includes a memory and a controller. The memory includes a first terminal configured to receive commands, a second terminal configured to receive or output data, and a plurality of memory units configured to store data. The controller transmits a read command for target data including a plurality of sub data units to the first terminal, transmits, to the first terminal, a start command instructing initiation of an operation to output one or more of the plurality of sub data units to the second terminal, and transmits, to the first terminal, a first data output command instructing output of a first sub data unit among the plurality of sub data units to the second terminal.
A memory device and a method of manufacturing the memory device are described. The memory device includes a source structure formed over a substrate, a gate stack formed over the source structure and including conductive layers alternately stacked with insulating layers, and a channel structure extending through the gate stack in a first direction and extending into the source structure. The channel structure includes a first channel layer extending in the first direction and located in the gate stack and the source structure, a memory layer surrounding a sidewall of the first channel layer and located between the gate stack and the first channel layer, and a second channel layer located between the source structure and the first channel layer and surrounding the sidewall of the first channel layer that extends into the source structure.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A memory device including a first substrate including a cell region and a peripheral region disposed around the cell region; a memory cell array disposed in the cell region of the first substrate; a second substrate disposed on the memory cell array; peripheral transistors disposed on the second substrate and connected to the memory cell array; a first insulating layer disposed in a trench that is located in the peripheral region of the first substrate, and including high density plasma oxide; and a second insulating layer on the first insulating layer.
G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
75.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device and a method for making the semiconductor device, the semiconductor device comprising a plurality of memory cells, each of the memory cells including: a first electrode layer; a memory layer; and a selector layer suitable for selecting the memory layer that is formed in an upper or lower portion of the memory layer and over the first electrode layer, wherein the selector layer includes a dielectric material layer that is doped with a first dopant, and wherein a lower portion region in the dielectric material layer of the selector layer which is adjacent to the first electrode layer has a lower dopant concentration than an upper portion region of the dielectric material layer.
Image sensing devices are disclosed. In an embodiment, an image sensing device includes a first diode and a second diode configured to adjust a total storage capacity of a floating diffusion region; and a conversion gain transistor configured to selectively connect the first diode to the floating diffusion region, allowing the image sensing device to achieve a desired total storage capacity and a corresponding conversion gain.
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
H04N 25/773 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD]
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
Embodiments of the present disclosure may provide a processing unit and a computing system that divide computations according to the types of computations performed during an inference computation using an artificial intelligence model and perform the divided computations by separate processing units, thereby being capable of reducing an overall time required for the inference computation and improving the performance of the inference computation.
An image processing device includes a target pixel defect determiner configured to determine whether a target pixel within a kernel is a defective pixel; a cluster defective pixel detector configured to detect at least one cluster defective pixel that serves as the defective pixel sharing a floating diffusion node with the target pixel, when the target pixel is determined to be the defective pixel; an offset correction determiner configured to determine whether to correct the target pixel and the at least one cluster defective pixel based on an offset value of the target pixel; and a defective pixel corrector configured to correct the target pixel and the at least one cluster defective pixel based on a determination to correct the target pixel and the at least one cluster defective pixel.
A method of manufacturing a semiconductor package of stacked semiconductor chips includes forming a reverse wire bond by bonding one end of a reverse wire to a chip pad of the second-highest semiconductor chip of the stacked semiconductor chips and connecting the other end of the reverse wire to a conductive bump on a chip pad of the uppermost semiconductor chip of the stacked semiconductor chips. The method also includes molding the stacked semiconductor chips with the reverse wire bond using a mold layer. The method further includes processing the mold layer to expose the conductive bump and the other end of the reverse wire in the reverse wire bond through an upper surface of the mold layer.
A storage device may include: a memory device for extracting bits having a first logic value among bits included in data received from outside the memory device, generating a plurality of compressed data chunks including the bits comprising the first logic value and position information representing positions of the bits having the first logic value in the data, and outputting the plurality of compressed data chunks in response to a data output command; and a memory controller for receiving the plurality of compressed data chunks from the memory device, and recovering the data, based on the bits having the first logic value, which are included in the plurality of compressed data, and the position information.
A semiconductor device includes: a substrate including a trench; a bottom gate electrode suitable for gap-filling a lower portion of the trench and including a silicon-doped first metal nitride; and a top gate electrode formed over the bottom gate electrode, and including a silicon-doped second metal nitride having a higher silicon content than a silicon content of the bottom gate electrode and having a higher ratio of a metal content to a nitrogen content than a ratio of a metal content to a nitrogen content of the bottom gate electrode.
A method for decoding data read from a memory and associated memory system. The method receives the data read from the memory as a read sequence of bits ri; decodes the read sequence using an irregular low density parity check (LDPC) matrix to produce a decoded sequence of bits di; detects with a deep neural network (DNN) convergence of t bits of the decoded sequence of bits di from a high degree column zone of the LDPC matrix; and establishes channel log likelihood ratios (LLRs) by modifying initial LLRs to the LLRs estimated by channel estimator using the t decoded bits in the high degree column zone of the LDPC matrix once the convergence is detected by the DNN.
In a method of forming an SOI substrate, a stopper layer having an etch selectivity different from a first wafer may be formed on the first wafer having a first surface and a second surface facing each other. A semiconductor layer having an etch selectivity different from the stopper layer may be formed on the stopper layer. A buried insulation layer may be formed on the semiconductor layer. The buried insulation layer may be formed by applying a compressive stress condition, to have a height of a central portion of the buried insulation layer being formed higher than a height of an edge portion of the buried insulation layer.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
84.
ERROR CORRECTION CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING SAME
An error correction circuit includes an error processing circuit, a poison processing circuit, and a data pattern conversion circuit. The error processing circuit receives data, generates delayed data, a parity signal, and syndrome information, and outputs error correction data generated by correcting errors in the data according to the syndrome information. The poison processing circuit outputs one of a write poison flag and a read poison flag as a poison pattern control signal in accordance with a write command. The data pattern conversion circuit converts the delayed data and the parity signal into a poison pattern according to the poison pattern control signal and outputs the poison pattern.
A memory device including a first semiconductor layer including a slim area, and a first cell area and a second cell area respectively arranged on both sides of the slim area in a first horizontal direction, and a second semiconductor layer, which vertically overlaps with the first semiconductor layer, and includes a pass transistor circuit connected to the first cell area and the second cell area through a word line, a block selection circuit for providing a block selection signal to the pass transistor circuit, and a voltage switch circuit for transmitting an operating voltage to the pass transistor circuit, wherein the voltage switch circuit may include a voltage switch region disposed in an under-slim region of the second semiconductor layer, wherein the under-slim region vertically overlaps with the slim area, and at least a part of the block selection circuit may be disposed in the under-slim region.
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/08 - Address circuitsDecodersWord-line control circuits
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
86.
MEMORY DEVICE AND MANUFACTURING METHOD OF THE MEMORY DEVICE
A memory device according to an embodiment of the present disclosure includes a stack structure including conductive layers and interlayer insulating layers, a channel layer penetrating the stack structure, a channel back gate layer surrounded by the channel layer, and a liner layer insulating the channel layer and the channel back gate layer from each other, wherein the channel layer is included in a first current path and the channel back gate layer is included in a second current path.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
87.
STORAGE DEVICE AND METHOD FOR OPERATING STORAGE DEVICE
A data storage device may include a memory device and a controller. The memory device may include a compression memory area where data is stored in a compressed state and a non-compression memory area where data is stored in a non-compressed state. The controller may: receive, from a host, a speculative memory read command indicating that there is a possibility that target data corresponding to a target logical address is to be read; search for, in response to receiving the speculative memory read command, where the target data is stored in the memory device, either in the compression memory area or the non-compression memory area; and determine whether to store the target data in a cache configured to store data read from the memory, based on where the target data is stored in the memory device, either in the compression memory area and the non-compression memory area.
A stacked memory device includes a first die including a first region and a second region, the first die being on a plane defined by a first direction and a second direction, and a die group stacked on the second region. A first layer is disposed beneath the first region, the first layer controlling transmission of signals between the die group and a processor through a plurality of channels, and an empty space is provided over on the first region.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
A stacked memory system includes a substrate including a first region and a second region, a base die and a core die group stacked in the first region, an integrated chip stacked on the core die group, and a connection die group connected between the integrated chip and the substrate in the second region.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/367 - Cooling facilitated by shape of device
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
An image sensing device includes a pulse signal generator that generates a first pulse signal having a first pulse width and a second pulse signal having a second pulse width; a laser pulse transmitter that transmits a first laser pulse based on the first pulse signal and a second laser pulse based on the second pulse signal; a reflected pulse receiver that receives a first reflected pulse when the first laser pulse is reflected from an object and a second reflected pulse when the second laser pulse is reflected from the object, and generate first image data and second image data based on the reflected pulses; and a distance information generator that generates a first histogram based on the first image data, a second histogram based on the second image data, and distance information for the object based on a difference between the first histogram and the second histogram.
A method of manufacturing a semiconductor device includes forming a cell chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer, flipping the cell chip, exposing a rear surface of the source layer by removing the first substrate from the cell chip, performing surface treatment on the rear surface of the source layer to reduce a resistance of the source layer, forming a peripheral circuit chip including a second substrate and a circuit on the second substrate, and bonding the cell chip including the source layer with a reduced resistance to the peripheral circuit chip.
H10D 86/85 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors characterised by only passive components
A semiconductor device includes a first gate structure including first conductive layers; a first stack at a level corresponding to the first gate structure; a second gate structure on the first gate structure and on the first stack, the second gate structure including second conductive layers; a second stack at a level corresponding to the second gate structure; and a third gate structure on the second gate structure and on the second stack, the third gate structure including third conductive layers. The semiconductor device also includes first contact vias extending into the first gate structure and respectively connected to the first conductive layers; second contact vias passing through the first stack, extending into the second gate structure, and respectively connected to the second conductive layers; and third contact vias passing through the first and second stacks, extending into the third gate structure, and respectively connected to the third conductive layers.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
93.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
Disclosed are a semiconductor device capable of alleviating or minimizing the interference between the storage node contacts, and a method for fabricating the semiconductor device. A semiconductor device includes a semiconductor substrate; a plurality of bit line structures disposed over the semiconductor substrate; island-shaped storage node contacts that are spaced apart from each other between neighboring bit line structures of the plurality of bit line structures; a plurality of plug isolation layers disposed between the island-shaped storage node contacts; and contact spacers disposed between each of the storage node contacts and each of the plurality of plug isolation layers, each contact spacer having different thicknesses at a central portion of the contact spacer and at both ends.
H10B 12/00 - Dynamic random access memory [DRAM] devices
94.
SEMICONDUCTOR PROCESS WASTEWATER TREATMENT SYSTEM TO WHICH ADVANCED OXIDATION PROCESS AND ANAEROBIC BIOLOGICAL PROCESS ARE APPLIED AND SEMICONDUCTOR PROCESS WASTEWATER TREATMENT METHOD USING THE SAME
Korea University Research and Business Foundation, Sejong Campus (Republic of Korea)
Inventor
Jang, Gwangil
Kim, Sunmin
Ahn, Sehyuk
Kim, Young-Jin
Lee, Song-Bok
Choi, Dong-Uk
Abstract
A semiconductor process wastewater treatment system and a method for treating semiconductor process wastewater using the system are disclosed. The disclosed semiconductor process wastewater treatment system comprises: an advanced oxidation reaction tank for advanced oxidation of a semiconductor process wastewater comprising tetramethyl ammonium hydroxide (TMAH) using a UV/PDS process that activates peroxydisulfate (PDS) with ultraviolet light (UV ray); an anaerobic biological reaction tank for biologically treating the semiconductor process wastewater that has passed through the advanced oxidation reactor, the anaerobic biological reaction tank configured to treat the semiconductor process wastewater with microorganisms comprising sulfate reducing bacteria (SRB) under anaerobic conditions, and configured to react sulfate generated in the advanced oxidation reactor with the sulfate reducing bacteria to generate H2S; and a gas separator for separating the H2S from gas generated in the anaerobic biological reactor.
C02F 1/20 - Treatment of water, waste water, or sewage by degassing, i.e. liberation of dissolved gases
C02F 1/469 - Treatment of water, waste water, or sewage by electrochemical methods by electrochemical separation, e.g. by electro-osmosis, electrodialysis, electrophoresis
C02F 1/66 - Treatment of water, waste water, or sewage by neutralisationTreatment of water, waste water, or sewage pH adjustment
C02F 1/72 - Treatment of water, waste water, or sewage by oxidation
Image sensing devices are disclosed. In an embodiment, an image sensing device includes a semiconductor substrate including photoelectric conversion elements configured to generate photocharges by converting incident light; and a metalens layer disposed over the semiconductor substrate, and configured to separate incident light into light components of different colors based on wavelength and to converge the separated light components onto corresponding photoelectric conversion elements. The metalens layer may include: a first metalens layer including first nano-structures and a first air layer disposed between the first nano-structures; a second metalens layer including second nano-structures and a second air layer disposed between the second nano-structures, wherein at least a portion of each of the second nano-structures is disposed on a corresponding first nano structure of the first nano structures; and a support layer disposed over the first air layer in a space between adjacent first nano-structures of the first nano-structures.
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
96.
3-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE WITH ALTERNATIVE MEMORY CHANNEL LAYER AND METHOD FOR FORMING THE SAME
A method for forming a 3D memory device is provided. The method includes providing a stacked structure including oxide layers and nitride layers alternately stacked together; forming a through hole in the stacked structure; forming a memory storage structure on a sidewall of the through hole in the stacked structure; and selectively forming a channel layer of a transition metal di-chalcogenide on the memory storage structure using an inhibition layer.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
97.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE
A semiconductor device including: a gate structure including insulating layers and conductive layers that are alternately stacked; a slit structure extending through the gate structure; a channel layer extending through the gate structure; a data storage layer including a first portion located between each of the conductive layers and the channel layer, a second portion located between each of the insulating layers and the slit structure, and a third portion extending in a horizontal direction to connect the first portion and the second portion to each other; and tunneling patterns located between the conductive layers and the channel layer, respectively, and separated from each other by the insulating layers.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
A semiconductor device may include a first circuit structure and a second circuit structure bonded onto the first circuit structure. The first circuit structure may include a first active region and a first guard ring region. The second circuit structure may include a second active region and a second guard ring region. The semiconductor device may further include a first upper contact plug disposed in the first active region and the second active region, passing through an interface between the first circuit structure and the second circuit structure, and a first upper contact guard ring disposed in the first guard ring region and the second guard ring region, passing through the interface. The second circuit structure may include a bit line in the second active region, and a bit guard ring disposed in the second guard ring region at substantially the same level as the bit line.
A ramp generator for generating a ramp signal from an image sensor is disclosed. The ramp generator includes a bias voltage generator configured to generate a bias voltage, and a plurality of ramp cells configured to generate a ramp signal based on the bias voltage. Each of the plurality of ramp cells includes a local sampling circuit configured to adjust a sampling timing point of the bias voltage.
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
H04N 25/709 - Circuitry for control of the power supply
100.
SEMICONDUCTOR DEVICE INCLUDING BONDING PADS AND METHOD FOR MEASURING CONTACT RESISTANCE OF BONDING PADS
A semiconductor device including a first test pattern in which the first upper test pad, first upper test contacts, and first upper conductive layers connecting the first upper test contacts are sequentially connected, a second test pattern in which the second lower test pad, second lower test contacts, and second lower conductive layers connecting the second lower test contacts are sequentially connected, and a third test pattern including a third upper conductive layer, a third lower conductive layer, a third upper test contact, a third upper test pad, a third lower test pad, and a third lower test contact.
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
