Abstract

A non-volatile memory device comprises at least one non-volatile memory cell, electrically connected to at least one bit line, a first select line, a second select line, a control line and a common line. Each non-volatile memory cell comprises a first select transistor, having a drain electrically connected to a bit line, and a gate electrically connected to the first select line; a second select transistor, having a source electrically connected to the common line, and a gate electrically connected to the second select line; and a transistor with a floating gate, having a drain electrically connected to a source of the first select transistor, a gate electrically connected to the control line, and a source electrically connected to a drain of the second select transistor; wherein when performing erase or write operation, the second select line is grounded, causing the second select transistor to turn off.

IPC Classes  ?

• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• G11C 16/10 - Programming or data input circuits
• G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups

Abstract

A non-volatile memory cell includes a tunneling part; a coupling transistor, including a coupling gate part, a first conductive region and a second conductive region, wherein the coupling gate part is coupled to the tunneling part and disposed in the first conductive region; a read transistor with a read gate part coupled to the tunneling part for forming an electron tunneling ejection path in an erase mode, and forming an electron tunneling injection path in a program mode; and a select transistor, connected in series with the read transistor, for forming a read path with the read transistor in a read mode.

IPC Classes  ?

• H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
• H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
• H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND

Abstract

A non-volatile memory cell includes a tunneling part; a coupling device; a read transistor; a first select transistor connected to the read transistor forming a read path with the read transistor in a read mode; an erase tunneling structure forming a tunneling ejection path in an erase mode; and a program tunneling structure forming a tunneling injection path in an program mode; wherein the read path is different from the tunneling ejection path and the tunneling injection path.

IPC Classes  ?

• H01L 27/115 - Electrically programmable read-only memories; Multistep manufacturing processes therefor
• G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
• H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
• G11C 16/02 - Erasable programmable read-only memories electrically programmable

Abstract

A method for erasing data stored in the memory cells of the floating gate flash memory is included. The method allows a plurality of sectors to be disposed in a same P well. The method includes erasing data stored in a first set of memory cells according to a control signal, randomly reading the data stored in a second set of memory cells affected by the erasing action of the first set of memory cells, and writing data read from the second set of memory cells onto the second set of memory cells.

IPC Classes  ?

• G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices