An ESD (electrostatic discharge) protection device includes a first enhancement mode HEMT (high-electron-mobility transistor) electrically connected between a protected node and a grounded node, and an RC network electrically connected between the protected node and the grounded node, The time constant of the RC network is set such that a gate of the first enhancement mode HEMT is pulled up to turn on the first enhancement mode HEMT for positive transient pulses at the protected node having a rise time less than the time constant of the RC network. The first enhancement mode HEMT is configured to shunt the protected node to the grounded node when on.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
A transistor device includes a gate trench structure extending from a first surface and into a wide band gap semiconductor body. A body region of a first conductivity type adjoins a sidewall of the gate trench structure. An auxiliary structure of the first conductivity type adjoins a bottom side of the gate trench structure. A drift structure of a second conductivity type adjoins a bottom side of the body region and includes a drift layer between a bottom side of the auxiliary structure and a second surface of the wide band gap semiconductor body. At a first position, a first sub-region of the drift structure extends from the bottom side of the body region to the drift layer. At a second position, a second sub-region of the drift structure extends from the bottom side of the body region to a top side of a transverse sub-region of the auxiliary structure.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
3.
POWER CONVERTER AND METHOD FOR OPERATING A POWER CONVERTER
A power converter and a method are disclosed. The power converter includes an input to receive three alternating input voltages; a switching circuit coupled to the input and comprising a three-phase half-bridge; an autotransformer circuit; and a rectifier circuit. The autotransformer circuit is coupled between the switching circuit and the rectifier circuit, and the rectifier circuit is coupled between the autotransformer circuit and an output of the power converter.
H02M 7/217 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
The disclosed concepts relate to a power supply incorporating a power pulsation buffer (PPB). The power supply comprises a power factor correction (PFC) stage including a DC-link capacitor, and an unregulated DC-DC converter that receives the DC-link voltage across the DC-link capacitor and generates an output voltage. The PPB is connected between the PFC stage and unregulated DC-DC converter, and comprises a buffer capacitor. The PFC stage is configured to regulate a voltage across the buffer capacitor, and the PPB is configured to regulate the DC-link voltage across the DC-link capacitor. As a result, the voltage across the DC-link capacitor may be maintained at a near-constant value, whilst the voltage across the buffer capacitor varies. This means that the DC-DC converter may be unregulated, efficient and highly compact, as an input voltage is closely regulated.
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 1/14 - Arrangements for reducing ripples from DC input or output
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A circuit that includes two current path circuits—a first current path circuit and a second current path circuit in which current flow is in opposite rotational directions in a current flow plane. If a same differential voltage is applied across the first current path circuit and the second current path circuit, this will induce relative counter rotational current in each current path circuit. This is true even if the first voltage and/or second voltage are changing. Accordingly, the counterflows at least partially cancel out electromagnetic interference across a range of frequencies.
A transistor device includes: a semiconductor substrate having a first major surface and an edge region laterally surrounding an active area; a trench in the first major surface in the active area; a field plate in a lower portion of the trench and a gate electrode in an upper portion of the trench above the field plate; and a contact extending into the first major surface laterally adjacent to and spaced apart from the trench. In the active area, an upper surface of the gate electrode is in contact with a first electrically insulating layer only. The first electrically insulating layer protrudes above the first major surface and has an upper surface and side walls that extend from the upper surface to the first major surface. The upper surface of the first electrically insulating layer is free of a second electrically insulating layer located on the side walls.
An insulated gate field effect transistor (IGFET) includes a trench structure extending, along a vertical direction, into a wide band gap semiconductor body from a first surface of the wide band gap semiconductor body. The IGFET further includes a body region of a first conductivity type, a source region of a second conductivity type, and a shielding region of the first conductivity type. The shielding region includes a first sub-region adjoining a bottom side of the trench structure, and a second sub-region adjoining a bottom side of the first sub-region. The first sub-region has a larger maximum doping concentration than the second sub-region. A vertical doping concentration profile of the first sub-region and a vertical doping concentration profile of the second sub-region overlap each other at the bottom side of the first sub-region.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/60 - Impurity distributions or concentrations
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
According to some embodiments, a communication device includes a signal generator configured to generate a carrier signal, control logic configured to encode first data in the carrier signal, a barrier device including an isolation barrier connected to the signal generator and a tuning circuit connected to the isolation barrier to establish a resonance condition for communicating the carrier signal over the isolation barrier, and a receiver configured to decode second data from a remote device based on at least one parameter of the carrier signal.
H03K 17/0412 - Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
A semiconductor package includes a leadframe comprising first leads and second leads, a substrate connected between the first leads and the second leads, a base plate, a first semiconductor transistor die connected between the base plate and the substrate and including a first source pad, a first drain pad, and a first gate pad, a second semiconductor transistor die connected between the base plate and the substrate and comprising a second source pad, a second drain pad, and a second gate pad, wherein the first semiconductor die and the second semiconductor die are interconnected to form a half-bridge circuit, wherein the first source pad of the first semiconductor die is electrically connected with the second drain pad of the second semiconductor die, an encapsulant embedding the first semiconductor die, the second semiconductor transistor die, and horizontal portions of the first leads and the second leads.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/367 - Cooling facilitated by shape of device
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
10.
VOLTAGE CONVERTER AND METHOD FOR PRODUCING A VOLTAGE CONVERTER
A voltage converter is provided, comprising:
a first circuit board with a first circuit section of the voltage converter, wherein the first circuit section comprises semiconductor chips embedded between metal layers of the first circuit board, and
a second circuit section a second circuit board with a second circuit section of the voltage converter, wherein the first circuit section is electrically coupled to the second circuit section.
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
A semiconductor device includes a leadframe, a first semiconductor chip arranged above a mounting surface of the leadframe, and a heatsink arranged above a top surface of the first semiconductor chip facing away from the mounting surface of the leadframe. At least one first lead of the leadframe extends towards a bottom surface of the heatsink facing the mounting surface of the leadframe. The at least one first lead is mechanically coupled to the bottom surface of the heatsink.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
12.
Semiconductor Package with Selective Surface Roughening
A method of forming a semiconductor package includes providing a metal lead frame comprising a die pad and a plurality of leads, mounting a high-voltage die on an upper surface of the die pad such that a load terminal of the high-voltage die is electrically connected to the die pad, mounting an electrical isolation pad on the die pad, and mounting a low-voltage die on the electrical isolation pad, wherein at least one of: mounting the high-voltage die, mounting the electrical isolation pad, and mounting the low-voltage die includes performing a float-limiting attachment process, wherein the float-limiting attachment process comprises performing a surface roughening process to an attachment surface that forms a border of roughened surface around a mounting area, arranging an attachment material within the mounting area with a mounting element disposed thereon, and liquifying the attachment material with the mounting element disposed thereon.
A transistor module, driver for transistor module, corresponding system and method are provided. The transistor module comprises a transistor, an overcurrent protection circuit configured to detect an overcurrent condition of the transistor and to set the transistor to an overcurrent protection state in response to detecting the overcurrent condition, and a signaling circuit coupled to a control terminal of the transistor module and configured to modify a signal level at the control terminal in response to the overcurrent protection circuit detecting the overcurrent condition.
A semiconductor package includes a substrate including a die pad, first and second discrete transistor dies mounted on the die pad, an encapsulant body that encapsulates the first and second discrete transistor dies, and a plurality of leads that are exposed from the encapsulant body, wherein the first and second discrete transistor dies are connected in parallel with one another by electrical interconnections that electrically connect common terminals of the first and second discrete transistor dies to one of the leads, and wherein at least one of the electrical interconnections has a balanced configuration that provides substantially identical electrical impedance as between the common terminals of the first and second discrete transistor dies and the lead to which they are connected.
According to some embodiments, a method for controlling a motor comprises determining a first angle encoder offset for a motor representing a difference between a mechanical angle of the motor and an electrical angle of the motor, sending a first command for movement of the motor in a first direction, modifying the first angle encoder offset to generate a second angle encoder offset based on a comparison of a first determined motor direction responsive to the first command and the first direction, and controlling the motor based on the second angle encoder offset.
A transistor package includes a semiconductor transistor chip having opposite first and second surfaces, one or a plurality of first load electrodes, one or a plurality of second load electrodes, and a control electrode on the first surface. A leadframe faces the first surface of the semiconductor transistor chip and includes a first terminal, a second terminal, and a control terminal of the package which are exposed at a bottom of the package. The first terminal is electrically coupled to the first load electrode(s). The second terminal is electrically coupled to the second load electrode(s). The control terminal is electrically coupled to the control electrode. The first terminal is aligned with a first side of the package. The second terminal is aligned with a second side opposite the first side. The control terminal is aligned with a third side of the package which connects between the first and second sides.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/528 - Layout of the interconnection structure
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
17.
Package with Thinner and Thicker Carriers for Carrying and Connecting Electronic Component
A package includes a first carrier including a component mounting area, a second carrier including at least one lead section, at least one electronic component mounted on the component mounting area, and an encapsulant encapsulating at least part of the at least one electronic component, encapsulating at least part of the first carrier including encapsulating the entire sidewalls of the first carrier, and encapsulating part of the second carrier, wherein the first carrier is assembled with the second carrier so that the at least one electronic component and/or the first carrier is electrically connected with the at least one lead section, and wherein the first carrier has a first thickness and the second carrier has a second thickness being smaller than the first thickness.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
18.
Method of Estimating Motor Speed and Motor Control System
A method of estimating motor speed includes: calculating a first estimate of rotor mechanical frequency of a motor based on measured time between successive counter pulses, each of the counter pulses corresponding to a fixed number of counts per revolution of the motor; calculating a second estimate of the rotor mechanical frequency based on the number of counter pulses over a fixed period of time; and dynamically revising an official estimate of the rotor mechanical frequency, by weighting the first and second estimates inversely proportional to one another based on the rotor mechanical frequency. A corresponding motor control system is also described.
A semiconductor device includes a die carrier, a semiconductor die, a first set of external connectors, and a second set of external connectors. The semiconductor die includes at least a first load electrode and a second load electrode, and is mounted onto the die carrier with the first load electrode being electrically connected to the die carrier. The first set of external connectors is electrically and thermally connected to the die carrier. The second set of external connectors is spaced apart from the die carrier and electrically connected to the second load electrode. An overall wire size of the second set of external connectors is greater than an overall wire size of the first set of external connectors.
A power converter assembly as discussed herein can be configured to include a controller. The controller is operative to: control delivery of input current from an input voltage source to a resonant power converter; monitor a first voltage (Vsplit) at a first node of the resonant power converter, the first node coupling a first capacitor and a second capacitor in series; and adjust a magnitude of the input current supplied from the input voltage source to the resonant power converter based upon the monitored first voltage.
H02M 7/04 - Conversion of AC power input into DC power output without possibility of reversal by static converters
H02M 7/25 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only arranged for operation in series, e.g. for multiplication of voltage
21.
ASYMMETRIC BI-DIRECTIONAL RECTIFIER ARCHITECTURE WITH LEG RECONFIGURATION FOR MULTI-PHASE OPERATION
Provided is an apparatus comprising a rectifier stage having a neutral line and configured to convert between an AC signal and a DC signal. The rectifier stage comprises at least one rectifier leg with neutral-point connected topology and at least one rectifier leg with flying capacitor topology. A reconfiguration switch is configured to switch between single-phase and three-phase operation of the rectifier stage.
H02M 7/219 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
B60L 53/20 - Methods of charging batteries, specially adapted for electric vehiclesCharging stations or on-board charging equipment thereforExchange of energy storage elements in electric vehicles characterised by converters located in the vehicle
H02M 1/14 - Arrangements for reducing ripples from DC input or output
H02M 1/44 - Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 7/217 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
22.
POWER CONVERTER WITH BALANCER INCLUDING FLYING CAPACITOR
An apparatus such as a power converter includes: an input interface operative to receive an output voltage generated by a power converter stage; compensation circuitry including switch circuitry and a flying capacitor to derive a compensation current from the output voltage received from the power converter stage; and an output interface operative to supply the compensation current to the power converter stage. Implementation of the compensation circuitry and corresponding generation of the compensation current as discussed herein reduces a respective ripple associated with the output voltage.
H02M 7/219 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
A power semiconductor device includes: a semiconductor substrate; a power transistor formed in a cell field of the semiconductor substrate; a reference terminal; a sense terminal; and a depletion mode sense transistor integrated in the semiconductor substrate and having a voltage tap region of a first conductivity type. The voltage tap region is electrically connected to the sense terminal and follows a drift zone potential of the power transistor until a normally conducting channel of the depletion mode sense transistor pinches off. A pinch-off point of the normally conducting channel of the depletion mode sense transistor is designed such that a voltage between the sense terminal and the reference terminal is clamped below a maximum drain/collector voltage of the power semiconductor device.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
24.
Group III Nitride Transistor Cell Including an Integrated Protection Diode
A Group III nitride transistor cell is provided that includes a Group III nitride-based body, a source finger, a gate finger, and a drain finger extending substantially parallel to one another and positioned on the Group III nitride-based body, the gate finger being arranged laterally between the source finger and the drain finger and including a p-type Group III nitride finger arranged on the Group III nitride body and a gate metal finger arranged on the p-type Group III nitride finger, and a protection diode. The protection diode is integrated into the Group III nitride transistor cell and operable to conduct current in a reverse direction when the Group III nitride transistor cell is switched off. The protection diode is electrically coupled between the source and drain fingers and is positioned on the Group III nitride body laterally between and spaced apart from the gate finger and the drain finger.
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 64/00 - Electrodes of devices having potential barriers
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
25.
ELECTRICAL CIRCUIT AND METHOD FOR DETERMINING RESISTOR VALUES AND METHOD FOR PROGRAMMING A TURN ON/OFF SPEED OF SWITCH CIRCUITRY
An apparatus as discussed herein includes: a first circuit node coupling a first resistor and a second resistor in series between an input voltage source and a reference voltage source; current mirror circuitry coupled to the first circuit node, the current mirror circuitry operative to: i) produce a first mirror current based a first current conveyed through the first resistor, and ii) produce a second mirror current based on a second current conveyed through the second resistor; and measurement circuitry operative to determine resistances of the first resistor and the second resistor via various techniques.
G01R 27/14 - Measuring resistance by measuring current or voltage obtained from a reference source
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
26.
SWITCHING CIRCUIT, POWER MODULE UNIT, AND MOTOR CONTROLLER CIRCUIT WITH VOLTAGE MONITORING UNIT
A switching circuit includes a power semiconductor device and a current mirror circuit. The power semiconductor device is in a switched current path between a switching node and a reference potential. The current mirror circuit includes a first transistor and a second transistor and copies a reference current through the first transistor by controlling an output current through the second transistor. The first transistor is electrically connected outside the switched current path and in series with the power semiconductor device in a first current path. The second transistor is in a second current path. The first current path and the second current path are electrically connected in parallel.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
27.
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING A CONDUCTIVE MEMBER AND A DIELECTRIC STRUCTURE IN A TRENCH
In an embodiment, a semiconductor device includes a semiconductor substrate having a first major surface, a trench extending from the first major surface into the semiconductor substrate and having a base and a side wall extending from the base to the first major surface. A conductive member is arranged in the trench and spaced apart from the side wall of the trench by a dielectric structure that is located in the trench. The dielectric structure includes a first chamber located at the base of the trench. The conductive member has a side wall having an inner surface and an outer surface. The inner surface surrounds a second chamber that is in fluid communication with the first chamber.
An atom trap device includes a substrate, a structured metal layer arranged above the substrate and configured to generate at least one of a magnetic, electric or electromagnetic field for controlling atoms in a zone above the structured metal layer, and a crystalline or polycrystalline dielectric material arranged between the substrate and the structured metal layer. The crystalline or polycrystalline dielectric material includes at least one planar layer extending substantially parallel to the structured metal layer. The crystalline or polycrystalline dielectric material is in contact with the structured metal layer.
A semiconductor arrangement includes first and second semiconductor packages separate from one another. Each semiconductor package includes a die carrier having opposite first and second main faces, a transistor die disposed on the first main face, a first lead connected to a first load electrode of the transistor die, a second lead connected to a gate electrode of the transistor die, and an encapsulant embedding at least part of the first main face of the die carrier, inner portions of the leads and the transistor die. The first lead of the first semiconductor package is electrically connected to the first lead of the second semiconductor package, forming a source-source connection. The second lead of the first semiconductor package and the second lead of the second semiconductor package are arranged between the first semiconductor package and the second semiconductor package.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/11 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in subclass
H10D 80/20 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising capacitors, power FETs or Schottky diodes
30.
POWER CONVERTER AND METHOD FOR OPERATING A POWER CONVERTER
A method for operating a power converter and a power converter are disclosed. The power converter includes: three first nodes and two second nodes; three transformers each comprising a first winding and a second winding inductively coupled with the first winding; a first circuit with three first stages each coupled to a respective one of the first nodes, the first winding of a respective one of the transformers, and a common circuit node; and a second circuit with four second stages each comprising a switched node and each coupled to the second nodes via further nodes. The second windings are connected in series, and the four second stages are connected to the second windings such that each second winding is connected between the switched nodes of a respective pair of the four second stages.
H02M 7/219 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 7/00 - Conversion of AC power input into DC power outputConversion of DC power input into AC power output
31.
METHOD FOR OPERATING A POWER CONVERTER AND POWER CON-VERTER
A power converter includes three input nodes each configured to receive a respective one of three alternating input voltages, and an output; three transformers each comprising a first winding and a second winding inductively coupled with the first winding; an input circuit with three input stages each coupled to a respective one of the input nodes, the first winding of a respective one of the transformers and a common circuit node; and an output circuit coupled to the second winding of each of the transformers and the output. The method includes detecting the lowest input voltage, which is that one of the input voltages having the lowest magnitude; connecting that one of the input nodes receiving the lowest input voltage to the common circuit node by the input stage connected to that one of the input nodes receiving the lowest input voltage.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A semiconductor arrangement includes first and second controllable semiconductor devices forming a half-bridge arrangement, each controllable semiconductor device including a control electrode and a controllable load path between a first load electrode and a second load electrode. At least one gate driver is configured to generate one or more control signals for one or more of the controllable semiconductor devices. The first controllable semiconductor device is arranged on and electrically coupled to a first lead frame of a plurality of lead frames. The second controllable semiconductor device is arranged on and electrically coupled to a second lead frame of the plurality of lead frames. The controllable semiconductor devices and the at least one gate driver are arranged in a molded package. Each lead frames is partly covered by the molded package and has at least one surface or section that is not covered by the molded package.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
33.
Semiconductor Package Having a Die Assembly with an Electrically Insulating Thickness-Matching Layer
A semiconductor package includes a laminate package body and a die assembly embedded within the laminate package body. The laminate package body includes a plurality of laminate dielectric layers stacked on top of one another and metallization layers interposed between the laminate dielectric layers. The die assembly includes a thermally conductive substrate that includes a planar upper surface, a semiconductor die mounted on the planar upper surface of the thermally conductive substrate, and an electrically insulating thickness-matching layer formed on the planar upper surface of the thermally conductive substrate and surrounding the semiconductor die. An upper surface of the electrically insulating thickness-matching layer is substantially coplanar with an upper surface of the semiconductor die. The upper surface of the electrically insulating thickness-matching layer and the upper surface of the semiconductor die form an upper surface of the die assembly.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A transistor device includes: a semiconductor substrate having a first major surface; elongate trenches extending from the first major surface into the semiconductor substrate and positioned substantially parallel to one another such that one or more inner elongate trenches are arranged between two outermost elongate trenches; an elongate mesa between neighbouring ones of the elongate trenches; and an edge trench extending from the first major surface into the semiconductor substrate and laterally surrounding the plurality of elongate trenches. The edge trench includes transverse trench portions that extend between longitudinal trench portions such that an inner trench corner is formed at each intersection between an inner side wall of the longitudinal trench portion and an inner side wall of the transverse trench portion. The inner trench corner of the edge trench has a radius of curvature that is greater than a width of the closest elongate mesa.
According to some embodiments, a receiver comprises a positive terminal, a negative terminal, a first isolation capacitor connected to the positive terminal, a second isolation capacitor connected to the negative terminal, a resistor circuit connected to the first isolation capacitor and the second isolation capacitor to define a first high pass filter, an amplifier connected to the first high pass filter, a level detector connected to the amplifier, and a second high pass filter connected between the first high pass filter and the level detector.
According to some embodiments, a multi-level power converter, includes an output terminal, a reference terminal, an inductor, a flying capacitor, a first switching stage including a first switch connected to the output terminal and connected to the flying capacitor at a first node, and a second switch connected to the flying capacitor at a second node and connected to the reference terminal, a second switching stage including a third switch connected to the first node and the inductor, and a fourth switch connected to the inductor and the second node, and a pre-charge unit connected to the flying capacitor and the output terminal and configured to pre-charge the flying capacitor based on a voltage at the output terminal during a start-up cycle of the multi-level power converter.
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 7/537 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
37.
CIRCUIT INCLUDING A TRANS-INDUCTANCE VOLTAGE REGULATOR
The disclosed technology relates to a circuit incorporating a trans-inductance voltage regulator (TLVR). The TLVR comprises multiple primary windings connected in series, and secondary windings inductively coupled to respective primary windings and connected between respective phase input nodes and a common output node. A second inductor is connected in series with the primary windings, and is inductively coupled to a first inductor. The first inductor is connected between equipotential nodes. That is, the first inductor is connected between two nodes that are provided with substantially the same voltage during steady state operation. Due to the inductive coupling of the TLVR to the primary inductor, when there is a surge of current between the equipotential nodes, the current slope may be managed by control of the TLVR. For example, the first inductor may be placed before a voltage converter-which may result in an improved transient response of the converter.
H02M 5/10 - Conversion of AC power input into AC power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into DC by static converters using transformers
38.
SEMICONDUCTOR DEVICE WITH A DIELECTRIC SPACER AND METHOD OF MANUFACTURING
A semiconductor device includes a package body having a topside in a first plane and a bottom side in a second plane parallel to the first plane. At least one lead protruding out of the package body has a first portion in a plane parallel to the first plane and a second portion being bent away from the first plane towards the second plane. A cavity is positioned between the at least one lead and a feature of the semiconductor device. A removable dielectric spacer is configured to be positioned in the cavity between the at least one lead and the feature. The dielectric spacer is longer than the at least one lead.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/32 - Holders for supporting the complete device in operation, i.e. detachable fixtures
H01L 23/367 - Cooling facilitated by shape of device
An atom trapping device having waveguides for guiding light for application to a plurality of atom trapping locations is described herein. Modulation arrangements are configured to perform optical modulation of light carried by the waveguides responsive to any control signals provided thereto. A multiplexer arrangement is configured to control which, if any, control signal(s), generated by one or more control signal generators, are provided to each modulation arrangement.
G21K 1/00 - Arrangements for handling particles or ionising radiation, e.g. focusing or moderating
G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour
40.
DEVICE FOR TRAPPING IONS AND METHODS FOR FABRICATING SAME
A method for fabricating a device for trapping ions includes forming a first metal layer over a substrate. The first metal layer is made of a first material. The method further includes forming a second metal layer over the first metal layer. The second metal layer is made of a second material different from the first material. The method further includes performing physical dry etching to form one or more first trenches in the second metal layer. The one or more first trenches extend to a lower side of the second metal layer. The method further includes performing chemical dry etching to form one or more second trenches in the first metal layer below the one or more first trenches. The one or more second trenches extend to a lower side of the first metal layer.
A high voltage semiconductor package includes a semiconductor device. The semiconductor device includes a high voltage semiconductor transistor chip having a front side and a backside. A low voltage load electrode and a control electrode are disposed on the front side of the semiconductor transistor chip. A high voltage load electrode is disposed on the backside of the semiconductor transistor chip. The semiconductor package further includes a dielectric inorganic substrate. The dielectric inorganic substrate includes a pattern of first metal structures running through the dielectric inorganic substrate and connected to the low voltage load electrode, and at least one second metal structure running through the dielectric inorganic substrate and connected to the control electrode. The front side of the semiconductor transistor chip is attached to the dielectric inorganic substrate by a wafer bond connection, and the dielectric inorganic substrate has a thickness of at least 50 μm.
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A power electronics device includes a voltage-driven transistor, a galvanically isolated gate driver and an energy storage device. The galvanically isolated gate driver is configured to receive a power signal, a turn-on signal, and a turn-off signal for the voltage-driven transistor over galvanic isolation implemented using a coreless transformer. The energy storage device is electrically connected to a gate of the voltage-driven power transistor and configured to store energy from the power signal received by the galvanically isolated gate driver and use the stored energy to stabilize a gate voltage of the voltage-driven power transistor during an on-state of the voltage-driven power transistor.
H03K 17/691 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit using transformer coupling
An electrical circuit arrangement includes a first diode and a semiconductor switching device electrically connected in series between a first node and a second node. The semiconductor switching device controls a switch current that includes a forward current through the first diode and a load current. A second diode and a calibration switching element are electrically connected in series between the first node and the second node. A voltage acquisition circuit obtains a voltage difference between a first voltage between the first node and the second node when the semiconductor switching device is on and the calibration switching element is off and a second voltage between the first node and the second node when the calibration switching element is on and the semiconductor switching device is off.
G01R 31/26 - Testing of individual semiconductor devices
G01R 31/327 - Testing of circuit interrupters, switches or circuit-breakers
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A phase shift full bridge (PSFB) converter includes: a transformer having primary and secondary sides; a first pair of switch devices connected in series at a first node coupled to a first terminal of the primary side; a second pair of switch devices connected in series at a second node coupled to a second terminal of the primary side; diode devices connected in series at a third node coupled to the first terminal; an inductor coupled between the first and third nodes; a secondary-side rectifier; and a controller. In one mode, the controller operates the second pair of switch devices as a leading power transfer leg and the first pair of switch devices as a lagging power transfer leg. In another mode, the controller operates the first pair of switch devices as the leading power transfer leg and the second pair of switch devices as the lagging power transfer leg.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
An apparatus, including: a multi-phase motor having stator windings; an inverter connected between a direct current (DC) supply voltage and ground, and having power switches connected to the stator windings of the multi-phase motor; and a motor controller operable to regulate a braking torque of the multi-phase motor during periods of battery power unavailability by applying control signals to the power switches in the inverter to boost the DC supply voltage using back electromagnetic force (BEMF) voltage induced in the stator windings, passively brake the multi-phase motor, or plug brake the multi-phase motor, for each phase of the multi-phase motor, based on the DC supply voltage, a rotor position of the multi-phase motor, and an angular speed of the multi-phase motor.
A semiconductor device includes a substrate and a die embedded in the substrate. The substrate is a multilayer substrate including: an electrically conductive topside layer forming a topside of the semiconductor device; an electrically conductive bottom side layer forming a baseplate of the semiconductor device; a first electrical connector, between the topside layer and the bottom side layer; and a second electrical connector coupling the bottom side layer and/or the topside layer to a potential other than ground.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/60 - Protection against electrostatic charges or discharges, e.g. Faraday shields
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
A device for trapping charged atomic objects includes: a substrate having a first major surface; at least one radio frequency (RF) electrode configured to generate an RF potential for trapping at least one ion along a trap axis, the at least one RF electrode including a plurality of RF segments arranged on the first major surface of the substrate, the plurality of RF segments being at least partly separated on the first major surface of the substrate; and a plurality of direct current (DC) electrodes configured to generate a DC potential.
A vertical junction field effect transistor includes a trench structure laterally arranged between mesa regions along a first lateral direction. The trench structure extends into a semiconductor body from a first surface of the semiconductor body. Each of the mesa regions includes a mesa channel region of a first conductivity type. The vertical junction field effect transistor further includes a gate region of a second conductivity type. The gate region adjoins at least part of opposite sidewalls of the trench structure and to a bottom side of the trench structure. The trench structure includes a silicon layer adjoining the gate region at the bottom side of the trench structure. A first thickness of the gate region at the bottom side of the trench structure is larger than a second thickness of the gate region at each of the opposite sidewalls of the trench structure.
H10D 30/80 - FETs having rectifying junction gate electrodes
H10D 30/83 - FETs having PN junction gate electrodes
H10D 62/60 - Impurity distributions or concentrations
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 64/62 - Electrodes ohmically coupled to a semiconductor
A circuit comprises a primary port for providing a primary voltage and a secondary port for providing a secondary voltage. The circuit comprises a primary side comprising at least one rectifier circuit coupled to the primary port. The rectifier circuit comprises a first primary winding coupled to a first terminal of the primary port via a first switch and coupled to a second terminal of the primary port via a tap. The rectifier circuit comprises a second primary winding coupled to the first terminal of the primary port via a second switch and coupled to the second terminal of the primary port via the tap between the first and the second winding. The circuit comprises a secondary side comprising a bridge circuit of switches and a resonant tank circuit coupled to the secondary port via the bridge circuit.
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
A controller for a power converter, and a method for operating a power converter is provided. The power converter comprises a switching circuit configured to receive alternating input voltages, and having switches connected to respective alternating input voltages and controllable to generate an alternating intermediate voltage. Furthermore, the power converter comprises a transmitter and rectifier circuit. For each period of the alternating intermediate voltage, the control scheme comprises the identification with the greatest and second alternating input voltages or greatest and second greatest line-to-line voltages, and then controlling the switching circuit to generate the alternating intermediate voltage based on the identified voltages. The length of the period of the alternating intermediate voltage is then adjusted for subsequent periods of the alternating intermediate voltage based at least in part on a measured value of the output voltage.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 7/12 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
51.
METHOD FOR OPERATING A POWER CONVERTER AND POWER CONVERTER
A method for operating a power converter and a power converter are disclosed. The method includes generating an alternating voltage (Vmn) based on three alternating input voltages (Va, Vb, Vc) received at an input (a, b, c) of a power converter. Generating the alternating voltage (Vmn) includes: generating the alternating voltage (Vmn) in an unregulated fashion by a switching circuit (1) comprising a three-phase half-bridge, controlling a waveform of the alternating voltage (Vmn) dependent on signal levels of the input voltages (Va, Vb, Vc), and controlling a power factor of power received at the input (a, b, c).
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 5/293 - Conversion of AC power input into AC power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into DC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
52.
METHOD FOR RELIABILITY PREDICTION AND ELECTRONIC CIRCUIT
According to an embodiment, a method is provided, comprising:
repeatedly performing a measurement of a plurality of operation parameters of an electronic circuit during operation of the electronic circuit,
for each measurement calculating, by the electronic circuit, a reliability prediction parameter of the electronic circuit based on the measurements and a reliability prediction model of the electronic circuit.
A semiconductor device is described. The semiconductor device includes: a trench formed in a first main surface of a semiconductor substrate; a field plate electrode disposed in a lower part of the trench; an insulating material separating the field plate electrode from the semiconductor substrate; and a strain-inducing material embedded in the field plate electrode. The field plate electrode comprises a different material than the strain-inducing material. The trench adjoins a region of the semiconductor substrate through which current flows in a first direction during operation of the semiconductor device. The strain-inducing material reaches an upper surface of the field plate electrode and terminates before reaching a lower surface of the field plate electrode, such that part of the field plate electrode is interposed between a lower surface of the strain-inducing material and a bottom of the trench. Additional device embodiments and methods of producing the device are also described.
A controller for a battery-powered PMSM (permanent magnet synchronous motor) is described. In one embodiment, the controller includes: a first controller configured to generate a flux generating voltage reference for the PMSM; a second controller configured to generate a torque generating voltage reference for the PMSM; and a battery capacity adjustment factor configured to adjust the flux generating voltage reference and the torque generating voltage reference, based on capacity of the battery. In another embodiment, the controller includes: a rotor position estimator configured to estimate a rotor electrical angle and a rotor electrical speed of the PMSM, based on a flux generating voltage reference for the PMSM, a torque generating voltage reference for the PMSM, a flux generating current feedback for the PMSM, and a torque generating current feedback for the PMSM, the rotor position estimator including a speed feedforward term. The controller embodiments are not necessarily mutually exclusive.
A power converter circuit is disclosed. The power converter circuit includes: a first regulated power converter having a first input and a first output; and a second regulated power converter having a second input and a second output. The inputs are configured to be coupled to a source, and the outputs are configured to be coupled to a load. The inputs are coupled in series; the outputs are coupled in parallel. The first regulated power converter is a regulated hybrid converter configured to transfer energy from the first input to the first output through at least one magnetic component and at least one capacitive component.
A package includes a functional chip configured to provide an electric function involving an electric current, and a sense chip configured to provide an electric sense signal which characterizes the electric current. The functional chip and the sense chip are physically separate chips.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
G01R 31/26 - Testing of individual semiconductor devices
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
A semiconductor device includes a diode section. At least some of a plurality of diode mesas in the diode section are coupled to the drift region via a second anode region electrically connected to the emitter terminal of the semiconductor device. The second anode region extends deeper along the vertical direction as compared to trenches in the diode section.
H10D 84/60 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of BJTs
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
Disclosed is a method for operating a switching element connected in parallel with a rectifier element and an electronic circuit. The method includes charging a capacitor coupled to load path nodes of an electronic switch, wherein the electronic switch includes a switching element and a rectifier element connected in parallel with a load path of the switching element and between the load path nodes; allowing the capacitor to be discharged via the load path nodes of the electronic switch; and comparing a capacitor voltage across the capacitor with a first voltage level.
H03K 3/012 - Modifications of generator to improve response time or to decrease power consumption
H03K 17/60 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being bipolar transistors
59.
METHOD OF DETERMINING A TEMPERATURE OF A TRANSISTOR, TRANSISTOR DRIVER DEVICE AND SYSTEM
A method of determining a temperature of a transistor is provided. The method includes providing a current pulse of a predefined length and a predefined current magnitude to a control terminal of the transistor, and measuring a voltage at the control terminal. The temperature of the transistor is then determined based on the measured voltage.
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
G01K 7/01 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using semiconducting elements having PN junctions
A method and a semiconductor die are disclosed. The method includes forming a semiconductor die based on a wafer. The wafer includes a semiconductor layer and a sacrificial layer formed on opposite sides of an insulating layer. The method includes: forming a separation structure that includes a separation trench laterally surrounding a die region in the first semiconductor layer of the wafer and that vertically extends from a first surface of the wafer through the semiconductor layer to the insulating layer of the wafer; removing the sacrificial layer; and detaching the die region along the separation structure to separate the semiconductor die from the wafer.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
A semiconductor package includes an encapsulant having a peripheral side wall with at least one recess therein. The recess has an inner bottom surface and side walls extending between the inner bottom surface and an outer surface of the peripheral side wall of the encapsulant. At least one lead extends from the inner bottom surface into the recess. The lead is spaced from the side walls of the recess.
An apparatus such as a switch circuit providing current monitoring as discussed herein may include a first switch fabricated via first semiconductor technology, a second switch fabricated via second semiconductor technology, and current monitor circuitry. The current monitor circuitry may include the second switch. The current monitor circuitry can be configured to provide mirroring of a magnitude of second current through the second switch with respect to a magnitude of first current through the first switch. The apparatus as discussed herein may further include a signal converter operative to convert a first control signal controlling the first switch into a second control signal operative to control the second switch. Additionally, the apparatus as discussed herein may include a gate drive voltage compensation circuit and/or a temperature compensation circuit to provide compensation and a more accurate output signal indicating a magnitude of the first current through the first switch.
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
A power converter includes: a first circuit path including a first transformer winding connected in series with a first capacitor between a first node of the first circuit path and a second node of the first circuit path, the second node of the first circuit path is connected to an output node of the power converter; a second circuit path including a second transformer winding connected in series with a second capacitor between a first node of the second circuit path and a second node of the second circuit path, the second node of the second circuit path is connected to the output node of the power converter. First switch circuitry controls connectivity of the first node of the first circuit path to the second node of the first circuit path. Second switch circuitry controls connectivity of the first node of the second circuit path to the second node of the second circuit path.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
According to one configuration, an inductor assembly comprises: a first material, second material, and one or more electrically conductive paths. A first electrically conductive path extends through the first material. In one example, the first material is not magnetically permeable material or has a low magnetic permeability. The second electrically conductive path extends through the second material. In one example, the second material is magnetically permeable material and has a higher magnetic permeability than the first material. The inductor assembly as discussed herein can be implemented in a circuit in which the second electrically conductive path supports current in one direction while the first electrically conductive path 10 (such as a return path) can be configured to support current in a second direction opposite the first direction.
H01F 41/02 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformersApparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets
H02M 3/00 - Conversion of DC power input into DC power output
65.
SEMICONDUCTOR PACKAGE WITH CARRIER SUPPORT STRUCTURE
A method of forming a semiconductor package includes providing a lead frame that comprises a plurality of leads connected with a peripheral structure; providing a plurality of die pads each having a power switching device mounted thereon; providing a first circuit carrier with a controller device mounted thereon, the controller device being configured to control a switching operation of the power switching devices; forming a mechanical connection between the first circuit carrier and the lead frame; and performing an encapsulation process to form an electrically insulating encapsulant body that encapsulates the power switching devices and the controller device, wherein the first circuit carrier is physically supported by the mechanical connection prior to performing the encapsulation process, and wherein forming the mechanical connection comprises an electrical interconnection processing technique.
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
66.
HYBRID SWITCHED CAPACITOR CONVERTER WITH FLYING CAPACITOR
An apparatus such as a power converter includes: a first circuit path including first windings coupled in series, each of the first windings magnetically coupled to each other; a second circuit path including second windings coupled in series, each of the second windings magnetically coupled to each other; and switch circuitry operative to selectively switch between electrically connecting a flying capacitor in series with the first circuit path and electrically connecting the flying capacitor in series with the second circuit path. A controller controls the switch circuitry in the power converter to convert an input voltage into an output voltage.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
67.
SWITCHED MODE ELECTRICAL POWER SUPPLIES AND CORRE-SPONDING CONTROL
An electrical power supply device configured for providing a load current, the electrical power supply device comprising: a half bridge circuit comprising a high-side power transistor and a low side power transistor; a gate driver circuit configured to drive the high-side power transistor and the low-side power transistor alternatively in a first switching mode; a load current sensing device, wherein the load current sensing device comprises for sensing a portion of the load current in the second switching mode a low-side sensing transistor and a low-side regulator; a load current sensing refining device, wherein the load current sensing refining device comprises a low-side current adding device configured for adding a low-side refining current to a low-side feedback loop during the second switching mode in order to refine a low-side sensing signal for the portion of the load current in the second switching mode at the output of the low-side regulator.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
68.
SEMICONDUCTOR ARRANGEMENT AND METHOD FOR MONITORING A SEMICONDUCTOR ARRANGEMENT
A semiconductor arrangement and a method for operating a semiconductor arrangement are disclosed. The semiconductor arrangement includes: a plurality of semiconductor bodies; a housing in which the plurality of semiconductor bodies are arranged; and a sensor circuit including a plurality of temperature sensors. At least one of the temperature sensors is integrated in each of the semiconductor bodies. Each of the temperature sensors is connected between a first pin and a second pin of the housing.
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
G01K 7/01 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using semiconducting elements having PN junctions
G01K 13/00 - Thermometers specially adapted for specific purposes
69.
TRANSISTOR PACKAGE WITH AREAL INTERNAL INTERCONNECT
A semiconductor chip package includes a semiconductor transistor chip having a first side and a second side opposite the first side. The first side includes first load current chip pads and second load current chip pads. An interconnect substrate includes a first metal layer, a second metal layer, and an insulating material disposed between the first metal layer and the second metal layer. The first metal layer includes a pattern of holes, the second metal layer includes a pattern of protrusions, and the protrusions pass through the holes. The semiconductor transistor chip is mounted on the interconnect substrate with the first side facing the interconnect substrate. The first metal layer is connected to a plurality of the first load current chip pads and the second metal layer is connected via the pattern of protrusions to a plurality of the second load current chip pads.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
H10D 80/20 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising capacitors, power FETs or Schottky diodes
A method of fabricating a lead frame packaged device includes providing a lead frame including at least one wire bond area and a plurality of leads extending from the at least one wire bond area, wherein each wire bond area includes a plurality of bond pads; depositing a nickel plating on each wire bond area to form nickel-plated bond pads; depositing a plating masking material on the nickel plating to form a masking layer on the nickel plating; depositing a tin plating on the lead frame, including on the plurality of leads, wherein the plating masking material prevents the tin plating from making contact with the nickel plating; removing the masking layer from the lead frame to expose the nickel plating on each wire bond area; attaching a die to the lead frame; and forming wire bonds between the die and the nickel-plated bond pads.
An ion trap device includes a dielectric substrate and a via hole extending through the dielectric substrate from a first main surface of the dielectric substrate to a second main surface of the dielectric substrate. The ion trap device further includes an electrically conductive etch stop layer arranged on the first main surface of the dielectric substrate, the etch stop layer covering the via hole. The ion trap device further includes a metal layer of an ion trap at least partially arranged on the etch stop layer and an electrically conductive material arranged in the via hole. The etch stop layer electrically couples the electrically conductive material and the metal layer.
G21K 1/14 - Arrangements for handling particles or ionising radiation, e.g. focusing or moderating using charge exchange devices, e.g. for neutralising or changing the sign of the electrical charges of beams
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
72.
SEMICONDUCTOR DEVICE WITH HIGH-VOLTAGE SEMICONDUCTOR ELEMENT
A semiconductor device includes a high-voltage semiconductor element with a first doped region of a first conductivity type. The first doped region at least partly laterally surrounds a central portion. The central portion and the first doped region may form an auxiliary junction. A second doped region of a second conductivity type at least partly laterally surrounds the first doped region. A drift region of the first or second conductivity type extends from the first doped region to the second doped region, and forms a first pn junction with the first doped region or the second doped region.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A chip package includes a first plate-shaped metal carrier structure, a second plate-shaped metal carrier structure and a third plate-shaped metal carrier structure. The chip package further includes a first GaN chip sandwiched between the first metal carrier structure and the second metal carrier structure, and a second GaN chip sandwiched between the second metal carrier structure and the third metal carrier structure. The chip package is configured to be attached to an application board in an orientation in which the plate-shaped metal carrier structures and the GaN chips are inclined vertical relative to the application board.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
74.
TRANS-INDUCTOR VOLTAGE REGULATOR (TLVR) INDUCTOR MODULE AND POWER ELECTRONICS ASSEMBLY INCLUDING THE TLVR INDUCTOR MODULE
A trans-inductor voltage regulator (TLVR) inductor module includes: a magnetic core; a first winding embedded in the magnetic core; a second winding embedded in the magnetic core and inductively coupled to the first winding; a third winding embedded in the magnetic core; a fourth winding embedded in the magnetic core and inductively coupled to the third winding; and a first integrated metallic connector that connects the second winding and the fourth winding in a series loop. A power electronics assembly that includes the TLVR inductor module is also described.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
Driver circuitry configured to operate in a first mode or a second mode to drive a power switch is described. The driver circuitry is operable in a first mode in which the driver circuitry controls the power switch to turn off when, or slightly before, a current through the secondary side switch crosses zero. The driver circuitry is also operable in a second mode in which the driver circuitry controls the power switch to turn on and turn off based a driver input signal from a controller.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
B60L 53/22 - Constructional details or arrangements of charging converters specially adapted for charging electric vehicles
H02J 7/02 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from AC mains by converters
An ion shuttling system includes a plurality of first electrodes connected to a system configured to selectively provide an ion movement control voltage to each electrode of the plurality of first electrodes, a voltage source configured to provide one or more compensation voltages, a plurality of compensation electrodes comprising a plurality of compensation electrode pairs, where each compensation electrode pair of the plurality of compensation electrode pairs is associated with one or more different first electrodes of the plurality of first electrodes, and a plurality of switches, where each switch of the plurality of switches is connected at a respective first node to a compensation electrode of the plurality of compensation electrodes and is configured to selectively connect the respective compensation electrode to the voltage source.
A resistive current measurement device comprises: a substrate comprising a first conductive layer and a second conductive layer that is separate from the first conductive layer; a plurality of resistors arranged at the substrate, wherein each resistor of the plurality of resistors is connected between the first conductive layer and the second conductive layer; and a first measurement terminal connected to the first conductive layer and a second measurement terminal connected to the second conductive layer, wherein the first and second measurement terminals are configured for connecting a voltage measurement device for measuring a voltage across the plurality of resistors.
G01R 1/20 - Modifications of basic electric elements for use in electric measuring instrumentsStructural combinations of such elements with such instruments
G01R 31/26 - Testing of individual semiconductor devices
78.
MULTI-PHASE POWER SUPPLY SYSTEM WITH SELF CURRENT BALANCE CAPABILITY
An apparatus includes a power converter controller. The power converter controller receives first input. A magnitude of the first input is derived from combined output current supplied from multiple power converters to a load. The power converter controller also receives second input indicating a magnitude of first output current supplied from a first power converter of the multiple power converters to the load. The combined output current includes the first output current supplied from the first power converter to the load. Based on a comparison of the second input to the first input, the power converter controller adjusts a leading edge and/or a trailing edge of a first pulse width modulation control signal. Additional examples of supporting signal edge control are discussed herein.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
A method of manufacturing a semiconductor device includes forming a plurality of patterns of metal structures in a dielectric inorganic substrate wafer. The metal structures are accommodated in recesses of the dielectric inorganic substrate wafer and at least partly connect through the dielectric inorganic substrate. The method further includes providing a semiconductor wafer comprising a front side and a backside, wherein a plurality of electrodes is disposed on the front side of the semiconductor wafer. The front side of the semiconductor wafer is bonded to the dielectric inorganic substrate wafer to form a composite wafer, wherein the plurality of patterns of metal structures is connected to the plurality of electrodes. The composite wafer is separated into composite chips.
H01L 21/463 - Mechanical treatment, e.g. grinding, ultrasonic treatment
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
80.
CONSTANT POWER BUCK-BOOST POWER CONVERTER AND METHODS
An apparatus as discussed herein can be configured to include a first circuit operative to receive an input voltage supplied by an input voltage source. A series circuit path including an inductor and a second circuit also receives the input voltage. The first circuit may be coupled to the second circuit. The series circuit path including the inductor and the second circuit produces a respective output voltage to power load based at least in part on input from the first circuit.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
An apparatus as discussed herein can be configured to include a first analog-to-digital converter operative to convert a first analog voltage into a first digital signal; a digital-to-analog converter operative to convert the first digital signal into a second analog voltage; a switched capacitor circuit coupled to the digital-to-analog converter, the switched capacitor circuit is operative to store a sample of the second analog voltage; and a second analog-to-digital converter operative to convert an analog error voltage into a second digital signal, the analog error voltage based on a difference between the sample of the second analog voltage received from the switched capacitor circuit and a sample of the first analog voltage.
A right-hand semiconductor device includes a control connector, a first load connector, and a second load connector, the connectors being arranged in the same plane and protruding out of a package of the semiconductor device, forming the fingers of a right-hand arrangement. The control connector is followed by the first load connector and the first load connector is followed by the second load connector. The second load connector is a thumb of the right-hand arrangement. The package includes a top side and a bottom side opposite the top side. The right-hand arrangement is seen from a topside view.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
A gate driver system includes a plurality of gate drivers, each gate driver having a fault output node switchable between a fault state indicating a detected fault by the respective gate driver and an operating state. Timing arrangements are provided for each of the gate drivers, with each timing arrangement configured to switch a common node to a first state, responsive to the fault output node of the respective gate driver being set to the fault state (e.g., responsive to a trigger event). Then, after a predetermined time period having elapsed from a trigger event, the common node is released from the first state. As the predetermined time period for each of the timing arrangements is different, the amount of time between the trigger event and the common node being released from the first state may be measured to identify which gate driver among gate drivers that reported a fault.
H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
H03K 17/30 - Modifications for providing a predetermined threshold before switching
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
An ion trap device in which a return line portion and one or more signal line portions, for driving an electrode of the ion trap device, are configured to run alongside one another in close proximity for a majority of the length of the return line portion.
In a power semiconductor device, a deep semiconductor region is provided in addition to a barrier structure. The barrier structure is spatially separated from a trench structure in an active region and arranged in a transition region between the active region and an edge termination region of the power semiconductor device.
An application board includes a first main face and a plurality of electrical contact areas disposed on the first main face. The electrical contact areas include one or more first electrical contact areas and one or more second electrical contact areas. A recess such as a slot or a groove is disposed in the first main face. The recess spaces a first portion of the application board from a second portion of the application board. The first electrical contact areas are disposed on the first portion of the application board and the second electrical contact areas are disposed on the second portion of the application board.
A method of controlling a BLDC (brushless DC) motor having a plurality of phases each energized by a different leg of an inverter includes: generating a trapezoidal current reference signal for each phase of the BLDC motor that has a current ramp-up phase with a step profile along which the trapezoidal current reference signal has zero slope for a portion of the current ramp-up phase and non-zero slope elsewhere, and a current ramp-down phase with a step profile along which the trapezoidal current reference signal has zero slope for a portion of the current ramp-down phase and non-zero slope elsewhere; and adjusting a duty cycle of a switching control signal for each leg of the inverter, such that a current through each inverter leg is forced to follow the trapezoidal current reference signal for the corresponding phase. A corresponding controller is also described.
An apparatus as discussed herein can be configured to include a delay line analog-to-digital converter operable to convert an analog error voltage into a digital error voltage signal. Additionally, the apparatus can be configured to include an integrator function as well as a digital to analog converter. The integrator function is operable to produce a digital value representative of an analog input voltage, the digital value adjusted based on samples of the digital error voltage signal generated by the delay line analog-to-digital converter. The digital-to-analog converter operative to convert the digital value received from the integrator function into a second analog voltage, the analog error voltage being a difference between the input voltage and the second analog voltage.
A semiconductor device includes a semiconductor body having a first major surface, a source region of a first conductivity type, a body region of a second conductivity type, and a drift region of the first conductivity type. A first trench extends from the first major surface of the semiconductor body into the semiconductor body along a first direction. A first gate electrode is located in the first trench. A second trench extends from the first major surface of the semiconductor body into the semiconductor body. A conductive material is located in the second trench. The conductive material is in electrical contact with the source region and the body region of the semiconductor body. A first sidewall of the second trench corresponds to a first lattice plane of the semiconductor body.
A semiconductor device includes: a substrate; a die having a first and a second surface, the die being embedded in the substrate; a first heatsink arranged at a first surface of the substrate; and a second heatsink arranged at a second surface of the substrate. The substrate includes a thermally conductive structure arranged between the first surface of the die and the first heatsink, and a thermally isolating structure arranged between the second surface of the die and the second surface of the substrate opposite the first surface.
A device for trapping one or more ions includes a substrate and an application board. The substrate includes: a metal layer structure having a first electrode and a second electrode of an ion trap; a first terminal electrically connected to the first electrode; and a second terminal electrically connected to the second electrode. The application board includes circuitry and the substrate is mounted on the application board, such that the first terminal and the second terminal of the substrate are electrically connected to the circuitry of the application board.
One example in this disclosure includes a winding driver assembly comprising: a substrate; a first switch affixed to a first surface of the substrate; a second switch affixed to a second surface of the substrate, the first switch and the second switch connected in series via a first circuit path extending through the substrate; and a capacitor disposed in series in a second circuit path extending through the substrate, the first switch and the second switch connected in series via the second circuit path. The placement of the component such as first switch, second switch, first circuit path, second circuit path, etc., discussed herein uses a respective inductive loop associated with the winding driver assembly.
A power semiconductor device includes: a semiconductor body configured to conduct a forward load current between first and second load terminals; a main control terminal; an auxiliary control terminal isolated from the main control terminal; a control electrode structure including: main control electrodes electrically connected to the main control terminal and configured to control the forward load current, and auxiliary control electrodes electrically connected to the auxiliary control terminal and configured to control an overload current; and an overload structure electrically connected between the second load terminal and the auxiliary control terminal, the overload structure configured to apply an auxiliary control voltage greater than a threshold voltage to the auxiliary control trench electrodes, if a voltage between the first and second load terminals exceeds a maximal value and/or if the voltage between the second load terminal and the auxiliary control terminal is above a breakthrough voltage of the overload structure.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
94.
TRANSISTOR DEVICE HAVING A CAPACITIVE VOLTAGE DIVIDER CIRCUIT
A transistor device includes: a substrate; an epitaxial layer stack formed on the substrate, the epitaxial layer stack including a heterojunction between two epitaxial layers having different band gaps, the heterojunction defining a channel region of the transistor device; a source terminal electrically connected to a source region of the epitaxial layer stack; a drain terminal electrically connected to a drain region of the epitaxial layer stack; a gate terminal electrically connected to a gate structure laterally between the source region and the drain region; a substrate terminal electrically connected to the substrate; and a capacitive voltage divider circuit electrically connected between the source region and the substrate. In a blocking state of the transistor device, the capacitive voltage divider circuit is configured to clamp the electric potential of the substrate to a positive value. Additional transistor device embodiments are described.
H03K 17/56 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
95.
SYNCHRONOUS RECTIFIER CONTROL FOR SECONDARY SIDE TURN-ON PROTECTION
A controller associated with a power supply determines a first ratio value. The first ratio value may be a ratio of a second time duration with respect to a first time duration, where the second time duration is a measured time duration associated with demagnetizing of a transformer in a first control cycle. The first time duration may be a measured time duration of activating a first switch in the first control cycle, where activation of the first switch operative to control a magnitude of primary current through a primary winding of the transformer. For second control cycle occurring subsequent to the first control cycle, the controller calculates an ON-time duration for activating the second switch based on the determined first ratio value.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/38 - Means for preventing simultaneous conduction of switches
A transport box for an ion trap module includes a base including a mounting surface configured to mount the ion trap module and a lid configured to be attached to the base to form a hermetically sealed first volume in the transport box. The ion trap module is enclosable in the first volume. The base and the lid are manufactured from at least one of a metal, a metal alloy, and a low-outgassing polymer.
B01D 53/04 - Separation of gases or vapoursRecovering vapours of volatile solvents from gasesChemical or biological purification of waste gases, e.g. engine exhaust gases, smoke, fumes, flue gases or aerosols by adsorption, e.g. preparative gas chromatography with stationary adsorbents
A half-bridge gate driver includes a phase node terminal configured to be coupled to a phase node to which a high-side transistor and a low-side transistor of a half-bridge are coupled; a diode comprising an anode and a cathode, wherein the cathode is coupled to the phase node terminal; and a comparator comprising a first input terminal coupled to the anode of the diode for receiving a measurement value indicative of a phase voltage at the phase node terminal, a second input terminal coupled to a threshold source for receiving a threshold, and an output terminal configured to output a comparison result indicating whether the measurement value satisfies the threshold. The phase node terminal is configured to be connected to a high-side supply potential by the high-side transistor, and is configured to be connected to a low-side supply potential by the low-side transistor.
H02M 1/32 - Means for protecting converters other than by automatic disconnection
G01R 31/26 - Testing of individual semiconductor devices
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 1/36 - Means for starting or stopping converters
H02M 7/539 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters with pulse width modulation
According to some embodiments, a motor controller has a first controller operating in a start-up mode and configured to apply a high frequency injection signal to a motor, extract a motor parameter based on a measured response to the high frequency injection signal, determine an alignment error of the motor based on the measured response, and correct the motor parameter based on the alignment error to generate a corrected motor parameter, and a second controller operating in a control mode and configured to control the motor based on the corrected motor parameter
Disclosed is a coupler arrangement. The coupler arrangement includes a coupler having: a first planar conductor and a second planar conductor that are inductively or dielectrically coupled and spaced apart from each other in a first direction; an insulating layer above the first planar conductor; and a field plate layer above the insulating layer. The field plate layer is connected between a terminal of the first planar conductor and a reference terminal that is spaced apart from the first planar conductor.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
A method of parameter estimation for a PMSM (permanent magnet synchronous motor) includes: iteratively revising an estimate of an inductance parameter of the PMSM, until the estimate either converges to a predetermined accuracy level or diverges; and controlling a magnitude of phase currents injected into the PMSM during each iteration of revising the estimate of the inductance parameter. Additional methods of PMSM parameter estimation are described, including rotor flux linkage estimation.
