A semiconductor device includes: a trench formed in a surface of a semiconductor substrate and extending lengthwise in a direction parallel to the surface; a body region adjoining the trench; a source region adjoining the trench above the body region; a drift region adjoining the trench below the body region; a field electrode in a lower part of the trench and separated from the substrate; and a gate electrode in an upper part of the trench and separated from the substrate and the field electrode. A first section of the field electrode is buried below the gate electrode in the trench. A second section of the field electrode transitions upward from the first section in a direction toward the surface. The separation between the second section and the gate electrode is greater than or equal to the separation between the first section and the gate electrode.
A power converter assembly for transformer assembly as discussed herein may include multiple electrically conductive paths such as a first electrically conductive path, a second electrically conductive path, and a third electrically conductive path. The first electrically conductive path extends through the magnetically permeable material. The second electrically conductive path extends through the magnetic permeable material. The second electrically conductive path is inductively coupled to the first electrically conductive path via the magnetically permeable material. The third electrically conductive path is disposed in the magnetically permeable material and extends along the first electrically conductive path and the second electrically conductive path.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformersApparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
3.
MODULATION SIGNAL GENERATION AVOIDING FORBIDDEN REGIONS
An apparatus for generating an applicable control signal, including: a control module operable to generate a reference control signal that avoids, but is effectively within, a forbidden region by alternating the reference control signal between upper and lower levels of the forbidden region; an error determination module operable to generate an error signal based on a difference between the reference control signal and the applicable control signal; and a compensation module operable to noise-shape the error signal to suppress a portion of the error signal resulting from avoiding the forbidden region, and to modify the reference control signal based on the noise-shaped error signal, wherein the modified reference control signal is output by the apparatus as the applicable control signal for generating a modulation signal.
H02P 7/29 - Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual DC dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices using semiconductor devices controlling armature supply only using pulse modulation
4.
MOLDED POWER DIE PACKAGE WITH VERTICAL INTERCONNECT
A power die package includes a power die having a plurality of bond pads at an upper surface of the power die. The package further includes a plurality of contact structures. A contact structure includes: a bond wire bonded to one of the plurality of bond pads and folded back to the bond pad to form a closed loop, or at least three bumps laterally spaced from one another and disposed on one or more bond pads; and a continuous longitudinally extended electrically conductive element connected to the at least three bumps in at least three contact positions. The conductive element bends away from the power die between pairs of consecutive contact positions. The package further includes a mold compound partially encapsulating the contact structure. The mold compound includes an outer surface facing away from the power die. The contact structure is partially exposed at the outer surface.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
A method of balancing voltages on flying capacitors in a multilevel power converter is provided (along with an associated controller). The power converter includes one or more flying capacitors. Pairs of switches in the power converter are controlled by pulse width modulated (PWM) control signals. The different pairs of switches are controlled by PWM control signals having a phase/timing shift between them. To balance the voltage on the one or more flying capacitors, one set of pulses can be widened or narrowed while another set is widened or narrowed. To change their widths, one edge of each pulse is modulated, while the other edge is unchanged. More specifically, the leading edge of one set of pulses is modulated, while the trailing edge of the other set of pulses is modulated.
H02M 7/483 - Converters with outputs that each can have more than two voltage levels
H02M 7/5395 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
A molded power package includes a laser-activatable mold compound having laser-activated regions which are plated with an electrically conductive material to form metal pads and/or metal traces at a first side of the mold compound. A semiconductor power die with bond pads is embedded in the laser-activatable mold compound. A bond pad interconnect electrically connects the bond pads of the semiconductor power die to the metal pads and/or metal traces at the first side of the laser-activatable mold compound. The semiconductor power die is mounted on a carrier section of a leadframe. A carrier interconnect section of the leadframe integral with the carrier section electrically connects the carrier section to the metal pads and/or metal traces at the first side of the laser-activatable mold compound. An upper surface of the carrier interconnect section is at a height that is elevated relative to an upper surface of the carrier section.
A multi-phase resonant power converter includes: a power stage on a primary side of the multi-phase resonant power converter, the power stage including bridge converter legs each configured to receive an AC input voltage and implement a separate phase of the power converter; a transformer device having a primary side winding for each bridge converter leg and a secondary side winding for each primary side winding; a power circuit electrically connected to the secondary side windings on a secondary side of the multi-phase resonant power converter; a primary-side controller configured to operate the bridge converter legs at a switching frequency; and a separate resonant tank electrically connected to a midpoint of each bridge converter leg. Each resonant tank includes a resonant capacitor in series with the primary side winding for that bridge converter leg. A resonant frequency of each resonant tank is tuned to within +/−50% of the switching frequency.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 3/00 - Conversion of DC power input into DC power output
8.
VOLTAGE CONTROLLER USING VOLTAGE FEEDBACK AND POWER FEED-FORWARD
A method of controlling a switched-mode power supply (SMPS) based on a pulse-width modulation (PWM) control signal is provided to convert an input voltage to an output voltage. The method includes generating an error signal based on a difference between the output voltage and a target output voltage; filtering the error signal to generate a filtered error signal; generating a feed-forward signal based on at least one feed-forward parameter related to at least one of the output voltage, the input voltage, an output power of the SMPS, or an output current corresponding to the output voltage; adding the feed-forward signal and the filtered error signal to generate an integrator input signal; and applying a nonlinear integration function to the integrator input signal to generate the PWM control signal.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 1/12 - Arrangements for reducing harmonics from AC input or output
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
9.
ELECTRONIC MODULE HAVING A CLIP CONNECTED TO A SEMICONDUCTOR PACKAGE
An electronic module includes a semiconductor package, and a clip connected to the semiconductor package. The clip is connected to or includes at least one fastening element which is configured to make a connection to an external heatsink.
H01L 25/11 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in subclass
10.
POWER DELIVERY CONTROL AND OVER CURRENT PROTECTION
A power supply as discussed herein includes a controller. The controller receives an output voltage feedback signal outputted from a resonant power converter. The output voltage feedback signal tracks a magnitude of an output voltage outputted from the resonant power converter to power a load. An error voltage generator generates an error voltage signal based on a comparison of the output voltage feedback signal to a setpoint reference voltage. The output voltage feedback signal derives a control period setting from an error voltage. The controller controls switching of switches in the resonant power converter in accordance with the derived control period setting.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A power converter assembly includes a first circuit board and a second circuit board. The first circuit board includes power converter circuitry operative to control conversion of an input voltage into an output voltage. The second circuit board is disposed substantially orthogonal to the first circuit board. The second circuit board is operative to: i) receive the output voltage, and ii) convey the output voltage to an output of the second circuit board such as a host circuit board. Additionally, the power converter assembly can be configured to include an over-mold assembly operative to provide connectivity between the first circuit board and the second circuit board. More specifically, the over-mold assembly can be configured to include an inductor component to output the output voltage to the second circuit board based on current received by the inductor component from the input voltage received over a first electrically conductive path between the second circuit board and the first circuit board.
H02M 3/00 - Conversion of DC power input into DC power output
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
An intelligent power module includes a plurality of controllable semiconductor devices that each include a control electrode, a gate driver configured to generate one or more control signals for one or more of the plurality of controllable semiconductor devices, and one or more bridging devices that each include a housing, a plurality of contact pads arranged on an outside of the housing, and one or more electrical connections arranged inside the housing. Each of the one or more electrical connections electrically couples two of the plurality of contact pads to each other. At least one of the bridging devices is electrically coupled between the control electrodes of one or more of the plurality of controllable semiconductor devices and the gate driver, respectively, and is configured to route one or more control signals from the gate driver to the control electrodes of the one or more controllable semiconductor devices.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/367 - Cooling facilitated by shape of device
H01L 25/11 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in subclass
13.
INVERTER SYSTEMS FEATURING HYBRID TCM/CCM MODULATION SCHEME
To reduce switching losses, an inverter circuitry of this disclosure may operate using triangular current mode (TCM) control for the semiconductor devices to achieve zero voltage switching (ZVS) at the turn-on of the semiconductor switches. In contrast to other techniques, such as operating the inverter circuitry in continuous conduction mode (CCM), switching devices experience hard switching (usually associated to body-diode hard commutation) at turn-on, and therefore experience the associated switching losses. The inverter circuitry of this disclosure is controlled by processing circuitry, which is configured to apply a smart frequency modulation scheme that enables TCM operation.
H02M 7/529 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only with automatic control of output waveform or frequency by pulse width modulation using digital control
H02M 1/084 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters using a control circuit common to several phases of a multi-phase system
H02M 7/5387 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
14.
SINGLE ENDED CONVERSIONS ON A TRUE DIFFERENTIAL ANALOG TO DIGITAL CONVERTER (ADC)
This disclosure describes analog to digital converter (ADC) circuitry configured to receive either a differential input signal or a single-ended (SE) input signal and output a digital representation of the input signal using the full-scale of the ADC output. The ADC circuitry of this disclosure includes a true differential ADC that, when receiving a SE input signal is configured to make two adjustments to the ADC characteristic. One adjustment is to shift the ADC characteristic by the reference voltage of the ADC, e.g., Varef. The second adjustment is to multiply the input signal by two, e.g., to double the input signal magnitude.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
15.
TRANS-INDUCTANCE VOLTAGE REGULATORS AND TRANSFORMER ASSEMBLIES
A power converter assembly may include multiple electrically conductive paths such as a first electrically conductive path, a second electrically conductive path, and a third electrically conductive path. The first electrically conductive path extends through first magnetically permeable material; the second electrically conductive path extending through second magnetically permeable material. The third electrically conductive path extends through both the first magnetically permeable material and the second magnetically permeable material. For example, the first electrically conductive path may be disposed alongside and in parallel with a first portion of the third electrically conductive path in the first magnetically permeable material; the second electrically conductive path may be disposed alongside and in parallel with a second portion of the third electrically conductive path in the second magnetically permeable material.
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
According to some embodiments, a motor controller for controlling a motor includes a position interface configured to receive a motor position signal indicative of a position of the motor, and a pulse width modulation (PWM) unit configured to generate a PWM signal for driving the motor. An angle and speed unit is configured to determine a speed and a position of the motor based on transitions in the motor position signal, wherein transition intervals are defined between the transitions, determine a PWM count of cycles in the PWM signal during a first transition interval of the transition intervals, and update the position of the motor during a second transition interval of the transition intervals based on the PWM count to generate an updated position. A controller is configured to send a control signal for controlling the motor to the PWM unit based on the speed and the updated position.
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters with pulse width modulation
17.
METHOD FOR FORMING ELECTRODES, SEMICONDUCTOR DEVICE AND SEMICONDUCTOR WAFER
Disclosed is a method for forming electrodes, a semiconductor device, and a semiconductor wafer. The semiconductor wafer includes: a plurality of semiconductor bodies and kerf regions arranged between the semiconductor bodies; at least one device electrode arranged above at least one of the semiconductor bodies; and at least one kerf electrode arranged above at least one of the kerf regions. The at least one device electrode includes a first device electrode layer patterned from a first electrically conducting layer and a second device electrode layer patterned from a second electrically conducting layer different from the first electrically conducting layer. The at least one kerf electrode includes a first kerf electrode layer patterned from the first electrically conducting layer and is devoid of a second kerf electrode layer.
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 25/11 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in subclass
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
A lateral high voltage semiconductor device includes a semiconductor substrate with a frontside and a semiconductor element. The semiconductor element includes: a first semiconductor region of a first conductivity type formed within the semiconductor substrate; a second semiconductor region formed within the semiconductor substrate and spaced apart from the first semiconductor region in a first lateral direction parallel to the frontside; and an extension region adjoining the second semiconductor region. The semiconductor device is configured to control a load current between the first and second semiconductor regions. The extension region extends along the frontside of the semiconductor substrate and includes at least one mesa protruding at the frontside of the semiconductor substrate.
Disclosed is a method forming an electrode and a transistor device. The transistor device comprises a gate runner (41) and a drain runner (43) that are spaced apart from each other. The gate runner and the drain runner comprise a respective first device electrode layer and a second device electrode layer (421, 423), wherein, in the gate runner (41), the first device electrode layer (411) protrudes for a first distance (p11) in a direction facing away from the drain runner (43) and protrudes less than the first distance (p11) below the second device electrode layer (421) in the direction of the drain runner (43), and, in the drain runner (43), the first device electrode layer (413) protrudes for a second distance (p31) different from zero below the second device electrode layer (423) in the direction of the gate runner (41).
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/283 - Deposition of conductive or insulating materials for electrodes
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
The disclosure relates to a semiconductor die, comprising a semiconductor body; a semiconductor device in an active area of the semiconductor body; an edge termination structure arranged laterally between the active area and a lateral edge of the die; a chipping stopper trench; the chipping stopper trench arranged laterally between the edge termination structure and the lateral edge of the die, wherein the chipping stopper trench is unfilled.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/00 - Details of semiconductor or other solid state devices
A method of forming a semiconductor includes forming a superjunction structure comprising a plurality of superjunction columns that alternate in conductivity type along a lateral direction of the semiconductor substrate; and forming a plurality of transistor cells in an active area of the semiconductor substrate, each of the transistor cells being configured to control a vertical current flowing through superjunction structure, wherein forming the transistor cells includes forming source regions and body regions below the source regions; wherein forming the body regions includes forming a body layer extending from a main surface of the semiconductor substrate, wherein a dopant profile of second conductivity type dopants in the body layer increases moving from the main surface into the semiconductor substrate until it reaches a maximum at first depth from the main surface, and wherein the first depth is below a bottom depth of the source regions.
Disclosed is a resistor arrangement and a transistor device with a resistor arrangement. The resistor arrangement includes a resistive layer and first and second contact electrodes each formed on top of the resistive layer and each connected to the resistive layer. The first and second contact electrodes are spaced apart from each other in a first direction. Each of the first and second contact electrodes includes an inner section longitudinally extending in a second direction perpendicular to the first direction. The inner sections of the first and second contact electrodes are at least approximately parallel to each other. At least one of the first and second contact electrodes includes at least one end section adjoining the respective first section and being spaced apart from the other one of the first and second contact electrodes farther than a distance between the inner sections of the first and second contact electrodes.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
Disclosed is a transistor device. In an embodiment, the transistor device includes a plurality of transistor cells and a source electrode. Each of the transistor cells includes: a source region of a first doping type; a body region of a second doping type complementary to the first doping type and adjoining the source region; a gate electrode adjacent to the body region, dielectrically insulated from the body region by a gate dielectric, and arranged in a gate trench extending from a first surface of a semiconductor body into the semiconductor body; and a body contact region adjoining the body region and electrically connected to the source electrode. A distance between the body contact region and the gate dielectric is less than 300 nanometers.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
Disclosed is method for producing a transistor device and a transistor device. The transistor device includes a gate arrangement. The gate arrangement includes: a plurality of gate electrodes, each gate electrode being arranged in a respective gate trench extending from a first surface of a semiconductor body into the semiconductor body and dielectrically insulated from the semiconductor body by a respective gate dielectric; an insulating layer above the first surface of the semiconductor body and the gate electrodes; at least one contact opening in the insulating layer above each gate electrode; a plurality of contact fingers, each contact finger being connected to a respective gate electrode in a respective contact opening; and a connector connecting the contact fingers with each other.
Disclosed is a semiconductor wafer including a test structure. The test structure includes a pad arrangement arranged above a kerf region of a semiconductor wafer. The pad arrangement includes: contact pads arranged in series in a first direction; and two alignment pads arranged in series with the contact pads in the first direction such that the contact pads are arranged between the two alignment pads. Each of the contact pads comprises a metal. Each of the alignment pads is different from each of the contact pads and is configured to be irreversibly deformed when coming into contact with a probe needle.
Disclosed is a transistor device with an edge termination structure and a method. The method includes forming an edge termination structure of a transistor device. Forming the edge termination structure includes: forming an edge trench in an edge region of a semiconductor body such that the edge trench has a trench bottom and an inner trench sidewall facing an inner region of the semiconductor body; and forming a first edge region of a second doping type adjacent to the inner trench sidewall. Forming the first edge region includes implanting dopant atoms of the second doping type at least into the inner trench sidewall.
A method of forming a semiconductor includes forming a superjunction structure comprising a plurality of superjunction columns that alternate in conductivity type along a lateral direction of the semiconductor substrate; and forming a plurality of transistor cells in an active area of the semiconductor substrate, each of the transistor cells being configured to control a vertical current flowing through superjunction structure, wherein forming the transistor cells includes forming source regions and body regions below the source regions; wherein forming the body regions includes forming a body layer extending from a main surface of the semiconductor substrate, wherein a dopant profile of second conductivity type dopants in the body layer increases moving from the main surface into the semiconductor substrate until it reaches a maximum at first depth from the main surface, and wherein the first depth is below a bottom depth of the source regions.
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
29.
A SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING THE SAME
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
30.
SUPERJUNCTION DEVICE WITH IMPROVED EDGE TERMINATION
A semiconductor device includes a semiconductor body including a main surface, a rear surface, and an outer edge side; a superjunction structure including a plurality of superjunction columns that alternate in conductivity type along a lateral direction of the semiconductor body; an active region including a plurality of transistor cells; and a peripheral region laterally separating the active region from the outer edge side, the peripheral region being devoid of the transistor cells; wherein the superjunction structure includes a first cell region and a second cell region, wherein the superjunction columns in the second cell region have a lower dopant concentration than the superjunction columns in the first cell region, wherein the first cell region is disposed within a central part of the active region, and wherein the second cell region at least partially overlaps with an outer part of the active region that adjoins the peripheral region.
An LLC (inductor-inductor-capacitor) converter, including: a primary current sensing circuit operable to sense a primary current of the LLC converter; and a protection circuit coupled between the primary current sensing circuit and power switches of the LLC converter, and operable to increase a switching frequency of the LLC converter when an amplitude of the primary current falls below a predefined low current reference value after a predefined blanking time after a phase transition of the LLC converter.
H02M 1/04 - Circuits specially adapted for the generation of grid-control or igniter-control voltages for discharge tubes incorporated in static converters for tubes with grid control
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A level shifter for a power converter includes: a differential detector; a first transistor having a drain electrically connected to a first node of the differential detector, a gate electrically connected to ground or a fixed DC voltage, and a source; a second transistor having a drain electrically connected to a second node of the differential detector, a gate electrically connected to ground or a fixed DC voltage, and a source; a first circuit configured to dynamically control a voltage applied to the source of the first transistor based on a digital signal input to the level shifter; and a second circuit configured to dynamically control a voltage applied to the source of the second transistor based on the digital signal. The differential detector is configured to translate the digital signal to a different voltage level based on a differential current between the first transistor and the second transistor.
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
33.
GROUP III NITRIDE-BASED TRANSISTOR DEVICE HAVING A P-TYPE SCHOTTKY GATE
In an embodiment, a Group III nitride-based transistor device is provided that includes a Group III nitride-based body and a p-type Schottky gate including a metal gate on a p-doped Group III nitride structure. The p-doped Group III nitride structure includes an upper p-doped GaN layer in contact with the metal gate and having a thickness d1, a lower p-doped Group III nitride layer having a thickness d2 and including p-doped GaN that is arranged on and in contact with the Group III nitride-based body, and at least one p-doped AlxGa1−xN layer arranged between the upper p-doped GaN layer and the lower p-doped Group III nitride layer, wherein 0
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/43 - Electrodes characterised by the materials of which they are formed
According to some embodiments, a method for controlling a motor comprises receiving mechanical angle data and electrical angle data representing a position of the motor, setting an encoder offset between the mechanical angle data and the electrical angle data, determining extremum values of a phase current of the motor, adjusting the encoder offset based on the extremum values to generate an adjusted encoder offset, determining an estimated motor position and an estimated motor speed based on the mechanical angle data, the electrical angle data, and the adjusted encoder offset, and generating a drive signal for the motor based on the estimated motor position and the estimated motor speed.
A semiconductor device includes a vertical power transistor having a plurality of power transistor cells. Each power transistor cell includes a source region at a first main surface of a semiconductor substrate, a drain region at a second main surface of the semiconductor substrate opposite the first main surface, a gate trench extending into the semiconductor substrate from the first main surface, a gate electrode in the gate trench and comprising doped polycrystalline silicon, and a dielectric material separating the gate electrode from the semiconductor substrate. An upper central part of each of the gate electrodes of the power transistor cells is occupied by a metal silicide region that adjoins the doped polycrystalline silicon. A method of producing the semiconductor device is also described.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A semiconductor device includes: a silicon layer having a thickness in a range of 2 μm to 200 μm between a frontside and a backside of the silicon layer; a first device region and a second device region laterally isolated from one another in the silicon layer by an isolation structure that extends from the frontside to the backside of the silicon layer; a first insulation layer on the frontside of the silicon layer; a first patterned metallization on the first insulation layer; a second insulation layer on the backside of the silicon layer; and a second patterned metallization on the second insulation layer. The first patterned metallization provides lateral electrical routing along the frontside of the silicon layer. The second patterned metallization provides lateral electrical routing along the backside of the silicon layer. Additional embodiments of semiconductor devices and methods of producing the semiconductor devices are also described.
The disclosure relates to a semiconductor device having a gate electrode in a vertical gate trench and a channel region laterally aside the gate trench. The gate electrode includes an outer gate region made of an outer gate material, a metal inlay region made of a metal material, and a spacer region. The outer gate material and the spacer region are each different from the metal material. The spacer region, the metal inlay region, and the outer gate region are, at least in a vertical section of the gate electrode, consecutively arranged from a center position within the gate electrode laterally outwardly towards the channel region.
SEMICONDUCTOR PACKAGE INCLUDING ONE OR MORE SOLDER JOINTS ELECTRICALLY AND MECHANICALLY COUPLING FIRST AND SECOND POWER SEMICONDUCTOR CHIPS TO A LEADFRAME PART AND METHOD FOR FABRICATING THEA SEMICONDUCTOR PACKAGE
A semiconductor package includes a power semiconductor chip comprising SiC, and a leadframe part including Cu. The power semiconductor chip is arranged on the leadframe part. A solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part includes at least one intermetallic phase.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/00 - Details of semiconductor or other solid state devices
A transistor device and a method for forming a transistor device are disclosed. The transistor device includes: a semiconductor body; first trenches extending from a first surface of the semiconductor body into the semiconductor body; second trenches extending from the first surface into the semiconductor body; a drift region adjoining each of the second trenches; source regions separated from the drift region by a respective body region; and gate electrodes arranged in the first trenches adjacent to at least one of the body regions and dielectrically insulated from the at least one of the body regions by a gate dielectric. Each of the second trenches is configured to induce a strain in regions of the drift region adjoining the respective second trench.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A system is provided for overcurrent protection of a multi-phase trans-inductance voltage regulator. The multi-phase trans-inductance voltage regulator comprises a plurality of transformers, each transformer comprising a primary inductor and a secondary inductor. The primary inductor of each transformer is provided between a respective input node and a common output node, and the secondary inductors of the plurality of transformers are connected in series. Each input node is connected to a respective one of a plurality of phase inputs. The system includes a first sensor arrangement configured to measure a current flowing through the secondary inductors. The system also includes a controller configured to generate an overcurrent fault signal based at least in part on the measured current flowing through the secondary inductors. Also disclosed is a multi-phase trans-inductance voltage regulator including the system, and an associated controller and method for overcurrent protection of a multi-phase trans-inductance voltage regulator.
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
G01R 15/14 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A controller for a permanent magnet synchronous motor includes a first control loop having a first filter. The first filter has a back-EMF voltage vector input, a magnetic flux vector output with a constant phase shift that is independent of motor speed, and an amplitude response that is inversely proportional to rotor electrical frequency. The first control loop is configured to: generate an adjusted magnetic flux vector from the magnetic flux vector output by the first filter and compensate for the constant phase shift introduced by the first filter; estimate the rotor electrical frequency from the adjusted magnetic flux vector; and feedback a filtered version of the rotor electrical frequency estimate to the first filter as an estimation of the rotor electrical frequency.
A high-electron mobility transistor includes a semiconductor body including a barrier region, a channel region, and a two-dimensional charge carrier gas channel, first and second electrodes that are each in electrical contact with the two-dimensional charge carrier gas channel, and a gate structure laterally in between the first and second electrodes, wherein the gate structure comprises a gate electrode and a first region of doped type III-V semiconductor material in between the gate electrode and the two-dimensional charge carrier gas channel, wherein the first region of doped type III-V semiconductor material comprises a plurality of side faces that define a plan view geometry of the first region, and wherein in the plan view geometry of the first region at least two lateral boundaries of the first region that intersect one another extend along crystallographically equivalent planes of the doped type III-V semiconductor material.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 27/095 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being Schottky barrier gate field-effect transistors
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A device for controlling trapped ions includes a semiconductor substrate. The semiconductor substrate includes a plurality of optical detectors. A dielectric layer is disposed over the semiconductor substrate. The dielectric layer includes one or a plurality of lenses. An electrode structure is disposed over the dielectric layer. The electrode structure includes electrodes of an ion trap configured to trap one or more ions in a space above the electrode structure.
In an embodiment, a method for fabricating a semiconductor package includes: embedding a semiconductor device in an insulating layer; forming a contact pad having an area that does not overlap the semiconductor device; and forming a vertical current redistribution structure that includes substantially parallel vertical current paths arranged in the insulating layer and extending perpendicular to the area of the contact pad that does not overlap the semiconductor device. The substantially parallel vertical current paths are non-uniformly distributed over the area of the contact pad that does not overlap the semiconductor device.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
A power device cell includes: a metallic body having a first main surface, a second main surface opposite the first main surface, and a side face vertically extending between the first and second main surfaces; a vertical power semiconductor die in a recess formed in the first main surface of the metallic body; and an organic and/or glass electrical insulator covering the second main surface of the metallic body such that the power device cell is electrically insulated at least at a first side that includes the organic and/or glass electrical insulator. The organic and/or glass electrical insulator is confined to the metallic body. A backside of the vertical power semiconductor die is configured to be at a different electric potential than a frontside of the vertical power semiconductor die. The metallic body is at the same electric potential as the backside of the vertical power semiconductor die.
A lateral semiconductor device includes: a semiconductor substrate; a first insulator layer formed on the semiconductor substrate; and a semiconductor layer formed on the first insulator layer opposite to the semiconductor substrate. The semiconductor layer includes a first region of a first conductivity type, a second region of a second conductivity type opposite to the first conductivity type, and an intermediate region interposed between the first region and the second region and defining a first lateral distance between the first region and the second region. The intermediate region has a lower doping concentration than the first region and the second region. A doping concentration of the first region at an interface to the intermediate region and a doping concentration of the second region at an interface to the intermediate region both exceed 1×1018 cm−3. The first lateral distance is at most 800 nm.
A semiconductor device includes: a semiconductor substrate; an epitaxial layer or layer stack on the semiconductor substrate; a plurality of transistor cells of a first type formed in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor; a plurality of transistor cells of a second type different than the first type and formed in a second region of the epitaxial layer or layer stack; and an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack. Sidewalls and a bottom of the isolation structure include a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack. Methods of producing the semiconductor device are also described.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/76 - Making of isolation regions between components
H01L 21/765 - Making of isolation regions between components by field-effect
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A motor controller includes a measurement interface configured to measure a mechanical angle of a shaft driven by a motor and a rotational speed of the shaft, and generate a speed feedback signal representative of the rotational speed, a speed regulator, and a current regulator. The speed regulator includes an error component configured to generate a speed error signal based on a difference between a speed reference signal and the speed feedback signal; a proportional integral controller configured to, based on the speed error signal, regulate a torque reference value that is configured to sustain a speed reference value; and a load torque ripple compensator configured to apply a torque feedforward function to reduce a load torque ripple in the torque reference value. The current regulator is configured to drive motor currents of the motor for generating a torque corresponding to the torque reference value.
H02P 21/22 - Current control, e.g. using a current control loop
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters with pulse width modulation
49.
POWER SEMICONDUCTOR DEVICE AND POWER ELECTRONICS ASSEMBLY
A power semiconductor device includes a molded package and an insulated metal substrate (IMS). The molded package includes one or more power semiconductor dies embedded in a mold compound and forming part of a power electronics circuit A metallic region exposed at a topside of the molded package forms part of a primary thermal pathway for heat dissipated by the one or more power semiconductor dies during operation. The IMS includes a copper layer attached to the metallic region exposed at the topside of the molded package, an aluminum layer at an opposite side of the IMS as the copper layer, and an organic isolation layer that electrically isolates the copper layer and the aluminum layer from one another. The copper layer provides no electrical rerouting for the molded package. A power electronics assembly including a plurality of the power semiconductor devices mounted to a circuit board is also described.
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
50.
Power Electronics Device and Sensing Method for a GaN Die Included in the Power Electronics Device
A power electronics device includes first and second semiconductor dies. The first die includes: a main GaN power transistor; a first GaN current sense transistor having a source electrically connected to a second current sense terminal; a second GaN current sense transistor; a diode device electrically connected in series between the drains of the main GaN power transistor and second GaN current sense transistor; and a voltage protection device electrically connecting the drain of the second GaN current sense transistor to a first current sense terminal. The second die includes current sense and short circuit detection circuits electrically connected to the current sense terminals. The short circuit detection circuit detects when the drain current of the main GaN power transistor exceeds a predetermined value and when the main GaN power transistor is in saturation.
H03K 17/041 - Modifications for accelerating switching without feedback from the output circuit to the control circuit
H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A monolithically integrated bidirectional switch includes: an input terminal; an output terminal; a control terminal; a compound semiconductor substrate; a common drift region in the compound semiconductor substrate and in series between the input terminal and the output terminal; a first gate; and a second gate. One of the first gate and the second gate is a normally-on gate and the other one of the first gate and the second gate is a normally-off gate, such that the monolithically integrated bidirectional switch is configured to conduct current in a single direction from the input terminal to the output terminal through the common drift region. A corresponding power electronic system that uses the monolithically integrated bidirectional switch is also described.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
52.
TYPE III-V SEMICONDUCTOR DEVICE WITH MULTI-LAYER BARRIER REGION
A semiconductor device includes a barrier region and a channel region, source and drain electrodes, and a gate structure that is configured to control a conductive connection between the source and drain electrodes, wherein the barrier region comprises a first barrier layer, a second barrier layer, and a third barrier layer, wherein in a central portion of the device the second barrier layer and the third barrier layer are disposed over the channel region, wherein in outer lateral portions of the device the first barrier layer is disposed over the channel region, and wherein a molar fraction of a second type III element in the central portion is higher than a molar fraction of the second type III element in the first barrier layer.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
A package includes: a vertically extending first electronic component with at least one exposed electrically conductive first terminal; a vertically extending second electronic component with at least one exposed electrically conductive second terminal; and a clip with an accommodation volume in which the first electronic component and the second electronic component are accommodated and are held together. The at least one first terminal and the at least one second terminal are electrically accessible at a bottom of the clip.
A power conversion circuit is described herein. In accordance with one embodiment, the circuit includes a first converter stage configured to provide a DC bus voltage and a second converter stage configured to receive the DC bus voltage and to generate an output voltage therefrom. The second converter stage includes at least a main branch and a partial power branch, wherein the main branch is configured to provide, at its output, a first voltage from the DC bus voltage based on a fixed conversion ratio and the partial power branch is configured to provide, at its output, an adjustable second voltage from the DC bus voltage. The outputs of the main branch and the partial power branch are connected in series to provide the output voltage. The circuit further includes a controller configured to control, in order to set the output voltage, the first converter stage to adjust the DC bus voltage and to control the partial power branch to adjust the second voltage.
H02M 7/5387 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 1/44 - Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
55.
APPLICATION OF A PROTECTIVE ATOMIC LAYER DEPOSITION (ALD) OR PLASMA-ENHANCED CHEMICAL VAPOR DEPOSITION (PECVD) LAYER ON A SEMICONDUCTOR DIE CONNECTED TO A SUBSTRATE VIA A SINTERED LAYER
A method for fabricating a semiconductor device includes: providing a substrate; applying a sinter paste layer to the substrate; placing a semiconductor die on or above the sinter paste layer; performing a sintering process to convert the sinter paste layer to a sintered layer; and applying a protective layer by atomic layer deposition or by plasma-enhanced chemical layer deposition onto the semiconductor die and the sintered layer.
A transistor device includes a semiconductor substrate having a first major surface and one or more transistor cells. Each transistor cell may include a columnar trench in the semiconductor substrate. The columnar trench includes a field dielectric, base, and a side wall. The side wall may extend from the base to the first major surface. The field dielectric may line the base and side wall of the columnar trench. A first thickness of the field dielectric at a first distance from the base is smaller than a second thickness of the field dielectric at a second distance from the base. The first distance is greater than the second distance. A columnar field plate with a cavity may be arranged in the columnar trench. A first perimeter of the columnar field plate at the first distance is greater than a second perimeter of the columnar field plate at the second distance.
A method includes: providing a Group III nitride-based substrate having a first major surface and a doped Group III nitride region; forming a first passivation layer configured as a hydrogen diffusion barrier on the first major surface; forming a first opening in the first passivation layer and exposing at least a portion of the doped Group III nitride region from the first passivation layer; activating a first doped Group III nitride region whilst the first passivation layer is located on the first major surface and the doped Group III nitride region is at least partly exposed from the first passivation layer; forming a second passivation layer on the first passivation layer and on the doped Group III nitride region; forming a second opening in the first and second passivation layers and exposing a portion of the doped Group III nitride region; and forming a contact in the second opening.
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A micro-fabricated device for controlling trapped ions includes a first ion trap module including first electrodes configured to trap ions in a zone above the first electrodes and a second ion trap module laterally arranged next to the first ion trap module and including second electrodes configured to trap ions in a zone above the second electrodes. The first ion trap module and the second ion trap module are mechanically connected. The first electrodes and the second electrodes are aligned relative to each other so as to be configured to provide a shuttling of ions between the first ion trap module and the second ion trap module along the first electrodes and the second electrodes.
A transistor device and a method for producing source regions of a transistor device are disclosed. The transistor device includes a semiconductor body with a plurality of mesa regions and a plurality of transistor cells each formed in a respective one of the mesa regions. Each transistor cell includes: a source region of a first doping type; a gate region of a second doping type complementary to the first doping type and spaced apart from the source region; a channel region of the first doping type; and a transition region different from the source region and the gate region. The transition region is arranged between the source region and the gate region and adjoins both the source region and the gate region.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
A power converter and a method are disclosed. The power converter includes a converter circuit with a first electronic switch and a first inductor connected in series with the first electronic switch; a control circuit configured to control operation of the first electronic switch and comprising a first input node; and a sense circuit. The sense circuit includes a sense resistor connected in series with the first electronic switch;
a second inductor inductively coupled with the first inductor and coupled to the first input node of the control circuit; and
a first coupling circuit coupling the sense resistor to the first input node of the control circuit. The first coupling circuit includes a first resistor coupled between the sense resistor and the first input node, and a second electronic switch connected in parallel with the first resistor. The control circuit is further configured to control operation of the second electronic switch.
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A power module includes: a power input terminal; a power output terminal at a same side of the power module as the power input terminal; a first power stage configured to receive an input voltage from the power input terminal and output a phase current at a switch node of the first power stage, the first power stage including an inductor that includes a conductor extending through a magnetic core, the conductor having a first end which is electrically connected to the switch node and a second end opposite the first end; and a first metal clip electrically connecting the second end of the conductor to the power output terminal such that power is delivered to and from the power module at the same side of the power module. A method of producing the power module and electronic assembly that includes the power module are also described.
A method for operating a power converter arrangement, a controller for controlling operation of a power converter arrangement, and a power converter arrangement are disclosed. The method includes operating a power converter arrangement in a first operating mode. The power converter arrangement includes: a first power converter (1) comprising input nodes (a, b, c) each configured to receive a respective one of input voltages (Va, Vb, Vc) each referenced to a first ground node (n), and configured to provide first and second intermediate voltages (Vx, Vz) each referenced to a second ground node (y); and a second power converter connected between the first power converter (1) and an output (p, r) of the power converter arrangement.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
63.
MULTI-PHASE POWER SUPPLY SYSTEM AND CONTROL OF DYNAMIC LOAD
An apparatus includes a controller. The controller is operative to determine a magnitude of first output current supplied from a first power converter to a dynamic load and determine a magnitude of second output current supplied from a second power converter to power the dynamic load. The controller controls a magnitude of the first output current with respect to a magnitude of the second content output current depending on a magnitude of total output current consumed by the dynamic load.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
64.
SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR COMPONENT AND METHODS
In an embodiment, a semiconductor die includes a base substrate having a first major surface, a second major surface opposing the first major surface, and a material other than a Group III nitride. A Group III nitride layer arranged on the first major surface of the base substrate includes a Group III nitride device. A first metallization structure is arranged on the Group III nitride layer and a second metallization structure is arranged on the second major surface of the base layer. The second metallization structure includes an electrically insulating inorganic layer arranged directly on the second major surface.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
An apparatus such as a clamp circuit includes a first circuit component and a second circuit component. The first circuit component may be coupled to a first circuit path. The second circuit component may be coupled to the first circuit component. The second circuit component may be configured to control operation of the first circuit component such that current received from the first circuit path passes through a combination of the first circuit component and the second circuit component to a ground reference voltage. In other words, controlled operation of the first circuit component results in sinking of the current received from the first circuit path through the first circuit component and the second circuit component to the reference voltage node such as ground. In one example, the first circuit component is controlled to sink the current through the clamp circuit when a supply voltage is below a threshold level.
H03K 17/22 - Modifications for ensuring a predetermined initial state when the supply voltage has been applied
H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
H03K 17/30 - Modifications for providing a predetermined threshold before switching
66.
PROTECTING A POWER INVERTER BY SENSING A PHASE NODE VOLTAGE
A monolithic half-bridge gate driver includes a phase node terminal configured to be coupled to a phase node to which a high-side transistor and a low-side transistor of a half-bridge are coupled; a diode comprising an anode and a cathode, wherein the cathode is coupled to the phase node terminal; and a comparator comprising a first input terminal coupled to the anode of the diode for receiving a measurement value indicative of a phase voltage at the phase node terminal, a second input terminal coupled to a threshold source for receiving a threshold, and an output terminal configured to output a comparison result indicating whether the measurement value satisfies the threshold. The phase node terminal is configured to be connected to a high-side supply potential by the high-side transistor, and is configured to be connected to a low-side supply potential by the low-side transistor.
H02M 1/32 - Means for protecting converters other than by automatic disconnection
G01R 31/26 - Testing of individual semiconductor devices
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 1/36 - Means for starting or stopping converters
H02M 7/539 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
A micro-fabricated device for controlling trapped ions includes a first substrate having a main surface. A structured first metal layer is disposed over the main surface of the first substrate. The structured first metal layer includes electrodes configured to trap an ion at a position space above the first substrate. A first optical layer disposed beneath or over the position includes a first laser light path extending in a direction substantially parallel to the main surface of the first substrate. The first optical layer also includes one or more light processing elements configured to manipulate laser light on the first laser light path.
A multi-phase controller includes a summer circuit configured to sense a plurality of phase currents generated by a plurality of power stages and generate a summed current value representative of a total current generated by the plurality of power stages; and a current limit controller configurable in a current-limit mode or a non-current-limit mode based on the summed current value and configured to limit the total current to a predefined value during the current-limit mode. The current limit controller includes a threshold selector circuit and a mode configuration circuit. The threshold selector circuit selects a first threshold or a second threshold as a selected threshold based on a configuration signal. The mode configuration circuit monitors a duration during which a comparison result indicates that the summed current value satisfies the selected threshold, and generates the configuration signal based on whether the first duration satisfies a duration threshold.
A semiconductor chip includes a semiconductor body having a main surface and a rear surface opposite the main surface, a first bond pad disposed on the main surface, a second bond pad disposed on the rear surface, a first switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the first bond pad, and a second switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the second bond pad.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A vehicle system of a vehicle includes a viewing tracking system configured to monitor a driver viewing direction of a vehicle driver and generate driver viewing direction information that indicates the driver viewing direction of the vehicle driver; and an image projection system configured to receive the driver viewing direction information and project an image into the driver viewing direction of the vehicle driver based on the driver viewing direction information. An image projection direction of the image projection system at which the image is projected varies based on a change in the driver viewing direction of the vehicle driver.
B60W 50/14 - Means for informing the driver, warning the driver or prompting a driver intervention
B60K 35/00 - Instruments specially adapted for vehiclesArrangement of instruments in or on vehicles
B60Q 1/04 - Arrangement of optical signalling or lighting devices, the mounting or supporting thereof or circuits therefor the devices being primarily intended to illuminate the way ahead or to illuminate other areas of way or environments the devices being headlights
B60W 40/08 - Estimation or calculation of driving parameters for road vehicle drive control systems not related to the control of a particular sub-unit related to drivers or passengers
A semiconductor package includes an input side including input pins an output side including high voltage pins, an isolation structure that galvanically isolates the input side from the output side, an input driver die mounted on the input side and electrically connected with the input pins, first and second power transistor dies mounted on the output side and each having a first load terminal electrically connected with the high voltage pins, an output driver die that is communicatively coupled to the input driver die driver die via the isolation structure and is electrically connected with gate terminals of the first and second power transistor dies, and one or more electrically conductive structures forming a direct electrical connection between load terminals of the first and second power transistor dies, wherein the output driver die is mounted on one of the one or more electrically conductive structures.
A power semiconductor device includes: a semiconductor body with a drift region of a first conductivity type; a first load terminal at a first side of the semiconductor body; a second load terminal at a second side of the semiconductor body opposite the first side, the power semiconductor device configured to conduct a load current between the load terminals; a control terminal at the first side configured to receive a control signal for controlling the load current; within an active region at least partially surrounded by an edge termination region, first trenches laterally confining mesas for conducting the load current, having control trenches electrically connected to the control terminal, and arranged in accordance with a first average pitch; and in a region laterally overlapping the control terminal, second trenches arranged in accordance with a second average pitch different from the first average pitch and electrically connected to the control terminal.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
The disclosure relates to a semiconductor die with a semiconductor body. The semiconductor die includes a vertical transistor device having a source region and a drain region at opposite sides of the semiconductor body, the source region and the drain region being of a first doping type. The semiconductor die also includes a lateral transistor device having: a source region and a drain region at the same side of the semiconductor body; a body region laterally between the source region and the drain region; and a gate electrode. The gate electrode of the lateral transistor device is disposed in a gate trench laterally aside the body region. The lateral transistor device is disposed in a well region of a second doping type opposite to the first doping type.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
74.
SEMICONDUCTOR DIE WITH A VERTICAL TRANSISTOR DEVICE
A semiconductor die with a semiconductor body includes a transistor device having: a source region at a first side of the semiconductor body; a drain region at a second side of the semiconductor body; a trench extending from the first side into the semiconductor body and having an elongated lateral extension; a first trench electrode configured for channel creation or field shaping, having an elongated lateral extension, and disposed in the trench; and a control electrode contact contacting the first trench electrode from the first side and configured to apply an electrical potential, the control electrode contact disposed at a first lateral position. A sense electrode contact contacting the first trench electrode from the first side is configured to sense a voltage from the first trench electrode. The sense electrode contact is disposed at a second lateral position which is spaced from the first lateral position.
A high voltage semiconductor device includes a substrate having a background doping of a first conductivity type. The substrate includes doped shielding regions of a complementary second conductivity type formed along a first substrate surface. An insulator layer is formed on the first substrate surface. A semiconductor layer is formed on the insulator layer opposite the substrate. A first interlayer dielectric is formed on the semiconductor layer. A first metal layer including laterally separated first field plate elements is formed on first portions of the first interlayer dielectric in a high voltage termination region. A second interlayer dielectric is formed on the first metal layer and on second portions of the first interlayer dielectric between the first field plate elements.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
76.
CONDITIONAL ACTIVE THERMAL CONTROL TO INCREASE POWER SEMICONDUCTOR LIFETIME AND EFFICIENCY
A gate driver system includes an active thermal control (ATC) circuit that monitors load current changes of a load current conducted by a transistor, and enables or disables an ATC of the transistor based on the load current changes. The ATC circuit is configured to evaluate load current changes that satisfy a duration threshold as qualified load current changes. The ATC circuit is configured to detect a direction and a magnitude of a qualified load current change, compare the magnitude of the qualified load current change to a threshold, and enable the ATC of the transistor if the qualified load current change has a decreasing direction and the magnitude of the qualified load current change satisfies the threshold. The ATC circuit is configured to regulate, while the ATC is enabled, a power dissipation parameter to regulate a power dissipation of the transistor.
A gate driver for driving a half-bridge is disclosed, which includes a low voltage control logic, a high side switch control circuit and a low side switch control circuit. The low voltage control circuit generates an internal pulsed high side control signal based on a high side control signal and a common protection function blanking control signal and a low side protection function activation signal based on a low side control signal and the common protection function blanking control signal. The high side switch control circuit includes a high side protection function circuit, which is enabled based on a first pulse of the internal pulsed high side control signal and is activated based on a second pulse of the internal high side pulsed control signal. The low side switch control includes a low side protection function circuit, which is activated based on the protection function activation signal.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
78.
SEMICONDUCTOR DEVICE WITH AN ACTIVE DEVICE REGION AND A CURRENT SENSOR REGION
A semiconductor device is provided. The semiconductor device includes a substrate and an active device region having gate trenches formed at a first main surface of the semiconductor substrate. The semiconductor device further includes a current sensor region having gate trenches formed at the first main surface of the semiconductor substrate. The semiconductor device further includes a transition region arranged between the active device region and the current sensor region. The transition region includes a supplementary trench formed at the first main surface of the semiconductor substrate. The supplementary trench separates the gate trenches of the active device region from the gate trenches of the current sensor region. An electrode formed in the supplementary trench is neither electrically connected to gate electrodes formed in the gate trenches of the active device region nor electrically connected to gate electrodes formed in the gate trenches of the current sensor region.
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
G01K 7/01 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using semiconducting elements having PN junctions
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
79.
Cascode Solid-State Switch Device and Power Electronics System
A cascode solid-state switch device includes a normally-off transistor and a normally-on transistor having a source electrically connected to a drain of the normally-off transistor. A gate charge of the cascode solid-state switch device is independent of both a voltage class of the cascode solid-state switch device and a drain-to-source on-state resistance of the cascode solid-state switch device. A circuit component of the cascode solid-state switch device and a power electronics circuit that includes the cascode solid-state switch device are also described.
H03K 17/691 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit using transformer coupling
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
80.
Power Conversion Regulator Circuit Including a Processing Circuit Configured to Implement an Artificial Neural Network
A power conversion regulator circuit includes: a regulator input configured to be dynamically supplied with a feedback signal representative of an output parameter of a power converter circuit; a regulator output configured to dynamically provide a control signal to the power converter circuit, for making adjustments to the output of the power converter circuit; a processing circuit configured to (a) implement an artificial neural network having a plurality of artificial neurons, wherein the artificial neural network is configured to compute a machine-learning-based (ML-based) error signal, based on at least the feedback signal and a target level for the output parameter, and (b) output a correction signal, based at least in part on the ML-based error signal; and regulator circuitry configured to generate the control signal for outputting via the regulator output, based at least in part on the correction signal.
A switched-mode power supply includes a power semiconductor device that includes a semiconductor body comprising transistor cells and a drift zone between a drain layer and the transistor cells, the transistor cells comprising source zones, wherein the device exhibits a first output charge gradient when a voltage between the drain layer and the source zones of the transistor cells increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device, wherein the device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
A method includes forming a laminate structure including an electrically insulating core layer having a first side and a second side, a first redistribution layer arranged on the first side and a second redistribution layer arranged on the second side, providing a first transistor device and a second transistor device, and providing a control chip, embedding the first transistor device, the second transistor device and the control chip in the core layer, forming a half-bridge circuit that comprises the first transistor device connects to the second transistor device, wherein first sides of the control chip, and one of the first and second transistor devices face towards the first redistribution layer, wherein the second transistor device comprises one or more conductive device that electrically couple gate electrodes at the first side of the second transistor device to a pad arranged on a second side of the second transistor device.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
83.
BIDIRECTIONAL SEMICONDUCTOR SWITCH WITH PASSIVE DISCHARGE CIRCUIT
A semiconductor device includes: a semiconductor body having an active region and a substrate region beneath the active region; a bidirectional switch having first and second gate structures configured to control a conductive state of a channel in the active region, and first and second input-output terminals electrically connected to the channel; and a passive discharge circuit in parallel with the bidirectional switch and configured to utilize a fraction of a voltage across the first and second input-output terminals to switch on a transistor device that electrically connects the substrate region to the input-output terminal at the lower potential during an off-state of the bidirectional switch and during ZVS (zero-voltage switching) transition periods.
H03K 17/56 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices
84.
ASYMMETRICAL HALF BRIDGE FLYBACK POWER CONVERTERS AND METHODS
A power supply controller is operative to: control switching of a first asymmetrical half bridge flyback power converter to supply first current from a secondary winding SW1 of the first asymmetrical half bridge flyback power converter during a first portion of a switch control cycle to produce an output voltage, the first asymmetrical half bridge flyback power converter operative to block the first current through the secondary winding SW1 during a second portion of the control cycle; and control switching of a second asymmetrical half bridge flyback power converter to supply second current from a secondary winding SW2 of the second asymmetrical half bridge flyback power converter during a second portion of the switch control cycle to produce the output voltage, the second asymmetrical half bridge flyback power converter operative to block the second current through the secondary winding SW2 during the first portion of the control cycle.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 3/00 - Conversion of DC power input into DC power output
85.
Segmented Movement Control Electrodes in Ion Traps
A system is provided that includes: at least one radio frequency (RF) electrode extending along a first direction, the at least one RF electrode configured to generate an RF field, where a first RF electrode of the least one RF electrode is disposed in a substrate, and a plurality of direct current (DC) electrodes that are spaced apart along at least the first direction, the plurality of DC electrodes configured to generate an electric field, where the RF field and the electric field are configured to trap an ion at a first position, the first position being spaced apart from the substrate by a first distance, where each DC electrode of the plurality of DC electrodes has a respective width in the first direction that is less or equal to 0.2 times the first distance.
An ion trap system and method of using an ion trap system, the system including a substrate, a radio frequency (RF) source configured to provide an RF signal, an RF electrode disposed in the substrate and connected to the RF source, a direct current (DC) source configured to provide a DC signal, a DC electrode disposed in the substrate and connected to the DC source, wherein the DC electrode is separate from the RF electrode, and a coupling compensation system configured to provide a compensating RF signal associated with the RF signal.
A semiconductor device includes: a plurality of transistor cells formed in a semiconductor body. The plurality of transistor cells includes: a plurality of stripe-shape gate trenches formed in a first main surface of the semiconductor body; and a plurality of field plate trenches separate from the stripe-shape gate trenches. At least one field plate trench is laterally interposed between each pair of neighboring stripe-shape gate trenches. Each stripe-shape gate trench includes a gate electrode, a gate dielectric between the gate electrode and a sidewall of the stripe-shape gate trench, and an oxide between the gate electrode and a bottom of the stripe-shape gate trench, the oxide having a vertical thickness that is greater than eight times a lateral thickness of the gate dielectric and/or greater than a vertical thickness of the gate electrode. A method of producing the semiconductor device is also described.
In an embodiment, a semiconductor device includes an edge termination region laterally surrounding an active area. The active area includes active transistor cells. The edge termination region includes one or more inactive cells, each including a first columnar trench and a first termination mesa arranged adjacent to the first columnar trench. Each first columnar trench includes a base, a side wall, a field plate, and a field dielectric arranged on the base and the side wall and surrounding the field plate. Each first termination mesa includes a drift region of a first conductivity type and a body region of a second conductivity type arranged above the drift region. Each field dielectric of the first columnar trenches has a first thickness in an upper region of the field plate and a second thickness in a lower region of the field plate, the first thickness being smaller than the second thickness.
A power converter is presented. The power converter may be configured to convert an input voltage into an output voltage. The power converter May comprise a switching bridge circuit. The power converter may comprise a transformer with primary windings, first secondary windings connected between a first transformer terminal and a second transformer terminal, and second secondary windings connected between the second transformer terminal and a third transformer terminal. The power converter may comprise a resonant tank circuit comprising the primary windings of the transformer. The power converter may comprise a buck power converter circuit coupled between the first secondary windings and an output of the power converter.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 3/00 - Conversion of DC power input into DC power output
90.
POWER CONVERTER AND METHOD OF OPERATING A POWER CONVERTER
A power converter is provided. The power converter includes a transformer having a primary side winding and a secondary side winding, an oscillator circuit coupled to the primary side winding forming a resonant oscillator with the primary side winding and an output circuit coupled to the secondary side winding and configured to generate an output signal based on energy received from the secondary side winding. A secondary side controller is configured to transmit a control signal based on a controlled variable related to the output signal via the transformer to the primary side controller, and the primary side controller is configured to start or stop and oscillation of the resonant oscillator based on the control signal.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 3/00 - Conversion of DC power input into DC power output
91.
TRENCH JUNCTION FIELD EFFECT TRANSISTOR INCLUDING A MESA REGION
A trench junction field effect transistor, trench JFET (100), is proposed. The trench JFET (100) includes a mesa region (103) confined by first and second trenches (1061, 1062) spaced apart from each other in a first lateral direction (x1) of a semiconductor body (102), the first and second trenches (1061, 1062) extending from a first surface (108) into the semi-conductor body (102); a mesa channel region (104) of a first conductivity type (103); a first control region (1101) of a second conductivity type complementary to the first conductivity type arranged in the mesa region (103) adjacent to the first trench (1061); and a second control region (1102) of the second conductivity type arranged in the mesa region (103) adjacent to the second trench (1062). The mesa channel region (104) is arranged, in the first lateral direction (x1), between the first control region (1101) and the second control region (1102), and the first control region (1101) is electrically coupled to a source contact (S), and the second control region (1102) is electrically coupled to a gate contact (G).
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/808 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a PN junction gate
A molded package includes: a first semiconductor die embedded in a mold compound and including a normally-on bidirectional switch device having first and second normally-on gates and first source and second sources; a second semiconductor die embedded in the mold compound and including a first normally-off switch device having a normally-off gate, a source, and a drain; a third semiconductor die embedded in the mold compound and including a second normally-off switch device having a normally-off gate, a source, and a drain, the drain of the first normally-off switch device being electrically connected to the first source of the normally-on bidirectional switch device and the drain of the second normally-off switch device being electrically connected to the second source of the normally-on bidirectional switch device in a cascode configuration to form a bidirectional power switch; and an externally accessible source terminal electrically connected to each source of each switch device.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
93.
GATE DRIVER SYSTEM FOR DETECTING A SHORT CIRCUIT CONDITION
A driver system includes a first half-bridge that generates a first load current at a first output node, a second half-bridge that generates a second load current at a second output node, a first voltage charging device coupled to the first output node, and a second voltage charging device coupled to the second output node. A method of detecting a short circuit condition in the driver system includes detecting a first charging time at which a first charging voltage of the first voltage charging device is charged to a first threshold voltage; detecting a second charging time at which a second charging voltage of the second voltage charging device is charged to a second threshold voltage; and detecting the short circuit condition on a condition that a time difference between the first charging time and the second charging time is less than a time difference threshold.
H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
G01R 31/52 - Testing for short-circuits, leakage current or ground faults
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
H02M 7/5387 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters with pulse width modulation
94.
POWER FACTOR CORRECTION SYSTEM, CONTROLLER AND METHOD OF CONTROLLING A POWER FACTOR CORRECTION SYSTEM
A multi-phase PFC (power factor correction) system, controller, and method of controlling the multi-phase PFC system are described. The method includes operating the phases under variable frequency control to interleave current delivered by the plurality of phases to a load. During a switching cycle for the phases, a phase synchronization correction indicator is activated if a predetermined crossing point along a rising or falling slope of the current delivered by a second phase is misaligned with the same predetermined crossing point along the opposite slope of the current delivered by a first phase. During the next switching cycle, a switching period of the second phase is adjusted if the phase synchronization correction indicator was activated during the previous switching cycle.
A transistor device includes: a plurality of transistor cells in a semiconductor substrate; and a source pad above the semiconductor substrate and electrically connected to a source region and a body region of the transistor cells. A first group of the transistor cells has a first body region average doping concentration. A second group of the transistor cells has a second body region average doping concentration higher than the first body region average doping concentration. The transistor cells of the first and second groups are interleaved. The transistor cells have a first source region density in a first area of the semiconductor substrate underneath a region of the source pad designated for clip contacting, and a second source region density lower than the first source region density in a second area of the semiconductor substrate outside the first area.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 23/00 - Details of semiconductor or other solid state devices
A cryogenic system includes an ion trap device configured to be mounted on a trap socket. A magnetic radiation shield of a superconducting material surrounds an ion trap region of the ion trap device. The magnetic radiation shield forms part of the ion trap device and/or the trap socket. A magnet is enclosed by the magnetic radiation shield.
A power converter and a power conversion method are disclosed. The power converter includes a plurality of resonant converter stages (1a, 1b, 1c) each Including an input (Ina, Inb, Inc) and an output (Outa, Outb, Outc); a rectifier circuit (6); and a control circuit (7) configured to control operation of the plurality of resonant converter stages (1a, 1b, 1c). The input (Ina, Inb, Inc) of each of the plurality of converter stages (1a, 1b, 1c) is configured to receive a respective input voltage (Vina, Vinb, Vinc). The rectifier circuit (6) is connected to the outputs (Outa, Outb, Outc) of the plurality of converter stages (1a, 1b, 1c) and is configured to provide an output signal (Vout, Iout) based on a cascaded voltage that is dependent converter stage output voltages (Vseca, Vsecb, Vsecc) provided at the outputs (Outa, Outb, Outc) of the resonant converter stages (1a, 1b, 1c).
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 3/00 - Conversion of DC power input into DC power output
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A control circuit (100) is provided, for controlling switching elements of a switched-mode power supply (10). The control circuit includes a control input (112), for receiving a pulse width modulated, PWM, control signal comprising a series of control pulses. The control circuit has a primary output (120), for controlling a primary switching element of the switched-mode power supply. Also provided are: a synchronous rectifier module (SR) incorporating the control circuit (100); and a switched mode power supply incorporating the synchronous rectifier module (SR).
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
A method of producing a semiconductor device includes providing a semiconductor die, providing a metal joining partner, forming a diffusion solderable region by an inkjet metal printing process, forming an assembly to include the diffusion solderable region in between the metal joining partner and the semiconductor die, and performing a diffusion soldering process that forms a soldered joint from the diffusion solderable region in between the semiconductor die and the metal joining partner.
A semiconductor device includes: a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; and a trench structure extending into the semiconductor substrate from the first main surface. The trench structure includes: an upper section extending into the semiconductor substrate from the first main surface; a lower section at an opposite end of the trench structure as the upper section; a first intermediary section between the upper section and the lower section; a field plate in the upper section and dielectrically insulated from the semiconductor substrate; and a first dielectric material completely filling the lower section. The lower section, the upper section, and the first intermediary section have different geometries and/or different dielectric materials. Methods of producing the semiconductor device are also described.
