A signal receiving apparatus includes a phase recovery look, a phase estimation circuit, a phase noise detection circuit, and a bandwidth setting circuit. The phase recovery loop performs a phase recovery process on an input signal according to a bandwidth setting. The phase estimation circuit generates an estimated phase associated with the input signal. The phase noise detection circuit determines a phase noise amount according to the estimated phase. The bandwidth setting circuit calculates an average and a variance of the phase noise amounts, and adjusts the bandwidth setting of the phase recovery loop according to the average and the variance.
Apparatus and methods are described for a video encoder that uses reference motion vectors (MVs) with reduced precision to generate predicted MVs. The video encoder receives a block of pixels of a video frame and generates a MV for encoding the block of pixels by motion compensation. The video encoder creates a reduced-precision MV by reducing a precision of the generated MV based on a precision reduction scaling factor. The video encoder also stores the reduced-precision MV in a MV buffer as a reference MV for temporal or spatial MV prediction.
H04N 19/52 - Processing of motion vectors by encoding by predictive encoding
H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
H04N 19/517 - Processing of motion vectors by encoding
H04N 19/59 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/31 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using hierarchical techniques, e.g. scalability in the temporal domain
H04N 19/33 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using hierarchical techniques, e.g. scalability in the spatial domain
H04N 19/91 - Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
3.
Symbol rate estimating device and method and adjacent channel interference detecting device
A symbol rate estimating device includes: a power spectrum density (PSD) estimating unit, estimating a PSD of an input signal; an index searching unit, searching for a cut-off frequency index in the PSD; an adjacent channel interference (ACI) detecting unit, detecting whether the input signal has ACI to generate a detection signal; a threshold adjusting unit, generating an adjusted index number threshold according to the detection signal; an index output unit, outputting the cut-off frequency index according to the adjusted index number threshold; and a symbol calculating unit, calculating a symbol rate of the input signal according to the cut-off frequency index.
An input/output circuit includes a first switch element, a control voltage providing circuit and a floating voltage providing circuit. The first switch element includes a control terminal, a first path terminal, a second path terminal and a base terminal. The first path terminal receive a first voltage, and the second path terminal receives a second voltage. The control voltage providing circuit provides a control voltage to the control terminal of the first switch element. The floating voltage providing circuit provides the larger between the first voltage and the second voltage to the base terminal of the first switch element, so as to prevent a leakage current from being generated between the first voltage source or the second voltage source and the base terminal of the first switch element.
H03K 17/16 - Modifications for eliminating interference voltages or currents
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
5.
Signal processing device and associate equalization circuit and signal processing method
A signal processing device for a receiver includes: a descrambler, descrambling an input signal to generate a descrambled signal; a phase recovery circuit, performing phase recovery according to the descrambled signal to generate a phase recovered signal; an equalization module, performing equalization according to the phase recovered signal to generate an equalized signal; and a decoder, decoding the equalized signal to obtain data included in the input signal.
A roll-off parameter determining module disposed at a receiving terminal is provided. The receiving terminal receives first roll-off information of a first frame and second roll-off information of a second frame. The first frame is adjacent to the second frame. The module for determining a roll-off parameter includes: a register unit; a first determining unit, determining whether one of the first roll-off information and the second roll-off information includes a first data type, and generating a first roll-off parameter indicator; a second determining unit, determining whether one of the first roll-off information and the second roll-off information includes a second data type and outputting a second roll-off parameter indicator; and a look-up table (LUT) unit, looking up an LUT according to the first roll-off parameter indicator and a second roll-off parameter indicator to output a roll-off parameter.
H04N 7/173 - Analogue secrecy systemsAnalogue subscription systems with two-way working, e.g. subscriber sending a programme selection signal
H04N 21/266 - Channel or content management, e.g. generation and management of keys and entitlement messages in a conditional access system or merging a VOD unicast channel into a multicast channel
H04N 21/2383 - Channel coding of digital bit-stream, e.g. modulation
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
7.
Current-mode receivers for induction-based communication and related methods
A transceiver for use in induction-based communication protocols, such as radio-frequency identification (RFID) and near field communication (NFC), is described. The transceiver may be arranged such that the transmitter and the receiver share a common input/output (I/O) terminal. The transceiver may be configured to interrogate a transponder to which it is inductively coupled, and to wait for the transponder's response. Data transmitted back by the transponder may be detected by sensing an impedance modulation at the I/O terminal or at a node whose impedance varies with the I/O terminal. The impedance modulation may be sensed by allowing a current to be modulated by the impedance variation and by converting the current into a voltage. The corresponding voltage modulation may be sensed by a receiver.
A scan output flip-flop is provided. The scan output flip-flop outputs a scan-out signal at a first output terminal and includes a selection circuit, a control circuit, and a scan-out stage circuit. The selection circuit is controlled by a first test enable signal to transmit a data signal on a first input terminal or a test signal on a second input terminal to an output terminal of the selection circuit to serve as an input signal. The control circuit is coupled to the output terminal of the selection circuit and controlled by a first clock signal to generate a first control signal and a second control signal according to the input signal. The second control signal is the inverse of the first control signal. The scan-out stage circuit is controlled by the first control signal and the second control signal to generate the scan-out signal.
A level shift includes a bias voltage providing circuit, a level shifting circuit and an output switching circuit. The level shifting circuit includes a high level shifting unit and a low level shifting unit. When the high level shifting unit is in a cut-off state, the high level shifting unit further receives a first bias voltage such that the high level shifting unit is in a partially cut-off state, accordingly increasing a response speed of the high level shifting unit. When the low level shifting unit is in a cut-off state, the low level shifting unit further receives a second bias voltage such that the low level shifting unit is in a partially cut-off state, accordingly increasing a response speed of the low level shifting unit. The level shifter of the present application provides a higher response speed.
H03L 5/00 - Automatic control of voltage, current, or power
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
10.
Decoding circuit applied to multimedia apparatus and associated decoding method
A decoding circuit applied to a multimedia apparatus is provided. The decoding circuit is for decoding encoded data to generate system information, and includes multiple processing circuits and a determination circuit. The multiple processing circuits individually process the encoded data to generate multiple processed signals, and respectively correspond to multiple bit combinations of a part of the system information. The determination circuit determines the system information according to the multiple processed signals.
H03M 7/00 - Conversion of a code where information is represented by a given sequence or number of digits to a code where the same information is represented by a different sequence or number of digits
H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H04H 40/90 - Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups specially adapted for satellite broadcast receiving
A multi-core video decoder system includes a plurality of video decoder cores and a storage device. The video decoder cores are used to decode a picture, wherein each of the video decoder cores decodes a portion of the picture. The storage device has at least one shared storage space accessed by different video decoder cores of the video decoder cores. In addition, an associated video decoding method includes: performing a plurality of video decoding operations to decode a picture, wherein each of the video decoding operations decodes a portion of the picture; and controlling different video decoding operations of the video decoding operations to access at least one shared storage space.
H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
A circuit for demodulating an input signal is described. The circuit may be configured to demodulate signals modulated with amplitude-based modulation schemes, such as amplitude shift keying (ASK), such that information is encoded in the amplitude of the signals. The circuit may comprise an amplitude detector for extracting the envelope of a received amplitude-modulated signal, a phase/frequency detector for detecting phase and/or frequency shifts, and a selector configured to select one between the output of the amplitude detector and the output of the phase/frequency detector. The selector may be controlled by a control circuit including a delay unit.
A circuit for demodulating an input signal is described. The circuit may be configured to demodulate signals modulated with amplitude-based modulation schemes, such as amplitude shift keying (ASK). The demodulator may comprise a clock extractor configured to generate a clock signal in response to receiving an amplitude-modulated input signal, a phase shifter configured to generate a sampling signal by phase-shifting the clock signal by approximately π/2, and a sampler configured to sample the input signal in correspondence to one or more edges (such as one or more falling edges) of the sampling signal. In this way, the amplitude-modulated input signal may be sampled at its peak, or at least near its peak, thus ensuring high signal fidelity.
H04L 27/152 - Demodulator circuitsReceiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements using controlled oscillators, e.g. PLL arrangements
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04N 7/084 - Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band with signal insertion during the horizontal blanking interval
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
14.
Method and apparatus for performing image processing operation based on frame/algorithm selection
An exemplary image processing method includes the following steps: receiving an image input composed of at least one source image; receiving algorithm selection information corresponding to each source image; checking corresponding algorithm selection information of each source image to determine a selected image processing algorithm from a plurality of different image processing algorithms; and performing an object oriented image processing operation upon the source image based on the selected image processing algorithm. The algorithm selection information indicates an image quality of each source image and is generated from one of an auxiliary sensor, an image processing module of an image capture apparatus, a processing circuit being one of a video decoder, a frame rate converter, and an audio/video synchronization (AV-Sync) module, or is a user-defined mode setting.
A bandwidth adjusting method for a phase-locked loop (PLL) unit of a phase recovery module includes: adjusting an operating bandwidth of the PLL unit to a first bandwidth; measuring multiple first phase errors between a compensated input signal, which is generated according to an input signal and a phase compensating signal that the PLL unit generates, and a reference clock signal, and obtaining a first statistical value of the first phase errors; adjusting the operating bandwidth of the PLL unit to a second bandwidth; measuring multiple second phase differences between the compensated input signal and the reference clock signal, and obtaining a second statistical value of the second phase differences; and adjusting the operating bandwidth according to the first statistical value and the second statistical value. The first bandwidth and the second bandwidth are obtained by interpolating an upper bandwidth limit and a lower bandwidth limit.
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
16.
Method and apparatus of video compression for pre-stitched panoramic contents
Methods and apparatus of compression for pre-stitched pictures captured by multiple cameras of a panoramic video capture device are disclosed. At the encoder side, stitching information associated with a stitching process to form the pre-stitched pictures is used to encode a current block according to embodiments of the present invention, where the stitching information comprises calibration data, matching results, seam position, blending level, sensor data, or a combination thereof. In one embodiment, the stitching information corresponds to matching results associated with a projection process, and projection-based Inter prediction is used to encode the current block by projecting a reference block in a reference pre-stitched picture to coordinates of the current block. In another embodiment, the stitching information corresponds to seam information associated with seam detection, and seam-based Inter prediction is used to encode the current block by utilizing the seam information.
H04N 19/597 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding specially adapted for multi-view video sequence encoding
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/192 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding the adaptation method, adaptation tool or adaptation type being iterative or recursive
H04N 5/232 - Devices for controlling television cameras, e.g. remote control
G06T 3/40 - Scaling of whole images or parts thereof, e.g. expanding or contracting
H04N 19/85 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression
H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
H04N 19/46 - Embedding additional information in the video signal during the compression process
H04N 19/146 - Data rate or code amount at the encoder output
Aspects of the disclosure provide a method for merging compressed access units according to compression rates and/or positions of the respective compressed access units. The method can include receiving a sequence of compressed access units corresponding to a sequence of raw access units partitioned from an image or a video frame and corresponding to a sequence of memory spaces in a frame buffer, determining a merged access unit including at least two consecutive compressed access units based on compression rates and/or positions of the sequence of compressed access units. The merged access unit is to be stored in the frame buffer with a reduced gap between the at least two consecutive compressed access units compared with storing the at least two consecutive compressed access units in corresponding memory spaces in the sequence of memory spaces.
G09G 5/393 - Arrangements for updating the contents of the bit-mapped memory
G09G 5/395 - Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
H04N 19/423 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
H04N 19/426 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements using memory downsizing methods
H04N 19/39 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using hierarchical techniques, e.g. scalability involving multiple description coding [MDC], i.e. with separate layers being structured as independently decodable descriptions of input picture data
H04N 19/59 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
H04N 1/32 - Circuits or arrangements for control or supervision between transmitter and receiver
18.
Image processing method applied to a display and associated circuit
A circuit applied to a playback device includes an image format determining circuit, a control circuit, an image processing module and a blending circuit. The image format determining circuit receives an image signal and determines whether the format of the image signal is a standard dynamic range (SDR) or a high dynamic range (HDR) to generate a determination result. The control circuit generates a control signal according to the determination result. The image processing module selects an image processing setting corresponding to one of the SDR format and the HDR format, and processes the image signal according to the image processing setting to generate a processed image signal. The blending circuit superimposes an interface image onto the processed image signal to generate an output image signal to a display.
H04N 5/235 - Circuitry for compensating for variation in the brightness of the object
H04N 5/232 - Devices for controlling television cameras, e.g. remote control
H04N 21/435 - Processing of additional data, e.g. decrypting of additional data or reconstructing software from modules extracted from the transport stream
A frequency adjusting device includes a voltage droop detector and a frequency divider. The voltage droop detector compares a supply voltage with a lower threshold voltage to output a comparison result. When the supply voltage is greater than the threshold voltage, the frequency divider outputs a result of dividing a basic clock signal by a first value as a clock signal. When the supply voltage is smaller than the threshold voltage, the frequency divider outputs a result of dividing the basic clock signal by a second value as the clock signal.
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
H03K 5/1252 - Suppression or limitation of noise or interference
A method for adjusting brightness of a display panel and a brightness adjustment system are provided. The brightness adjustment system includes a display panel and a first controller. According to the provided method, the first controller receives first brightness control data and receives first image data to be displayed on the display panel. The first controller further converts the first image data into second image data according to the first brightness control data for adjusting the brightness of the display panel.
G06F 3/048 - Interaction techniques based on graphical user interfaces [GUI]
H04N 9/64 - Circuits for processing colour signals
H04N 9/73 - Colour balance circuits, e.g. white balance circuits or colour temperature control
G06F 3/0484 - Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
G09G 3/3275 - Details of drivers for data electrodes
21.
Device applied to display and associated image display method
A device applied to a display includes a receiving circuit, a detecting circuit, an image processing circuit and a response time enhancing circuit. The receiving circuit receives an input image signal. The detecting circuit detects a frame rate of image data of a frame in the input image signal. The image processing circuit performs image processing on the image data of the frame to generate a target pixel value of multiple pixels in the frame. The response time enhancing circuit determines multiple adjusted pixel values of the multiple pixels according to the frame rate, and outputs the adjusted pixel values to a display panel. For a pixel, the adjusted pixel values generated for the pixel under different frame rates are different.
A display control device includes a detector, a frequency adjusting signal generator, a clock generator and an output timing generator. The detector compares an input field reference signal with an output field reference signal to determine a time difference signal. The frequency adjusting signal generator outputs a frequency adjusting signal. The clock generator outputs a clock according to the frequency adjusting signal. The output timing generator generates an output field synchronization signal according to the clock. The clock generator adjusts the frequency of the clock according to the frequency adjusting signal.
A television signal processing circuit includes an audio/video (AV) signal generating circuit, an intermediate frequency (IF) mixer, a first filter, a radio-frequency (RF) mixer, a second filter and a digital-to-analog converter (DAC). The AV signal generator generates a digital AV signal. The IF mixer converts the digital AV signal to an IF AV signal. The first filter filters the IF AV signal to generate a filtered IF AV signal. The RF mixer converts the filtered IF AV signal to an RF AV signal. The second filter filters the RF AV signal to generate a filtered RF AV signal. The DAC converts the filtered RF AV signal to an analog AV signal and transmits the analog AV signal to an antenna.
H04N 21/439 - Processing of audio elementary streams
H04N 21/44 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
A stereo-phonic frequency modulation receiver includes: a frequency modulation demodulation circuit, receiving a reception signal, and generating a demodulated signal according to the reception signal; a frequency-division demultiplexer, generating a sum signal, a difference signal and a pilot amplitude signal according to the demodulated signal; a dual sound channel separation circuit, generating a left-channel output signal and a right-channel output signal according to the sum signal and a weakened difference signal; and a weakening circuit, weakening the difference signal according to the pilot amplitude signal or a signal-to-noise ratio (SNR) to generate the weakened difference signal.
H04H 20/47 - Arrangements characterised by circuits or components specially adapted for broadcast specially adapted for broadcast systems covered by groups specially adapted for stereophonic broadcast systems
H04H 20/48 - Arrangements characterised by circuits or components specially adapted for broadcast specially adapted for broadcast systems covered by groups specially adapted for stereophonic broadcast systems for FM stereophonic broadcast systems
G10L 19/008 - Multichannel audio signal coding or decoding using interchannel correlation to reduce redundancy, e.g. joint-stereo, intensity-coding or matrixing
A video encoder has a processing circuit and a universal binary entropy (UBE) syntax encoder. The processing circuit processes pixel data of a video frame to generate encoding-related data, wherein the encoding-related data comprise at least quantized transform coefficients. The UBE syntax encoder processes a plurality of syntax elements to generate UBE syntax data. The encoding-related data are represented by the syntax elements. The processing circuit operates according to a video coding standard. The video coding standard supports arithmetic encoding. The UBE syntax data contain no arithmetic-encoded syntax data.
H04N 19/13 - Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
H04N 21/23 - Processing of content or additional dataElementary server operationsServer middleware
H04N 21/84 - Generation or processing of descriptive data, e.g. content descriptors
H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
H04N 19/18 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a set of transform coefficients
H04N 19/174 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
H04N 21/2365 - Multiplexing of several video streams
H04N 21/2665 - Gathering content from different sources, e.g. Internet and satellite
H04N 21/2343 - Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements
H04N 21/845 - Structuring of content, e.g. decomposing content into time segments
26.
Backlight control and image compensation method applied to display and associated control method
A control method of a display includes a statistics circuit, a backlight determining circuit and a backlight control circuit. The display includes a backlight module having a maximum luminance. The statistics module receives frame, and generates luminance statistical information of a plurality of blocks included in the frame. The backlight determining circuit determines a backlight intensity corresponding to each of the blocks according to the luminance statistical information of the blocks and the maximum luminance. At least one of the backlight intensities corresponding to the blocks is greater than a normal luminance, which is a backlight intensity corresponding to one of the blocks when a maximum power is evenly distributed on light emitting elements of the display. The backlight control circuit controls the luminance of the backlight module according to the backlight intensities.
G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source
G09G 5/06 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using colour palettes, e.g. look-up tables
27.
Method and apparatus of inter coding for VR video using virtual reference frames
A method and apparatus of video encoding or decoding for a video encoding or decoding system applied to multi-face sequences corresponding to a 360-degree virtual reality sequence are disclosed. According the present invention, one or more multi-face sequences representing the 360-degree virtual reality sequence are derived. If Inter prediction is selected for a current block in a current face, one virtual reference frame is derived for each face of said one or more multi-face sequences by assigning one target reference face to a center of said one virtual reference frame and connecting neighboring faces of said one target reference face to said one target reference face at boundaries of said one target reference face. Then, the current block in the current face is encoded or decoded using a current virtual reference frame derived for the current face to derive an Inter predictor for the current block.
H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
H04N 19/167 - Position within a video image, e.g. region of interest [ROI]
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/597 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding specially adapted for multi-view video sequence encoding
A method for detecting a notch band is applied to a multicarrier communication system that operates in a wideband. The method includes: receiving a received signal, and generating a plurality of frequency-domain signals according to the received signal; performing a magnitude operation on the frequency-domain signals to obtain a plurality of magnitude values; determining a plurality of ratios of a first magnitude set among the magnitude values to a second magnitude set among the magnitude value to determine whether the received signal contains a notch band.
A method and apparatus for video coding using template-based Intra prediction are disclosed. According to one method, where determining whether to apply the template-based Intra prediction or one or more parameters associated with the template-based Intra prediction depends on the current block size. According to yet another method, the quad-tree plus binary tree (QTBT) structure is used to partition an image or one or more areas of the current image into blocks. If the template-based Intra prediction is used for a current block and the current block is non-square, the width and height of the L-shaped reference pixel line are determined according to width and height of the current block. The L-shaped reference pixel line comprises a top reference pixel segment above the top template and a left reference pixel segment adjacent to a left side of the left template.
H04N 19/159 - Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
H04N 19/122 - Selection of transform size, e.g. 8x8 or 2x4x8 DCTSelection of sub-band transforms of varying structure or type
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
H04N 19/119 - Adaptive subdivision aspects e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
H04N 19/11 - Selection of coding mode or of prediction mode among a plurality of spatial predictive coding modes
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/182 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a pixel
30.
Method for compressing image data and image data compressing system
H04N 19/146 - Data rate or code amount at the encoder output
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/15 - Data rate or code amount at the encoder output by monitoring actual compressed data size at the memory before deciding storage at the transmission buffer
H04N 19/132 - Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
H04N 19/184 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being bits, e.g. of the compressed video stream
A video processing device capable of automatically determining an operation mode is provided. The video processing device includes a control signal processing circuit and a controller. The control signal processing circuit receives a control signal from a transmitter, and, according to at least one data access address indicated by the control signal, performs at least steps of determining whether the data access address satisfies a predetermined access address, and outputting a notification signal when the data access address satisfies the predetermined access address. The controller causes the video processing device to operate in a first mode according to the notification signal, and causes the video processing device to operate in a second mode when the notification signal is not received within a predetermined time interval.
A decoding apparatus includes a differential decoder, an error correction decoder and a controller. The differential decoder performs differential decoding according to a differential encoding dependency to generate a differential decoding result. The error correction decoder performs a decoding process on multiple packets that need to be corrected according to the differential decoding result to accordingly generate respective error correction records, wherein the packets are generated according to the differential decoding results, and the packets include a first packet and a second packet. When the error correction record of the first packet indicates that the decoding process of the first packet is unsuccessful, the controller generates a set of error position information according to the error correction record of the second packet, and requests the error correction decoder to perform another decoding process on the first packet according to the error position information.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
33.
Method and circuit for estimating channel state and associated receiver
A method for estimating a channel state of an audio/video signal includes: estimating a first response and a second response according to the audio/video signal, wherein the first response corresponds to an echo path and the second response corresponds to a reference path; calculating a plurality of phase differences at a plurality of time points between the first response and the second response; determining whether the echo path is a Doppler path according to the phase differences; and when it is determined that the echo path is the Doppler path, calculating a phase rotation frequency of the Doppler path according to a difference between at least two of the phase differences.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
34.
Method of background residual prediction for video coding
A method and apparatus for video encoding or decoding utilizing adaptive background residual prediction is disclosed. The present invention adaptively applies background residual prediction to a current block based on a selection decision. The coding block is split into one or more coding sub-blocks. A reference sub-block in a reference picture is located for a current coding sub-block of the current coding block according to a motion vector associated with the current coding block. A background reference sub-block in a background picture is located for the reference sub-block, where the background reference sub-block is at a first co-located location as the reference sub-block. The method then selects a first predictor or a second predictor to encode or decode the current sub-block based on a selection decision. The first predictor corresponds to the reference sub-block, and the second predictor is derived according to the reference sub-block and the background picture.
H04N 19/17 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
H04N 19/46 - Embedding additional information in the video signal during the compression process
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
H04N 19/103 - Selection of coding mode or of prediction mode
H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
H04N 19/119 - Adaptive subdivision aspects e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
H04N 19/147 - Data rate or code amount at the encoder output according to rate distortion criteria
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/553 - Motion estimation dealing with occlusions
35.
Control circuit of multimedia device and data processing method thereof
A data processing method of a multimedia device is disclosed. The multimedia device pauses playback of multimedia data in response to a pause signal. The method includes: buffering the multimedia data before the pause signal is received to obtain prerecorded multimedia data; writing the prerecorded multimedia data into a storage unit in response to the pause signal; reading the prerecorded multimedia data from the storage unit in response to a playback signal; and playing the prerecorded multimedia data.
H04N 21/439 - Processing of audio elementary streams
H04N 21/6336 - Control signals issued by server directed to the network components or client directed to client directed to decoder
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H04N 21/433 - Content storage operation, e.g. storage operation in response to a pause request or caching operations
H04N 19/15 - Data rate or code amount at the encoder output by monitoring actual compressed data size at the memory before deciding storage at the transmission buffer
H04N 5/073 - Arrangements or circuits at the transmitter end for mutually locking plural sources of synchronising signals, e.g. studios or relay stations
H04N 21/24 - Monitoring of processes or resources, e.g. monitoring of server load, available bandwidth or upstream requests
H04N 21/44 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
36.
Electronic device and associated signal processing method
An electronic device includes a transmission interface, a driving circuit, a receiving circuit, a sampling circuit, a detecting circuit, a timing control circuit and a processing circuit. The transmission interface is for connecting to another electronic device via a connecting cable. The driving circuit outputs a backward signal via the transmission interface to the another electronic device. The receiving circuit receives a received signal including the backward signal and a forward signal from the transmission interface. The sampling circuit samples the received signal to obtain a plurality of sample results. The detecting circuit detects transitions of the sample results to obtain a plurality of detection results. The processing circuit generates a control signal according to the detection results, and adjusts a time point at which the driving circuit outputs the backward signal through the timing control circuit.
Video playback method and control terminal thereof are provided. The invention receives video data stream, determines if a to-be-decoded frame meets a discard condition according to the time stamp of the to-be-decoded frame, if the discard condition is met, discards the non-reference frame to be decoded in the video data stream, and if the discard condition is not met, decodes the to-be-decoded frame into to-be-output frame; determines if the to-be-output frame meets the discard condition according to the time stamp of the to-be-output frame; if the discard condition is met, discards the to-be-output frame; if the discard condition is not met, outputs the to-be-output frame as output frame, such that the time intervals of the time stamps of the sequentially output frames according to the display order are equal.
H04N 5/765 - Interface circuits between an apparatus for recording and another apparatus
H04N 21/43 - Processing of content or additional data, e.g. demultiplexing additional data from a digital video streamElementary client operations, e.g. monitoring of home network or synchronizing decoder's clockClient middleware
H04N 21/8547 - Content authoring involving timestamps for synchronizing content
H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
H04N 19/132 - Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
38.
Method for playing data and apparatus and system thereof
A method for data playing and an associated apparatus and system are provided. The method may be applied to a player apparatus. The player apparatus receives the data to be played from outside and stores the received data in a buffer. The method specifically includes the steps of: determining whether an amount of buffered data for the data to be played in the buffer is changed, wherein the buffered data input speed for the buffer is fixed; and when determining that the amount of buffered data is changed, adjusting a playing speed of the player apparatus, such that the buffered data output speed and the buffered data input speed are the same for the buffer.
G10L 21/043 - Time compression or expansion by changing speed
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
39.
Digital signal up-converting apparatus and related digital signal up-converting method
A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.
G01R 21/06 - Arrangements for measuring electric power or power factor by measuring current and voltage
G01R 23/00 - Arrangements for measuring frequenciesArrangements for analysing frequency spectra
H03F 1/24 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively in discharge-tube amplifiers
A video processing apparatus includes an external storage device, a hardware entropy engine, and a software execution engine. The hardware entropy engine performs entropy processing of a current picture, and further outputs count information to the external storage device during the entropy processing of the current picture. When loaded and executed by the software execution engine, a software program instructs the software execution engine to convert the count information into count table contents, and generate a count table in the external storage device according to at least the count table contents. The count table is referenced to apply a backward adaptation to a probability table that is selectively used by the hardware entropy engine to perform entropy processing of a next picture.
H04N 19/13 - Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
H04N 19/91 - Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
41.
Video transmitting system with on-the-fly encoding and on-the-fly delivering and associated video receiving system
A video transmitting system includes a source buffer, a video encoder, a bitstream buffer, and a transmitting circuit. The source buffer receives pixel data of pixels of a video frame. The video encoder retrieve pixel data of a portion of the pixels of the video frame from the source buffer, and starts encoding the pixel data of the portion of the pixels before pixel data of a last pixel of the video frame is received by the source buffer. The bitstream buffer receives a network abstraction layer (NAL) stream from the video encoder, wherein the NAL stream is generated by encoding the pixel data of the portion of the pixels. The transmitting circuit retrieves the NAL stream from the bitstream buffer, and starts outputting the NAL stream before the pixel data of the last pixel of the video frame is encoded by the video encoder.
H04N 19/10 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
H04N 19/15 - Data rate or code amount at the encoder output by monitoring actual compressed data size at the memory before deciding storage at the transmission buffer
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04N 19/423 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
H04N 19/436 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
H04N 19/182 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a pixel
A television system includes: a storage unit, storing a plurality of candidate multimedia files and a plurality of program instructions; a display unit; a trigger signal receiving unit, receiving a trigger signal; and a processing unit, executing the program instructions to perform operations of: playing a target multimedia file via the display unit, generating target characteristic information according to the target multimedia file, generating a plurality of sets of candidate characteristic information respectively corresponding to the candidate multimedia files according to the candidate multimedia files, selecting one of the candidate multimedia files according to the target characteristic information and the candidate characteristic information in response to the trigger signal, and playing the selected candidate multimedia file via the display unit to replace the playback of the target multimedia file.
A device providing an automatic channel changing function includes: a receiving unit, receiving recommended program data, first user data and second user data from a first AV playing device; a storage unit, storing reference data; a look-up unit, generating channel changing data according to the recommended program data, the first user data, the second user data and the reference data; and a transmitting unit, transmitting the channel changing data to a second AV playing device according to the second user data.
H04N 21/442 - Monitoring of processes or resources, e.g. detecting the failure of a recording device, monitoring the downstream bandwidth, the number of times a movie has been viewed or the storage space available from the internal hard disk
H04N 21/438 - Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
H04N 21/466 - Learning process for intelligent management, e.g. learning user preferences for recommending movies
H04N 21/482 - End-user interface for program selection
H04N 21/84 - Generation or processing of descriptive data, e.g. content descriptors
H04N 21/41 - Structure of clientStructure of client peripherals
H04N 21/434 - Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams or extraction of additional data from a video streamRemultiplexing of multiplex streamsExtraction or processing of SIDisassembling of packetised elementary stream
H04N 21/8547 - Content authoring involving timestamps for synchronizing content
H04N 21/658 - Transmission by the client directed to the server
An equalizing apparatus includes a feedforward filter, a soft slicer and a feedback filter. The feedforward filter processes an input signal. The soft slicer performs a soft decision according to an input signal of the feedforward filter and a feedback signal of the feedback filter to generate a decision result signal. The feedback filter generates the feedback signal according to the decision result signal.
An image-based motion sensor has a camera system and a processing system. The camera system generates an image output including a plurality of captured images. The processing system obtains a motion sensor output by processing the image output, and identifies a user input as one of a plurality of pre-defined user actions according to the motion sensor output. Different functions of at least one application performed by one electronic device are controlled by the pre-defined user actions. The motion sensor output includes information indicative of at least one of a motion status and an orientation status of the image-based motion sensor. Each of the captured images has more than one color component, and only values of one single color component are involved in obtaining the motion sensor output.
A communication device includes: a detecting unit, performing a mobility detection in a time interval to generate a detection result; a selecting unit, selecting a channel estimation method from a plurality of channel estimation methods according to the detection result; and a channel estimating unit, coupled to the selecting unit, performing a channel estimation on a channel for receiving a signal according to the selected channel estimation method.
A stream decoding method is provided. The stream includes a plurality of frames. The method includes: obtaining a display order of a current frame that belongs to a group by parsing a header of the current frame; and determining whether to decode the current frame or to drop instead of decoding the current frame according to the display order of the current frame.
H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
G06K 9/36 - Image preprocessing, i.e. processing the image information without deciding about the identity of the image
H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
H04N 19/132 - Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
H04N 19/156 - Availability of hardware or computational resources, e.g. encoding based on power-saving criteria
48.
Multimedia communication apparatus and control method for multimedia data transmission over standard cable
A multimedia communication apparatus, suitable for a first multimedia apparatus, is adapted to transmit or receive multimedia data and is electrically connectable to a standard connector. The standard connector may be non-reversibly or reversibly connected to a plug of a standard cable, and includes a plurality of the pins. The pins include multiple differential signal pins serving as multiple multimedia channels, a power pin serving as a power line, a first polarity pin, a first data pin and a ground pin. The multimedia communication apparatus includes a control logic and a multimedia signal processor. The multimedia signal processor transmits or receives multimedia data to/from a second multimedia apparatus through the multimedia channels, and further power handshakes or exchanges information with the second multimedia apparatus. The information is for controlling a multiplexer to switch the multimedia channels.
A communication apparatus for correcting a situation of a spectrum inverted signal includes a channel estimation module and an equalization module. The channel estimation module determines a channel estimation parameter, and receives at least one frame signal to generate a convolution restored frame signal corresponding to the frame signal. The equalization module includes a first computation circuit and a second computation circuit. The first computation circuit receives the channel estimation parameter and the convolution restored frame signal to generate a transformation channel estimation parameter and a transformed convolution restored frame signal. The second computation circuit receives the transformed channel estimation parameter and the transformed convolution restored frame signal to generate an original frame signal corresponding to the frame signal. The first computation circuit further feeds back a transient original frame signal to the channel estimation module to update the channel estimation parameter.
H04B 10/2531 - Arrangements specific to fibre transmission for the reduction or elimination of distortion or dispersion due to chromatic dispersion using spectral inversion
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
Adaptive envelope extracting apparatus, signal decoding apparatus and short-distance contactless communication apparatus applying the adaptive envelope extracting apparatus, and method thereof
An envelope extracting apparatus includes: a clock extracting device arranged to extract a clock signal of a receiving modulation signal according to a first biasing voltage; and an edge detecting device arranged to generate a detecting signal to indicate an envelope edge of the receiving modulation signal according to a delayed clock signal of the clock signal and a second biasing voltage.
A frame rate control method is provided. The frame rate control method includes the following step: detecting a frame rate of an image signal generated by an image processing apparatus to generate a first detection result; detecting a system load on the image processing apparatus to generate a second detection result; and determining whether to provide a frame rate limit to limit the frame rate according to at least the first detection result and the second detection result.
A method for correcting flickers in a single-shot multiple-exposure image and associated apparatus is provided. The single-shot multi-exposure image includes first image data and second image data. The method includes the steps of: computing a first vertical profile for the first image data and a second vertical profile for the second image data; computing a flicker modulation function according to the first vertical profile and the second vertical profile; and multiplying each pixel in the second image data by the flicker modulation function to correct flickers.
A control method for a decision feedback equalizer (DFE) includes: generating a channel impulse response (CIR) estimation vector according to an input signal at a CIR estimation frequency; generating an FFE coefficient according to the CIR estimation vector at a first frequency; generating an FBE coefficient according to the CIR estimation vector, and the FFE coefficient at a second frequency; generating a feed-forward equalization filtered result according to the input signal and the FFE coefficient; generating a feed-backward equalization filtered result according to a decision signal and the FBE coefficient; and generating an updated decision signal according to the feed-forward equalization filtered result and the feed-backward equalization filtered result. At least one of the first frequency and the second frequency is smaller than the CIR estimation frequency.
A method of handling a near field communications (NFC) device includes setting a low power polling number, wherein the low power polling number is non-fixed; detecting whether any NFC device is nearby; performing low power polls until either at least one NFC device is detected or the number of low power polls reaches the low power polling number; performing a full power polling; and adjusting the low power polling number after the full power polling.
A buffer write method for a buffer, including a plurality of M-bit storage units, has following steps: obtaining pixel data of a plurality of first N-bit pixels of a picture; calculating a corresponding start address of the buffer for the pixel data of the first N-bit pixels; and storing the first N-bit pixels of the picture according to the calculated start address of the buffer in the M-bit storage units by a buffer controller. The storing step includes fully storing at least one of the first N-bit pixels in one of the M-bit storage units storage units, wherein M and N are positive integers, and M is not divisible by N.
An integrated circuit includes a data sampler and a digital logic circuit. The data sampler provides multiple signal samples at a speed twice a symbol rate according to a local clock signal and the inverted local clock signal. The signal samples include a first symbol sample, and a second symbol sample that occurs later than the first symbol sample. The signal samples further include an interpolated sample between the first and second symbol samples. The digital logic circuit compares the first symbol sample with the interpolated sample to generate pre phase correction data, and compares the second symbol sample with the interpolated sample to generate post phase correction data. The pre phase correction data is generated earlier than the post phase correction data. The local clock signal and the inverted local clock signal have substantially a phase difference of 180 degrees.
A sequence estimation device includes a grouping unit, a sequence estimation unit and a combination unit. The grouping unit groups a first plurality of equalized signals into a plurality of equalized signal groups according to a grouping rule. The sequence estimation unit, coupled to the grouping unit, processes the plurality of equalized signal groups according to a sequence estimation rule to obtain a plurality of estimated signal groups, respectively. The combination unit, coupled to the sequence estimation unit, permutes the plurality of estimated signal groups to a plurality of estimated signals according to the grouping rule.
A method and system for encoding a group of coding blocks and packetizing the compressed data into slices/packets with hard-limited packet size are disclosed. According to the present invention, a packetization map for at least a portion of a current picture is determined. The packetization map associates coding blocks in at least a portion of the current picture with one or more packets by identifying a corresponding group of coding blocks for each packet of said one or more packets. The corresponding group of coding blocks for each packet is then encoded according to the packetization map and the size of each packet is determined. The packet size is checked. If any packet size exceeds a constrained size, a new packetization map is generated and the corresponding group of coding blocks for each packet is encoded according to the new packetization map.
H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
H04N 19/17 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
H04N 19/15 - Data rate or code amount at the encoder output by monitoring actual compressed data size at the memory before deciding storage at the transmission buffer
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/174 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
H04N 19/169 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
59.
Smart playback method for TV programs and associated control device
A smart playback method for TV programs includes: converting voice data to text data including a plurality of words; selecting a keyword from the words in the text data; providing a TV program according to the keyword; and controlling a screen to play the TV program.
G10L 21/00 - Speech or voice signal processing techniques to produce another audible or non-audible signal, e.g. visual or tactile, in order to modify its quality or its intelligibility
H04N 21/443 - OS processes, e.g. booting an STB, implementing a Java virtual machine in an STB or power management in an STB
H04N 21/422 - Input-only peripherals, e.g. global positioning system [GPS]
H04N 21/482 - End-user interface for program selection
G06F 17/27 - Automatic analysis, e.g. parsing, orthograph correction
H04N 21/462 - Content or additional data management e.g. creating a master electronic program guide from data received from the Internet and a Head-end or controlling the complexity of a video stream by scaling the resolution or bit-rate based on the client capabilities
H04N 21/466 - Learning process for intelligent management, e.g. learning user preferences for recommending movies
60.
Electronic device capable of displaying and performing color compensation and color compensation method
The disclosure provides an electronic device capable of displaying and performing color compensation and a color compensation method. The color compensation method comprises: obtaining one or more brightness values for an original image from at least one of a screen brightness value and an ambient brightness value of the electronic device; determining whether each of the one or more brightness values is lower than a corresponding one of one or more threshold values, respectively; and enabling a color enhancement mode in events where each of the one or more brightness values is lower than the corresponding one of one or more threshold values, respectively, wherein the color enhancement mode comprises performing a color saturation compensation to enhance a saturation of the original image for display on a screen of the electronic device.
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G09G 5/02 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
61.
Processor and apparatus capable of reducing image flicker and a related method
An apparatus capable of reducing image flicker, including: a processor and an image capture device. The processor is configured to: detect whether a telecom operator is currently offering a telecommunication service to the apparatus; search a mapping history of utility frequencies from a storage device and determine whether the telecom operator is mapped to a utility frequency after detecting that the telecom operator is currently offering a telecommunication service to the apparatus; and obtain the utility frequency mapped to the telecom operator from the mapping history to be a current utility frequency after determining the utility frequency mapped to the telecom operator. The image capture device, coupled to the processor, is configured to operate with an exposure time adjusted according to the current utility frequency.
H04N 5/235 - Circuitry for compensating for variation in the brightness of the object
H04W 4/02 - Services making use of location information
H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
A control method for a delay locked loop includes: delaying an input signal to generate an internal signal; delaying the internal signal to generate an output signal; and selectively providing a reference clock signal or the output signal as the input signal according to the output signal and the internal signal.
H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
63.
Method and apparatus for self-forming a tree topology network in a communications network
A method for self-forming a tree topology network is provided. The method is used in a communications apparatus. The method includes: broadcasting a discovery message; determining whether the communications apparatus receives one or more discovery responses from one or more nodes in a lower level of the tree topology network; and establishing a link with each node in the lower level according to the discovery responses.
A capacitive sensor structure includes: a substrate; a multilayer wire structure, disposed on the substrate to form a passive sensing circuit; and a semiconductor chip, formed thereon a control circuit, fixedly mounted on a surface of the substrate and electrically connected to the multilayer wire structure.
A decoding method applied to a convolutionally coded signal is provided. The method includes: adjusting first input information according to a first scaling factor to generate first a-priori information; b) decoding the convolutionally coded signal according to systematic information and the first a-priori information to generate first extrinsic information; c) adjusting second input information according to a second scaling factor to generate second a-priori information, wherein the second scaling factor is generated according to the first extrinsic information and the first a-priori information; and d) decoding the convolutionally coded signal according to the systematic information and the second a-priori information to generate second extrinsic information. One of step (b) and step (d) further generates a-posteriori information as a decoding result.
A rendering method executed by a graphics processing unit includes: loading a vertex shading command from a first command queue to a shader module; executing the vertex shading command for computing the varying of the vertices to perform a vertex shading operation by taking the vertices as first input data; storing first tessellation stage commands into a second command queue; loading the first tessellation stage commands to the shader module; and executing the first tessellation commands for computing first tessellation stage outputs to perform a first tessellation stage of the one or more tessellation stages by taking the varying of the vertices as second input data. The vertex shading command is stored into the first command queue by a first processing unit. The varying of the vertices and the first tessellation stage outputs are stored in a cache of the graphics processing unit.
A hybrid video encoding method and system using a software engine and a hardware engine. The software engine receives coding unit data associated with a current picture, and performs a first part of the video encoding operation by executing instructions. The first part of the video encoding operation generates an inter predictor and control information corresponding to the coding unit data of the current picture. The first part of the video encoding operation stores the inter predictor into an off-chip memory. The hardware engine performs a second part of the video encoding operation according to the control information. The second part of the video encoding operation receives the inter predictor, and subtracts the inter predictor from the coding unit data to generate a residual signal. The second part of the video encoding operation then transforms and quantizes the residual signal to generate transformed and quantized residual signal, and encodes the transformed and quantized residual signal to generate an encoded video bitstream.
H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
H04N 19/43 - Hardware specially adapted for motion estimation or compensation
H04N 19/433 - Hardware specially adapted for motion estimation or compensation characterised by techniques for memory access
H04N 19/423 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
68.
Apparatus for dynamically adjusting video decoding complexity, and associated method
An apparatus for dynamically adjusting video decoding complexity includes a decoding resolution control circuit and an adaptive spatial resolution decoder. The decoding resolution control circuit is arranged to dynamically determine whether at least one portion of multiple frames should be decoded in accordance with a specific resolution differing from an original resolution of the frames. In addition, the adaptive spatial resolution decoder is arranged to decode the frames according to whether the at least one portion of the frames should be decoded in accordance with the specific resolution. In particular, the apparatus further includes a system capability analyzing circuit arranged to analyze system capability of at least a portion of the apparatus, in order to generate analyzing results for being sent to the decoding resolution control circuit. An associated method is also provided.
H04N 19/59 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
H04N 19/159 - Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
H04N 19/132 - Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
H04N 19/152 - Data rate or code amount at the encoder output by measuring the fullness of the transmission buffer
H04N 19/156 - Availability of hardware or computational resources, e.g. encoding based on power-saving criteria
H04N 19/177 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a group of pictures [GOP]
H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
H04N 19/11 - Selection of coding mode or of prediction mode among a plurality of spatial predictive coding modes
H04N 19/117 - Filters, e.g. for pre-processing or post-processing
H04N 19/139 - Analysis of motion vectors, e.g. their magnitude, direction, variance or reliability
H04N 19/43 - Hardware specially adapted for motion estimation or compensation
69.
Video frame transmitting system and video frame transmitting method
A video frame transmitting system transmitting at least one output video frame to a display based on content of at least one input video frame. The video frame transmitting system has a display driver receiving an active input video frame and outputting the active input video frame as the output video frame to the display. The video frame transmitting system comprises: an application processor, receiving the input video frame, for determining the input video frame as the active input video frame if the content of the input video frame is different from content of a previous input video frame, and for determining the input video frame as a skip input video frame if the content of the input video frame is the same as the content of the previous input video frame. The application processor outputs the active input video frame to the display driver but does not output the skip input video frame.
A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.
G01R 21/06 - Arrangements for measuring electric power or power factor by measuring current and voltage
G01R 23/00 - Arrangements for measuring frequenciesArrangements for analysing frequency spectra
H03F 1/24 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively in discharge-tube amplifiers
A device for eliminating a channel effect is provided. A time-domain channel estimating unit generates a channel estimation result according to a first reference signal. A fast Fourier transform (FFT) unit performs FFT on the channel estimation result to generate a plurality of channel frequency responses corresponding to a plurality of frequency indices. An adjusting unit receives a plurality of input signals, and determines whether to adjust the input signal of each of the frequency indices according to the amplitude of the channel frequency response of each of the frequency indices to generate a set of adjusted signals. An inverse fast Fourier transform (IFFT) unit performs IFFT on a set of output signals associated with the set of adjusted signals to generate a feedback signal. The time-domain channel estimating unit further generates another channel estimation result according to a second reference signal and the feedback signal.
An electronic device and an associated method for displaying image data on a first display device of a first electronic device and a second display device of a second electronic device external of the first electronic device are provided. The method includes the steps of: determining whether image data to be displayed on the first and second display devices are the same; when the image data to be displayed on the first and second display devices are the same, estimating the first resource consumption required when the extension mode is selected for displaying the image data and the second resource consumption required when the mirror mode is selected for displaying the image data; and determining to display the image data on the first and second display devices in the extension mode or the mirror mode according to the first and second estimated resource consumption.
A Viterbi decoding apparatus includes a main decoder, a re-encoder, an adjusting module, a secondary decoder and a secondary result generating module. The main decoder performs a Viterbi decoding process on input data to generate a set of main decoded results. The re-encoder performs a convolutional encoding process on the set of main decoded results to generate a set of re-encoded results. The adjusting module adjusts the input data according to the set of re-encoded results to generate adjusted input data corresponding to a predetermined path in a Viterbi trellis diagram. The secondary decoder generates a plurality of symbols according to the adjusted input data. The secondary result generating module generates a set of secondary decoded results according to the plurality of symbols and the set of main decoded results.
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
75.
Method and data processing apparatus supporting simultaneous playback
A data processing apparatus supporting simultaneous playback includes a processor, two tuners, a receiving element and a transmitting element. The first tuner generates first television data transmitted via a first frequency range, and provides the first television data to an internal playback device. The second tuner generates second television data transmitted via a second frequency range. The receiving element receives a data request for a selected television channel from an external electronic device. In response to the data request, the processor controls the second tuner to generate the second television data including video/audio data of the selected television channel. When the internal playback device performs playback according to the first television data, the transmitting element transmits the video/audio data of the selected television channel to the external electronic device for playback.
H04N 21/41 - Structure of clientStructure of client peripherals
H04N 21/437 - Interfacing the upstream path of the transmission network, e.g. for transmitting client requests to a VOD server
H04N 21/462 - Content or additional data management e.g. creating a master electronic program guide from data received from the Internet and a Head-end or controlling the complexity of a video stream by scaling the resolution or bit-rate based on the client capabilities
76.
Time de-interleaving circuit and time de-interleaving method for reducing a number of times of accessing memory
A time de-interleaving circuit applied to a communication system to de-interleave an interleaved signal is provided. The interleaved signal includes a plurality of cells. The time de-interleaving circuit includes a memory module and a buffering memory module. The memory module stores the cells, which are in a unit of a plurality of cells to form a plurality of cell groups. The memory module is accessed in a unit of one cell group. The buffering memory module buffers a part of the cells from the memory module to arrange an output sequence of the cells.
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
H03M 13/05 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
G06F 3/06 - Digital input from, or digital output to, record carriers
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/25 - Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
77.
Methods and apparatus for intra picture block copy in video compression
Implementations of techniques of intra picture block copy in video compression are described. In one example implementation, a method may include: identifying a first block of pixels of a plurality of pixels of a picture as a reference block for reconstructing a second block of pixels of the plurality of pixels of the picture; determining an overlapped region of the second block that overlaps with the first block; and reconstructing pixels in the overlapped region based on a first set of pixels and a second set of pixels of the first block.
H04N 11/02 - Colour television systems with bandwidth reduction
H04N 19/593 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial prediction techniques
H04N 19/139 - Analysis of motion vectors, e.g. their magnitude, direction, variance or reliability
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/11 - Selection of coding mode or of prediction mode among a plurality of spatial predictive coding modes
H04N 19/583 - Motion compensation with overlapping blocks
H04N 19/182 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a pixel
H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
78.
Electronic device with equalization, integrated circuit and methods therefor
An electronic device for a wireless communication system is described. The electronic device comprises: a receiver configured to receive a modulated signal on a communication channel; and a processor, coupled to the receiver and configured to: process the received modulated signal; identify a communication channel characteristic based on the processed received modulated signal; select an equalizer having a first set of equalization coefficients based on the identified communication channel characteristic, wherein the first set of equalization coefficients is selected from a plurality of equalization coefficients, each of the plurality of equalization coefficients being associated with different communication channel characteristics; equalize the processed received modulated signal on the communication channel using the selected equalizer; and detect the equalized received modulated signal.
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
H04W 4/00 - Services specially adapted for wireless communication networksFacilities therefor
H04B 5/00 - Near-field transmission systems, e.g. inductive or capacitive transmission systems
H04L 1/20 - Arrangements for detecting or preventing errors in the information received using signal-quality detector
G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
79.
Self testing device for memory channels and memory control units and method thereof
A memory self-testing device for testing a plurality of memory control units includes: a test control unit, coupled to the memory control units, generating a plurality of access request signals and a plurality of sets of data; a channel control unit, coupled to the test control unit and the memory control units, determining a leading feedback signal among a plurality of feedback signals; and a data control unit, coupled to the test control unit and the memory control units, storing the sets of data, and transmitting the sets of data to the memory control units according to a plurality of read/write signals. The feedback signals and the read/write signals are generated by the memory control units in response to the access request signals. The test control units generate the sets of data according to the leading feedback signal.
G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store
G11C 29/16 - Implementation of control logic, e.g. test mode decoders using microprogrammed units, e.g. state machines
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
A display method for video conferencing and an associated video conferencing system are provided. The video conferencing system includes a display, an image capturing unit, and a network interface unit. The method includes the steps of: utilizing the image capturing unit to capture images of a local user in a video conference; performing foreground segmentation on the captured images to obtain a foreground object; flipping the foreground object horizontally; identifying a human face from the flipped foreground object and correcting a facing angle of the human face; determining interaction data from the local user on the display; encoding the interaction data and the flipped foreground object into an interaction stream and a video stream, respectively; packing the interaction stream and the video stream into an output stream; and transmitting the output stream to a remote user of the video conference through the network interface unit.
G06F 3/0488 - Interaction techniques based on graphical user interfaces [GUI] using specific features provided by the input device, e.g. functions controlled by the rotation of a mouse with dual sensing arrangements, or of the nature of the input device, e.g. tap gestures based on pressure sensed by a digitiser using a touch-screen or digitiser, e.g. input of commands through traced gestures
G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
G06T 3/60 - Rotation of whole images or parts thereof
G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
G06F 3/0484 - Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
G06F 1/16 - Constructional details or arrangements
H04M 1/02 - Constructional features of telephone sets
81.
Syntax parsing apparatus with multiple syntax parsing circuits for processing multiple image regions within same frame or processing multiple frames and related syntax parsing method
A syntax parsing apparatus includes a plurality of syntax parsing circuits and a dispatcher. Each of the syntax parsing circuits has at least entropy decoding capability. The syntax parsing circuits generate a plurality of entropy decoding results of a plurality of image regions within a same frame, respectively. The dispatcher assigns bitstream start points of the image regions to the syntax parsing circuits, and triggers the syntax parsing circuits to start entropy decoding, respectively.
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
H04N 19/436 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
H04N 19/593 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial prediction techniques
H04N 19/91 - Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
H04N 19/127 - Prioritisation of hardware or computational resources
H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
H04N 19/174 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
H04N 19/184 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being bits, e.g. of the compressed video stream
H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
82.
Video decoding apparatus and method for selectively bypassing processing of residual values and/or buffering of processed residual values
An exemplary video decoding apparatus includes a first decoding unit configured for decoding a first encoded block to generate first residual values, a first detecting unit configured for detecting whether all of the first residual values have a same first value, a first processing circuit configured for processing the first residual values to generate first processed residual values, and a second processing circuit configured for generating a decoded block corresponding to the first encoded block. When all of the first residual values have the same first value, the first detecting unit controls the second processing circuit to generate the decoded block without referring to the first processed residual values.
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/129 - Scanning of coding units, e.g. zig-zag scan of transform coefficients or flexible macroblock ordering [FMO]
H04N 19/12 - Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264
A wireless receiving device includes: a time-domain channel estimation circuit, generating channel information in the time domain according to a part of a received signal; a fast Fourier transform (FFT) circuit, coupled to the time-domain channel estimation circuit, transforming another part of the received signal and the channel information to the frequency domain to generate a plurality of sets of received data; an equalizer, coupled to the FFT circuit, adjusting the received data to generate a plurality of sets of complex equalized data; an adjusting unit, coupled to the equalizer, adjusting the sets of complex equalized data such that the sets of adjusted equalized data is closer to the origin of a complex plane; and a decision circuit, generating a plurality of sets of binary data according to the sets of adjusted equalized data.
An apparatus for multi-standard bin decoding in a video decoder for decoding two video coded in two different video coding standards is disclosed. The apparatus includes a first bin decoder to decode one or more first bin strings, a second bin decoder to decode one or more second bin strings, a standard change control module coupled to the first bin decoder and the second bin decoder and a system controller coupled to the standard change control module, the first bin decoder and the second bin decoder. The standard change control module or the system controller selects either a next slice or picture to be decoded by the first bin decoder or the second bin decoder based on one or more control parameters including the decoding time information.
H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
H04N 19/174 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
H04N 19/91 - Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
85.
Estimating method, sampling frequency offset calculating method, and phase estimating method and device
An estimating method for estimating a phase difference of two frames is provided. The estimating method includes: providing a first sequence according to a header of a first frame; providing a second sequence according to a header of a second frame, wherein the first and second frames are successive frames, and the first and second sequences are pseudo noise sequences; performing a correlation calculation according to the first and second sequences to generate a plurality of correlation values; and estimating the phase difference between the first and second frames according to the correlation values.
A communication system includes a receiving circuit and a phase error estimating circuit. The receiving circuit receives an input signal x, which has an input phase θ in a polar coordinate system. According to partial differentiation performed on the natural logarithm of a function f(x, θ), the phase error estimating circuit generates an estimated phase error of the input signal x. f(x, θ) represents a probability function of receiving the input signal x at the receiving circuit.
A graphics processing unit (GPU) is provided to preemptively flush one or more bins. The GPU generates bin data of a display area according to an association of primitive data with the bins that correspond to the display area. Upon detecting an adaptive condition, a signal is generated to indicate that one or more bins of a first frame are to be flushed in a first order before the first frame is fully binned. The signal interrupts bin flush of a second frame in a second order in order to flush the one or more bins of the first frame in the first order. After the one or more bins of the first frame are flushed, the bin flush of the second frame is resumed in the second order.
A method for testing an Integrated Circuit (IC) with Near Field Communication (NFC) technology according to a first embodiment of the present invention includes: utilizing a BB modem of the IC to generate a known data pattern; modulating the known data pattern to generate a modulated data pattern; sending the modulated data pattern on the transmitting path to an NFC antenna of the IC and utilizing the NFC antenna to loop the modulated data pattern back to the receiving path; demodulating the modulated data pattern; and determining if the data pattern on the transmitting path is the same as the data pattern on the receiving path. When the data pattern on the transmitting path is not the same as the data pattern on the receiving path, it is determined that the IC fails.
A video displaying method, applied to an electronic apparatus comprising a first display, comprising: (a) selecting a plurality of video contents from a plurality of candidate video contents; and (b) simultaneously displaying selected video contents selected in the step (a), respectively in sub-windows on the first display. Related video decoding methods are also disclosed.
H04N 21/472 - End-user interface for requesting content, additional data or servicesEnd-user interface for interacting with content, e.g. for content reservation or setting reminders, for requesting event notification or for manipulating displayed content
H04N 21/2343 - Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements
H04N 21/482 - End-user interface for program selection
H04N 21/462 - Content or additional data management e.g. creating a master electronic program guide from data received from the Internet and a Head-end or controlling the complexity of a video stream by scaling the resolution or bit-rate based on the client capabilities
H04N 21/4402 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
H04N 21/458 - Scheduling content for creating a personalised stream, e.g. by combining a locally stored advertisement with an incoming streamUpdating operations, e.g. for OS modules
A signal receiver with adaptive software information adjustment of a communication system is provided. The signal receiver receives a modulated signal comprising a plurality of packets, and includes: a demodulating circuit, configured to demodulate the modulated signal to generate a plurality of sets of soft information corresponding to each packet; a software information adjusting circuit, coupled to the demodulating circuit, configured to adjust the sets of soft information according to a distribution of the sets of soft information corresponding to each packet; a quantizer, coupled to the soft information adjusting circuit, configured to quantize the adjusted sets of soft information to generate a plurality of sets of data; and a decoder, coupled to the quantizer, configured to decode the data.
A method and apparatus for three-dimensional video encoding and decoding using disparity derived depth prediction are disclosed. Embodiments of the present invention determine a disparity vector related to a collocated texture block in the dependent view and generate converted depth samples from the disparity vector. The generated converted depth samples are used as a predictor or Merge candidate for the current depth block. The Merge candidate corresponding to the converted depth samples can be placed in the merging candidate list at a location before TMVP (temporal motion vector predictor) merging candidate. The converted depth samples can be generated from the disparity vector according to a function of the disparity vector. Information associated with the function can be signaled explicitly to a decoder or derived implicitly by the decoder. One aspect of the present invention addresses simplified disparity to depth conversion, specifically division-free disparity-to-depth conversion.
H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
H04N 13/161 - Encoding, multiplexing or demultiplexing different image signal components
H04N 19/597 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding specially adapted for multi-view video sequence encoding
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/46 - Embedding additional information in the video signal during the compression process
H04N 19/136 - Incoming video signal characteristics or properties
H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
H04N 19/52 - Processing of motion vectors by encoding by predictive encoding
H04N 13/00 - Stereoscopic video systemsMulti-view video systemsDetails thereof
92.
Method for controlling lighting element and associated system
A method for controlling at least one lighting element includes: setting a dimming speed; determining a dimming level according to the dimming speed; and using the dimming level to perform a stepped dimming operation to brighten or dim the lighting element.
A receiving circuit for a digital television is provided. The receiving circuit of the digital television, adapted to process a digital television signal to generate transmission data, includes: a front-end circuit, configured to process the digital television signal to generate an interleaved signal; a setting unit, configured to provide a setting value associated with a digital video standard of the digital television signal; a frequency de-interleaving and time de-interleaving circuit, configured to select a frequency de-interleaving scheme and a time de-interleaving scheme corresponding to different digital video standards according to the setting value, and to process the interleaved signal to generate a de-interleaved signal; a quadrature amplitude modulation (QAM) demapping circuit, configured to demap the de-interleaved signal to generate a demapped signal; and a decoder, configured to decode the demapped signal to generate the transmission data.
H04N 21/434 - Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams or extraction of additional data from a video streamRemultiplexing of multiplex streamsExtraction or processing of SIDisassembling of packetised elementary stream
H04N 21/234 - Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs
H04N 21/44 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
H04N 21/438 - Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
94.
Display control method and device for application program interface
A display control method for an application program interface is provided. The method includes: determining an appropriate resolution corresponding to the application program to be executed from at least two selectable resolutions; determining configuration information according to the appropriate resolution; establishing a display window having a size equal to a size corresponding to the appropriate resolution according to the configuration information, and loading a resource file corresponding to the application program interface; and rendering the application program interface in the display window on the a display device according to the appropriate resolution and the resource file. Through the above method, the present invention is capable of selecting an appropriate resolution for displaying an application program interface.
G09G 5/00 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
G09G 5/391 - Resolution modifying circuits, e.g. variable screen formats
G09G 5/36 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of individual graphic patterns using a bit-mapped memory
95.
Signal demodulation apparatus and signal demodulation method
A signal demodulation apparatus includes: a clock generation device arranged to generate a clock signal according to an inputting modulation signal; and a demodulation device arranged to demodulate the inputting modulation signal to generate a demodulation signal according to the clock signal; wherein a signal edge of the clock signal substantially aligns to a turning point of the inputting modulation signal.
An embodiment of the invention provides a method of processing a mosaicked image. First, the mosaicked image is up-sampled along a first direction to generate a first intermediate image. Then, the first intermediate image is resized along the first direction to generate a second intermediate image. Next, the second intermediate image is up-sampled along a second direction to generate a third intermediate image. Afterward, the third intermediate image is resized along the second direction to generate a resized and partly demosaicked image.
A method and apparatus for video encoding or decoding utilizing adaptive background residual prediction is disclosed. The present invention adaptively applies background residual prediction to a current block based on a selection decision. The coding block is split into one or more coding sub-blocks. A reference sub-block in a reference picture is located for a current coding sub-block of the current coding block according to a motion vector associated with the current coding block. A background reference sub-block in a background picture is located for the reference sub-block, where the background reference sub-block is at a first co-located location as the reference sub-block. The method then selects a first predictor or a second predictor to encode or decode the current sub-block based on a selection decision. The first predictor corresponds to the reference sub-block, and the second predictor is derived according to the reference sub-block and the background picture.
H04N 7/12 - Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
H04N 19/147 - Data rate or code amount at the encoder output according to rate distortion criteria
H04N 19/17 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
H04N 19/119 - Adaptive subdivision aspects e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
98.
Transmitter circuit, communication unit and method for amplifying a complex quadrature signal
A transmitter circuit includes a frequency generation circuit configured to generate a local oscillator signal and a digital modulator configured to: receive data to be transmitted; quadrature modulate the received data to at least a first, Q, modulated value and a second, I, modulated value; examine the quadrature modulated data to determine if the first, Q, modulated value exceeds a limit, and in response thereto selectively modify the quadrature modulated values to a first modified, Q′, modulated value and a second modified, I′, modulated value thereby bringing only a value of the first modified, Q′, modulated value to within the limit. A local oscillator phase is selected in order to map the first modified, Q′, modulated value and second modified, I′, modulated value to desired quadrature values. A digital power amplifier, DPA, coupled to the digital quadrature modulator, is configured to amplify the quadrature modified modulated data.
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
Examples of efficient MAC address storage are described, including methods and an apparatus. A method may involve obtaining a plurality of identifications associated with one or more applications executed on a computing apparatus, with each identification of the plurality of identifications different from one another. The method may also involve storing an identification entry representative of the plurality of identifications associated with the one or more applications. The identification entry may require an amount of memory space for storage less than an amount of memory space required to store the plurality of identifications associated with the one or more applications. The plurality of identifications may be a plurality of MAC addresses. The one or more applications may be one or more virtual machines.
G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines
H04L 12/741 - Header address processing for routing, e.g. table lookup
H04L 29/12 - Arrangements, apparatus, circuits or systems, not covered by a single one of groups characterised by the data terminal
G06F 12/109 - Address translation for multiple virtual address spaces, e.g. segmentation
H04L 29/08 - Transmission control procedure, e.g. data link level control procedure
H04L 12/713 - Route fault prevention or recovery, e.g. rerouting, route redundancy, virtual router redundancy protocol [VRRP] or hot standby router protocol [HSRP] using node redundancy, e.g. VRRP
H04L 12/721 - Routing procedures, e.g. shortest path routing, source routing, link state routing or distance vector routing
100.
Video decoding method/device of detecting a missing video frame
Video decoding device is disclosed. The video decoding device comprises a demultiplexer, a first decoder and a controller. The demultiplexer receives a Transport Stream to recover video Packetized Elementary Stream (PES) to determine a presentation time stamp (PTS) and a decoding time stamp (DTS) in a PES header of the PES. The first decoder retrieves a video frame from the video PES to determine temporal reference of the video frame. The controller receives the PTS, the DTS, and the temporal reference to determine whether there is a missing video frame.
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
H04N 19/895 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving methods or arrangements for detection of transmission errors at the decoder in combination with error concealment
H04N 19/577 - Motion compensation with bidirectional frame interpolation, i.e. using B-pictures
H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
patents