The present invention provides a semiconductor device that exhibits a high field effect mobility. The semiconductor device has an oxide semiconductor, a first through fourth insulators, and a first through third conductors, wherein: the second insulator is disposed on the first insulator; the oxide semiconductor is disposed on the first insulator and covers the second insulator; the first conductor and the second conductor are disposed on the oxide semiconductor; the third insulator is disposed on the first conductor and the second conductor and has an opening that overlaps with a region between the first conductor and the second conductor; the fourth insulator overlays the oxide semiconductor and is disposed in the opening; the third conductor is disposed on the fourth insulator in the opening; in a cross-sectional view in the channel width direction, the height of the second insulator is greater than the width of the second insulator; the oxide semiconductor has, in a region overlaying the third conductor, a first layer, a second layer on the first layer, and a third layer on the second layer; the first layer has gallium; the second layer has indium oxide; the third layer has indium, gallium, and oxygen; and the indium content in the second layer is higher than the indium content in the third layer.
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
HMDs are worn on a user's head, and therefore, weight reduction is desired. The present invention realizes an HMD that is lightweight, has a wide adjustable range, and can be smoothly put on to a user's head. A flexible secondary battery is used as one power supply to this head-mounted device, and is disposed close to the occipital region. Having such flexibility means that it is possible to realize the HMD which can be bent according to the shape of the occipital region of the user, and which can be smoothly put on to the user's head.
G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
3.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
Provided is a semiconductor device that has a large on-state current. The semiconductor device includes a first conductive layer, a first insulating layer on the first conductive layer, a second conductive layer on the first insulating layer, an oxide layer, a first oxide semiconductor layer on the oxide layer, a second oxide semiconductor layer on the first oxide semiconductor layer, a second insulating layer on the second oxide semiconductor layer, and a third conductive layer on the second insulating layer. The first conductive layer has a first recess. The first insulating layer and the second conductive layer have a first opening at a position overlapping the first recess. In the first opening, the first oxide semiconductor layer is positioned opposite the first insulating layer with the oxide layer therebetween. In the first opening, the third conductive layer is positioned opposite the first oxide semiconductor layer with the second insulating layer therebetween. The oxide layer includes gallium oxide. The first oxide semiconductor layer includes indium oxide. The second oxide semiconductor layer includes one or both of gallium and indium.
G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H01L 21/203 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using physical deposition, e.g. vacuum deposition, sputtering
H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H05B 33/14 - Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
H10B 99/00 - Subject matter not provided for in other groups of this subclass
H10D 1/68 - Capacitors having no potential barriers
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10K 50/115 - OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers comprising active inorganic nanostructures, e.g. luminescent quantum dots
Provided is a novel display device. A first element layer includes a display drive unit and an image data processing unit. A second element layer includes a display unit and a storage unit. The display unit includes a pixel circuit. The storage unit includes a storage circuit. The image data processing unit has the function of generating second image data by performing a product-sum operation, based on a convolutional neural network, on first image data input to the image data processing unit. The display drive unit receives the second image data as input and has the function of driving the pixel circuit to perform display, based on the second image data, in the display unit. Weight data used in the convolutional neural network is data stored in the storage circuit.
G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
Provided is a highly reliable display device. The display device includes a first light-emitting device, a second light-emitting device, a first conductive layer, a second conductive layer, a first layer, a second layer, and a light-blocking layer. The first light-emitting device includes a first pixel electrode, a first electroluminescence layer disposed above the first pixel electrode, and a common electrode disposed above the first electroluminescence layer. The second light-emitting device includes a second pixel electrode, a second electroluminescence layer disposed above the second pixel electrode, and a common electrode disposed above the second electroluminescence layer. The first layer is located above the first conductive layer. The first pixel electrode contacts an upper surface and a side surface of the first layer and an upper surface of the first conductive layer. The second layer is located above the second conductive layer. The second pixel electrode contacts an upper surface and a side surface of the second layer and an upper surface of the second conductive layer. The light-blocking layer has a section which is located between the first pixel electrode and the second pixel electrode.
H10K 59/122 - Pixel-defining structures or layers, e.g. banks
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H05B 33/12 - Light sources with substantially two-dimensional radiating surfaces
H05B 33/14 - Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material
H05B 33/22 - Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of auxiliary dielectric or reflective layers
Provided is a novel semiconductor device. The semiconductor device comprises a first transistor, a second transistor, a driving transistor, and a light-emitting element, wherein one of the source and drain of the first transistor is connected to the gate of the driving transistor, which is a holding node for a video signal, and the other of the source and drain of the first transistor is connected to one of the source and drain of the second transistor and one electrode of a capacitive element. The first transistor and the second transistor are preferably OS transistors.
G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10K 59/123 - Connection of the pixel electrodes to the thin film transistors [TFT]
H10K 59/131 - Interconnections, e.g. wiring lines or terminals
Provided is a display apparatus with high light outcoupling efficiency. The present invention provides a display element having a plano-convex lens on a light-emitting element, wherein the plano-convex lens has a substantially rectangular shape in a top view, and the curvature of the convex side is different in a first direction parallel to a first side of the substantially rectangular shape and in a second direction perpendicular to the first side. Each of a cross section including the optical axis in the first direction and a cross section including the optical axis in the second direction has, in the following order proceeding from the apex of the convex side to the planar side of the plano-convex lens, a first region, a second region, and a third region with different surface curvatures, and the second region has the smallest radius of curvature. By using a plano-convex lens with such a shape, light emitted by the light-emitting element can be efficiently cast in a frontal direction.
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
G02B 3/06 - Simple or compound lenses with non-spherical faces with cylindrical or toric faces
H05B 33/14 - Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material
H10K 50/115 - OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers comprising active inorganic nanostructures, e.g. luminescent quantum dots
H10K 59/95 - Assemblies of multiple devices comprising at least one organic light-emitting element wherein all light-emitting elements are organic, e.g. assembled OLED displays
H10K 59/122 - Pixel-defining structures or layers, e.g. banks
The present invention provides an electronic device having an authentication function. The electronic device has a display unit. The display unit has a plurality of light-emitting elements and a plurality of light-receiving elements. The light-receiving element receives light emitted from the light-emitting element and then reflected from a subject. When the illuminance of external light is equal to or less than a first value, the light-emitting element emits light at a first illuminance and the light-receiving element receives light during a first detection period. When the illuminance of the external light is higher than the first value, the light-emitting element emits light at a second illuminance higher than the first illuminance, and the light-receiving element receives light during a second detection period shorter than the first detection period.
G06F 3/042 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by opto-electronic means
G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
G06K 7/10 - Methods or arrangements for sensing record carriers by electromagnetic radiation, e.g. optical sensingMethods or arrangements for sensing record carriers by corpuscular radiation
G06K 7/14 - Methods or arrangements for sensing record carriers by electromagnetic radiation, e.g. optical sensingMethods or arrangements for sensing record carriers by corpuscular radiation using light without selection of wavelength, e.g. sensing reflected white light
G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G09G 3/30 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels
G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
G09G 5/00 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
H05B 33/14 - Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
H10K 59/13 - Active-matrix OLED [AMOLED] displays comprising photosensors that control luminance
H10K 59/60 - OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
H10K 59/65 - OLEDs integrated with inorganic image sensors
H10K 59/123 - Connection of the pixel electrodes to the thin film transistors [TFT]
H10K 59/131 - Interconnections, e.g. wiring lines or terminals
H10K 65/00 - Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element and at least one organic radiation-sensitive element, e.g. organic opto-couplers
9.
DESIGN ASSISTANCE DEVICE AND DESIGN ASSISTANCE METHOD
Provided is a design assistance device which is excellent in convenience, usefulness, and reliability. The design assistance device: receives a plurality of pieces of layout data indicating the layout of circuit blocks, and constraint condition data indicating constraint conditions on the arrangement of the circuit blocks; and then converts, into three-dimensional coordinate data, two-dimensional coordinate data indicating layout regions of the circuit blocks. Then, the design assistance device outputs, to a language model, prompt data including the constraint condition data and the three-dimensional coordinate data, and generates layout data based on suggestions for arrangement positions of the circuit blocks, indicated by the language model. Subsequently, the design assistance device verifies the layout data, and when rearrangement of the circuit blocks is determined to be necessary, prompts a user of the design assistance device to modify the constraint condition data. After receiving the modified constraint condition data, the design assistance device performs generation of layout data by using the language model again.
The present invention reduces the burden on developers in a system development process. This information processing method includes: a step in which a language model is requested to generate a test case on the basis of specifications input from a user; a step in which the language model is requested to generate a correspondence table between the test case generated by the language model and the specifications; a step in which the correspondence table generated by the language model is presented to the user; a step in which the language model is requested to generate program code on the basis of the specifications and the test case; a step in which a test based on the test case is carried out on the program code generated by the language model; a step in which if the test fails, the language model is requested to generate a comment for the error; and a step in which if the test is successful, a first report is created and presented to the user.
The present invention provides a novel information processing system. The information processing system is for predicting the behavior of individual modules when a semiconductor device is operated, and comprises: a graph accepting means for accepting input of an adjacency matrix representing connections between the modules of the semiconductor device and a feature matrix representing design specifications of each of the modules; and a graph processing means for predicting and outputting a label matrix representing the behavior of the individual modules when the semiconductor device is operated, said prediction being based on the adjacency matrix and the feature matrix, wherein the graph processing means comprises a neural network that has been trained by machine learning in which adjacency matrices representing connections between modules of semiconductor devices designed in the past, feature matrices representing design specifications for each of said modules, and label matrices representing the behavior of each of said modules are used as supervisory data.
G06F 30/33 - Design verification, e.g. functional simulation or model checking
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G06F 119/06 - Power analysis or power optimisation
G06F 119/08 - Thermal analysis or thermal optimisation
12.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a semiconductor device having micro-sized transistors. The semiconductor device includes: first to fourth conductive layers; a semiconductor layer; and first to third insulative layers. The first conductive layer, the first insulative layer, the second conductive layer, the second insulative layer, and the third conductive layer overlap in the given order. The first insulative layer, the second conductive layer, the second insulative layer, and the third conductive layer have an opening reaching the first conductive layer. In the opening, the semiconductor layer contacts an upper surface of the first conductive layer, a lateral surface of the first insulative layer, a lateral surface of the second conductive layer, a lateral surface of the second insulative layer, and a lateral surface of the third conductive layer. The third insulative layer contacts an upper surface of the semiconductor layer. The fourth conductive layer overlaps the opening and contacts an upper surface of the third insulative layer.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
13.
AMPLIFIER CIRCUIT, MEMORY CIRCUIT, AND ELECTRONIC DEVICE
The present invention provides an amplifier circuit that writes to, or reads from, a memory cell with reduced power consumption. The amplifier circuit includes first to sixth switches and a sense amplifier. The sense amplifier is of the latch type and has a first input/output terminal and a second input/output terminal. A first terminal of the first switch is electrically connected to a first terminal of the second switch, and a second terminal of the second switch is electrically connected to a first terminal of the third switch and the first input/output terminal of the sense amplifier. A first terminal of the fourth switch is electrically connected to a first terminal of the fifth switch, and a second terminal of the fifth switch is electrically connected to a first terminal of the sixth switch and the second input/output terminal of the sense amplifier. Each of a control terminal of the first switch and a control terminal of the fifth switch is electrically connected to first wiring, and each of a control terminal of the third switch and a control terminal of the sixth switch is electrically connected to second wiring.
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 11/405 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
The present invention provides a high-aperture-ratio display device. The present invention provides a high-definition display device. The display device includes a first to a third conductive layers, a first semiconductor layer, and a first and a second insulating layers. The first insulating layer has an island-like shape and includes a first surface located on the first conductive layer. The first surface is a part of a side surface of the first insulating layer, and includes two or more regions having different normal directions. The second conductive layer is located on the first insulation layer. The first semiconductor layer includes a first portion in contact with an upper surface of the first conductive layer, a second portion in contact with an upper surface of the second conductive layer, and a third portion in contact with a first surface of the first insulating layer. The second insulating layer covers the third portion. The third conductive layer covers the third portion via the second insulating layer.
Provided is a new electronic apparatus. The present invention has a system control unit, a light emission drive unit, a light emitting device, an imaging device, and an image synthesis unit. The system control unit has a light emission luminance setting unit for setting the luminance of the light emitting device. The light emission drive unit has a luminance switching unit that switches the luminance of the light emitting device from a first luminance level to a second luminance level. The light emitting device has a function of exposing a subject to be imaged by the imaging device to light at the first luminance level or second luminance level. The imaging device has a function of outputting, to the image synthesis unit, first image data obtained by imaging the subject that has been exposed by the light emitting device at the first luminance level, and second image data obtained by imaging the subject that has been exposed by the light emitting device at the second luminance level.
H04N 23/741 - Circuitry for compensating brightness variation in the scene by increasing the dynamic range of the image compared to the dynamic range of the electronic image sensors
Provided is a small-scale and highly accurate biological information acquisition device. An acquired photoplethysmogram is converted into a plurality of frequency components by fast Fourier transform, and a portion of the resultant data is quantized and input to a neural network (NN) to perform personal identification or emotion recognition. In this case, quantization to a low number of bits makes it possible to use a small-scale NN and to perform high-speed determination. Furthermore, performing quantization reflecting flag representation makes it possible to enhance accuracy. Since the NN is small-scale, biological information acquisition processing can be performed at high speed and safely without using a highly functional cloud-based workstation or the like.
Provided is a battery having excellent charge/discharge characteristics even in a low-temperature environment. The battery has a positive electrode, a negative electrode, an electrolytic solution, and a separator. The electrolytic solution and the separator are provided between the positive electrode and the negative electrode. The negative electrode includes a carbon material. The electrolytic solution contains a lithium salt, a potassium salt, a fluorinated cyclic carbonate, and a fluorinated chain-like carbonate. In the battery, the carbon material contains graphite, the anion of the lithium salt and the anion of the potassium salt are different from each other, the fluorinated cyclic carbonate includes fluoroethylene carbonate, and the fluorinated chain-like carbonate includes methyl trifluoropropionate.
H01M 10/0568 - Liquid materials characterised by the solutes
H01M 4/131 - Electrodes based on mixed oxides or hydroxides, or on mixtures of oxides or hydroxides, e.g. LiCoOx
H01M 4/133 - Electrodes based on carbonaceous material, e.g. graphite-intercalation compounds or CFx
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01M 4/587 - Carbonaceous material, e.g. graphite-intercalation compounds or CFx for inserting or intercalating light metals
H01M 10/0525 - Rocking-chair batteries, i.e. batteries with lithium insertion or intercalation in both electrodesLithium-ion batteries
H01M 10/0569 - Liquid materials characterised by the solvents
18.
INFORMATION PROCESSING METHOD AND INFORMATION PROCESSING DEVICE
Provided is an information processing system having excellent convenience, usability, and reliability. The information processing system has a function which, when an account title and a descriptive text thereof have been added to a database, or when a descriptive text of an account title has been modified, collects account titles having similar descriptive texts and transaction data in which the account titles are registered from the database. The information processing system has a function for performing a first process for selecting a re-registration proposal for an account title relating to the collected transaction data, from among the collected account titles on the basis of the descriptive texts. The information processing system has a function for performing a second process for collecting transaction data for which an inappropriate re-registration proposal has been presented, and presenting the reason why the re-registration proposal has been presented as a re-registration proposal for an account title. The first process and the second process are performed using a language model. After the second process, the user of the information processing system can modify an account title registered in the database.
Provided is a highly reliable semiconductor device. This semiconductor device includes a first electroconductive layer, a first insulating layer on the first electroconductive layer, a second electroconductive layer on the first insulating layer, an oxide layer, an oxide semiconductor layer on the oxide layer, a second insulating layer on the oxide semiconductor layer, and a third electroconductive layer on the second insulating layer. The first electroconductive layer has a first recess. The first insulating layer and the second electroconductive layer each have a first opening at a position overlapping the first recess. The oxide semiconductor layer faces, within the first opening, the first insulating layer across the oxide layer. The third electroconductive layer faces, within the first opening, the oxide semiconductor layer across the second insulating layer. The film thickness of the oxide layer is less than the film thickness of the oxide semiconductor layer. The resistivity of the oxide layer is higher than the resistivity of the oxide semiconductor layer.
G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H01L 21/203 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using physical deposition, e.g. vacuum deposition, sputtering
H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H01L 21/365 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
H10B 99/00 - Subject matter not provided for in other groups of this subclass
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
The present invention provides a highly safe secondary battery. The secondary battery comprises a positive electrode, wherein: the positive electrode includes positive electrode active material particles and a fibrous conductive material; the positive electrode active material particles contain lithium cobalt oxide; the positive electrode active material particles each have a surface layer part that has a rock salt type crystal structure and an internal part that has a layered rock salt type crystal structure; the surface layer part contains cobalt, nickel, magnesium, and fluorine; the internal part contains cobalt and aluminum, and in a planar view of the positive electrode or a cross-sectional view of the positive electrode, there is a region where the fibrous conductive material surrounds substantially all of the positive electrode active material particles.
H01M 4/62 - Selection of inactive substances as ingredients for active masses, e.g. binders, fillers
H01M 4/36 - Selection of substances as active materials, active masses, active liquids
H01M 4/131 - Electrodes based on mixed oxides or hydroxides, or on mixtures of oxides or hydroxides, e.g. LiCoOx
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
21.
METHOD FOR DESIGNING ORGANIC COMPOUND AND SYSTEM FOR DESIGNING ORGANIC COMPOUND
Provided is a system for designing an organic compound. This system involves a step for setting, in a first organic compound group, a first objective variable group from a first explanatory variable group, a step for training an autoencoder on the molecular structure of the first organic compound group and acquiring a first latent variable group corresponding to the molecular structure of the first organic compound group, a step for training a regression model on a correlation between the first latent variable group and the first objective variable group, a step for generating a second latent variable group using a random number, a step for acquiring the molecular structure of a second organic compound group from the second latent variable group using the autoencoder, a step for acquiring a predicted value of the second objective variable group from the second latent variable group using the regression model, a step for selecting a third organic compound group from the second organic compound group using the predicted value of the second objective variable group, and a step for calculating a second explanatory variable group of the third organic compound group. The first explanatory variable group and the second explanatory variable group have information pertaining to molecular orientation.
Provided is a semiconductor device having a small footprint. A semiconductor device includes a first and a second transistors and a first to a third insulating layers. The first transistor includes a first and a second conductive layers, a first semiconductor layer, a gate insulating layer, and a first gate electrode. The second transistor includes a third and a fourth conductive layers, a second semiconductor layer, a gate insulating layer, and a second gate electrode. The third conductive layer, the first insulating layer, the first conductive layer, the second insulating layer, and the third insulating layer are provided in this order, and the second and fourth conductive layers are provided on the third insulating layer. The second conductive layer, the third insulating layer, and the second insulating layer include a first opening reaching the first conductive layer, and the first semiconductor layer is provided in a manner such as to cover the first opening. The fourth conductive layer, the third insulating layer, the second insulating layer, and the first insulating layer include a second opening reaching the third conductive layer, and the second semiconductor layer is provided in a manner such as to cover the second opening. The gate insulating layer is located on the first semiconductor layer and the second semiconductor layer. The first gate electrode and the second gate electrode are located on the gate insulating layer.
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
H10D 1/68 - Capacitors having no potential barriers
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Provided is a multiplication circuit with reduced power consumption. The multiplication circuit has a first cell and a second cell. Each of the first cell and the second cell has a function for serving as a current source circuit. The first cell has a function that generates a first current corresponding to the gate-source voltage of a first transistor, and the second cell has a function that generates a reference current corresponding to the gate-source voltage of a second transistor. The multiplication circuit has a function for amplifying the first current to a third current in accordance with the ratio between the reference current and a second current, such amplification performed by changing the reference current of the second cell to the second current. In order to hold the gate-source voltage of each of the first transistor and the second transistor, each of the first cell and the second cell includes a switch unit. Each switch unit includes: transistors in series; and a capacitive element connected between the transistors.
G06G 7/60 - Analogue computers for specific processes, systems, or devices, e.g. simulators for living beings, e.g. their nervous systems
G06G 7/16 - Arrangements for performing computing operations, e.g. amplifiers specially adapted therefor for multiplication or division
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
Provided is a new design system that exhibits excellent convenience, usefulness, or reliability. The design system has a calculation unit, a control unit, and a database. The database stores therein a plurality of sets of data items, in each of which an initial version file including an error, a completed version file in which the error has been corrected, and information related to correction of the error are associated with one another. The calculation unit has a function of identifying one initial version file from a plurality of initial version files included in the database and providing a set of data items including the one initial version file to the control unit. The control unit has a function of receiving a first initial version file, and a function of outputting the set of data items provided from the calculation unit. The one initial version file identified by the calculation unit includes an error having a high degree of similarity to the first initial version file.
Provided is a semiconductor device including transistors of a very small size. The semiconductor device includes first and second transistors, and first and second insulating layers. Both of the two transistors are vertical transistors, and the second transistor is provided overlapping the first transistor. One (a first conductive layer) of the source electrode and the drain electrode of the first transistor, the first insulating layer, and the other (a second conductive layer) of the source electrode and the drain electrode of the first transistor are provided in this order, and these components have an overlapping region. An opening reaching the first conductive layer is provided in the second conductive layer and the first insulating layer, and a semiconductor layer, a gate insulating layer, and a gate electrode are provided in this order in contact with the side wall and the bottom surface of the opening. The second insulating layer is provided so as to fill a recess in the gate electrode of the first transistor, and one of the source electrode and the drain electrode of the second transistor is provided on and in contact with the gate electrode.
Provided is a semiconductor device having small-size transistors. This semiconductor device includes: first and second transistors; and first and second insulating layers. The two transistors are both vertical transistors, and the second transistor is provided so as to be superimposed on the first transistor. The following are provided in order given and have overlapping regions: one (first conductive layer) of a source electrode and a drain electrode of the first transistor; the first insulating layer; and the other (second conductive layer) of the source electrode and the drain electrode of the first transistor. An opening reaching the first conductive layer is provided in the second conductive layer and the first insulating layer. A semiconductor layer, a gate insulating layer, and a gate electrode are provided in that order and in contact with a lateral wall and the bottom surface of the opening. The second insulating layer is provided so that a recess of the gate electrode of the first transistor is embedded in the second insulating layer. One of a source electrode and a drain electrode of the second transistor is provided in contact with the top of the gate electrode.
G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H05B 33/10 - Apparatus or processes specially adapted to the manufacture of electroluminescent light sources
H05B 33/14 - Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10K 59/124 - Insulating layers formed between TFT elements and OLED elements
H10K 59/131 - Interconnections, e.g. wiring lines or terminals
H10K 71/00 - Manufacture or treatment specially adapted for the organic devices covered by this subclass
27.
INFORMATION PROCESSING SYSTEM, ELECTRONIC DEVICE, AND INFORMATION PROCESSING METHOD
The present invention provides an information processing system that shortens the time required for circuit design. The information processing system includes first to third devices and a storage device. The first device comprises a design tool and calculates report data by acquiring a design parameter and code. Also, the first device generates a target parameter in accordance with the report data. The storage device saves a pair containing a design parameter and a target parameter as training data. The second device comprises a first program including a machine learning model, and uses the training data to infer a design parameter that would result in a favorable target parameter. The third device comprises a second program including a natural language model, and rewrites the code according to the inferred design parameter. The information processing system searches for a favorable design parameter by repeating the operations of the first to third devices and collecting training data.
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
28.
INFORMATION PROCESSING METHOD AND INFORMATION PROCESSING DEVICE
The present invention provides an information processing method excellent in convenience, usefulness, and reliability. The information processing method includes: first processing for selecting an account title related to transaction information on the basis of an explanatory sentence of the account title; and second processing for correcting the explanatory sentence of the account title so that the account title can be correctly selected in the first processing when the selection of the account title is not appropriate. The first processing and the second processing are performed using a language model. When an account title cannot be selected in the first processing, the reason why the account title cannot be selected is presented, and after the additional information is received, the first processing is performed again.
The present invention is for reducing the manufacturing cost of a semiconductor component. This semiconductor device is formed of a semiconductor chip, a wiring board, and a first bonding wire. The semiconductor chip has a first electrode. The wiring board has a second electrode. The semiconductor chip is fixed to the wiring board. The first bonding wire has a portion in contact with the first electrode, a portion in contact with the second electrode, and a portion having an arch-like shape therebetween. The first bonding wire has carbon nanotubes.
Provided is a novel semiconductor device. This semiconductor device includes first to fourth transistors, a first capacitive element, and a second capacitive element. The first to fourth transistors each have a gate, a first terminal, and a second terminal. The first terminal of the first transistor is electrically connected to a first electrode of the first capacitive element, the gate of the third transistor, and the gate of the fourth transistor. The first terminal of the second transistor is electrically connected to the second terminal of the first transistor, the second terminal of the fourth transistor, and a first electrode of the second capacitive element. The gates of the first transistor and the second transistor are electrically connected to each other. Second electrodes of the first capacitive element and the second capacitive element are electrically connected to each other.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
31.
INFORMATION PROCESSING SYSTEM AND INFORMATION PROCESSING METHOD
Provided is a novel information processing system that exhibits exceptional convenience, usefulness, or reliability. The information processing system can be used for comparing an original sentence with a translated sentence and checking whether translation is accurately performed, and has a function of performing information processing that differ between a case where literal translation is required and a case where inclusion of liberal translation is permitted. The information processing system has a function of, when a translated sentence includes a liberally translated portion in the case where literal translation is required, detecting said liberally translated portion, and urging a user of the information processing system to revise said portion, and further has a function of determining the correspondence relationship between words and phrases of the original sentence and the translated sentence. Still further, the information processing system has a function of, in the case where inclusion of liberal translation is permitted, determining whether the translated sentence is synonymous with the original sentence.
Provide is a display device with good light extraction efficiency. The display device has a convex lens on a light-emitting element, wherein a second layer is provided on and in contact with the convex lens and a first layer is provided on and in contact with the second layer. In this configuration, by providing steps in which the refractive index sequentially decreases in the advancement direction of light, steps in the refractive index can be reduced at interfaces and reflection at the interfaces can be reduced. Accordingly, the light extraction efficiency of the display device can be increased.
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
Provided is a novel inspection system. This layout data inspection system comprises: a reception means for receiving layout data to be inspected; a circuit pattern generation means for generating a circuit pattern from the layout data; a detection model generation means for generating a detection model by means of machine learning by using, as teacher data, a plan view of a circuit pattern that includes a shape abnormality and a cross-sectional view of a circuit pattern that includes a shape abnormality; a detection means for detecting, by using the detection model, a shape abnormality in the circuit pattern generated from the received layout data; and an output means for outputting detection information including position information for the detected shape abnormality.
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
34.
SECONDARY BATTERY, ELECTRONIC DEVICE, VEHICLE, SHIP, METHOD FOR PRODUCING SECONDARY BATTERY, METHOD FOR PRODUCING POSITIVE ELECTRODE ACTIVE MATERIAL, AND METHOD FOR PRODUCING ACTIVATED SPHERICAL POROUS CARBON
Provided is a method for producing a high-capacity lithium-ion secondary battery. This method comprises: a step for mixing activated spherical porous carbon and sulfur to produce activated spherical porous carbon in which sulfur is supported; a step for mixing a binder solution with the activated spherical porous carbon that supports the sulfur to produce a slurry; a step for applying the slurry to the surface of a current collector and drying the slurry; and a step for carrying out a pressing treatment to produce an electrode for a secondary battery. The pressing treatment is preferably performed under heating.
The present invention provides a method for producing a light-emitting device featuring a high degree of design freedom and favorable yields. The method comprises: forming a first electrode on top of an insulating surface; forming an organic compound layer having at least an emissive layer on top of the first electrode; forming an aluminum-containing sacrificial layer on the surface of the organic compound layer; forming a mask overlapping at least a portion of the first electrode on top of the sacrificial layer; forming the sacrificial layer into an island shape by lithography using a mask; forming the organic compound layer into an island shape by using the island-shaped sacrificial layer as a mask; exposing the surface of the island-shaped organic compound layer by etching with an aqueous solution containing hydrofluoric acid and a Brønsted acid with a pH of 3 or higher; and forming a second electrode to cover the island-shaped organic compound layer.
Acetylene black, which is used as a conductivity aid, is a material that tends to agglomerate. Reducing the quantity of conductivity aid makes agglomeration occur less readily, but the electronic conductivity of an electrode as a whole will decrease. Accordingly, one objective of the present invention is to provide a secondary battery in which the quantity of conductivity aid is reduced while also having sufficient electronic conductivity of an electrode as a whole. A lithium-ion secondary battery disclosed in the present specification has a positive electrode, a separator, and a negative electrode. In the positive electrode, layers containing bundles of carbon nanotubes whose long axes are oriented in one direction and layers containing positive electrode active material are alternately stacked on a positive electrode current collector.
H01M 4/13 - Electrodes for accumulators with non-aqueous electrolyte, e.g. for lithium-accumulatorsProcesses of manufacture thereof
H01M 4/58 - Selection of substances as active materials, active masses, active liquids of inorganic compounds other than oxides or hydroxides, e.g. sulfides, selenides, tellurides, halogenides or LiCoFySelection of substances as active materials, active masses, active liquids of polyanionic structures, e.g. phosphates, silicates or borates
H01M 4/505 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of manganese of mixed oxides or hydroxides containing manganese for inserting or intercalating light metals, e.g. LiMn2O4 or LiMn2OxFy
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
The present invention provides a highly reliable display device. The present invention provides a display device in which photodegradation of transistors is suppressed. The display device includes a first transistor that is a vertical transistor, a second transistor that is a top-gate transistor, a first insulating layer, and a first conductive layer. The first transistor has a top electrode and a bottom electrode. The top electrode and the second transistor are located on the first insulating layer. The first conductive layer has a region below the first insulating layer and overlapping the second transistor. The first conductive layer and the bottom electrode are located on the same surface, and contain the same material.
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
Provided is an accounting business assist method using a language model. The accounting business assist method includes a first process for extracting an electronic mail related to an order, and a second process for extracting information from the electronic mail related to the order. The first process and the second process are executed by using the language model. The accounting business assist method also includes a process for narrowing down electronic mails by using a search expression before the first process, and a process for registering, in a database, the information extracted in the second process.
The present invention provides a semiconductor device having a transistor of very small size. The present invention has a transistor, a first insulation layer, and a second insulation layer. The transistor has a semiconductor layer, a first electroconductive layer, and a second electroconductive layer. The first electroconductive layer and the first insulation layer are provided such that the heights of the respective upper surfaces thereof are substantially the same. The second insulation layer is provided on the first electroconductive layer and the first insulation layer. The second electroconductive layer is provided on the second insulation layer. The second electroconductive layer and the second insulation layer each have an opening reaching the first electroconductive layer. The semiconductor layer is provided in contact with the upper surface of the first electroconductive layer, the side surface of the second insulation layer, and the side surface of the second electroconductive layer within each of the openings.
G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
This invention provides a sentence generation system having a novel configuration. A processing unit acquires parallel sentence data by transmitting, to a first language model via a network, a first instruction sentence for selecting a sentence in which a plurality of events are described in parallel from first target data, using input data as the first target data. A third instruction sentence is acquired by transmitting, to the first language model via the network, a second instruction sentence for generating an instruction sentence in which the parallel sentence data is expressed as an expression including a feature related to second target data, using the parallel sentence data as the second target data. Sentence data related to the parallel sentence data is acquired by transmitting, to the first language model via the network, a third instruction sentence for generating a sentence based on third target data, using the input data and the parallel sentence data as the third target data. The output unit outputs output data in which the sentence data is appended to the input data.
Provided is a semiconductor device that occupies little area. The semiconductor device has a horizontal transistor and a vertical transistor combined therein. A CMOS semiconductor device is achieved as a result of a p-channel transistor being constituted by the horizontal transistor and an n-channel transistor being constituted by the vertical transistor. An insulating layer is provided on a gate electrode of the horizontal transistor, and a lower electrode of the vertical transistor is provided on the insulating layer. Silicon is used for a semiconductor layer of the horizontal transistor, and a metal oxide is used for a semiconductor layer of the vertical transistor.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Provided are a learning method for an organic compound design model, in which a large language model is used, and an organic compound design system. The present invention comprises: a step for generating, through use of a first large language model, a first organic compound group by using a user sentence; a step for calculating a physical property value of a first organic compound of the first organic compound group by scientific calculation; a step for evaluating a demand achievement degree from a correlation between the user sentence, the molecular structure of the first organic compound, and the physical property value through use of a second large-scale language model; a step for generating training data in which the user sentence, the molecular structure of the first organic compound, and the demand achievement degree are combined; a step for constructing a reward model by using the training data; a step for creating a pseudo user sentence; a step for generating, through use of the first large language model, a second organic compound group by using the pseudo user sentence; a step for generating pseudo reward data by evaluating the molecular structure of a second organic compound of the second organic compound group through use of the reward model; and a step for updating a parameter of the first large language model by using the pseudo reward data.
Provided is a molecular structure generation method in which a large language model is used and which exhibits high versatility and excellent precision. Provided is a molecular structure generation method comprising: a step for inputting a first instruction sentence in which a compound, which serves as a base, and a requirement for characteristics are combined with molecular structure information of a compound corresponding to the compound and a natural sentence; a step for separating a part of the molecular structure information of the compound and a part of the requirement for the characteristics; a step for generating a plurality of similar compounds on the basis of the molecular structure information of the compound which serves as a base; a step for extracting information regarding the characteristics from the requirement for the characteristics; and a step for inputting a second instruction sentence for a large language model. To the second instruction sentence, at least the information regarding the characteristics and, as an example of the molecular, the plurality of similar compounds are inputted.
Provided is a novel positive electrode active material. Also provided is a battery with excellent charge and discharge characteristics. This battery has a positive electrode. The positive electrode has a positive electrode active material layer. The positive electrode active material layer has positive electrode active material particles containing magnesium, titanium, nickel, aluminum, and lithium cobalt oxide. XPS analysis of the plurality of positive electrode active material particles in the positive electrode active material layer shows a peak in the range from 850 eV to 860 eV inclusive and at a position at least 0.5 eV higher than the peak position in XPS analysis of nickel(II) oxide.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01M 4/38 - Selection of substances as active materials, active masses, active liquids of elements or alloys
Provided is an optical device that is compact, lightweight, and achieves high light use efficiency. This optical device has: a catadioptric system that achieves high light use efficiency and causes image formation positions on two optical paths to coincide with each other; and a singlet lens that has the function of optical correction or the like and is between a non-polarized light source and the catadioptric system. A resin lens is disposed in an optical path using non-polarized light, and a glass lens that does not substantially generate birefringence is disposed in an optical path using polarized light. Thus, the partial unpolarization of polarized light can be prevented, and an optical device that is lightweight and achieves high light use efficiency with little stray light can be provided.
G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
One aspect of the present invention provides a charging control system that is capable of effectively using regenerative electric power without wasting the regenerative electric power. Generated regenerative electric power is efficiently stored in a second secondary battery and then stored in a main first secondary battery. Charging from the second secondary battery to the first secondary battery is performed via a DC-DC converter. The charge state of the first secondary battery and the charge state of the second secondary battery are controlled. When the first secondary battery is close to full charge and is likely to deteriorate, it is possible to perform charging from the first secondary battery to the second secondary battery.
B60L 53/20 - Methods of charging batteries, specially adapted for electric vehiclesCharging stations or on-board charging equipment thereforExchange of energy storage elements in electric vehicles characterised by converters located in the vehicle
B60L 58/18 - Methods or circuit arrangements for monitoring or controlling batteries or fuel cells, specially adapted for electric vehicles for monitoring or controlling batteries of two or more battery modules
H01G 11/08 - Structural combinations, e.g. assembly or connection, of hybrid or EDL capacitors with other electric components, at least one hybrid or EDL capacitor being the main component
H01M 4/38 - Selection of substances as active materials, active masses, active liquids of elements or alloys
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01M 10/0525 - Rocking-chair batteries, i.e. batteries with lithium insertion or intercalation in both electrodesLithium-ion batteries
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
47.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a semiconductor device having a high operating speed. In this invention, a second insulator is formed on top of a first insulator, and raised sections are formed in the second insulator. An oxide semiconductor film is deposited to cover the second insulator, and oxide semiconductors in contact with the lateral surfaces of the raised sections are formed by anisotropic etching. A third insulator is deposited to cover the second insulator and the oxide semiconductor film, and CMP is performed to planarize the top surface of the third insulator. The second and third insulators are etched to form a fourth insulator in contact with the bottom surface of the oxide semiconductors. A first conductor is formed to cover the oxide semiconductors and the fourth insulator, and a fifth insulator with an opening is formed on top of the first conductor. The first conductor is processed to form second and third conductors facing each other across the opening. A sixth insulator and a fourth conductor are formed inside the opening.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
48.
INFORMATION PROCESSING SYSTEM AND INFORMATION PROCESSING METHOD
Provided is a novel information processing system that exhibits exceptional convenience, usefulness, or reliability. This information processing system includes a first information processing device and a second information processing device. The first information processing device has: a function for receiving input of a first-language document; a function for translating the first-language document to a second language; a function for reverse-translating the second-language document to the first language; a function for comparing the two same-language documents and determining whether the documents are synonymous; a function for transmitting, to the second information processing device, a prompt including a first-language document A that is determined to not be synonymous in the aforementioned determination and instruction text for inducing generation of a first-language document B that is synonymous with the document A, thereby acquiring the document B; and a function for outputting the document B. The second information processing device has a function for generating the document B in accordance with the prompt.
The present invention provides a novel information processing system. First, an image corresponding to a processing range which is at least a part of a layout of a semiconductor device is received. Next, by using a detection model, a shape based on a design rule prepared in advance is extracted from the image, and a tag indicating a type of the design rule and a bounding box indicating a position of the shape are assigned to the shape. Next, a position of a correction target area in the layout corresponding to the position of the bounding box in the image is calculated. Next, vertex information of a pattern element included in the correction target area and layer information to which the pattern element belongs are acquired. Next, an instruction sentence is created using the tag, the vertex information, and the layer information. Next, a response sentence including a layout correction proposal based on the instruction sentence is generated using a language model. Finally, the response sentence is output.
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
50.
SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC EQUIPMENT
Provided is a semiconductor device in which an off-current is reduced. The semiconductor device includes a drive transistor, a first transistor, a second transistor, a third transistor, a first capacitive element, and a light-emitting device. A back gate of the first transistor is electrically connected to one of a source and a drain of the second transistor, and one of a source and a drain of the third transistor. The gate of the first transistor is electrically connected to a first wiring, a gate of the second transistor is electrically connected to the first wiring, and a gate of the third transistor is electrically connected to a second wiring. One of a source and a drain of the first transistor is electrically connected to a gate of the drive transistor, and a first terminal of the first capacitive element. One of a source and a drain of the drive transistor is electrically connected to a second terminal of the first capacitive element and one of an anode and a cathode of the light-emitting device.
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
H10K 59/123 - Connection of the pixel electrodes to the thin film transistors [TFT]
H10K 59/131 - Interconnections, e.g. wiring lines or terminals
Provided is a semiconductor device having a small footprint. This semiconductor device includes a first transistor, a second transistor, and a first insulating layer. The first transistor includes a first conductive layer, a first metal oxide layer, a gate insulating layer, and a first gate electrode. The second transistor includes a second conductive layer, a third conductive layer, a second metal oxide layer, a gate insulating layer, and a second gate electrode. The first insulating layer is located above the first conductive layer and the second conductive layer and includes a first opening reaching the first conductive layer. The first insulating layer and the third conductive layer include a second opening reaching the second conductive layer. The first metal oxide layer includes: a first region in contact with the upper surface of the first conductive layer; a second region in contact with a lateral surface of the first insulating layer; and a third region in contact with the upper surface of the first insulating layer. The third region is in contact with the second region. The second metal oxide layer is in contact with the upper surface of the second conductive layer, the lateral surface of the first insulating layer, and a lateral surface of the third conductive layer.
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Provided is a semiconductor device that can be miniaturized or highly integrated, a semiconductor device that is highly reliable, a semiconductor device that has low power consumption, or a semiconductor device that has a high operation speed. This semiconductor device includes: a first transistor including a first conductive layer to a third conductive layer, a first oxide semiconductor layer, and a charge accumulation layer; a second transistor including a fourth conductive layer, a fifth conductive layer, and a second oxide semiconductor layer; and a first insulating layer. The first insulating layer is located above the first conductive layer and the fourth conductive layer, and includes: a first opening overlapping the first conductive layer; and a second opening overlapping the fourth conductive layer. A second conductive layer and the fifth conductive layer are located above the first insulating layer. The first oxide semiconductor layer is located in the first opening. In the first opening, the charge accumulation layer is located between the first oxide semiconductor layer and the third conductive layer. The second oxide semiconductor layer is located in the second opening.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
H10D 1/68 - Capacitors having no potential barriers
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 89/00 - Aspects of integrated devices not covered by groups
The present invention provides a semiconductor device that is easily scaled down. The semiconductor device has a semiconductor layer, a first electrode, a second electrode, a gate insulation layer, and a gate electrode. The semiconductor layer has a tubular portion. The gate electrode has a portion located on the inner side of the tubular portion. The gate insulation layer has a portion located between the semiconductor layer and the gate electrode. The second electrode has a portion located above the first electrode. The semiconductor layer has a portion in contact with the top surface of the second electrode, above the tubular portion. The semiconductor layer also has a portion in contact with the top surface of the first electrode, below the tubular portion. The semiconductor layer further includes a two-dimensional layered material.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
Provided is a positive electrode that maintains high discharge capacity even after undergoing a charge/discharge cycle test. A positive electrode according to the present invention can be used in a lithium ion secondary battery. Said positive electrode comprises positive electrode active material particles, wherein: the positive electrode active material particles contain lithium, cobalt, oxygen, magnesium, fluorine, nickel, aluminum, and titanium; and in a cross-sectional SEM image of the positive electrode, the number of cracks is not more than 0.06 per square micrometer and the total length of cracks is not more than 0.06 μm per square micrometer. Alternatively, when the charge/discharge cycle test is performed 50 times and then the positive electrode is taken out and a cross-sectional SEM image of the positive electrode is obtained, the number of pits in the positive electrode active material particles of the positive electrode is not more than 0.25 per square micrometer.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01M 4/36 - Selection of substances as active materials, active masses, active liquids
55.
METHOD FOR PRODUCING POSITIVE ELECTRODE ACTIVE SUBSTANCE
The present invention provides a method for producing a positive electrode active substance having good cycle characteristics. This method for producing a positive electrode active substance comprises: mixing lithium cobaltate having a median diameter (D50) of 10 µm or less with a first additional element source to form a first mixture; subjecting the first mixture to a first heating to form a first composite oxide; mixing the first composite oxide with a second additional element source to form a second mixture; subjecting the second mixture to second heating to form a second composite oxide; mixing the second composite oxide with a third additional element source to form a third mixture; and subjecting the third mixture to third heating. The first additional element source comprises a magnesium compound and a fluorine compound. The second additional element source comprises an aluminum compound and a nickel compound. The third additional element source comprises a titanium compound. The duration of the second heating and the duration of the third heating are each shorter than the duration of the first heating.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
An aspect of the present invention provides a positive electrode active material with enhanced lithium ion insertion and desorption. Also provided is a positive electrode active material or a composite oxide with a crystal structure resistant to collapse even after repeated charge-discharge cycles. In order to prevent a lithium cobalt oxide surface layer portion from forming a rock salt structure that creates resistance, lithium fluoride is added to the lithium cobalt oxide to create a layered rock salt structure on a portion of the surface. The subsequent addition of magnesium fluoride allows for the presence of a barrier layer with a net structure of Mg-F bonds or Mg-O bonds in the surface layer portion, while still maintaining the layered rock salt structure on the portion of the surface.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
Provided is a novel semiconductor device. This semiconductor device includes first to third transistors, a first capacitive element, and a second capacitive element. The first to third transistors each have a gate, a first terminal, and a second terminal. The first terminal of the first transistor is electrically connected to a first electrode of the first capacitive element and the gate of the third transistor. The first terminal of the second transistor is electrically connected to the second terminal of the first transistor and a first electrode of the second capacitive element. The gates of the first transistor and the second transistor are electrically connected to each other. The second electrodes of the first capacitive element and the second capacitive element are electrically connected to each other.
H10B 12/00 - Dynamic random access memory [DRAM] devices
G11C 11/405 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 99/00 - Subject matter not provided for in other groups of this subclass
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
Provided is a semiconductor device with a high operating speed. This semiconductor device includes first and second transistors and a capacitive element. The first transistor has a first oxide semiconductor. The second transistor has a second oxide semiconductor. An insulating body with first to third openings is disposed on top of the first and second transistors, such that the gate of the first transistor is located inside the first opening, the gate of the second transistor is located inside the second opening, and the third opening is located over the source and the drain of the first transistor. A dielectric and a top electrode of the capacitive element are located inside the third opening. In a cross-sectional view in the channel width direction, the height of the first oxide semiconductor is longer than the width of the first oxide semiconductor, and the first and second oxide semiconductors are aligned on the same line. Either the source or the drain of the first transistor is electrically connected with the gate of the second transistor.
H10D 64/60 - Electrodes characterised by their materials
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
59.
INFORMATION PROCESSING SYSTEM AND INFORMATION PROCESSING METHOD
The present invention provides a novel information processing system that excels in convenience, usefulness, or reliability. The information processing system is formed from three components. The first component accepts configuration data and code written using a hardware description language. The second component embodies a semiconductor device on the basis of the code and configuration data, arranges and wires standard cells, and performs verification according to design rules, simulation of operating characteristics, and timing analysis. A design history document is also generated. The third component performs processing using a large language model to classify the design history document and propose approaches for correcting the code and the configuration data.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
Provided is a light-emitting device with good reliability. Provided is a light-emitting device comprising a first electrode, a second electrode, and a light-emitting layer, wherein the light-emitting layer is positioned between the first electrode and the second electrode, the light-emitting layer has a light-emitting layer and an electron injection layer, the electron injection layer contains a metal oxide and a first organic compound, and the first organic compound is an organic compound having a phenanthroline ring with an electron-donating group.
Provided is a novel display apparatus with superior convenience, utility, or reliability. The present invention uses a display apparatus having a first light-emitting device, a second light-emitting device, a first conductive layer, a first layer, and a second layer. The first light-emitting device comprises a first electrode, a second electrode, and a first unit. The first unit is sandwiched between the first and second electrodes. The first unit includes a luminescent material. The second light-emitting device is adjacent to the first light-emitting device. The second light-emitting device comprises a third electrode, a fourth electrode, and a second unit. The third electrode is adjacent to the first electrode. The third electrode is disposed with a first gap between itself and the first electrode. The second unit is sandwiched between the third and fourth electrodes. The second unit includes a luminescent material. The first conductive layer includes the second electrode and the fourth electrode. The first conductive layer has an area overlapping the first gap. The first layer is sandwiched between the first conductive layer and the first gap. The first layer is in contact with a lateral surface of the first unit and a lateral surface of the second unit. The first layer has insulating properties. The second layer is sandwiched between the first conductive layer and the first layer. The second layer is thicker than the first conductive layer. The second layer has conductive properties.
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
One aspect of the present invention provides a secondary battery that can be used over a wide temperature range and is not easily affected by ambient temperatures. Also provided is a highly safe secondary battery. The secondary battery comprises a positive electrode, a negative electrode, and an electrolyte layer between the positive and negative electrodes. The positive electrode has, on a positive electrode collector, a positive electrode active material, a first lithium-ion conductive polymer, a first lithium salt, and a conductive material. The electrolyte layer has a second lithium-ion conductive polymer and a second lithium salt. Since there is no or very little organic solvent, a secondary battery that is less prone to catch fire can be obtained, and safety is improved.
H01M 4/36 - Selection of substances as active materials, active masses, active liquids
H01M 4/62 - Selection of inactive substances as ingredients for active masses, e.g. binders, fillers
H01M 4/131 - Electrodes based on mixed oxides or hydroxides, or on mixtures of oxides or hydroxides, e.g. LiCoOx
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01M 10/0565 - Polymeric materials, e.g. gel-type or solid-type
63.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
The present invention provides a transistor that can be reduced in size. This semiconductor device includes a transistor and a first insulation layer. The transistor has a first electroconductive layer, a second electroconductive layer, a third electroconductive layer, a semiconductor layer, and a second insulation layer. The first insulation layer has a first opening that reaches the first electroconductive layer, an upper part of the first insulation layer being narrowed. The second electroconductive layer is disposed above the first insulation layer. The semiconductor layer has a first portion in contact with the upper surface of the first electroconductive layer, a second portion in contact with the upper surface of the second electroconductive layer, and a third portion in contact with the side surface of the first insulation layer inside the first opening. The second insulation layer covers the semiconductor layer inside the first opening. The third electroconductive layer covers the second insulation layer inside the first opening. The third portion overlaps the protruding upper part of the first insulation layer in the first opening. The first portion and the second portion include more impurity elements than the third portion.
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H01L 21/316 - Inorganic layers composed of oxides or glassy oxides or oxide-based glass
H01L 21/318 - Inorganic layers composed of nitrides
Provided is a light-emitting device having excellent characteristics. The light-emitting device is one of a plurality of light-emitting devices that are formed on the same insulation surface, and comprises a first electrode, a second electrode, and an organic compound layer. The first electrode is independent of an adjacent one of the light-emitting devices. The second electrode is shared with an adjacent one of the light-emitting devices. The organic compound layer is located between the first electrode and the second electrode. The organic compound layer has a light-emitting layer and an electron injection layer. The electron injection layer is located between the light-emitting layer and the second electrode. The light-emitting layer and the electron injection layer are independent of an adjacent one of the light-emitting devices. The outline of the light-emitting layer matches or almost matches the outline of the electron injection layer. The electron injection layer has a mixture layer containing a metal, a first organic compound, and a second organic compound. The first organic compound has a phenanthroline ring having an electron donating group. The second organic compound has a π electron deficient heteroaromatic ring.
The present invention provides a storage apparatus which consumes little power. Memory cells of the storage apparatus are in a staggered arrangement and are provided in regions where orthogonal word lines and bit lines intersect. Adjacent word lines have different heights. Such a configuration makes it possible to reduce the number of memory cells per word line and makes it possible to reduce power consumption when reading data. Furthermore, it is possible to provide, in the same cell array, a pair of bit lines that connect to a sense amplifier, and therefore it is possible to reduce noise.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
The present invention provides a semiconductor device that is easily miniaturized. Provided is a semiconductor device with reduced parasitic capacitance. This semiconductor device has a first insulating layer, a second insulating layer, a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulating layer. The first conductive layer is located on top of the second insulating layer and has a first opening that reaches the second insulating layer. The first insulating layer is located on top of the first conductive layer and has a second opening that overlaps the first opening. The second conductive layer is located on top of the first insulating layer. The semiconductor layer has: a portion in contact with the second conductive layer; a portion located inside the second opening, along the lateral surface of the first insulating layer; a portion inside the first opening, in contact with the lateral surface of the first conductive layer; and a portion at the bottom of the first opening, in contact with the top surface of the second insulating layer. The third insulating layer covers the semiconductor layer inside the first opening and inside the second opening. The third conductive layer covers the third insulating layer inside the first opening and inside the second opening.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
Provided is a novel semiconductor device. This semiconductor device comprises a light-emitting element and a drive transistor having a gate and a back gate, and has: a first function for supplying a first potential to the back gate; a second function for supplying a video signal to the gate of the drive transistor and maintaining a second potential corresponding to the video signal at the back gate of the drive transistor; and a third function for, after execution of the second function, supplying a third potential to the gate of the drive transistor and supplying a current corresponding to the second potential to the light-emitting element.
G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
68.
INFORMATION PROCESSING SYSTEM AND INFORMATION PROCESSING METHOD
The present invention provides an information processing system that uses a language model to assist with correction of a document. The information processing system includes an accepting unit and a processing unit. The accepting unit functions to accept document data. The processing unit is configured to execute the following: processing to divide a document included in the document data into a plurality of first blocks; processing to create a prompt including a target sentence containing one of the plurality of first blocks and an instruction sentence containing an instruction for correcting the sentence; processing to acquire at least one second block by transmitting a prompt to a language model over a network, the second block being a proposed correction to the target sentence included in the prompt; processing to update the document data by replacing one of the plurality of first blocks with one of the at least one second block; processing to determine whether correction is necessary for one or both of the first block and the second block; and processing to evaluate the second block.
The present invention provides a highly reliable semiconductor device. In the semiconductor device, a transistor is provided on a base insulator, and includes an oxide semiconductor that has a fin shape in a cross-sectional view in the channel width direction. An insulator is provided under the oxide semiconductor. The upper end part of the insulator and the lower end part of the oxide semiconductor coincide or substantially coincide with each other. In a cross-sectional view in the channel width direction of the transistor, a first angle formed by the side surface of the insulator and the upper surface of the base insulator is less than 90°. Meanwhile, a second angle formed by the side surface of the oxide semiconductor and the upper surface of the insulator is larger than the first angle, and is 90° or around 90°. A gate insulator is disposed so as to cover the insulator and the oxide semiconductor, and a gate electrode is disposed on the gate insulator. In a cross-sectional view in the channel width direction of the transistor, the bottom surface of the gate electrode is located below the bottom surface of the oxide semiconductor.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10D 1/68 - Capacitors having no potential barriers
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Provided is a manufacturing system for a light-emitting device, with which it is possible to continuously process steps from light-emitting device formation to sealing. In this manufacturing system having an in-line type cluster, a substrate surface is angled (greater than 90 degrees, 135 degrees) relative to the horizontal plane during processing in manufacturing apparatuses such as a vapor deposition apparatus and during movement between the manufacturing apparatuses. During resist coating and exposure processing, the substrate surface is roughly parallel to the horizontal plane.
H10K 71/12 - Deposition of organic active material using liquid deposition, e.g. spin coating
H10K 71/13 - Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing
H10K 71/16 - Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering
H10K 71/40 - Thermal treatment, e.g. annealing in the presence of a solvent vapour
Provided is a novel semiconductor device. The semiconductor device has: a first conductive layer that functions as the drain of a first transistor; a second conductive layer, above the first conductive layer, that functions as the source of the first transistor; a first semiconductor layer including a channel formation region of the first transistor; a third conductive layer having a shape that conforms to a lateral surface of the first semiconductor layer and including a region that functions as the gate of the first transistor, a region that functions as the drain of a second transistor above the first transistor, and a region in contact with the second conductive layer; a fourth conductive layer, above the third conductive layer, that functions as the source of the second transistor; a second semiconductor layer including a channel formation region of the second transistor; and a fifth conductive layer having a shape that conforms to a lateral surface of the second semiconductor layer and including a region that functions as the gate of the second transistor and a region in contact with the fourth conductive layer, wherein the first and fifth conductive layer function as power lines, and the third conductive layer functions as a signal line.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
Provided is a highly reliable semiconductor device. The semiconductor device includes an oxide semiconductor layer, first to third electroconductive layers, and first to third insulating layers. The first insulating layer is positioned on the first electroconductive layer. The second electroconductive layer is positioned on the first insulating layer. The first electroconductive layer has a first recess. The first insulating layer and the second electroconductive layer have a first opening at a position overlapping the first recess. The second insulating layer is in contact, in the first opening, with at least the side surface of the first insulating layer. The oxide semiconductor layer is in contact with the upper surface of the second electroconductive layer and the bottom surface and the side surface of the first recess, and is in contact, in the first opening, with the second insulating layer. The third insulating layer is located, in the first opening, on the inner side of the oxide semiconductor layer. The third conductive layer is located, in the first opening, on the inner side of the third insulating layer. The first insulating layer has a barrier property against hydrogen. The second insulating layer has a function of capturing or fixing hydrogen.
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
H10D 1/68 - Capacitors having no potential barriers
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 64/60 - Electrodes characterised by their materials
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
Provided is a semiconductor device having a small footprint. This semiconductor device has a first transistor, a second transistor, and a first insulating layer. The first transistor has a first electroconductive layer, a first metal oxide layer, a gate insulating layer, and a first gate electrode. The second transistor has a second electroconductive layer, a third electroconductive layer, a second metal oxide layer, a gate insulating layer, and a second gate electrode. The first insulating layer is positioned on the first electroconductive layer and the second electroconductive layer and has a first opening reaching the first electroconductive layer. The first insulating layer and the third electroconductive layer have a second opening reaching the second electroconductive layer. The first metal oxide layer has a first region in contact with the upper surface of the first electroconductive layer, a second region in contact with the side surface of the first insulating layer, and a third region in contact with the upper surface of the first insulating layer. The third region is in contact with the second region. The second metal oxide layer is in contact with the upper surface of the second electroconductive layer, the side surface of the first insulating layer, and the side surface of the third electroconductive layer.
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
One aspect of the present invention provides: a lithium ion secondary battery which is lightweight and has a high capacity per weight; and a method for manufacturing the same. Instead of a metal, a resin material is used for an exterior body of a secondary battery. Sulfur or a sulfur compound is used as a positive electrode active material of the secondary battery. In addition, a solid electrolyte is used instead of an electrolyte in which lithium polysulfide dissolves. By employing the solid electrolyte, safety is enhanced due to the non-flammable nature thereof.
H01M 10/0585 - Construction or manufacture of accumulators having only flat construction elements, i.e. flat positive electrodes, flat negative electrodes and flat separators
H01M 4/13 - Electrodes for accumulators with non-aqueous electrolyte, e.g. for lithium-accumulatorsProcesses of manufacture thereof
H01M 4/38 - Selection of substances as active materials, active masses, active liquids of elements or alloys
Provided is a storage device with a novel configuration. In this invention, a first sense amplifier section, a second sense amplifier section, a word line drive circuit section, a sense amplifier drive circuit section, and a controller section are included. A sense amplifier drive block control signal is a signal for setting a state in which a plurality of sense amplifier drive blocks control first sense amplifier blocks. A word line drive block control signal is a signal for setting a state in which a plurality of word line drive blocks output word signals to memory cells connected to the first sense amplifier blocks. A second sense amplifier control signal is a signal for setting a state in which one second sense amplifier block accesses data read out to the first sense amplifier blocks via a second bit line.
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
Provided is a drive circuit with reduced power consumption. The drive circuit comprises: a control circuit; a first switch; a second switch; an amplifier; and a storage circuit. An output terminal of the amplifier is electrically connected to a first terminal of the first switch, an input terminal of the amplifier is electrically connected to a first terminal of the second switch, and a second terminal of the first switch is electrically connected to a second terminal of the second switch. The control circuit has a function of calculating a gradation difference between a first image signal input to the control circuit and a second image signal input from the storage circuit. The control circuit also has a function of comparing the gradation difference with a reference value and outputting a comparison result as a first logic signal. In addition, the control circuit has a function of inputting the first logic signal to a control terminal of the first switch, and a function of generating a second logic signal in which the logic of the first logic signal is inverted and inputting the second logic signal to a control terminal of the second switch.
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
G09G 3/3291 - Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
The present invention provides a highly integrated semiconductor device with high data retention capacity and data readout reliability. This semiconductor device has a transistor with a back gate, a first capacitive element, and a second capacitive element, wherein the first capacitive element has: as one electrode, a conductive layer formed by the same process as a first gate electrode; as a dielectric layer, a first gate insulating layer; and as the other electrode, the source electrode or the drain electrode of the transistor. The second capacitive element has: as one electrode, a conductive layer formed by the same process as a second gate electrode; as a dielectric layer, a second gate insulating layer; and as the other electrode, the source electrode or the drain electrode of the transistor.
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
78.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a semiconductor device having a high operating speed. The semiconductor device is produced by forming a first coating film and a second coating film on a first insulator, processing the second coating film to form a first layer, processing the second coating film while using the first layer as a mask to form a second layer, performing a heat treatment step to form a second insulator to cover at least a lateral surface of the second layer, forming a first oxide semiconductor to cover the lateral surface of the second layer as well as lateral and top surfaces of the first layer, the first oxide semiconductor covering the lateral surface of the second layer with the second insulator in between, processing the first oxide semiconductor using anisotropic etching to thereby form a second oxide semiconductor in contact with a lateral surface of the second insulator, removing the first layer, removing the second layer, and removing the second insulator, thereby exposing the lateral surface of the second oxide semiconductor that had been covered by the second insulator.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/41 - Electrodes characterised by their shape, relative sizes or dispositions
Provided is a semiconductor device that can be miniaturized or highly integrated. A semiconductor device according to the present invention has a first insulator that is on a substrate, a second insulator that is on the first insulator, an oxide semiconductor that contacts an upper surface of the second insulator, a pair of first conductors that contact an upper surface of the oxide semiconductor and are separated from each other on the oxide semiconductor, and a pair of second conductors that are respectively positioned on the pair of first conductors. The first insulator includes silicon and oxygen. The second insulator provides a barrier against hydrogen. The distance between the pair of second conductors is greater than the distance between the pair of first conductors.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10D 1/68 - Capacitors having no potential barriers
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 64/60 - Electrodes characterised by their materials
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
80.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
The present invention provides a semiconductor device with a small footprint. The semiconductor device has a first and a second transistor and a first insulating layer. The first transistor has a first semiconductor layer, a second insulating layer, and first to third conductive layers. The first insulating layer has a first opening reaching the first conductive layer. The second conductive layer is located on the first insulating layer and has a second opening. The first semiconductor layer has a first region in contact with the upper surface of the first conductive layer and a second region in contact with the side surface of the first insulating layer. The second insulating layer is located on the first semiconductor layer. The third conductive layer has a region overlapping the first semiconductor layer. The second transistor has a second semiconductor layer, a second insulating layer, and a fourth conductive layer. The second semiconductor layer is located between the first insulating layer and the second insulating layer, and has a third region overlapping the fourth conductive layer and a fourth region not overlapping the fourth conductive layer. The first region and the fourth region contain boron or phosphorus.
Provided is a semiconductor device that can be miniaturized or highly integrated. The semiconductor device has first to third transistors and first to fifth interconnects. The first to third transistors are superimposed in this order. The first transistor has a first semiconductor layer and a first gate. The second transistor has a second semiconductor layer and second and third gates sandwiching the second semiconductor layer. The third transistor has a third semiconductor layer and fourth and fifth gates sandwiching the third semiconductor layer. The following are connected to one another: the first gate and the first interconnect; one of either the source or the drain of the first transistor and one of either the source or the drain of the second transistor; the other of either the source or the drain of the first transistor and the second interconnect; the other of either the source or the drain of the second transistor and the third interconnect; the second gate and one of either the source or the drain of the third transistor ; the other of either the source or the drain of the third transistor and the fourth interconnect; and the fourth gate and the fifth interconnect.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
82.
POSITIVE ELECTRODE ACTIVE MATERIAL PARTICLE AND METHOD FOR PRODUCING POSITIVE ELECTRODE ACTIVE MATERIAL PARTICLE
Provided is a novel positive electrode active material particle. Provided is a positive electrode active material particle that can be used in a lithium ion secondary battery, wherein: when a plurality of the positive electrode active material particles are analyzed using X-ray photoelectron spectroscopy, there is a Mg-F bond derived from a magnesium fluoride starting material; and as regards concentration peaks in a surface layer when the positive electrode active material particle is subjected to STEM-EDX analysis, the peak concentration (atomic%) of fluorine is at least 0.75 times and at most 1.25 times the peak concentration (atomic%) of magnesium, and the peak concentration (atomic%) of titanium is at least 0.5 times and at most 1.5 times the peak concentration (atomic%) of nickel.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01M 4/36 - Selection of substances as active materials, active masses, active liquids
H01M 4/1315 - Electrodes based on mixed oxides or hydroxides, or on mixtures of oxides or hydroxides, e.g. LiCoOx containing halogen atoms, e.g. LiCoOxFy
H01M 4/13915 - Processes of manufacture of electrodes based on mixed oxides or hydroxides, or on mixtures of oxides or hydroxides, e.g. LiCoOx containing halogen atoms, e.g. LiCoOxFy
When an environmental temperature sensor for a secondary battery senses a high temperature exceeding the maximum temperature of an acceptable range, a problem arises wherein the supply of power from the secondary battery is stopped and an electronic device becomes unusable. It has been problematic that, when the environmental temperature sensor for a secondary battery senses a high temperature, an emergency call cannot be made by the electronic device. In the present invention, a microcontroller unit (MCU, also referred to as microcomputer) for high temperature operation is provided separately from a CPU used during normal operation. When an environmental temperature sensor for a secondary battery senses a high temperature, the CPU used during normal operation is caused to transition to a deep sleep mode, and an electronic device is controlled by the MCU for high temperature operation. It should be noted that, during normal operation of the CPU, the MCU for high temperature operation is in the deep sleep mode.
G06F 1/3293 - Power saving characterised by the action undertaken by switching to a less power-consuming processor, e.g. sub-CPU
G06F 1/28 - Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
G06F 1/30 - Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
Provided is a semiconductor device which has a novel configuration. This semiconductor device includes a memory cell, a first sense amplifier, a product-sum operation circuit, and a second sense amplifier. The first sense amplifier, the second sense amplifier, and the product-sum operation circuit are provided in a first element layer. The memory cell is provided in a second element layer. The second element layer is provided in a layer above the first element layer. The memory cell is electrically connected to the first sense amplifier and the product-sum operation circuit with a first bit line interposed therebetween. The second sense amplifier is electrically connected to the first sense amplifier and the product-sum operation circuit via a second bit line. The first sense amplifier has a function of outputting first data held in the memory cell to the product-sum operation circuit and the second sense amplifier in accordance with a column selection signal. The product-sum operation circuit has a function of executing a product-sum operation of the first data and the second data supplied from the second sense amplifier over the second bit line in accordance with the column selection signal.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
The present invention provides a semiconductor device with a fast operating speed. A first insulator is disposed on a substrate, a second insulator is disposed on the first insulator, an oxide semiconductor is disposed on the first insulator and covers the second insulator, a first conductor and a second conductor are disposed on the oxide semiconductor, a third insulator is disposed on the first and second conductors and has an opening overlapping an area between the first and second conductors, a fourth insulator is disposed in the opening, overlapping the oxide semiconductor, a third conductor is disposed on the fourth insulator in the opening, the sides of the first insulator coincide or substantially coincide with the sides of the oxide semiconductor, the sides of the first conductor, and the sides of second conductor in a plan view, the film thickness of the first insulator is greater than the film thickness of the fourth insulator, and the height of the second insulator is greater than the width of the second insulator in a cross-sectional view in the channel width direction.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 99/00 - Subject matter not provided for in other groups of this subclass
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Provided is a semiconductor device with a high operating speed. An oxide semiconductor has a channel formation region of a first transistor and a channel formation region of a second transistor. A first insulator on top of the oxide semiconductor has a region that functions as a gate insulator film of the first transistor. A second insulator on top of the oxide semiconductor has a region that functions as a gate insulator film of the second transistor. A fourth conductor on top of the first insulator has a region that functions as the gate electrode of the first transistor and a plurality of regions that overlap the oxide semiconductor in a top view. A fifth conductor on top of the second insulator has a region that functions as the gate electrode of the second transistor and a plurality of regions that overlap the oxide semiconductor in a top view. The height of the oxide semiconductor is greater than the width of the oxide semiconductor in a top view.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
87.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a semiconductor device that exhibits a fast operating speed. The semiconductor device includes a transistor, and the transistor includes a plurality of oxide semiconductors having a fin shape in a cross-sectional view in the channel width direction. Below the oxide semiconductor there is disposed an insulator having a shape in plan view that matches or substantially matches the oxide semiconductor. A gate insulator is disposed so as to cover the insulator and the oxide semiconductor, and a gate electrode is disposed on the gate insulator. In a cross-sectional view in the channel width direction of the transistor, the bottom surface of the gate electrode is disposed below the bottom surface of the oxide semiconductor. The insulator under the oxide semiconductor functions to capture or fix hydrogen.
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
88.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a semiconductor device with a high operating speed. The semiconductor device includes a transistor, the transistor having a plurality of oxide semiconductors with a fin-like shape in a cross-sectional view in the channel width direction. A source electrode includes a first conductor and a second conductor on top of the first conductor. A drain electrode includes a third conductor and a fourth conductor on top of the third conductor. The first and third conductors protrude out farther than the second and fourth conductors, respectively. An interlayer dielectric is provided on top of the third and fourth conductors. The interlayer dielectric has an opening that overlaps with the oxide semiconductors. A barrier insulator is provided inside the opening so as to contact side surfaces of the first and second conductors and side surfaces of the third and fourth conductors. A gate insulator is provided on top of the barrier insulator so as to contact the oxide semiconductors, the side surface of the first conductor, and the side surface of the second conductor, and a gate electrode is provided on top of the gate insulator.
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 99/00 - Subject matter not provided for in other groups of this subclass
The present invention provides a semiconductor device with reduced power consumption. The semiconductor device has a first circuit that generates a first potential and a second circuit that includes a first transistor and a second transistor, each of which is a vertical transistor, wherein after the first potential is supplied to the back gate of the first transistor via the source and drain of the second transistor, the back gate of the first transistor is put into a floating state by turning off the second transistor.
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
90.
DISPLAY DEVICE, DISPLAY MODULE, AND ELECTRONIC APPARATUS
Provided is a novel display device that has excellent convenience, utility, and reliability. The display device includes a first light-emitting device, a second light-emitting device, a first conductive layer, a first insulating layer, a second insulating layer, and a second conductive layer. The first light-emitting device comprises a first electrode, a second electrode, and a first unit. The first unit is sandwiched between the first electrode and the second electrode and includes a light-emitting material. The second light-emitting device includes a third electrode, a fourth electrode, and a second unit. The third electrode is adjacent to the first electrode. The third electrode is disposed so as to sandwich a first gap with the first electrode. The second unit is sandwiched between the third electrode and the fourth electrode and includes a light-emitting material. The first conductive layer includes the second electrode and the fourth electrode. The first conductive layer comprises a region overlapping the first gap. The first insulating layer is in contact with a side surface of the first unit and a side surface of the second unit. The first insulating layer comprises a region overlapping an outer peripheral portion of the first electrode. A first opening surrounded by the region is provided, and the first opening has a convex shape in a top view. The second insulating layer comprises a flat portion, the flat portion overlaps the first opening, and the flat portion is disposed below the first electrode. The second conductive layer sandwiches the flat portion with the first electrode and includes a connection part that electrically connects the second conductive layer and the first electrode at a position overlapping the region.
H10K 59/122 - Pixel-defining structures or layers, e.g. banks
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H10K 50/814 - Anodes combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
H10K 50/824 - Cathodes combined with auxiliary electrodes
H10K 59/95 - Assemblies of multiple devices comprising at least one organic light-emitting element wherein all light-emitting elements are organic, e.g. assembled OLED displays
H10K 59/121 - Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
H10K 59/131 - Interconnections, e.g. wiring lines or terminals
Provided is a novel semiconductor device. The present invention comprises a first transistor, a second transistor, and a third transistor, either the source or the drain of the first transistor being electrically connected to the gate of the second transistor, either the source or the drain of the second transistor being electrically connected to the gate of the third transistor, the gate of the first transistor being electrically connected to a first wiring to which a constant potential is applied, and the other of the source and the drain of the first transistor being electrically connected to a second wiring.
H10B 12/00 - Dynamic random access memory [DRAM] devices
G11C 11/405 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
92.
ORGANIC SEMICONDUCTOR DEVICE, LIGHT-EMITTING DEVICE, LIGHT-RECEIVING DEVICE, AND DISPLAY APPARATUS
The present invention provides a light-emitting device having good reliability. The present invention also provides a display apparatus having good reliability and high definition. Provided are: a light-emitting device which has a pixel electrode, a common electrode, and an organic compound layer positioned between the pixel electrode and the common electrode, and in which the organic compound layer has a hole transport layer, a light-emitting layer, and an electron transport layer, the hole transport layer contains an organic compound represented by the following structural formula (h100), and the electron transport layer contains an organic compound represented by the following structural formula (e100); and a display apparatus that has a plurality of said light-emitting devices in a display unit.
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H10K 30/30 - Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation comprising bulk heterojunctions, e.g. interpenetrating networks of donor and acceptor material domains
H10K 30/60 - Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation in which radiation controls flow of current through the devices, e.g. photoresistors
H10K 65/00 - Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element and at least one organic radiation-sensitive element, e.g. organic opto-couplers
H10K 85/60 - Organic compounds having low molecular weight
Provided is a semiconductor device having a novel configuration. The present invention is provided with a first transistor, a capacitor, and a second transistor. The first transistor has a silicon layer having a channel formation region. The capacitor has a first electrode and a second electrode. The second transistor has an oxide semiconductor layer having a channel formation region. The first electrode is electrically connected to a first gate electrode of the first transistor. The second electrode is electrically connected to the source electrode or the drain electrode of the second transistor. The first electrode is provided along a side surface and the bottom section of a first opening section provided in a first insulating layer on the first gate electrode. The oxide semiconductor layer is provided along a side surface and the bottom section of a second opening section provided in a second insulating layer on the second electrode. In a plan view, the first gate electrode, the first electrode, the second electrode, and the oxide semiconductor layer have overlapping regions.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
Space probes used on planets other than Earth and on asteroids need to withstand severe environmental conditions. One aspect of the present invention provides a space probe to which is mounted a secondary battery that can be used over a wide temperature range and is hardly affected by environmental temperatures. In addition, the present invention provides a secondary battery that is suitable for the space probe and is very safe. According to the present invention, an electrolyte is put in a container such as a bag and is sealed. The electrolyte is kept sealed in an airtight manner in the bag from Earth to a target planet, and is subjected to an impact at the time of landing on the target planet and after a while, the secondary battery is supplied with the electrolyte and functions as a secondary battery. A battery reaction does not occur until a portion of the bag of the electrolyte is broken by the impact.
The present invention provides a highly integrated semiconductor device with minute transistors. The semiconductor device has two vertical transistors and an insulating layer. The insulating layer is provided with a line-shaped aperture formed by an exposure device, and the two vertical transistors are provided opposite each other, with the opposing sidewalls of the aperture oriented in the channel length direction. The two vertical transistors share one of either the source electrode or the drain electrode, above which the gate electrode and the other of either the source electrode or the drain electrode of each transistor are superimposed in different areas. Gate insulating layers of the two transistors are each provided in contact with the sidewalls of the aperture. A semiconductor layer is provided along the sidewalls and bottom of the aperture, with the gate insulating layers interposed. The semiconductor layer is shared by the two vertical transistors.
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
G09F 9/33 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
G09F 9/35 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being liquid crystals
96.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a semiconductor device that can be miniaturized or highly integrated. This semiconductor device is provided with a memory cell having first to third vertical transistors. The first to third vertical transistors are provided stacked from the bottom in the given order. The first vertical transistor has a gate electrode between a lower electrode and an upper electrode, and the gate electrode surrounds a semiconductor layer. An insulating layer is embedded inside the semiconductor layer, and an upper surface of the insulating layer is positioned above an upper surface of the semiconductor layer in a region overlapping the upper electrode. The second and third vertical transistors have a gate electrode further inward than the semiconductor layer. A lower electrode of the second vertical transistor is positioned on the insulating layer and is in contact with the semiconductor layer of the first vertical transistor. The conductive layer used for the gate electrode of the second vertical transistor and the conductive layer used for a lower electrode of the third vertical transistor are the same.
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
97.
INFORMATION PROCESSING SYSTEM AND INFORMATION PROCESSING METHOD
The present invention provides an information processing system that can prevent the leakage of confidential information. The information processing system includes an accepting unit and a processing unit. The accepting unit has a function of accepting first text data and at least one first string. The processing unit is configured to execute: processing to convert the at least one first string to a second string associated with the first string in a 1:1 manner, thereby converting the first text data to second text data containing at least one second string; processing to transmit the second text data to a language model over a network, thereby acquiring third text data containing at least one second string; and processing to convert the at least one second string to the first string associated with the second string in a 1:1 manner, thereby converting the third text data to fourth text data. The second string contains a symbol.
Provided is a semiconductor device having a high operation speed. The present invention has an oxide semiconductor, first and second insulators, and first to third conductors. The oxide semiconductor is disposed on a substrate. The first conductor and the second conductor are disposed on the oxide semiconductor. The first insulator is disposed on the first conductor and the second conductor and has an opening that overlaps a region between the first conductor and the second conductor. The second insulator is disposed within the opening so as to overlap the oxide semiconductor. The third conductor is disposed on the second insulator within the opening. The height of the oxide semiconductor is greater than the width of the oxide semiconductor in a cross-sectional view in the channel width direction. In top view, there are two or more regions in which the oxide semiconductor and the third conductor overlap.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
99.
MEMORY CIRCUIT, PROCESSING DEVICE, AND ELECTRONIC EQUIPMENT
The present invention provides a memory circuit with reduced circuit area. The memory circuit has first through third layers, the first layer having a first transistor and a second transistor, the second layer having a third transistor and a fourth transistor, and the third layer having a fifth transistor and a sixth transistor. The first transistor, the third transistor, and the fifth transistor overlap each other, and the second transistor, the fourth transistor, and the sixth transistor overlap each other. A first terminal of the fifth transistor is electrically connected to the gate of the third transistor, a first terminal of the fourth transistor, and a first terminal of the first transistor, and a first terminal of the sixth transistor is electrically connected to the gate of the fourth transistor, a first terminal of the third transistor, and a first terminal of the second transistor.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Provided is an imaging device that makes it possible to acquire a high-definition image. An imaging device according to the present invention includes first to third transistors and a capacitor in a pixel circuit, and the first to third transistors are vertical transistors having channel formation regions provided following a side surface of an opening provided in an insulator, which makes it possible to reduce the occupied area. Furthermore, the first transistor and the third transistor have a region in which the first transistor and the third transistor overlap each other, and the second transistor has a region in which the second transistor and the capacitor overlap each other. Therefore, the layout area for the transistors and the capacitor can be reduced, which makes it possible to increase the pixel density.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H04N 25/79 - Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
patents
