A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first transistor that includes a first conductor, a first insulator, a first metal oxide, a second insulator, a second conductor, and a third conductor and a fourth conductor which cover parts of a top surface and parts of a side surface of the first metal oxide, which are stacked in this order from the bottom. A second transistor includes a fifth conductor, the first insulator, a second metal oxide, a third insulator, a sixth conductor, and a seventh conductor and a eighth conductor which cover parts of a top surface and parts of a side surface of the second metal oxide, which are stacked in this order from the bottom. A third transistor includes a ninth conductor, the first insulator, the second metal oxide, a fourth insulator, a tenth conductor, an eighth conductor, and an eleventh conductor covering part of the top surface and part of the side surface of the second metal oxide, which are stacked in this order from the bottom. One electrode of a capacitor including a material that can have ferroelectricity is electrically connected to the third conductor and the sixth conductor.
H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
A storage device that can be miniaturized or highly integrated is provided. A storage device includes a memory cell including a transistor and a capacitor, a first insulator, a second insulator over the first insulator, and a third insulator over the second insulator. The transistor includes an oxide over the first insulator, a first conductor and a second conductor over the oxide, a fourth insulator over the oxide, and a third conductor over the fourth insulator. The second insulator includes a first opening. The fourth insulator and the third conductor are placed in the first opening. The second insulator and the third insulator each include a second opening. The capacitor includes a fourth conductor in contact with the top surface of the second conductor, a fifth insulator over the fourth conductor, and a fifth conductor over the fifth insulator. The second insulator includes a third opening. The first insulator includes a fourth opening. The third insulator includes a fifth opening. The third opening overlaps with at least part of the fourth opening and at least part of the fifth opening in a plan view. A sixth conductor and part of the first conductor are placed inside the third opening. The sixth conductor includes a region in contact with part of the top surface and part of a side surface of the first conductor.
An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 μm is 1 aA or less.
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
4.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
A quinoxaline derivative that is a novel organic compound is provided. A quinoxaline derivative represented by General Formula (G1) has a structure in which a quinoxaline skeleton is bonded to the 9-position of an anthracene skeleton, the 10-position of the anthracene skeleton is bonded to a heteroaromatic ring, and the 3-position of the heteroaromatic ring is nitrogen.
A quinoxaline derivative that is a novel organic compound is provided. A quinoxaline derivative represented by General Formula (G1) has a structure in which a quinoxaline skeleton is bonded to the 9-position of an anthracene skeleton, the 10-position of the anthracene skeleton is bonded to a heteroaromatic ring, and the 3-position of the heteroaromatic ring is nitrogen.
A quinoxaline derivative that is a novel organic compound is provided. A quinoxaline derivative represented by General Formula (G1) has a structure in which a quinoxaline skeleton is bonded to the 9-position of an anthracene skeleton, the 10-position of the anthracene skeleton is bonded to a heteroaromatic ring, and the 3-position of the heteroaromatic ring is nitrogen.
In General Formula (G1) shown above, a and b each independently represent a substituted or unsubstituted arylene group having 6 to 13 carbon atoms in a ring. In addition, m and n are each independently 0, 1, or 2.
H10K 85/60 - Organic compounds having low molecular weight
C07D 401/10 - Heterocyclic compounds containing two or more hetero rings, having nitrogen atoms as the only ring hetero atoms, at least one ring being a six-membered ring with only one nitrogen atom containing two hetero rings linked by a carbon chain containing aromatic rings
C07D 403/10 - Heterocyclic compounds containing two or more hetero rings, having nitrogen atoms as the only ring hetero atoms, not provided for by group containing two hetero rings linked by a carbon chain containing aromatic rings
A parameter candidate for a semiconductor element is provided. A data set of measurement data is provided to a parameter extraction portion, and a model parameter is extracted. A first netlist is provided to a circuit simulator, simulation is performed using the first netlist and the model parameter, and a first output result is output. A classification model learns the model parameter and the first output result and classifies the model parameter. A second netlist and a model parameter are provided to the circuit simulator. A variable to be adjusted is supplied to a neural network, an action value function is output, and the variable is updated. The circuit simulator performs simulation using the second netlist and the model parameter. When a second output result to be output does not satisfy conditions, a weight coefficient of the neural network is updated. When the second output result satisfies the conditions, the variable is judged to be the best candidate.
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G06N 3/042 - Knowledge-based neural networksLogical representations of neural networks
The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
G11C 19/00 - Digital stores in which the information is moved stepwise, e.g. shift registers
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
A light-emitting element which has low driving voltage and high emission efficiency is provided. The light-emitting element includes, between a pair of electrodes, a hole-transport layer and a light-emitting layer over the hole-transport layer. The light-emitting layer contains a first organic compound having an electron-transport property, a second organic compound having a hole-transport property, and a light-emitting third organic compound converting triplet excitation energy into light emission. A combination of the first organic compound and the second organic compound forms an exciplex. The hole-transport layer contains at least a fourth organic compound whose HOMO level is lower than or equal to that of the second organic compound and a fifth organic compound whose HOMO level is higher than that of the second organic compound.
To reduce the manufacturing cost of a display device using a micro LED as a display element. To manufacture a display device using a micro LED as a display element in a high yield. Employed is a method for manufacturing a display device, including: forming a plurality of transistors in a matrix over a substrate (800), forming conductors (21, 23) electrically connected to the transistors over the substrate (800), and forming a plurality of light-emitting elements (51) in a matrix over a film (927). Each of the light-emitting elements (51) includes electrodes (85, 87) on one surface and the other surface is in contact with the film (927). The conductors (21, 23) and the electrodes (85, 87) are opposed to each other. An extrusion mechanism (929) is pushed out from the film (927) side to the substrate (800) side so that the conductors (21, 23) and the electrodes (85, 87) are in contact with each other, whereby the conductors (21, 23) and the electrodes (85, 87) are electrically connected to each other.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 23/00 - Details of semiconductor or other solid state devices
The invention of the application is the invention regarding a semiconductor device and a method for driving the semiconductor device. The semiconductor device includes first and second transistors, first to fifth switches, first to third capacitors, and a display element. The first transistor (M2) comprises a back gate, a gate of the first transistor is electrically connected to the first switch (M1), the second switch (M3) and the first capacitor (C1) are positioned between the gate of the first transistor and a source of the first transistor, the back gate of the first transistor is electrically connected to the third switch (M4), the second capacitor (C2) is positioned between the back gate of the first transistor and the source of the first transistor, the source of the first transistor is electrically connected to the fourth switch (M6) and a drain of the second transistor (M5), a gate of the second transistor is electrically connected to the fifth switch (M7), the third capacitor (C3) is positioned between the gate of the second transistor and a source of the second transistor, and the source of the second transistor is electrically connected to the display element (61).
G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.
G02F 1/136 - Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction.
G11C 19/18 - Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
G09G 3/3266 - Details of drivers for scan electrodes
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer having a channel formation region, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer and reduce impurities such as moisture. Moreover, the oxide semiconductor layer subjected to the heat treatment is slowly cooled under an oxygen atmosphere.
H10D 62/80 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
14.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes an oxide semiconductor layer including a crystalline region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region. The crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer.
H10D 62/80 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
H10D 99/00 - Subject matter not provided for in other groups of this subclass
To provide a light-emitting element which uses a fluorescent material as a light-emitting substance and has higher luminous efficiency. To provide a light-emitting element which includes a mixture of a thermally activated delayed fluorescent substance and a fluorescent material. By making the emission spectrum of the thermally activated delayed fluorescent substance overlap with an absorption band on the longest wavelength side in absorption by the fluorescent material in an S1 level of the fluorescent material, energy at an S1 level of the thermally activated delayed fluorescent substance can be transferred to the S1 of the fluorescent material. Alternatively, it is also possible that the S1 of the thermally activated delayed fluorescent substance is generated from part of the energy of a T1 level of the thermally activated delayed fluorescent substance, and is transferred to the S1 of the fluorescent material.
An imaging device that has an image processing function and is capable of a high-speed operation is provided. The imaging device has an additional function such as image processing, and can retain analog data obtained by an image capturing operation in pixels and extract data obtained by multiplying the analog data by a given weight coefficient. In the imaging device, the data is stored in a memory cell and pooling processing of data stored in a plurality of memory cells can be performed. The pixels are provided so as to have a region overlapping with at least one of the memory cells, a pooling processing circuit, and a reading circuit of the pixels; thus, an increase in the area of the imaging device can be inhibited even with an additional function.
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/79 - Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
A display device with high display quality and low power consumption is provided. In the display device, a first transistor, a second transistor, a first conductive layer, and a light-emitting diode package are included in a pixel, and then the light-emitting diode package includes a first light-emitting diode, a second light-emitting diode, a second conductive layer, a third conductive layer, and a fourth conductive layer. One of a source and a drain of the first transistor is electrically connected to the first light-emitting diode through the second conductive layer. One of a source and a drain of the second transistor is electrically connected to the second light-emitting diode through the third conductive layer. The first conductive layer supplied with a constant potential is electrically connected to the other electrodes of the first and second light-emitting diodes through the fourth conductive layer.
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
H10D 87/00 - Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
H10H 20/857 - Interconnections, e.g. lead-frames, bond wires or solder balls
Acetylene black, which is used as a conductivity aid, is a material that tends to agglomerate. Reducing the quantity of conductivity aid makes agglomeration occur less readily, but the electronic conductivity of an electrode as a whole will decrease. Accordingly, one objective of the present invention is to provide a secondary battery in which the quantity of conductivity aid is reduced while also having sufficient electronic conductivity of an electrode as a whole. A lithium-ion secondary battery disclosed in the present specification has a positive electrode, a separator, and a negative electrode. In the positive electrode, layers containing bundles of carbon nanotubes whose long axes are oriented in one direction and layers containing positive electrode active material are alternately stacked on a positive electrode current collector.
H01M 4/13 - Electrodes for accumulators with non-aqueous electrolyte, e.g. for lithium-accumulatorsProcesses of manufacture thereof
H01M 4/58 - Selection of substances as active materials, active masses, active liquids of inorganic compounds other than oxides or hydroxides, e.g. sulfides, selenides, tellurides, halogenides or LiCoFySelection of substances as active materials, active masses, active liquids of polyanionic structures, e.g. phosphates, silicates or borates
H01M 4/505 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of manganese of mixed oxides or hydroxides containing manganese for inserting or intercalating light metals, e.g. LiMn2O4 or LiMn2OxFy
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
A document reading support method using a language model is provided. The document reading support method includes the steps of: displaying a segmented document; receiving selection of a part of the document; inputting the part and an instruction sentence for summarizing the part to a language model; determining whether the number of tokens of the part is less than or equal to a predetermined value; and obtaining a summary of the part determined to have the tokens of less than or equal to the predetermined value.
A semiconductor device with high memory density is used. In the semiconductor device, a first memory layer and a second memory layer are sequentially stacked. Each of the first and second memory layers includes second to sixth insulators, an oxide, and first to fourth conductors. In each of the first and second memory layers, the second insulator and the oxide are sequentially stacked over a first insulator. The first and second conductors are located over the first and second insulators and the oxides in different regions. The third insulator is located over the first and second conductors and the first insulator, and the fourth insulator is located over the third insulator. The fifth insulator is located over the oxide and a side surface of the fourth insulator, and the third conductor is located over the fifth insulator. The sixth insulator is located over the second conductor and the side surface of the fourth insulator, and the fourth conductor is located over the sixth insulator. The fourth conductor of the first memory layer overlaps with the second insulator and the oxide of the second memory layer.
A semiconductor device including a transistor having a minute size is provided. The semiconductor device includes a transistor, a first insulating layer, and a second insulating layer. The transistor includes a first semiconductor layer, a first conductive layer, a second conductive layer including a region overlapping with the first conductive layer with the first insulating layer therebetween, a third conductive layer, and a third insulating layer. The second conductive layer and the first insulating layer have a first opening reaching the first conductive layer. The first semiconductor layer is in contact with a top surface and a side surface of the second conductive layer, a side surface of the first insulating layer, and a top surface of the first conductive layer. The third insulating layer is provided over the first insulating layer, the first semiconductor layer, and the second conductive layer. The third conductive layer is provided over the third insulating layer. The second insulating layer is provided over the third conductive layer and the third insulating layer.
A novel semiconductor device or the like is provided. The semiconductor device that includes a first flip-flop having a function of retaining input data in response to a clock signal and outputting first output data based on the input data; a second flip-flop having a function of retaining the input data in response to the clock signal and outputting second output data based on the input data; a third flip-flop having a function of retaining the input data in response to the clock signal and outputting third output data based on the input data; a majority circuit to which the first output data to the third output data are input and having a function of determining the most common logical value in the first output data to the third output data by majority decision making and outputting data of the determined logical value as fourth output data; and a switching circuit to which the first output data and the fourth output data are input and having a function of outputting output data based on the first output data or the fourth output data in response to a switching signal.
A novel semiconductor device is provided. One of a source and a drain of a first transistor is connected to one terminal of a first capacitor; the other of the source and the drain of the first transistor is connected to a bit line; a gate of the first transistor is connected to a word line; the other terminal of the first capacitor is connected to a first driver circuit; the first driver circuit is configured to output a first potential, output a second potential in conjunction with a timing when a potential of a selection signal that is supplied to the word line changes, and output a third potential in conjunction with a timing when a potential of data that is supplied to the bit line changes; a direction of change from the first potential to the second potential is opposite to a direction in which the potential of the selection signal changes; and a direction of change from the first potential to the third potential is opposite to a direction in which the potential of the data changes.
A semiconductor device which includes a thin film transistor having an oxide semiconductor layer and excellent electrical characteristics is provided. Further, a method for manufacturing a semiconductor device in which plural kinds of thin film transistors of different structures are formed over one substrate to form plural kinds of circuits and in which the number of steps is not greatly increased is provided. After a metal thin film is formed over an insulating surface, an oxide semiconductor layer is formed thereover. Then, oxidation treatment such as heat treatment is performed to oxidize the metal thin film partly or entirely. Further, structures of thin film transistors are different between a circuit in which emphasis is placed on the speed of operation, such as a logic circuit, and a matrix circuit.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H10D 62/80 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
H10D 99/00 - Subject matter not provided for in other groups of this subclass
An organic compound having a hole-transport property and a low refractive index is provided. An organic compound represented by General Formula (G1) shown below is provided. In General Formula (G1), Ar1 represents a substituted or unsubstituted arylene group having 6 to 13 carbon atoms in a ring, n represents an integer of 0 or 1, and Ar2 represents an aryl group having 6 to 10 carbon atoms in a ring and includes at least one branched-chain or cyclic alkyl group having 3 to 12 carbon atoms. The total number of carbon atoms of the branched-chain or cyclic alkyl group in Ar2 is more than or equal to 6. R1 to R4 each independently represent an alkyl group having 1 to 6 carbon atoms. R11 to R14 and R21 to R24 each independently represent a hydrogen atom or an alkyl group having 1 to 4 carbon atoms. Any one of R15 to R18 and any one of R25 to R28 each represent a bond directly bonded to a nitrogen atom, and the others each independently represent a hydrogen atom or an alkyl group having 1 to 4 carbon atoms.
An organic compound having a hole-transport property and a low refractive index is provided. An organic compound represented by General Formula (G1) shown below is provided. In General Formula (G1), Ar1 represents a substituted or unsubstituted arylene group having 6 to 13 carbon atoms in a ring, n represents an integer of 0 or 1, and Ar2 represents an aryl group having 6 to 10 carbon atoms in a ring and includes at least one branched-chain or cyclic alkyl group having 3 to 12 carbon atoms. The total number of carbon atoms of the branched-chain or cyclic alkyl group in Ar2 is more than or equal to 6. R1 to R4 each independently represent an alkyl group having 1 to 6 carbon atoms. R11 to R14 and R21 to R24 each independently represent a hydrogen atom or an alkyl group having 1 to 4 carbon atoms. Any one of R15 to R18 and any one of R25 to R28 each represent a bond directly bonded to a nitrogen atom, and the others each independently represent a hydrogen atom or an alkyl group having 1 to 4 carbon atoms.
H10K 85/60 - Organic compounds having low molecular weight
C07C 211/61 - Compounds containing amino groups bound to a carbon skeleton having amino groups bound to carbon atoms of six-membered aromatic rings of the carbon skeleton having amino groups bound to carbon atoms of six-membered aromatic rings being part of condensed ring systems of the carbon skeleton with at least one of the condensed ring systems formed by three or more rings
Provided is a semiconductor device capable of retaining data for a long time. The semiconductor device includes a cell provided with a capacitor, a first transistor, and a second transistor; the capacitor includes a first electrode, a second electrode, and a ferroelectric layer; the ferroelectric layer is provided between the first electrode and the second electrode and polarization reversal occurs by application of a first saturated polarization voltage or a second saturated polarization voltage whose polarity is different from that of the first saturated polarization voltage; and the first electrode, one of a source and a drain of the first transistor, and a gate of the second transistor are electrically connected to one another. In a first period, the first saturated polarization voltage is applied to the ferroelectric layer. In a second period, a voltage having a value between the first saturated polarization voltage and the second saturated polarization voltage is applied to the ferroelectric layer as a data voltage.
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
27.
TOUCH SENSOR, DISPLAY DEVICE, DISPLAY MODULE, AND ELECTRONIC DEVICE
Sensing time of a touch sensor is shortened to increase responsiveness of touch sensing. A display device includes a gate driver, a plurality of touch sensors, and a plurality of touch wirings. The gate driver has a function of supplying a scan signal to the plurality of touch wirings at the same timing, and the touch sensors in different positions sense a plurality of touches at the same timing. In this manner, the responsiveness of touch sensing is increased. The gate driver has a function of controlling a scan signal for refreshing display and a scan signal used by the touch sensor for sensing.
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
G06F 3/044 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
G06F 3/045 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using resistive elements, e.g. a single continuous surface or two parallel surfaces put in contact
G06F 3/047 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using sets of wires, e.g. crossed wires
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
28.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device having a large on-state current and high reliability is provided. The semiconductor device includes a first insulator, a first oxide over the first insulator, a second oxide over the first oxide, a third oxide and a fourth oxide over the second oxide, a first conductor over the third oxide, a second conductor over the fourth oxide, a fifth oxide over the second oxide, a second insulator over the fifth oxide, and a third conductor over the second insulator. The fifth oxide is in contact with a top surface of the second oxide, a side surface of the first conductor, a side surface of the second conductor, a side surface of the third oxide, and a side surface of the fourth oxide. The second oxide contains In, an element M, and Zn. The first oxide and the fifth oxide each contain at least one of constituent elements included in the second oxide. The third oxide and the fourth oxide each contain the element M. The third oxide and the fourth oxide include a region where the concentration of the element M is higher than that in the second oxide.
H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
29.
POSITIVE ELECTRODE ACTIVE MATERIAL AND SECONDARY BATTERY
A positive electrode active material that has high capacity and excellent charge and discharge cycle performance for a secondary battery is provided. A positive electrode active material that inhibits a decrease in capacity in charge and discharge cycles is provided. A high-capacity secondary battery is provided. A secondary battery with excellent charge and discharge characteristics is provided. A highly safe or reliable secondary battery is provided. A positive electrode active material contains lithium, cobalt, oxygen, and aluminum and has a crystal structure belonging to a space group R-3m when Rietveld analysis is performed on a pattern obtained by powder X-ray diffraction. In analysis by X-ray photoelectron spectroscopy, the number of aluminum atoms is less than or equal to 0.2 times the number of cobalt atoms.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01M 4/02 - Electrodes composed of, or comprising, active material
H01M 4/36 - Selection of substances as active materials, active masses, active liquids
H01M 10/0525 - Rocking-chair batteries, i.e. batteries with lithium insertion or intercalation in both electrodesLithium-ion batteries
H01M 10/0569 - Liquid materials characterised by the solvents
30.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
The semiconductor device includes a first insulating layer, a second insulating layer, an oxide semiconductor layer, and first to third conductive layers. The first conductive layer and the second conductive layer are connected to the oxide semiconductor layer. The second insulating layer includes a region in contact with the oxide semiconductor layer, and the third conductive layer includes a region in contact with the second insulating layer. The oxide semiconductor layer includes first to third regions. The first region and the second region are separated from each other, and the third region is located between the first region and the second region. The third region and the third conductive layer overlap with each other with the second insulating layer located therebetween. The first region and the second region include a region having a higher carbon concentration than the third region.
A display device having a photosensing function is provided. A display device having a biometric authentication function typified by fingerprint authentication is provided. A display device having a touch panel function and a biometric authentication function is provided. The display device includes a first substrate, a light guide plate, a first light-emitting element, a second light-emitting element, and alight-receiving element. The first substrate and the light guide plate are provided to face each other. The first light-emitting element and the light-receiving element are provided between the first substrate and the light guide plate. The first light-emitting element has a function of emitting first light through the light guide plate. The second light-emitting element has a function of emitting second light to a side surface of the light guide plate. The light-receiving element has functions of receiving the first light and converting the first light into an electric signal and functions of receiving the second light and converting the second light into an electric signal. The first light includes visible light, and the second light includes infrared light.
H10K 65/00 - Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element and at least one organic radiation-sensitive element, e.g. organic opto-couplers
A61B 5/00 - Measuring for diagnostic purposes Identification of persons
A61B 5/1172 - Identification of persons based on the shapes or appearances of their bodies or parts thereof using fingerprinting
A61B 5/145 - Measuring characteristics of blood in vivo, e.g. gas concentration or pH-value
A61B 5/1455 - Measuring characteristics of blood in vivo, e.g. gas concentration or pH-value using optical sensors, e.g. spectral photometrical oximeters
G06F 3/044 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
G09F 9/33 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
A transistor that is to be provided has such a structure that a source electrode layer and a drain electrode layer between which a channel formation region is sandwiched has regions projecting in a channel length direction at lower end portions, and an insulating layer is provided, in addition to a gate insulating layer, between the source and drain electrode layers and a gate electrode layer. In the transistor, the width of the source and drain electrode layers is smaller than that of an oxide semiconductor layer in the channel width direction, so that an area where the gate electrode layer overlaps with the source and drain electrode layers can be made small. Further, the source and drain electrode layers have regions projecting in the channel length direction at lower end portions.
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
33.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE
A semiconductor device having favorable electrical characteristics is provided. A semiconductor device having stable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, and a first conductive layer. The semiconductor layer includes an island-shaped top surface. The first insulating layer is provided in contact with a top surface and a side surface of the semiconductor layer. The first conductive layer is positioned over the first insulating layer and includes a portion overlapping with the semiconductor layer. In addition, the semiconductor layer includes a metal oxide, and the first insulating layer includes an oxide. The semiconductor layer includes a first region overlapping with the first conductive layer and a second region not overlapping with the first conductive layer. The first insulating layer includes a third region overlapping with the first conductive layer and a fourth region not overlapping with the first conductive layer. Furthermore, the second region and the fourth region contain phosphorus or boron.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/263 - Bombardment with wave or particle radiation with high-energy radiation
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
H10D 99/00 - Subject matter not provided for in other groups of this subclass
H10K 59/123 - Connection of the pixel electrodes to the thin film transistors [TFT]
35.
LIQUID CRYSTAL DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME
A driver circuit includes a circuit 200, a transistor 101_1, and a transistor 101_2. A signal is selectively input from the circuit 200 to a gate of the transistor 101_1 and the transistor 101_2, so that the transistor 101_1 and the transistor 101_2 are controlled to be on or off. The transistor 101_1 and the transistor 101_2 are turned on or off; thus, the wiring 112 and the wiring 111 become conducting or non-conducting.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
H10D 62/80 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
36.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region. The first region is a CAAC oxide semiconductor region. The pair of second regions and the pair of third regions are each an amorphous oxide semiconductor region containing a dopant. The dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions.
H10D 62/80 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
H10D 99/00 - Subject matter not provided for in other groups of this subclass
37.
ORGANIC SEMICONDUCTOR DEVICE, ORGANIC EL DEVICE, PHOTODIODE SENSOR, DISPLAY DEVICE, LIGHT-EMITTING APPARATUS, ELECTRONIC DEVICE, AND LIGHTING DEVICE
An organic semiconductor device with low driving voltage is provided. The organic semiconductor device includes a layer containing an organic compound between a pair of electrodes. The layer containing an organic compound includes a hole-transport region. The hole-transport region includes a first layer and a second layer. The first layer is positioned between the anode and the second layer. When a potential gradient of a surface potential of an evaporated film is set as GSP (mV/nm), a value obtained by subtracting GSP of an organic compound in the second layer from GSP of an organic compound in the first layer is less than or equal to 20 (mV/nm).
To increase the detection sensitivity of a touch panel, provide a thin touch panel, provide a foldable touch panel, or provide a lightweight touch panel. A display element and a capacitor forming a touch sensor are provided between a pair of substrates. Preferably, a pair of conductive layers forming the capacitor each have an opening. The opening and the display element are provided to overlap each other. A light-blocking layer is provided between a substrate on the display surface side and the pair of conductive layers forming the capacitor.
G06F 1/16 - Constructional details or arrangements
G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
G06F 3/044 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
G06F 3/045 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using resistive elements, e.g. a single continuous surface or two parallel surfaces put in contact
G06F 3/0488 - Interaction techniques based on graphical user interfaces [GUI] using specific features provided by the input device, e.g. functions controlled by the rotation of a mouse with dual sensing arrangements, or of the nature of the input device, e.g. tap gestures based on pressure sensed by a digitiser using a touch-screen or digitiser, e.g. input of commands through traced gestures
G06F 15/02 - Digital computers in generalData processing equipment in general manually operated with input through keyboard and computation using a built-in program, e.g. pocket calculators
Organometallic Compound For Protective Layer, Protective Layer, Method For Processing Organic Semiconductor Layer, and Method for Manufacturing Organic Semiconductor Device
The heat resistance of an organic semiconductor device including a step of forming an aluminum oxide film over and in contact with an organic semiconductor layer is improved. A heating step is performed after a layer containing an organometallic compound for a mask for an organic semiconductor layer, which is represented by General Formula (G1) below, is provided over the organic semiconductor layer.
The heat resistance of an organic semiconductor device including a step of forming an aluminum oxide film over and in contact with an organic semiconductor layer is improved. A heating step is performed after a layer containing an organometallic compound for a mask for an organic semiconductor layer, which is represented by General Formula (G1) below, is provided over the organic semiconductor layer.
The heat resistance of an organic semiconductor device including a step of forming an aluminum oxide film over and in contact with an organic semiconductor layer is improved. A heating step is performed after a layer containing an organometallic compound for a mask for an organic semiconductor layer, which is represented by General Formula (G1) below, is provided over the organic semiconductor layer.
In General Formula (G1), Ar represents a substituted or unsubstituted aryl group having 6 to 30 carbon atoms or a substituted or unsubstituted heteroaryl group having 1 to 30 carbon atoms, X represents oxygen or sulfur, M represents a metal, n represents an integer greater than or equal to 1 and less than or equal to 5, and n is the same as the valence of the metal M. Note that when n is greater than or equal to 2, a plurality of Ars may be the same or different and Xs may be the same or different. When Ar represents the substituted or unsubstituted heteroaryl group having 1 to 30 carbon atoms, a heteroatom of the heteroaryl group may be coordinated to the metal M.
A semiconductor device that can be miniaturized or highly integrated is provided. A storage device includes a first transistor, a second transistor, a first capacitor, and a second capacitor. The first capacitor includes a first electrode and a second electrode. The second capacitor includes the first electrode and a third electrode. One of a source and a drain of the first transistor is electrically connected to the second electrode; one of a source and a drain of the second transistor is electrically connected to the third electrode; and the first electrode includes a portion overlapping with each of the second electrode, the third electrode, the first transistor, and the second transistor and is supplied with a fixed potential or a ground potential.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10D 1/68 - Capacitors having no potential barriers
A novel organometallic complex that improves emission efficiency of a light-emitting device is provided. The organometallic complex represented by General Formula (G1) is provided. In the formula, X represents carbon or nitrogen, and the carbon is bonded to any one of hydrogen (including deuterium), a substituted or unsubstituted alkyl group, a substituted or unsubstituted cycloalkyl group, and a substituted or unsubstituted aryl group. Furthermore, R1 to R3 each independently represent any one of hydrogen (including deuterium), a substituted or unsubstituted alkyl group, a substituted or unsubstituted cycloalkyl group, and a substituted or unsubstituted aryl group. Furthermore, n represents an integer greater than or equal to 1 and less than or equal to 4. The borate ligands may be the same or different from each other. Furthermore, n's may be the same or different from each other. In the case where n is 2 or more, X's, R1's, and R2's may be the same or different from each other. In the case where n is 2 or less, R3's may be the same or different from each other.
A novel organometallic complex that improves emission efficiency of a light-emitting device is provided. The organometallic complex represented by General Formula (G1) is provided. In the formula, X represents carbon or nitrogen, and the carbon is bonded to any one of hydrogen (including deuterium), a substituted or unsubstituted alkyl group, a substituted or unsubstituted cycloalkyl group, and a substituted or unsubstituted aryl group. Furthermore, R1 to R3 each independently represent any one of hydrogen (including deuterium), a substituted or unsubstituted alkyl group, a substituted or unsubstituted cycloalkyl group, and a substituted or unsubstituted aryl group. Furthermore, n represents an integer greater than or equal to 1 and less than or equal to 4. The borate ligands may be the same or different from each other. Furthermore, n's may be the same or different from each other. In the case where n is 2 or more, X's, R1's, and R2's may be the same or different from each other. In the case where n is 2 or less, R3's may be the same or different from each other.
A semiconductor device with large memory capacity, a semiconductor device which can be miniaturized or highly integrated, a highly reliable semiconductor device, a semiconductor device with low power consumption, or a semiconductor device with high operating speed is provided. A first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer are provided over a first conductive layer in this order and each include an opening portion reaching the first conductive layer. In the opening portion of the second conductive layer, a third insulating layer, a first charge-accumulation layer, a fourth insulating layer, an oxide semiconductor layer, a fifth insulating layer, a second charge-accumulation layer, a sixth insulating layer, and a fourth conductive layer are provided in this order from a sidewall of the opening portion. The first conductive layer and the third conductive layer function as a source electrode or a drain electrode of a transistor. The fourth conductive layer functions as a first control gate. The second conductive layer functions as a second control gate.
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
A long-lifetime light-emitting device is provided. The light-emitting apparatus includes a first light-emitting device and a first color conversion layer. The first color conversion layer contains a first substance. An EL layer of the first light-emitting device includes a first layer, a second layer, a third layer, a light-emitting layer, and a fourth layer in this order from the anode side. The first layer contains a first organic compound and a second organic compound. The second layer contains a third organic compound. The third layer contains a fourth organic compound. The light-emitting layer contains a fifth organic compound and a sixth organic compound. The fourth layer contains a seventh organic compound. The first organic compound is an organic compound having an electron accepting property to the second organic compound. The fifth organic compound is an emission center substance. The HOMO level of the second organic compound is higher than or equal to −5.7 eV and lower than or equal to −5.4 eV.
A display device that has high display quality is provided. A highly reliable display device is provided. A display device with low power consumption is provided. A light-emitting element is electrically connected to one of a source and a drain of a first transistor. The other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of a second transistor. A gate electrode of the second transistor is electrically connected to one of a source and a drain of a third transistor. A semiconductor layer of the second transistor and a semiconductor layer of the third transistor each include indium, zinc and a third metal. The ratio of the number of indium atoms to the total number of the indium atoms, zinc atoms, and atoms of the third metal in the semiconductor layer of the second transistor is higher than or equal to 30 atomic % and lower than or equal to 100 atomic %. The second transistor has a function of controlling the amount of light emission of the light-emitting element.
G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
H10K 59/121 - Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
An imaging device which has a stacked-layer structure and can be manufactured easily is provided. The imaging device includes a signal processing circuit, a memory device, and an image sensor. The imaging device has a stacked-layer structure in which the memory device is provided above the signal processing circuit, and the image sensor is provided above the memory device. The signal processing circuit includes a transistor formed on a first semiconductor substrate, the memory device includes a transistor including a metal oxide in a channel formation region, and the image sensor includes a transistor formed on a second semiconductor substrate.
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
H10D 87/00 - Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
A display device includes a first region and a second region adjacent to the first region. A display element included in the first region has a function of reflecting visible light and a function of emitting visible light. A display element included in the second region has a function of emitting visible light. In an electronic device including the display device, the first region is located on a first surface (e.g., top surface) on which a main image is displayed, and the second region is located on a second surface (e.g., side surface) on which an auxiliary image is displayed.
G02F 1/1347 - Arrangement of liquid crystal layers or cells in which the final condition of one light beam is achieved by the addition of the effects of two or more layers or cells
G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G09G 3/00 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
H10F 55/10 - Radiation-sensitive semiconductor devices covered by groups , or being structurally associated with electric light sources and electrically or optically coupled thereto wherein the radiation-sensitive semiconductor devices control the electric light source, e.g. image converters, image amplifiers or image storage devices
It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
H10D 62/80 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 64/62 - Electrodes ohmically coupled to a semiconductor
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10K 59/121 - Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
H10K 59/123 - Connection of the pixel electrodes to the thin film transistors [TFT]
An imaging device capable of image processing is provided. The imaging device can retain analog data (image data) obtained by an image-capturing operation in a pixel and perform a product-sum operation of the analog data and a predetermined weight coefficient in the pixel to convert the data into binary data. When the binary data is taken in a neural network or the like, processing such as image recognition can be performed. Since enormous volumes of image data can be retained in pixels in the state of analog data, processing can be performed efficiently.
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
H04N 25/40 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
H04N 25/766 - Addressed sensors, e.g. MOS or CMOS sensors comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power
H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
An object is to provide a semiconductor device with large memory capacity. The semiconductor device includes first to seventh insulators, a first conductor, and a first semiconductor. The first conductor is positioned on a first top surface of the first insulator and a first bottom surface of the second insulator. The third insulator is positioned in a region including a side surface and a second top surface of the first insulator, a side surface of the first conductor, and a second bottom surface and a side surface of the second insulator. The fourth insulator, the fifth insulator, and the first semiconductor are sequentially stacked on the third insulator. The sixth insulator is in contact with the fifth insulator in a region overlapping the first conductor. The seventh insulator is positioned in a region including the first semiconductor and the sixth insulator.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
An object is to provide a light-emitting display device in which a pixel including a thin film transistor using an oxide semiconductor has a high aperture ratio. The light-emitting display device includes a plurality of pixels each including a thin film transistor and a light-emitting element. The pixel is electrically connected to a first wiring functioning as a scan line. The thin film transistor includes an oxide semiconductor layer over the first wiring with a gate insulating film therebetween. The oxide semiconductor layer is extended beyond the edge of a region where the first wiring is provided. The light-emitting element and the oxide semiconductor layer overlap with each other.
H10H 20/817 - Bodies characterised by the crystal structures or orientations, e.g. polycrystalline, amorphous or porous
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
51.
Display Device and Electronic Device Including the Display Device
The display device includes a first substrate provided with a driver circuit region that is located outside and adjacent to a pixel region and includes at least one second transistor which supplies a signal to the first transistor in each of the pixels in the pixel region, a second substrate facing the first substrate, a liquid crystal layer between the first substrate and the second substrate, a first interlayer insulating film including an inorganic insulating material over the first transistor and the second transistor, a second interlayer insulating film including an organic insulating material over the first interlayer insulating film, and a third interlayer insulating film including an inorganic insulating material over the second interlayer insulating film. The third interlayer insulating film is provided in part of an upper region of the pixel region, and has an edge portion on an inner side than the driver circuit region.
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
52.
DISPLAY UNIT, DISPLAY MODULE, AND ELECTRONIC DEVICE
An object is to provide a highly reliable display unit having a function of sensing light. The display unit includes a light-receiving device and a light-emitting device. The light-receiving device includes an active layer between a pair of electrodes. The light-emitting device includes a hole-injection layer, a light-emitting layer, and an electron-transport layer between a pair of electrodes. The light-receiving device and the light-emitting device share one of the electrodes, and may further share another common layer between the pair of electrodes. The hole-injection layer is in contact with an anode and contains a first compound and a second compound. The electron-transport property of the electron-transport layer is low; hence, the light-emitting layer is less likely to have excess electrons. Here, the first compound is the material having a property of accepting electrons from the second compound.
H10K 65/00 - Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element and at least one organic radiation-sensitive element, e.g. organic opto-couplers
An e-book reader in which destruction of a driver circuit at the time when a flexible panel is handled is inhibited. In addition, an e-book reader having a simplified structure. A plurality of flexible display panels each including a display portion in which display control is performed by a scan line driver circuit and a signal line driver circuit, and a binding portion fastening the plurality of display panels together are included. The signal line driver circuit is provided inside the binding portion, and the scan line driver circuit is provided at the edge of the display panel in a direction perpendicular to the binding portion.
G06F 3/147 - Digital output to display device using display panels
G09G 3/00 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G09G 3/3225 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
G09G 5/00 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
The display device includes: a flexible display panel including a display portion in which scanning lines and signal lines cross each other; a supporting portion for supporting an end portion of the flexible display panel; a signal line driver circuit for outputting a signal to the signal line, which is provided for the supporting portion; and a scanning line driver circuit for outputting a signal to the scanning line, which is provided for a flexible surface of the display panel in a direction which is perpendicular or substantially perpendicular to the supporting portion.
G02F 1/1345 - Conductors connecting electrodes to cell terminals
G02F 1/167 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect by electrophoresis
G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G09G 3/3208 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
G09G 5/00 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.
H03K 19/17728 - Reconfigurable logic blocks, e.g. lookup tables
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
H03K 19/17758 - Structural details of configuration resources for speeding up configuration or reconfiguration
H03K 19/17772 - Structural details of configuration resources for powering on or off
A semiconductor device that can be highly integrated is provided.
A semiconductor device that can be highly integrated is provided.
The semiconductor device includes a semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, and a first conductive layer. The third insulating layer is positioned over the semiconductor layer and includes a first opening over the semiconductor layer. The first conductive layer is positioned over the semiconductor layer, the first insulating layer is positioned between the first conductive layer and the semiconductor layer, and the second insulating layer is provided in a position that is in contact with a side surface of the first opening, the semiconductor layer, and the first insulating layer. The semiconductor layer includes a first portion overlapping with the first insulating layer, a pair of second portions between which the first portion is sandwiched and which overlap with the second insulating layer, and a pair of third portions between which the first portion and the pair of second portions are sandwiched and which overlap with neither the first insulating layer nor the second insulating layer. The first portion has a smaller width than the first opening and has a thinner shape of the semiconductor layer than the second portions, and the second portions have a thinner shape of the semiconductor layer than the third portions.
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
The present invention provides a highly reliable display device. The present invention provides a display device in which photodegradation of transistors is suppressed. The display device includes a first transistor that is a vertical transistor, a second transistor that is a top-gate transistor, a first insulating layer, and a first conductive layer. The first transistor has a top electrode and a bottom electrode. The top electrode and the second transistor are located on the first insulating layer. The first conductive layer has a region below the first insulating layer and overlapping the second transistor. The first conductive layer and the bottom electrode are located on the same surface, and contain the same material.
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
Provided is an accounting business assist method using a language model. The accounting business assist method includes a first process for extracting an electronic mail related to an order, and a second process for extracting information from the electronic mail related to the order. The first process and the second process are executed by using the language model. The accounting business assist method also includes a process for narrowing down electronic mails by using a search expression before the first process, and a process for registering, in a database, the information extracted in the second process.
The present invention provides a semiconductor device having a transistor of very small size. The present invention has a transistor, a first insulation layer, and a second insulation layer. The transistor has a semiconductor layer, a first electroconductive layer, and a second electroconductive layer. The first electroconductive layer and the first insulation layer are provided such that the heights of the respective upper surfaces thereof are substantially the same. The second insulation layer is provided on the first electroconductive layer and the first insulation layer. The second electroconductive layer is provided on the second insulation layer. The second electroconductive layer and the second insulation layer each have an opening reaching the first electroconductive layer. The semiconductor layer is provided in contact with the upper surface of the first electroconductive layer, the side surface of the second insulation layer, and the side surface of the second electroconductive layer within each of the openings.
G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A semiconductor device including a miniaturized transistor is provided. The semiconductor device includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer. The first insulating layer is provided over the first conductive layer. The first insulating layer has a first opening reaching the first conductive layer. The semiconductor layer is in contact with a top surface and a side surface of the first insulating layer and a top surface of the first conductive layer. The second conductive layer is provided over the semiconductor layer. The second conductive layer includes a second opening in a region overlapping with the first opening. The second insulating layer is provided over the semiconductor layer and the second conductive layer. The third conductive layer is provided over the second insulating layer. The first insulating layer has a stacked-layer structure of a third insulating layer and a fourth insulating layer over the third insulating layer. The fourth insulating layer includes a region having a film density higher than that of the third insulating layer.
A highly reliable memory device is provided. Of an information bit and a check bit forming a hamming code, the information bit having a larger bit length than the check bit is stored in a first memory portion, and the check bit is stored in the second memory portion. The hamming code is divided and stored in a plurality of memory portions, whereby occurrence of a soft error is suppressed. The first memory portion that needs a large memory capacity is formed using a Si transistor, and the second memory portion is formed using an OS transistor. A combination of memory scribing and bit interleaving achieves a highly reliable memory device.
A semiconductor device having high memory density is provided. The semiconductor device includes a first insulator, a first layer, a second insulator, a second layer, a third insulator, and a third layer, which are stacked in this order. Each of the first layer and the third layer includes a first and a second transistor and a first conductor. The second layer includes a second conductor. In the first transistor in each of the first and the third layer, a source and a drain are positioned on a semiconductor layer and a gate is positioned over the semiconductor layer. In the second transistor in each of the first and the third layer, a source and a drain are positioned on a semiconductor layer and a gate is positioned over the semiconductor layer. In each of the first and the third layer, the first conductor electrically connects a region on the source or the drain of the first transistor and a region on the gate of the second transistor. The first conductor and the second conductor in the first layer, and the semiconductor layer of the first transistor in the third layer overlap with each other.
A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a memory cell including first to third transistors and a capacitor. The second and third transistors share a metal oxide. The capacitor is provided between the first and second transistors. An insulator is provided over an electrode functioning as a source or a drain of the first transistor, and the insulator has an opening reaching the electrode. The capacitor is provided in the opening. One electrode of the capacitor includes, in the opening, a region in contact with the other of the source electrode and the drain electrode of the first transistor. The one electrode of the capacitor includes a region in contact with a gate electrode of the second transistor.
A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first memory cell, a second memory cell over the first memory cell, a first conductor, and a second conductor over the first conductor. The first memory cell and the second memory cell each include a transistor and a capacitor. One of a source and a drain of the transistor is electrically connected to a lower electrode of the capacitor. The first conductor includes a portion in contact with the other of the source and the drain of the transistor included in the first memory cell. A top surface of the first conductor includes a portion in contact with a bottom surface of the second conductor. The second conductor includes a portion in contact with the other of the source and the drain of the transistor included in the second memory cell.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H10B 12/00 - Dynamic random access memory [DRAM] devices
A novel information processing system that is highly convenient, useful, or reliable is provided. The information processing system includes a first component, a second component, and a third component. The first component has a function of receiving a text written in a natural language and a query for performing retrieval in design assets and transferring the text and the query to the third component, a function of providing a code, and a function of emphasizing a portion related to the code and then providing the design assets. The second component has a function of generating an intermediate code from the text in accordance with a prompt and transferring the intermediate code to the third component. The third component has a function of classifying the text into a predetermined class, generating the prompt, and transferring the prompt to the second component. The third component has a function of generating the code from the command using the received intermediate code as an argument in accordance with the syntax, and transferring the code to the first component.
A light-emitting device with high reliability is provided. The light-emitting device includes a first electrode, a second electrode, and an EL layer. The EL layer is positioned between the first electrode and the second electrode. The EL layer includes a light-emitting layer and an electron-injection layer. The electron-injection layer contains a metal or an oxide of the metal, a first organic compound, and a second organic compound. The first organic compound includes a first π-electron deficient heteroaromatic ring with an electron-donating group. The second organic compound includes a second π-electron deficient heteroaromatic ring. The LUMO level of the second organic compound is lower than that of the first organic compound by 0.20 eV or more.
A display device in which a peripheral circuit portion has high operation stability is provided. The display device includes a first substrate and a second substrate. A first insulating layer is provided over a first surface of the first substrate. A second insulating layer is provided over a first surface of the second substrate. The first surface of the first substrate and the first surface of the second substrate face each other. An adhesive layer is provided between the first insulating layer and the second insulating layer. A protective film in contact with the first substrate, the first insulating layer, the adhesive layer, the second insulating layer, and the second substrate is formed in the vicinity of a peripheral portion of the first substrate and the second substrate.
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
The display defects of a display device are reduced. The display quality of the display device is improved. The display device includes a display panel and a first conductive layer. The display panel includes a display element including a pair of electrodes. An electrode of the pair of electrodes which is closer to one surface of the display panel is supplied with a constant potential. A constant potential is supplied to the first conductive layer. The second conductive layer provided on the other surface of the display panel is in contact with the first conductive layer, whereby the second conductive layer is also supplied with the constant potential. The second conductive layer includes a portion not fixed to the first conductive layer.
G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
G06F 3/044 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
H05B 33/26 - Light sources with substantially two-dimensional radiating surfaces characterised by the composition or arrangement of the conductive material used as an electrode
A novel display panel that is highly convenient, useful, or reliable is provided. The display panel includes a display region, a first support, and a second support, the display region includes a first region, a second region, and a third region, the first region and the second region each have a belt-like shape extending in one direction, and the third region is sandwiched between the first region and the second region. The first support overlaps with the first region and is less likely to be warped than the third region, and the second support overlaps with the second region and is less likely to be warped than the third region. The second support can pivot on an axis extending in the one direction with respect to the first support.
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
G06F 1/16 - Constructional details or arrangements
H05K 5/00 - Casings, cabinets or drawers for electric apparatus
H05K 5/02 - Casings, cabinets or drawers for electric apparatus Details
A touch panel capable of performing display and sensing along a curved surface or a touch panel that maintains high detection sensitivity even when it is curved along a curved surface is provided. A flexible display panel is placed along a curved portion included in a surface of a support. A first film layer is attached along a surface of the display panel by a bonding layer. Second to n-th film layers (n is an integer of 2 or more) are sequentially attached along a surface of the first film layer by bonding layers. A flexible touch sensor is attached along a surface of the n-th film layer by a bonding layer.
A transistor with small parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A semiconductor device including the transistor can be provided. Provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. The oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor.
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
A high-resolution display device is provided. The display device includes a plurality of light-emitting units emitting light of different colors. The light-emitting unit has a microcavity structure and intensifies light with a specific wavelength. In the light-emitting units emitting light of different colors, reflective layers with different thicknesses are formed, an insulating layer is formed to cover the reflective layers, and then a top surface of the insulating layer is subjected to planarization treatment, whereby an insulating layer with different thicknesses is formed. After that, light-emitting elements emitting white light are formed over the planarized top surface of the insulating layer to overlap with the respective reflective layers, whereby the light-emitting units that intensify different colors due to different optical path lengths are separately formed.
An electronic device that enables smooth communication is provided. The electronic device includes a display portion including a first camera; a second camera; and an image processing portion. The second camera is positioned in a region not overlapping with the display portion. The first camera has a function of generating a first image of a subject, and the second camera has a function of generating a second image of the subject. The image processing portion includes a generator that performs learning using training data. The training data includes an image including a person's face. The image processing portion has a function of making the first image clear when the first image is input to the generator and a function of tracking the gaze of the subject on the basis of the second image.
An object is to stabilize electric characteristics of a semiconductor device including an oxide semiconductor to increase reliability. The semiconductor device includes an insulating film; a first metal oxide film on and in contact with the insulating film; an oxide semiconductor film partly in contact with the first metal oxide film; source and drain electrodes electrically connected to the oxide semiconductor film; a second metal oxide film partly in contact with the oxide semiconductor film; a gate insulating film on and in contact with the second metal oxide film; and a gate electrode over the gate insulating film.
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
75.
DISPLAY DEVICE AND MANUFACTURING METHOD OF DISPLAY DEVICE
A circuit capable of high-speed operation and a pixel are integrally formed over the same substrate. A first metal oxide film, a first metal film, and an island-shaped first resist mask are formed over a first insulating layer. An island-shaped first metal layer and an island-shaped first oxide semiconductor layer are formed and a part of a top surface of the first insulating layer is exposed; then, the first resist mask is removed. A second metal oxide film, a second metal film, and an island-shaped second resist mask are formed over the first metal layer and the first insulating layer. An island-shaped second metal layer and an island-shaped second oxide semiconductor layer are formed; then, the second resist mask is removed. The first metal layer and the second metal layer are removed.
One embodiment of the present invention provides a highly reliably display device in which a high mobility is achieved in an oxide semiconductor. A first oxide component is formed over a base component. Crystal growth proceeds from a surface toward an inside of the first oxide component by a first heat treatment, so that a first oxide crystal component is formed in contact with at least part of the base component. A second oxide component is formed over the first oxide crystal component. Crystal growth is performed by a second heat treatment using the first oxide crystal component as a seed, so that a second oxide crystal component is formed. Thus, a stacked oxide material is formed. A transistor with a high mobility is formed using the stacked oxide material and a driver circuit is formed using the transistor.
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
G09G 3/3266 - Details of drivers for scan electrodes
G09G 3/3275 - Details of drivers for data electrodes
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 99/00 - Subject matter not provided for in other groups of this subclass
77.
SPUTTERING TARGET, METHOD FOR MANUFACTURING SPUTTERING TARGET, AND METHOD FOR FORMING THIN FILM
There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.
B28B 11/24 - Apparatus or processes for treating or working the shaped articles for curing, setting or hardening
C04B 35/453 - Shaped ceramic products characterised by their compositionCeramic compositionsProcessing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxides based on zinc, tin or bismuth oxides or solid solutions thereof with other oxides, e.g. zincates, stannates or bismuthates
A novel organic compound is provided. That is, a novel organic compound that is effective in improving reliability of a light-emitting element is provided. The organic compound includes a condensed ring including a pyrimidine ring and is represented by General Formula (G1). In General Formula (G1), A represents a group having 6 to 100 carbon atoms and includes at least one of an aromatic ring and a heteroaromatic ring. The aromatic ring and the heteroaromatic ring may each include a substituent. Furthermore, Q represents oxygen or sulfur. A ring X represents a substituted or unsubstituted naphthalene ring or a substituted or unsubstituted phenanthrene ring.
H10K 85/60 - Organic compounds having low molecular weight
C07D 491/048 - Ortho-condensed systems with only one oxygen atom as ring hetero atom in the oxygen-containing ring the oxygen-containing ring being five-membered
H10K 50/11 - OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
A display device with a narrow bezel is provided. The display device includes a pixel circuit and a driver circuit which are provided on the same plane. The driver circuit includes a selection circuit and a buffer circuit. The selection circuit includes a first transistor. The buffer circuit includes a second transistor. The first transistor has a region overlapping with the second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. One of a source and a drain of the second transistor is electrically connected to the pixel circuit.
H10K 59/122 - Pixel-defining structures or layers, e.g. banks
G02F 1/133 - Constructional arrangementsOperation of liquid crystal cellsCircuit arrangements
G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G09G 3/3225 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
G09G 3/3258 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
H10K 10/84 - Ohmic electrodes, e.g. source or drain electrodes
H10K 50/115 - OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers comprising active inorganic nanostructures, e.g. luminescent quantum dots
H10K 50/814 - Anodes combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
H10K 59/121 - Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
H10K 59/128 - Active-matrix OLED [AMOLED] displays comprising two independent displays, e.g. for emitting information from two major sides of the display
H10K 71/20 - Changing the shape of the active layer in the devices, e.g. patterning
This invention provides a sentence generation system having a novel configuration. A processing unit acquires parallel sentence data by transmitting, to a first language model via a network, a first instruction sentence for selecting a sentence in which a plurality of events are described in parallel from first target data, using input data as the first target data. A third instruction sentence is acquired by transmitting, to the first language model via the network, a second instruction sentence for generating an instruction sentence in which the parallel sentence data is expressed as an expression including a feature related to second target data, using the parallel sentence data as the second target data. Sentence data related to the parallel sentence data is acquired by transmitting, to the first language model via the network, a third instruction sentence for generating a sentence based on third target data, using the input data and the parallel sentence data as the third target data. The output unit outputs output data in which the sentence data is appended to the input data.
Provided is a semiconductor device that occupies little area. The semiconductor device has a horizontal transistor and a vertical transistor combined therein. A CMOS semiconductor device is achieved as a result of a p-channel transistor being constituted by the horizontal transistor and an n-channel transistor being constituted by the vertical transistor. An insulating layer is provided on a gate electrode of the horizontal transistor, and a lower electrode of the vertical transistor is provided on the insulating layer. Silicon is used for a semiconductor layer of the horizontal transistor, and a metal oxide is used for a semiconductor layer of the vertical transistor.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
To provide a positive electrode active material in which a phase transition is inhibited and a secondary battery including the positive electrode active material. An unprecedented synthesis method has been developed in which lithium cobalt oxide particles are treated with a molten salt of MgF2—LiF as a reaction accelerator to facilitate the diffusion and doping of magnesium into lithium cobalt oxide bulk and to form a stable coating layer in the particle surface portion. Ex situ XRD analysis confirms the inhibition of the harmful phase transition and the emergence of a novel phase as the modified LiCoO2 is charged up to 4.7 V. The modified LiCoO2 shows high electrochemical performance during high-voltage operation. This technology provides a guideline for suppressing fundamental degradation associated with phase transition and achieving ultra-high energy density LiCoO2 positive electrodes.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01M 4/02 - Electrodes composed of, or comprising, active material
H01M 4/36 - Selection of substances as active materials, active masses, active liquids
A novel oscillator, an amplifier circuit, an inverter circuit, an amplifier circuit, a battery control circuit, a battery protection circuit, a power storage device, a semiconductor device, an electric device, and the like are provided. The semiconductor device includes an oscillator including a first transistor containing a metal oxide, and a second transistor to a fifth transistor, in which a first potential is supplied to a gate of the second transistor and a gate of the third transistor when the first transistor is turned on, and the first potential is held when the first transistor is turned off. The oscillator supplies a first signal based on the first potential to a first circuit. The first circuit performs at least one of shaping and amplification on the first signal. The second transistor and the fourth transistor are connected in series, and the third transistor and the fifth transistor are connected in series. A source or a drain of the third transistor is electrically connected to a gate of the fourth transistor, and a source or a drain of the fourth transistor is electrically connected to the gate of the third transistor.
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H02H 7/18 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for batteriesEmergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for accumulators
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
A power storage device with high output is provided, in which the specific surface area is increased while keeping the easy-to-handle particle size of its active material. The power storage device includes a positive electrode including a positive electrode current collector and a positive electrode active material layer, a negative electrode including a negative electrode current collector and a negative electrode active material layer, and an electrolyte. The negative electrode active material layer includes a negative electrode active material which is a particle in which a plurality of slices of graphite is overlapped with each other with a gap therebetween. It is preferable that the grain diameter of the particle be 1 μm to 50 μm. Further, it is preferable that the electrolyte be in contact with the gap between the slices of graphite.
H01B 1/04 - Conductors or conductive bodies characterised by the conductive materialsSelection of materials as conductors mainly consisting of carbon-silicon compounds, carbon, or silicon
A display device including a pixel having a memory. The pixel includes at least a display element, a capacitor, an inverter, and a switch. The switch is controlled with a signal held in the capacitor and a signal output from the inverter so that voltage is supplied to the display element. The inverter and the switch can be constituted by transistors with the same polarity. A semiconductor layer included in the pixel may be formed using a light-transmitting material. Moreover, a gate electrode, a drain electrode, and a capacitor electrode may be formed using a light-transmitting conductive layer. The pixel is formed using a light-transmitting material in such a manner, whereby the display device can be a transmissive display device while including a pixel having a memory.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
G11C 19/00 - Digital stores in which the information is moved stepwise, e.g. shift registers
H03B 1/00 - GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNERGENERATION OF NOISE BY SUCH CIRCUITS Details
H03K 3/00 - Circuits for generating electric pulsesMonostable, bistable or multistable circuits
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
87.
LIQUID CRYSTAL DISPLAY DEVICE AND SEMICONDUCTOR DEVICE
By increasing an interval between electrodes which drives liquid crystals, a gradient of an electric field applied between the electrodes can be controlled and an optimal electric field can be applied between the electrodes. The invention includes a first electrode formed over a substrate, an insulating film formed over the substrate and the first electrode, a thin film transistor including a semiconductor film in which a source, a channel region, and a drain are formed over the insulating film, a second electrode located over the semiconductor film and the first electrode and including first opening patterns, and liquid crystals provided over the second electrode.
An object is to provide a display device with excellent display characteristics, where a pixel circuit and a driver circuit provided over one substrate are formed using transistors which have different structures corresponding to characteristics of the respective circuits. The driver circuit portion includes a driver circuit transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using a metal film, and a channel layer is formed using an oxide semiconductor. The pixel portion includes a pixel transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using an oxide conductor, and a semiconductor layer is formed using an oxide semiconductor. The pixel transistor is formed using a light-transmitting material, and thus, a display device with higher aperture ratio can be manufactured.
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
H10D 99/00 - Subject matter not provided for in other groups of this subclass
89.
Display System, Display Device, and Light-Emitting Apparatus
A highly convenient display system is provided. A display system that enables a screen to be operated easily with a laser pointer is provided. A display system that enables a screen to be operated by a large number of people is provided. The display system includes a light-emitting apparatus and a display device. The light-emitting apparatus includes a means for emitting visible laser light and a means for emitting invisible light. The display device includes a display unit including a means for displaying an image and a means for obtaining positional information on a portion irradiated with the visible light, and a means for receiving the invisible light. The display system has a function of performing processing in accordance with the positional information when the invisible light is received.
G06F 3/0354 - Pointing devices displaced or positioned by the userAccessories therefor with detection of 2D relative movements between the device, or an operating part thereof, and a plane or surface, e.g. 2D mice, trackballs, pens or pucks
G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
H10K 65/00 - Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element and at least one organic radiation-sensitive element, e.g. organic opto-couplers
The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.
H10B 12/00 - Dynamic random access memory [DRAM] devices
G11C 5/10 - Arrangements for interconnecting storage elements electrically, e.g. by wiring for interconnecting capacitors
G11C 11/401 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
Provided are a learning method for an organic compound design model, in which a large language model is used, and an organic compound design system. The present invention comprises: a step for generating, through use of a first large language model, a first organic compound group by using a user sentence; a step for calculating a physical property value of a first organic compound of the first organic compound group by scientific calculation; a step for evaluating a demand achievement degree from a correlation between the user sentence, the molecular structure of the first organic compound, and the physical property value through use of a second large-scale language model; a step for generating training data in which the user sentence, the molecular structure of the first organic compound, and the demand achievement degree are combined; a step for constructing a reward model by using the training data; a step for creating a pseudo user sentence; a step for generating, through use of the first large language model, a second organic compound group by using the pseudo user sentence; a step for generating pseudo reward data by evaluating the molecular structure of a second organic compound of the second organic compound group through use of the reward model; and a step for updating a parameter of the first large language model by using the pseudo reward data.
Provided is a molecular structure generation method in which a large language model is used and which exhibits high versatility and excellent precision. Provided is a molecular structure generation method comprising: a step for inputting a first instruction sentence in which a compound, which serves as a base, and a requirement for characteristics are combined with molecular structure information of a compound corresponding to the compound and a natural sentence; a step for separating a part of the molecular structure information of the compound and a part of the requirement for the characteristics; a step for generating a plurality of similar compounds on the basis of the molecular structure information of the compound which serves as a base; a step for extracting information regarding the characteristics from the requirement for the characteristics; and a step for inputting a second instruction sentence for a large language model. To the second instruction sentence, at least the information regarding the characteristics and, as an example of the molecular, the plurality of similar compounds are inputted.
Provided is a novel positive electrode active material. Also provided is a battery with excellent charge and discharge characteristics. This battery has a positive electrode. The positive electrode has a positive electrode active material layer. The positive electrode active material layer has positive electrode active material particles containing magnesium, titanium, nickel, aluminum, and lithium cobalt oxide. XPS analysis of the plurality of positive electrode active material particles in the positive electrode active material layer shows a peak in the range from 850 eV to 860 eV inclusive and at a position at least 0.5 eV higher than the peak position in XPS analysis of nickel(II) oxide.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01M 4/38 - Selection of substances as active materials, active masses, active liquids of elements or alloys
Provided is an optical device that is compact, lightweight, and achieves high light use efficiency. This optical device has: a catadioptric system that achieves high light use efficiency and causes image formation positions on two optical paths to coincide with each other; and a singlet lens that has the function of optical correction or the like and is between a non-polarized light source and the catadioptric system. A resin lens is disposed in an optical path using non-polarized light, and a glass lens that does not substantially generate birefringence is disposed in an optical path using polarized light. Thus, the partial unpolarization of polarized light can be prevented, and an optical device that is lightweight and achieves high light use efficiency with little stray light can be provided.
G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
One aspect of the present invention provides a charging control system that is capable of effectively using regenerative electric power without wasting the regenerative electric power. Generated regenerative electric power is efficiently stored in a second secondary battery and then stored in a main first secondary battery. Charging from the second secondary battery to the first secondary battery is performed via a DC-DC converter. The charge state of the first secondary battery and the charge state of the second secondary battery are controlled. When the first secondary battery is close to full charge and is likely to deteriorate, it is possible to perform charging from the first secondary battery to the second secondary battery.
B60L 53/20 - Methods of charging batteries, specially adapted for electric vehiclesCharging stations or on-board charging equipment thereforExchange of energy storage elements in electric vehicles characterised by converters located in the vehicle
B60L 58/18 - Methods or circuit arrangements for monitoring or controlling batteries or fuel cells, specially adapted for electric vehicles for monitoring or controlling batteries of two or more battery modules
H01G 11/08 - Structural combinations, e.g. assembly or connection, of hybrid or EDL capacitors with other electric components, at least one hybrid or EDL capacitor being the main component
H01M 4/38 - Selection of substances as active materials, active masses, active liquids of elements or alloys
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01M 10/0525 - Rocking-chair batteries, i.e. batteries with lithium insertion or intercalation in both electrodesLithium-ion batteries
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
96.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a semiconductor device having a high operating speed. In this invention, a second insulator is formed on top of a first insulator, and raised sections are formed in the second insulator. An oxide semiconductor film is deposited to cover the second insulator, and oxide semiconductors in contact with the lateral surfaces of the raised sections are formed by anisotropic etching. A third insulator is deposited to cover the second insulator and the oxide semiconductor film, and CMP is performed to planarize the top surface of the third insulator. The second and third insulators are etched to form a fourth insulator in contact with the bottom surface of the oxide semiconductors. A first conductor is formed to cover the oxide semiconductors and the fourth insulator, and a fifth insulator with an opening is formed on top of the first conductor. The first conductor is processed to form second and third conductors facing each other across the opening. A sixth insulator and a fourth conductor are formed inside the opening.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A scan line to which a selection signal or a non-selection signal is input from its end, and a transistor in which a clock signal is input to a gate, the non-selection signal is input to a source, and a drain is connected to the scan line are provided. A signal input to the end of the scan line is switched from the selection signal to the non-selection signal at the same or substantially the same time as the transistor is turned on. The non-selection signal is input not only from one end but also from both ends of the scan line. This makes it possible to inhibit the potentials of portions in the scan line from being changed at different times.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided.
A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided.
The semiconductor device includes a semiconductor layer, a first insulating layer, and a first conductive layer. The first insulating layer is provided over the semiconductor layer. The first conductive layer is provided over the first insulating layer. The semiconductor layer includes a first region that overlaps with the first conductive layer and the first insulating layer, a second region that does not overlap with the first conductive layer and overlaps with the first insulating layer, and a third region that overlaps with neither the first conductive layer nor the first insulating layer. The semiconductor layer contains a metal oxide. The second region and the third region contain a first element. The first element is one or more elements selected from boron, phosphorus, aluminum, and magnesium. The first element exists in a state of being bonded to oxygen.
An electronic device of a novel embodiment, specifically an arm-worn electronic device used while being worn on an arm, is provided. An arm-worn secondary battery used while being worn on an arm is provided. An electronic device is provided, which includes a structure body having a curved surface as a support structure body, a flexible secondary battery including a film as an exterior body over the curved surface of the support structure body, and a display portion including a plurality of display elements between a pair of films over the secondary battery. The plurality of display elements and the secondary battery overlap with each other at least partly. It is possible to provide an electronic device which has a small maximum thickness of 1 cm or less and a light weight of 50 g or less even when an arm-worn secondary battery is provided with a display portion
A memory device having an error detection function and being capable of storing a large amount of data per unit area is provided. A driver circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers each of which includes a memory cell using the thin film transistor can be stacked over the semiconductor substrate, so that the amount of data that can be stored per unit area can be increased. Part of a peripheral circuit including the memory device can be formed using a thin film transistor, and thus, an error detection circuit is formed using the thin film transistor and stacked over the semiconductor substrate.
