An electronic device having an authentication method with a high security level is provided. The electronic device includes a pixel portion, a sensor portion, an authentication portion, and a housing. The pixel portion includes a display element and a light-receiving element. The pixel portion has a function of turning on the display element. The pixel portion has a function of obtaining authentication information by capturing an image of a target object touching the pixel portion. The sensor portion has a function of detecting attachment or detachment to a living body or an object. The authentication portion has a function of performing authentication processing with the use of the authentication information. The housing includes a first surface and a second surface opposite to the first surface. The pixel portion is positioned on the first surface and the sensor portion is positioned on the second surface.
A semiconductor device including a transistor, a first insulating layer, and a second insulating layer is provided. The transistor includes first to third conductive layers, a semiconductor layer, and a third insulating layer. The first insulating layer positioned above the first conductive layer includes an opening reaching the first conductive layer. The semiconductor layer includes a portion in contact with the top surface of the first conductive layer in the opening, a portion along a side surface and over of the first insulating layer. The third insulating layer covers the semiconductor layer in the opening. The third conductive layer covers the third insulating layer in the opening. The second insulating layer covers the third conductive layer. The second conductive layer includes a portion positioned over the third conductive layer with the second insulating layer therebetween.
A light-emitting device having favorable characteristics is provided. The light-emitting device is a tandem light-emitting device. In the light-emitting device, a first light-emitting layer and a second light-emitting layer include a first light-emitting substance and a second light-emitting substance, respectively. Each of the first and second light-emitting substances is a TADF material. At least one of first and second hole-transport layers includes an organic compound having a π-electron rich heteroaromatic ring and no triarylamine skeleton. A difference between a maximum peak wavelength of an emission spectrum of the first light-emitting substance and a maximum peak wavelength of an emission spectrum of the second light-emitting substance is less than or equal to 30 nm. The first and second light-emitting layers each emit light with a hue different from a hue of light emitted by a light-emitting layer included in at least one of a plurality of adjacent light-emitting devices.
H10K 50/13 - OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers specially adapted for multicolour light emission, e.g. for emitting white light comprising stacked EL layers within one EL unit
A high-definition display device is provided. A small display device is provided. In the display device, a first layer and a second layer are stacked and provided. The first layer includes a gate driver circuit and a source driver circuit, and the second layer includes a display portion. The gate driver circuit and the source driver circuit are provided to include a region overlapping with the display portion. The gate driver circuit and the source driver circuit have an overlap region where they are not strictly separated from each other. Five or more gate driver circuits and five or more source driver circuits can be provided.
G09G 3/3275 - Details of drivers for data electrodes
G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
G09G 3/3266 - Details of drivers for scan electrodes
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
G09G 5/377 - Details of the operation on graphic patterns for mixing or overlaying two or more graphic patterns
H10K 59/127 - Active-matrix OLED [AMOLED] displays comprising two substrates, e.g. display comprising OLED array and TFT driving circuitry on different substrates
5.
Organic Compound And Method For Synthesizing The Same
A 1,10-phenanthroline derivative or a 2,2′-bipyridine derivative having different substituents at symmetrical positions is provided. An organic compound represented by General Formula (G1) or General Formula (G2) below is provided. In General Formula (G1) or (G2) below, any one of X2 to X5 or any one of X6 to X9 represents a halogen or a trifluoromethanesulfonyl group, and the others represent hydrogens. Any one of R2 to R5 or any one of R6 to R9 represents an aliphatic cyclic amino group. Note that a carbon to which the halogen or the trifluoromethanesulfonyl group is bonded and a carbon to which the aliphatic cyclic amino group is bonded are at line-symmetrical positions in a main skeleton (a 1,10-phenanthroline skeleton or a 2,2′-bipyridine skeleton).
A 1,10-phenanthroline derivative or a 2,2′-bipyridine derivative having different substituents at symmetrical positions is provided. An organic compound represented by General Formula (G1) or General Formula (G2) below is provided. In General Formula (G1) or (G2) below, any one of X2 to X5 or any one of X6 to X9 represents a halogen or a trifluoromethanesulfonyl group, and the others represent hydrogens. Any one of R2 to R5 or any one of R6 to R9 represents an aliphatic cyclic amino group. Note that a carbon to which the halogen or the trifluoromethanesulfonyl group is bonded and a carbon to which the aliphatic cyclic amino group is bonded are at line-symmetrical positions in a main skeleton (a 1,10-phenanthroline skeleton or a 2,2′-bipyridine skeleton).
A display device provided with an image capturing function is provided. A display device with both high viewing angle characteristics and high image capturing performance is provided. The display device includes a light-emitting and light-receiving element and a color filter. The light-emitting and light-receiving element includes a light-emitting and light-receiving region having a function of emitting light of the first color and a function of receiving light of the second color. The color filter is positioned over the light-emitting and light-receiving element and has a function of transmitting the light of the first color and a function of blocking the light of the second color. The color filter includes an opening portion. The light-emitting and light-receiving region includes a portion positioned in the inside of the opening portion in the plan view.
An imaging device or a display device that is capable of clearly capturing an image of a fingerprint or the like can be provided. The display device includes a light-receiving element, a light-emitting element, a first substrate, a second substrate, a first resin layer, a second resin layer, and a light-blocking layer. The first resin layer, the second resin layer, and the second substrate are stacked over the first substrate. The light-receiving element and the light-emitting element are positioned between the first substrate and the first resin layer. The light-blocking layer is positioned between the first resin layer and the second resin layer and includes an opening portion overlapping with the light-receiving element. The opening portion in the light-blocking layer is positioned on an inner side of a light-receiving region of the light-receiving element in a plan view, and the width of the opening portion is less than or equal to the width of the light-receiving region. The second substrate is thicker than the first resin layer and the second resin layer. The thickness of a portion of the first resin layer, which overlaps with the light-receiving region of the light-receiving element, is greater than or equal to one time and less than or equal to 10 times as large as the width of the light-receiving region. The second substrate has a higher refractive index than the first resin layer and the second resin layer.
A display device capable of improving image quality is provided. A storage node is provided in each pixel and first data can be held in the storage node. Second data is added to the first data by capacitive coupling, which can be supplied to a display element. Thus, the display device can display a corrected image. A reference potential for the capacitive coupling operation is supplied from a power supply line or the like, and thus the first data and the second data can be supplied from a common signal line.
G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
H10D 62/80 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
H10K 59/121 - Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
H10K 59/131 - Interconnections, e.g. wiring lines or terminals
A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, the first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacitor through the first switch, and the second wiring is electrically connected to the first terminal of the capacitor through the third switch. The first terminal of the capacitor is electrically connected to a first terminal of the second switch, and a second terminal of the capacitor is electrically connected to the first amplifier circuit through the fourth switch. Current corresponding to the result of product-sum operation flows through each of the first and second wirings, and the current is converted into potentials by the first and second circuits. A difference between the converted potentials is held in the capacitor, and the difference is input to the first amplifier circuit and is output as a potential corresponding to the arithmetic operation result.
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G11C 11/54 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using elements simulating biological cells, e.g. neuron
H10B 12/00 - Dynamic random access memory [DRAM] devices
Provided is a light-emitting device having excellent luminous efficiency. Alternatively provided is a light-emitting device having excellent reliability. Alternatively provided is a display device having excellent luminous efficiency and excellent reliability. Provided is a light-emitting device comprising a first electrode, a second electrode, a light-emitting layer positioned between the first electrode and the second electrode, and a cap layer. The second electrode is positioned between the light-emitting layer and the cap layer. The cap layer has at least a first substance and a second substance. The first substance and the second substance are such that the ordinary refractive indexes, at a wavelength of 380-760 nm, of vapor-deposited films composed of the respective substances differ by 0.1 or more. The first substance is an organic compound having a saturated hydrocarbon group and a skeleton that has electron transport properties.
H10K 50/858 - Arrangements for extracting light from the devices comprising refractive means, e.g. lenses
C07D 213/16 - Heterocyclic compounds containing six-membered rings, not condensed with other rings, with one nitrogen atom as the only ring hetero atom and three or more double bonds between ring members or between ring members and non-ring members having three double bonds between ring members or between ring members and non-ring members having no bond between the ring nitrogen atom and a non-ring member or having only hydrogen or carbon atoms directly attached to the ring nitrogen atom containing only hydrogen and carbon atoms in addition to the ring nitrogen atom containing only one pyridine ring
C07D 239/26 - Heterocyclic compounds containing 1,3-diazine or hydrogenated 1,3-diazine rings not condensed with other rings having three or more double bonds between ring members or between ring members and non-ring members with only hydrogen atoms, hydrocarbon or substituted hydrocarbon radicals, directly attached to ring carbon atoms
C07D 241/36 - Heterocyclic compounds containing 1,4-diazine or hydrogenated 1,4-diazine rings condensed with carbocyclic rings or ring systems
C07D 251/14 - Heterocyclic compounds containing 1,3,5-triazine rings not condensed with other rings having three double bonds between ring members or between ring members and non-ring members with hydrogen or carbon atoms directly attached to at least one ring carbon atom
C07D 307/77 - Heterocyclic compounds containing five-membered rings having one oxygen atom as the only ring hetero atom ortho- or peri-condensed with carbocyclic rings or ring systems
C07D 401/10 - Heterocyclic compounds containing two or more hetero rings, having nitrogen atoms as the only ring hetero atoms, at least one ring being a six-membered ring with only one nitrogen atom containing two hetero rings linked by a carbon chain containing aromatic rings
C07D 401/14 - Heterocyclic compounds containing two or more hetero rings, having nitrogen atoms as the only ring hetero atoms, at least one ring being a six-membered ring with only one nitrogen atom containing three or more hetero rings
C07D 403/10 - Heterocyclic compounds containing two or more hetero rings, having nitrogen atoms as the only ring hetero atoms, not provided for by group containing two hetero rings linked by a carbon chain containing aromatic rings
C07D 405/10 - Heterocyclic compounds containing both one or more hetero rings having oxygen atoms as the only ring hetero atoms, and one or more rings having nitrogen as the only ring hetero atom containing two hetero rings linked by a carbon chain containing aromatic rings
C07D 405/14 - Heterocyclic compounds containing both one or more hetero rings having oxygen atoms as the only ring hetero atoms, and one or more rings having nitrogen as the only ring hetero atom containing three or more hetero rings
C07D 409/10 - Heterocyclic compounds containing two or more hetero rings, at least one ring having sulfur atoms as the only ring hetero atoms containing two hetero rings linked by a carbon chain containing aromatic rings
C07D 409/14 - Heterocyclic compounds containing two or more hetero rings, at least one ring having sulfur atoms as the only ring hetero atoms containing three or more hetero rings
C07D 491/048 - Ortho-condensed systems with only one oxygen atom as ring hetero atom in the oxygen-containing ring the oxygen-containing ring being five-membered
C07D 491/153 - Ortho-condensed systems the condensed system containing two rings with oxygen as ring hetero atom and one ring with nitrogen as ring hetero atom
The present invention provides a display device that achieves both high display quality and high reliability. The display device includes a circuit unit and a display unit. The circuit unit has a first transistor. The first transistor has a first semiconductor layer. The display unit has a display element and a pixel circuit. The pixel circuit has a second transistor. The second transistor has a second semiconductor layer. The first semiconductor layer contains indium oxide. The first semiconductor layer contains crystal grains. The grain size of the crystal grains is 0.3 μm or larger. The second semiconductor layer contains indium. The indium content in the first semiconductor layer is higher than the indium content in the second semiconductor layer.
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
Provided is a novel semiconductor device. This semiconductor device comprises a first element layer, a second element layer located on the first element layer, and a third element layer located on the second element layer, wherein: the first element layer has a first transistor that has silicon in a channel formation region; the second element layer has a second transistor that has indium oxide in a channel formation region; the third element layer has a third transistor that has IGZO in a channel formation region; a CMOS circuit is formed by the first transistor and the second transistor; a circuit formed by the third element layer is driven at a higher voltage than the CMOS circuit; and an insulation layer that has barrier properties against hydrogen is provided between the second element layer and the third element layer.
Provided is a highly reliable semiconductor device. This transistor has a first conductive layer, a second conductive layer, a first insulating layer, a first semiconductor layer, a second insulating layer, and a third conductive layer. The semiconductor layer has a crystalline oxide semiconductor layer that contains indium and oxygen. The oxide semiconductor layer has properties for transmitting oxygen at 2 × 1020atoms/cm3to 1 × 1021atoms/cm3in a heat treatment in which the heating temperature is 400°C and the treatment time is 8 hours. The oxide semiconductor layer also has properties such that a deuterium diffusion amount integral value thereof is 5 × 1012atoms/cm2to 1 × 1014atoms/cm2 in a heat treatment in which the heating temperature is 200°C and the treatment time is 8 hours.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
H10B 99/00 - Subject matter not provided for in other groups of this subclass
H10D 1/68 - Capacitors having no potential barriers
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Provided is a semiconductor device capable of reading data from a ferroelectric capacitor having a small amount of polarization. The semiconductor device includes first to fourth transistors, first and second capacitive elements, and first and second inverters. A first terminal of the first capacitive element is connected to a first terminal of each of the first and second transistors and to an input terminal of the first inverter. A first terminal of the second capacitive element is connected to a first terminal of each of the second and third transistors and to an input terminal of the second inverter. An output terminal of the first inverter is connected to a second terminal of each of the first and second transistors. An output terminal of the second inverter is connected to a second terminal of each of the third and fourth transistors. A gate of each of the first and third transistors is connected to first wiring. A gate of each of the second and fourth transistors is connected to second wiring.
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
The present invention provides a transistor having favorable electrical characteristics. A semiconductor device according to the present invention includes first through third conductive layers, a semiconductor layer, and first and second insulating layers. The first insulating layer is located on the first conductive layer and has an opening that extends to the first conductive layer. The second conductive layer is located on the first insulating layer. The semiconductor layer includes: a portion in contact with the upper surface and side surface of the second conductive layer; a portion in contact with the side surface of the first insulating layer within the opening; and a portion in contact with the upper surface of the first conductive layer within the opening. The second insulating layer covers the semiconductor layer within the opening. The third conductive layer covers the second insulating layer within the opening. Furthermore, the first conductive layer and the second conductive layer contain indium. In addition, the semiconductor layer contains indium oxide, no grain boundaries are observed in the portion in contact with the first insulating layer in a cross section parallel to the height direction of the opening, and the crystal orientations of two or more portions in contact with the first insulating layer coincide.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 99/00 - Subject matter not provided for in other groups of this subclass
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Provided is a metal oxide layer having high carrier mobility. A metal oxide layer, having indium and oxygen and having crystal grains, is formed. This method has: a first step for forming a crystal part on a base film; and a second step for forming a metal oxide layer covering the crystal part. In the second step, crystal grains are formed in the metal oxide layer by the first crystal growth and the second crystal growth. The first crystal growth occurs in a first direction. The second crystal growth occurs in a second direction perpendicular or substantially perpendicular to the first direction. The speed of the first crystal growth is higher than the speed of the second crystal growth.
H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H01L 21/203 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using physical deposition, e.g. vacuum deposition, sputtering
H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Provided is a novel semiconductor device. This invention involves a first transistor, a second transistor, and a light receiving element. One terminal of the light receiving element is connected to a first terminal of the first transistor, a second terminal of the first transistor is connected to a gate of the second transistor, the first transistor includes a first oxide semiconductor in a channel formation region, the second transistor includes a second oxide semiconductor in a channel formation region, the first oxide semiconductor is indium gallium zinc oxide, and the second oxide semiconductor is indium oxide.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
18.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
Provided is a semiconductor device having a high operating speed. The semiconductor device includes a transistor that uses indium oxide as a semiconductor layer, and an insulating layer. The source electrode and the drain electrode have an oxide that contains indium and a first metal element, and have a region in contact with an upper surface of the semiconductor layer. The film thickness of the source electrode and the drain electrode is thinner than the film thickness of the semiconductor layer. The insulating layer has a region in contact with an upper surface of the source electrode and the drain electrode. The insulating layer has a first opening between the source electrode and the drain electrode, and a gate insulating layer and a gate electrode are provided inside the first opening. The semiconductor layer has a recess that overlaps with the first opening. The source electrode and the insulating layer have a second opening, and the drain electrode and the insulating layer have a third opening. First and second plugs having a region in contact with the semiconductor layer, are respectively provided inside the second and third openings. The first and second plugs have a second metal element.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 99/00 - Subject matter not provided for in other groups of this subclass
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A semiconductor device that occupies a small area is provided. The semiconductor device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a first conductive layer, a second conductive layer, and a first insulating layer. The first insulating layer is provided over the first conductive layer. The second conductive layer is provided over the first insulating layer. The first insulating layer and the second conductive layer include an opening reaching the first conductive layer. The first semiconductor layer is in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a top surface and a side surface of the second conductive layer. The second semiconductor layer is provided over the first semiconductor layer. The third semiconductor layer is provided over the second semiconductor layer. The first semiconductor layer contains a first material. The second semiconductor layer contains a second material. The third semiconductor layer contains a third material. A band gap of the first material is larger than a band gap of the second material. A band gap of the third material is larger than the band gap of the second material.
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
20.
COMPUTER SYSTEM AND METHOD FOR OPERATING DATA PROCESSING DEVICE
A computer system with a small circuit area and reduced power consumption is used. The computer system includes a computer node including a processor and a three-dimensional NAND memory device. The three-dimensional NAND memory device includes a first string and a second string in different blocks. The first string includes a first memory cell, and the second string includes a second memory cell. On reception of first data and a signal including an instruction to write the first data, the controller writes the first data to the first memory cell. Then, the controller reads the first data from the first memory cell and writes the first data to the second memory cell. Thus, the computer node can eliminate a main memory such as a DRAM from the structure.
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
21.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
An object is to provide a high reliability thin film transistor using an oxide semiconductor layer which has stable electric characteristics. In the thin film transistor in which an oxide semiconductor layer is used, the amount of change in threshold voltage of the thin film transistor before and after a BT test is made to be 2 V or less, preferably 1.5 V or less, more preferably 1 V or less, whereby the semiconductor device which has high reliability and stable electric characteristics can be manufactured. In particular, in a display device which is one embodiment of the semiconductor device, a malfunction such as display unevenness due to change in threshold voltage can be reduced.
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10D 62/80 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
To provide a power storage device whose charge and discharge characteristics are unlikely to be degraded by heat treatment. To provide a power storage device that is highly safe against heat treatment. The power storage device includes a positive electrode, a negative electrode, a separator, an electrolytic solution, and an exterior body. The separator is located between the positive electrode and the negative electrode. The separator contains polyphenylene sulfide or solvent-spun regenerated cellulosic fiber. The electrolytic solution contains a solute and two or more kinds of solvents. The solute contains LiBETA. One of the solvents is propylene carbonate.
H01M 10/0569 - Liquid materials characterised by the solvents
G04G 19/00 - Electric power supply circuits specially adapted for use in electronic time-pieces
H01G 11/28 - Electrodes characterised by their structure, e.g. multi-layered, porosity or surface features arranged or disposed on a current collectorLayers or phases between electrodes and current collectors, e.g. adhesives
H01G 11/60 - Liquid electrolytes characterised by the solvent
H01G 11/62 - Liquid electrolytes characterised by the solute, e.g. salts, anions or cations therein
H01G 11/84 - Processes for the manufacture of hybrid or EDL capacitors, or components thereof
H01G 11/86 - Processes for the manufacture of hybrid or EDL capacitors, or components thereof specially adapted for electrodes
H01M 4/36 - Selection of substances as active materials, active masses, active liquids
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01M 4/587 - Carbonaceous material, e.g. graphite-intercalation compounds or CFx for inserting or intercalating light metals
The present invention provides a metal oxide layer having high carrier mobility. The present invention involves forming a metal oxide layer that has indium and oxygen, and that has crystal grains. The present invention includes: a first step for forming a crystal part on a base film having a groove part; and a second step for forming a metal oxide layer so as to cover the crystal part. During the second step, the crystal grains are formed in the metal oxide layer via first crystal growth and second crystal growth. The first crystal growth occurs in a first direction. The second crystal growth occurs in a second direction perpendicular or substantially perpendicular to the first direction. The speed of the first crystal growth is faster than the speed of the second crystal growth.
H01L 21/363 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using physical deposition, e.g. vacuum deposition, sputtering
H01L 21/365 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10D 1/68 - Capacitors having no potential barriers
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
25.
DISPLAY DEVICE, METHOD FOR OPERATING DISPLAY DEVICE, AND ELECTRONIC APPARATUS
The present invention provides a display device that can write data to a pixel at high speed. In this display device, a transistor capable of controlling a current that flows in response to light irradiation is used as a select transistor. The transistor is turned off by using a portion of a waveguide as a gate electrode and applying an appropriate potential to the waveguide, and is turned on by irradiating the transistor with light via the waveguide. Accordingly, since problems arising from interconnection resistance and interconnection capacitance do not occur, the select transistor can be operated at high speed, contributing to higher frame frequency and lower power consumption.
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
G09F 9/33 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
Provided is a novel semiconductor device. The semiconductor device has: a functional circuit having a first transistor; and a power supply circuit having a second transistor, wherein the first transistor is formed on a front surface side of a substrate, the second transistor is formed on a rear surface side of the substrate, the first transistor is electrically connected to the second transistor via a conductive layer formed on a rear surface side, the first transistor includes silicon in a semiconductor layer in which a channel is formed, and the second transistor includes an oxide semiconductor in a semiconductor layer in which a channel is formed.
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Provided is a novel information processing system that has enhanced convenience, usefulness, and reliability. An information processing device according to the present invention is composed of three components. The first component receives a positive example list and transmits the positive example list to the third component. The positive example list includes features of intended readers and features of a preferred writing style. The second component performs processing by using a large language model, and extracts features according to a first instruction sentence. The third component receives the positive example list and translation guidelines and shares this information. Additionally, the device extracts the features of the intended readers and the features of the preferred writing style, generates translation guidelines, and provides the translation guidelines including recommendations.
This semiconductor device improves the efficiency of arithmetic. In the semiconductor device, one of the source and the drain of a first transistor is connected to the gate of a second transistor and the gate of a third transistor, one of the source and the drain of the second transistor is connected to one of the source and the drain of the third transistor, a first signal line is connected to the other of the source and the drain of the second transistor, the second signal line is connected to the other of the source and the drain of the third transistor, the first signal line has a function of supplying an arithmetic signal, the second signal line has a function of supplying an inverted signal of the arithmetic signal, the third transistor has a polarity different from a polarity of the second transistor, and the first transistor has an oxide semiconductor in the channel formation region thereof.
H10B 12/00 - Dynamic random access memory [DRAM] devices
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G11C 11/405 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
A semiconductor device with a novel configuration is provided. The semiconductor device includes a first element layer including a bit line driver circuit; a second element layer including a first switch circuit, a first memory cell, and a first wiring provided between the first switch circuit and the first memory cell; and a third element layer including a second switch circuit, a second memory cell, and a second wiring provided between the second switch circuit and the second memory cell. The first switch circuit has a function of establishing a non-conduction state between the first wiring and a third wiring in data write operation or read operation of the second memory cell. The second switch circuit has a function of establishing a non-conduction state between the second wiring and the third wiring in data write operation or read operation of the first memory cell.
H10B 12/00 - Dynamic random access memory [DRAM] devices
G11C 11/405 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
30.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device that can be easily miniaturized is provided. A semiconductor device with reduced parasitic capacitance is provided. In the semiconductor device, an insulating layer functioning as a first spacer is provided between a lower electrode that is one of a source electrode and a drain electrode of a transistor and an upper electrode that is the other, and an insulating layer functioning as a second spacer is provided over the upper electrode. The first spacer, the upper electrode, and the second spacer are provided with a first opening portion reaching the lower electrode. Inside the first opening portion, a semiconductor layer where a channel is formed is provided to connect the lower electrode and the upper electrode. Inside the first opening portion, a gate insulating layer and a gate electrode are provided to overlap with the semiconductor layer. An interlayer insulating layer including a second opening portion reaching the gate electrode is provided over the second spacer, the semiconductor layer, the gate insulating layer, and the gate electrode. The gate electrode includes a region in contact with a wiring over the interlayer insulating layer inside the second opening portion.
A text generation system that supports understanding of both an inventor and a patent engineer and supports creation of appropriate claims for the invention in patent application. The text generation system is configured to perform processing using a language model, create a key point of the invention from material of the invention, create a claim proposal from the key point of the invention, and create a search formula from the claim proposal. In addition, the text generation system is configured to perform a patent search with use of the search formula.
A light-emitting device having favorable characteristics. The light-emitting device includes at least a light-emitting layer and a hole-transport layer between a pair of electrodes. The hole-transport layer is provided in contact with the light-emitting layer. The light-emitting layer contains a first compound serving as a host material and a second compound serving as a guest material. The hole-transport layer contains a third compound. A HOMO level of the second compound is higher than a HOMO level of the first compound. Each of the first compound and the third compound includes deuterium.
A position estimation system with low power consumption is provided. The position estimation system includes a comparison unit, a learning unit, a data acquisition unit, an inference unit, a data conversion unit, and an evaluation unit. The comparison unit has a function of calculating a first parallel movement amount and a first rotation amount on the basis of machine learning data representing geographic information. The learning unit has a function of generating a machine learning model through learning using the machine learning data, the first parallel movement amount, and the first rotation amount. The data acquisition unit has a function of acquiring acquisition data representing environmental information on the vicinity of a position estimation device. The inference unit has a function of inferring a second parallel movement amount and a second rotation amount, with use of the machine learning model, on the basis of the acquisition data and the machine learning data. The data conversion unit has a function of converting the machine learning data to evaluation data on the basis of the second parallel movement amount and the second rotation amount. The evaluation unit has a function of evaluating the degree of correspondence between the acquisition data and the evaluation data.
G06T 7/70 - Determining position or orientation of objects or cameras
G06T 7/246 - Analysis of motion using feature-based methods, e.g. the tracking of corners or segments
G06V 10/75 - Organisation of the matching processes, e.g. simultaneous or sequential comparisons of image or video featuresCoarse-fine approaches, e.g. multi-scale approachesImage or video pattern matchingProximity measures in feature spaces using context analysisSelection of dictionaries
G06V 10/771 - Feature selection, e.g. selecting representative features from a multi-dimensional feature space
A semiconductor device with a small variation in characteristics is provided. The semiconductor device includes an oxide, a first conductor and a second conductor over the oxide, a first insulator over the first conductor, a second insulator over the second conductor, a third conductor over the first insulator, a fourth insulator over the second insulator, a fifth insulator over the third insulator and the fourth insulator, a sixth insulator over the fifth insulator, a seventh insulator that is over the oxide and placed between the first conductor and the second conductor, an eighth insulator over the seventh insulator, a third conductor over the eighth insulator, and a ninth insulator over the third conductor and the sixth to eighth insulators. The third conductor includes a region overlapping the oxide. The seventh insulator includes a region in contact with each of the oxide, the first conductor, the second conductor, and the first to sixth insulators. The first insulator, the second insulator, the fifth insulator, and the ninth insulator are each a metal oxide having an amorphous structure.
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
H10D 87/00 - Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
The present invention provides a highly reliable storage device having a long data retention time. This storage device has a peripheral circuit and a plurality of memory cells. Each of the memory cells has a first transistor and a capacitive element. The peripheral circuit has a second transistor and a third transistor. A first terminal of the first transistor is electrically connected to a first terminal of the capacitive element, and a second terminal of the first transistor is electrically connected to a first terminal of the second transistor and a first terminal of the third transistor. Respective semiconductor layers of the first transistor, the second transistor, and the third transistor have mutually different compositions.
H10B 12/00 - Dynamic random access memory [DRAM] devices
G11C 11/405 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 99/00 - Subject matter not provided for in other groups of this subclass
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
The present invention provides a novel organometallic complex and a light-emitting device. The present invention provides an organometallic complex represented by general formula (G1). Note that R1, R2, and R4 to R31 each independently represent hydrogen (including deuterium), an alkyl group having 1 to 10 carbon atoms, or a substituted or unsubstituted aryl group having 6 to 18 carbon atoms, at least one of R2 and R4 represents an alkyl group having 1 to 10 carbon atoms, one or more of R18 to R22 represents an alkyl group having 3 to 10 carbon atoms or a substituted or unsubstituted aryl group having 6 to 18 carbon atoms, and R23 represents general formula (R-1).
C07F 15/00 - Compounds containing elements of Groups 8, 9, 10 or 18 of the Periodic Table
C07D 401/14 - Heterocyclic compounds containing two or more hetero rings, having nitrogen atoms as the only ring hetero atoms, at least one ring being a six-membered ring with only one nitrogen atom containing three or more hetero rings
H10K 50/12 - OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers comprising dopants
A semiconductor device that can be easily miniaturized is provided. A semiconductor device with reduced parasitic capacitance is provided. The semiconductor device includes a transistor, a first insulating layer, and a second insulating layer. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulating layer. The first insulating layer is positioned above the first conductive layer and includes a first opening reaching the first conductive layer. The second conductive layer is positioned above the first insulating layer. The semiconductor layer is in contact with the second conductive layer and a side surface of the first insulating layer and a top surface of the first conductive layer in the first opening. The third insulating layer is in contact with a top surface of the first insulating layer and the semiconductor layer in the first opening. The second insulating layer is positioned above the third insulating layer and includes a second opening reaching the third insulating layer in a position overlapping the first opening. The third conductive layer is provided to fill the second opening and the first opening.
An organic semiconductor device with low driving voltage is provided. The light-emitting device includes an anode, a cathode, and an EL layer between the anode and the cathode. The EL layer includes a hole-transport layer and a light-emitting layer. The hole-transport layer is positioned between the anode and the light-emitting layer. The hole-transport layer is not in contact with the anode. The hole-transport layer includes a transport layer material for a light-emitting device and the GSP_slope that is a potential gradient of a surface potential of an evaporated film of the material is higher than or equal to 20 (mV/nm).
H10K 30/30 - Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation comprising bulk heterojunctions, e.g. interpenetrating networks of donor and acceptor material domains
A light-emitting element with high luminous efficiency is provided. The light-emitting element contains a first organic compound and a second organic compound. The first and second organic compounds form an exciplex. The first organic compound emits no fluorescence but phosphorescence at a temperature ranging from low temperature to normal temperature. The luminescence quantum yield of the first organic compound is higher than or equal to 0% and lower than or equal to 40% at room temperature. Light emitted from the light-emitting element includes light emitted from an exciplex formed by the first organic compound and the second organic compound.
The formation method of graphene includes the steps of forming a layer including graphene oxide over a first conductive layer; and supplying a potential at which the reduction reaction of the graphene oxide occurs to the first conductive layer in an electrolyte where the first conductive layer as a working electrode and a second conductive layer with a as a counter electrode are immersed. A manufacturing method of a power storage device including at least a positive electrode, a negative electrode, an electrolyte, and a separator includes a step of forming graphene for an active material layer of one of or both the positive electrode and the negative electrode by the formation method.
Provided is a highly reliable semiconductor device. The semiconductor device comprises: a first insulating layer; a semiconductor layer covering a side surface of the first insulating layer; a first conductive layer in contact with a part of a side surface of the semiconductor layer; a second conductive layer provided at a distance from the first conductive layer and in contact with another part of the side surface of the semiconductor layer; a second insulating layer covering the first insulating layer and a part of the semiconductor layer; and a third conductive layer on the second insulating layer. The third conductive layer covers the first insulating layer and a part of the semiconductor layer with the second insulating layer therebetween.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Provided is a semiconductor device with a high operating speed. The semiconductor device includes first to third cells. The first cell has the function of holding a first potential corresponding to first data, the function of drawing a first current, corresponding to the first potential, from first wiring, and the function of drawing a second current, corresponding to the product of the first data and second data, from the first wiring by changing the potential of second wiring according to the second data. The second cell has the function of holding a second potential corresponding to reference data, the function of drawing a third current, corresponding to the second potential, from the second wiring, and the function of changing the third current flowing in the second wiring to a fourth current corresponding to the second data by changing the potential of the second wiring in response to a change from the reference data to the second data. The third cell has the function of holding a third potential corresponding to the product of the first data and the second data, and the function of supplying a fifth current corresponding to the third potential to the first wiring or third wiring.
G06G 7/60 - Analogue computers for specific processes, systems, or devices, e.g. simulators for living beings, e.g. their nervous systems
G06G 7/184 - Arrangements for performing computing operations, e.g. amplifiers specially adapted therefor for integration or differentiation using capacitive elements
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 99/00 - Subject matter not provided for in other groups of this subclass
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
Provided is a novel aromatic amine derivative represented by General Formula (G1) below (In the formula, A represents oxygen or sulfur, and R1 to R7 individually represent any of a hydrogen atom, an alkyl group having 1 to 6 carbon atoms, a substituted or unsubstituted phenyl group, and a substituted or unsubstituted biphenyl group. In addition, α1 and α2 individually represent a substituted or unsubstituted phenylene group. Further, Ar1 represents a substituted or unsubstituted condensed aromatic hydrocarbon having 14 to 18 carbon atoms included in a ring. Further, Ar2 represents a substituted or unsubstituted aryl group having 6 to 13 carbon atoms included in a ring. Further, j and n are individually 0 or 1, and p is 1 or 2.)
Provided is a novel aromatic amine derivative represented by General Formula (G1) below (In the formula, A represents oxygen or sulfur, and R1 to R7 individually represent any of a hydrogen atom, an alkyl group having 1 to 6 carbon atoms, a substituted or unsubstituted phenyl group, and a substituted or unsubstituted biphenyl group. In addition, α1 and α2 individually represent a substituted or unsubstituted phenylene group. Further, Ar1 represents a substituted or unsubstituted condensed aromatic hydrocarbon having 14 to 18 carbon atoms included in a ring. Further, Ar2 represents a substituted or unsubstituted aryl group having 6 to 13 carbon atoms included in a ring. Further, j and n are individually 0 or 1, and p is 1 or 2.)
H05B 33/14 - Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material
H05B 33/28 - Light sources with substantially two-dimensional radiating surfaces characterised by the composition or arrangement of the conductive material used as an electrode of translucent electrodes
H10K 50/11 - OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
H10K 85/60 - Organic compounds having low molecular weight
A solid-state imaging device with high productivity and improved dynamic range is provided. In the imaging device including a photoelectric conversion element having an i-type semiconductor layer, functional elements, and a wiring, an area where the functional elements and the wiring overlap with the i-type semiconductor in a plane view is preferably less than or equal to 35%, further preferably less than or equal to 15%, and still further preferably less than or equal to 10% of the area of the i-type semiconductor in a plane view. Plural photoelectric conversion elements are provided in the same semiconductor layer, whereby a process for separating the respective photoelectric conversion elements can be reduced. The respective i-type semiconductor layers in the plural photoelectric conversion elements are separated by a p-type semiconductor layer or an n-type semiconductor layer.
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
H01L 23/528 - Layout of the interconnection structure
H04N 23/54 - Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
H10F 10/17 - Photovoltaic cells having only PIN junction potential barriers
Provided is a novel lithium ion secondary battery. This lithium ion secondary battery has a positive electrode and a negative electrode. The positive electrode has positive electrode active material particles. The positive electrode active material particles include lithium, cobalt, oxygen, magnesium, fluorine, nickel, and aluminum. The positive electrode active material particles have a surface layer section having an edge region, and an interior section. The interior section has an R-3m space group layered rock salt-type crystal structure. When a side-by-side arrangement of bright spots on the surface of the positive electrode active material particles as observed in a cross-sectional STEM image of a surface where lithium is inserted/extracted is treated as a first row, at least a portion of a fourth row through a ninth row that are located in the interior direction of the positive electrode active material particles have characteristics of a spinel-type crystal structure. In a STEM-EELS analysis of the fourth row through the ninth row, magnesium and nickel are detected at positions where only the Wyckoff position 16c of an Fd-3m space group overlaps, and nickel is detected at a position where only the Wyckoff position 16d overlaps.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
C01G 51/42 - Complex oxides containing cobalt and at least one other metal element containing alkali metals, e.g. LiCoO2
H01M 4/36 - Selection of substances as active materials, active masses, active liquids
H01M 4/38 - Selection of substances as active materials, active masses, active liquids of elements or alloys
H01M 4/131 - Electrodes based on mixed oxides or hydroxides, or on mixtures of oxides or hydroxides, e.g. LiCoOx
A semiconductor device that has both low power consumption and high performance is provided. The semiconductor device includes a first and second transistors. The first transistor includes a first conductive layer, a first insulating layer over the first conductive layer, a second conductive layer over the first insulating layer, a second insulating layer over the second conductive layer, a third insulating layer over the second insulating layer, a third conductive layer over the third insulating layer, and a first semiconductor layer. The second conductive layer includes a first opening reaching the first insulating layer in a region overlapping with the first conductive layer. The first to third insulating layers and the third conductive layer include a second opening reaching the first conductive layer in a region overlapping with the first opening. The first semiconductor layer is in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second insulating layer, a side surface of the third insulating layer, and a top surface and a side surface of the third conductive layer. The second transistor includes a fourth conductive layer, the first to third insulating layers over the fourth conductive layer, and a second semiconductor layer over the third insulating layer.
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator over a substrate; a second insulator over the first insulator; a third insulator over the second insulator; an oxide semiconductor placed over the second insulator and covering the third insulator; a first conductor and a second conductor over the oxide semiconductor; a fourth insulator placed over the first conductor and the second conductor; a fifth insulator placed over the oxide semiconductor; and a third conductor placed over the fifth insulator. The second insulator and the fourth insulator include an opening reaching the oxide semiconductor and reaching the first insulator in a region not overlapping with the oxide semiconductor, in a region between the first conductor and the second conductor. The fifth insulator and the third conductor are placed in the opening. The height of the third insulator is larger than the width of the third insulator in the cross-sectional view in the channel width direction. The bottom surface of the third conductor in a region not overlapping with the oxide semiconductor in the opening is positioned below the bottom surface of the oxide semiconductor.
A data processing system including three components is provided. A first component receives a scope of claims, a notice of reasons for refusal, an argument draft, and a forecast. A second component receives a prompt, receives and transmits the forecast to a third component, and performs processing using a large language model. The third component receives the scope of claims, the notice of reasons for refusal, and the argument draft, and shares them. The third component including two subcomponents receives and transmits the forecast to the first component. A first subcomponent performs processing using a database including an examination record and a search engine. The search engine extracts an examination record list in accordance with a query. The system has a function of creating a forecast of an examination result and an argument draft in view of the scope of claims, an examiner, a technical field, and the like.
A semiconductor device with high reliability is provided. The semiconductor device includes a first transistor, a second transistor, a capacitor, and first to fourth wirings. The first transistor includes a first gate and a second gate, and one of a source and a drain of the first transistor is connected to the first wiring and the second gate, and the other of the source and the drain is connected to one of a source and a drain of the second transistor and one electrode of the capacitor. A gate of the second transistor is connected to the other electrode of the capacitor, and the other of the source and the drain of the second transistor is electrically connected to the second wiring. The first wiring is supplied with a first potential, and the second wiring is supplied with a second potential and a third potential alternately. The third wiring is connected to the first gate and supplied with a first signal. The fourth wiring is connected to the gate of the second transistor and supplied with a second signal obtained by inverting the first signal.
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
A system with high processing speed and low power consumption is provided. The system includes an imaging device and an arithmetic circuit. The imaging device includes an imaging portion, a first memory portion, and an arithmetic portion, and the arithmetic circuit includes a second memory portion. The imaging portion has a function of converting light reflected by an external subject into image data, and the first memory portion has a function of storing the image data and a first filter for performing first convolutional processing in a first layer of a neural network. The arithmetic portion has a function of performing the first convolutional processing using the image data and the first filter to generate first data. The second memory portion has a function of storing the first data and a plurality of filters for performing convolutional processing in and after a second layer of the neural network. The arithmetic circuit has a function of performing processing in and after the second layer of the neural network using the first data to generate a depth map of the image data.
A light-emitting device includes a first electrode, a second electrode, a light-emitting layer, a first layer, and a second layer. The first electrode is over a substrate and is between the second electrode and the substrate. The light-emitting layer is between the first electrode and the second electrode. The first layer is between the first electrode and the light-emitting layer. The second layer is between the second electrode and the light-emitting layer. One of the first electrode and the second electrode is an anode and the other is a cathode. A GSP slope (mV/nm) of one of the light-emitting layer and the first layer closer to the cathode is larger than a GSP slope (mV/nm) of the other closer to the anode. A GSP slope (mV/nm) of one of the light-emitting layer and the second layer closer to the anode is larger than a GSP slope (mV/nm) of the other closer to the cathode.
Provided is a storage device that has a novel configuration. A first memory cell includes first to third transistors. A second memory cell includes fourth to sixth transistors. A switch circuit includes seventh and eighth transistors. One of the source and the drain of the seventh transistor is connected to one of the source and the drain of the first transistor and the gate of the second transistor. The other of the source and the drain of the seventh transistor is connected to one of the source and the drain of the fifth transistor and one of the source and the drain of the sixth transistor. One of the source and the drain of the eighth transistor is connected to one of the source and the drain of the second transistor and one of the source and the drain of the third transistor. The other of the source and the drain of the eighth transistor is connected to one of the source and the drain of the fourth transistor and the gate of the fifth transistor.
G11C 11/405 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 99/00 - Subject matter not provided for in other groups of this subclass
Provided is a semiconductor device which allows for miniaturization and a high level of integration. This semiconductor device includes a first transistor, a second transistor, and a third transistor. The first transistor is a p-channel transistor. The second transistor is an n-channel transistor positioned to overlap on top of the first transistor. The third transistor is an n-channel transistor positioned to overlap on top of the second transistor. The gate of the first transistor and one of either the source or the drain of the second transistor are electrically connected at a first node. One of either the source or the drain of the first transistor, the gate of the second transistor, and one of either the source or the drain of the third transistor are electrically connected at a second node. Each of the first transistor, the second transistor, and the third transistor is a vertical transistor.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
Provided is a display device having high display quality. The display device includes: pixels in which threshold value correction of a drive transistor can be performed; and first and second spacers. The pixels include first to third vertical transistors and a light-emitting element. The second spacer is provided on the first spacer. The first vertical transistor has a region located inside first and second openings provided in the first spacer. The second and third vertical transistors each have regions located inside third and fourth openings provided in the second spacer. The third and fourth openings are provided so as to overlap the first vertical transistor. Thus, the channel length of the first vertical transistor is equal to or greater than the channel lengths of the second and third vertical transistors. The first vertical transistor functions as a drive transistor. The second and third vertical transistors function as switches.
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
H10K 59/123 - Connection of the pixel electrodes to the thin film transistors [TFT]
H10K 59/124 - Insulating layers formed between TFT elements and OLED elements
Provided is a transistor that has a small footprint, or a method for producing the same. This method for producing a semiconductor device that has a crystalline semiconductor layer has: a first step for forming a semiconductor layer on an insulating layer in which a groove section is provided; a second step for forming a mask on the semiconductor layer; a third step for etching the semiconductor layer on the insulating layer, where the mask is not formed; and a fourth step for etching the semiconductor layer in the groove section, where the mask is not formed. The surface of the semiconductor layer on the insulating layer is formed so as to have a first crystal plane, and the surface of the semiconductor layer on a side surface of the groove section is formed so as to have a second crystal plane.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A light-emitting device in which variation in luminance of pixels is suppressed. A light-emitting device includes at least a transistor, a first wiring, a second wiring, a first switch, a second switch, a third switch, a fourth switch, a capacitor, and a light-emitting element. The first wiring and a first electrode of the capacitor are electrically connected to each other through the first switch. A second electrode of the capacitor is connected to a first terminal of the transistor. The second wiring and a gate of the transistor are electrically connected to each other through the second switch. The first electrode of the capacitor and the gate of the transistor are electrically connected to each other through the third switch. The first terminal of the transistor and an anode of the light-emitting element are electrically connected to each other through the fourth switch.
G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
G09G 3/3291 - Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
A novel organometallic complex and light-emitting device that excel in convenience, usefulness, or drive efficiency are provided. In the organometallic complex represented by General Formula (G1), one or both of R1 and R7 represent a substituted or unsubstituted heteroaryl group having 3 to 20 carbon atoms or a substituted or unsubstituted aryl group having 6 to 13 carbon atoms; in the case where the heteroaryl group has a substituent, the substituent has 1 to 5 hetero atoms of any of a nitrogen atom, an oxygen atom, and a sulfur atom; and the other of R1 and R7, R2 to R6, and R8 to R20 each independently represent hydrogen, an alkyl group having 1 to 10 carbon atoms, or a substituted or unsubstituted aryl group having 6 to 13 carbon atoms.
A novel organometallic complex and light-emitting device that excel in convenience, usefulness, or drive efficiency are provided. In the organometallic complex represented by General Formula (G1), one or both of R1 and R7 represent a substituted or unsubstituted heteroaryl group having 3 to 20 carbon atoms or a substituted or unsubstituted aryl group having 6 to 13 carbon atoms; in the case where the heteroaryl group has a substituent, the substituent has 1 to 5 hetero atoms of any of a nitrogen atom, an oxygen atom, and a sulfur atom; and the other of R1 and R7, R2 to R6, and R8 to R20 each independently represent hydrogen, an alkyl group having 1 to 10 carbon atoms, or a substituted or unsubstituted aryl group having 6 to 13 carbon atoms.
A transistor having a minute size is provided. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, and a semiconductor layer. The first insulating layer is provided over the first conductive layer and includes an opening reaching the first conductive layer and a depressed portion surrounding the opening in a plan view. The second conductive layer is provided to cover the inner wall of the depressed portion and includes a region facing the semiconductor layer with the first insulating layer therebetween. The semiconductor layer is provided to include a region overlapping with the opening and is in contact with the top surface of the first conductive layer, the side surface of the first insulating layer, the side surface of the second conductive layer, and the top surface of the second conductive layer. The second insulating layer is provided in contact with the top surface of the semiconductor layer. The third conductive layer is provided over the second insulating layer to cover the inner wall of the opening and includes a region facing the semiconductor layer with the second insulating layer therebetween.
A document viewing device that contributes to smooth execution of the work is provided. The document viewing device includes an input unit, a registration unit, a display control unit, and a display unit. The input unit has a function of receiving a document designated by a user. The registration unit has a function of registering a comment in a comment-given portion that is part of the document. The display control unit has a function of making the display unit display the comment so that the user can be made aware that whether a person who has registered the comment is the user or any of the other users different from the user.
G06F 40/169 - Annotation, e.g. comment data or footnotes
G06F 3/0481 - Interaction techniques based on graphical user interfaces [GUI] based on specific properties of the displayed interaction object or a metaphor-based environment, e.g. interaction with desktop elements like windows or icons, or assisted by a cursor's changing behaviour or appearance
A semiconductor device which is easily miniaturized is provided. A semiconductor device that can be highly integrated is provided. A first insulating layer includes an opening; a first conductive layer is positioned along the opening; a third insulating layer is positioned along the first conductive layer; a second conductive layer is positioned in a depression portion of the third insulating layer; a second insulating layer is positioned over the second conductive layer and includes a slit reaching the second conductive layer; a third conductive layer is positioned over the second insulating layer; a semiconductor layer includes a portion in contact with a side surface of the third conductive layer, a portion in contact with a side surface of the second insulating layer in the slit, and a portion in contact with a top surface of the second conductive layer in the slit; a fourth insulating layer covers the semiconductor layer in the slit; a fourth conductive layer covers the fourth insulating layer in the slit; the second conductive layer includes a first layer, a second layer, and a third layer; a top surface of the first layer includes a depression portion; the second layer is positioned in the depression portion of the first layer; and the third layer is positioned over the first layer and the second layer.
A light-emitting device with high emission efficiency is provided. A light-emitting device with high reliability is provided. A light-emitting device with high emission efficiency and high reliability is provided. The light-emitting device includes a first electrode, a second electrode, a light-emitting layer positioned between the first electrode and the second electrode, and a cap layer. The second electrode is positioned between the light-emitting layer and the cap layer. The cap layer includes at least a first substance and a second substance. The first substance and the second substance are substances having a difference of 0.1 or more between ordinary refractive indices of respective evaporated films at a wavelength of 380 nm to 760 nm. The first substance is a monoamine compound having an alkyl group. The second substance is an organic compound having a carbazole skeleton.
H10K 50/13 - OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers specially adapted for multicolour light emission, e.g. for emitting white light comprising stacked EL layers within one EL unit
An electronic device with a novel structure is provided. The electronic device includes a display apparatus, a gaze detection portion, and an arithmetic portion. The display apparatus includes a display portion divided into a plurality of sub-display portions and a functional circuit including a luminance conversion circuit. The gaze detection portion has a function of detecting the user's gaze. The arithmetic portion has a function of allocating the plurality of sub-display portions to a first section or a second section with the use of the detection result of the gaze detection portion. The functional circuit has a function of performing display on the sub-display portion included in the first section with a first driving frequency and performing display on the sub-display portion included in the second section with a second driving frequency lower than the first driving frequency. The luminance conversion circuit has a function of converting image data displayed on the second section to image data with reduced luminance to be displayed in the sub-display portion.
An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
G11C 19/28 - Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
G11C 19/18 - Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
H01L 25/03 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
H05K 7/02 - Arrangements of circuit components or wiring on supporting structure
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
A semiconductor device that can perform product-sum operation with low power consumption is provided. The semiconductor device includes first and second circuits. The first circuit includes a first holding node and the second circuit includes a second holding node. The first circuit is electrically connected to first and second input wirings and first and second wirings, the second circuit is electrically connected to the first and second input wirings and the first and second wirings, and the first and second circuits have a function of holding first and second potentials corresponding to first data at the first and second holding nodes. When potentials corresponding to second data are input to the first and second input wirings, the first circuit outputs a current to one of the first wiring and the second wiring, and the second circuit outputs a current to the other of the first wiring and the second wiring. The currents output by the first and second circuits to the first wiring and the second wiring are determined in accordance with the first and second potentials held at the first and second nodes.
G11C 11/401 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
G11C 11/54 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using elements simulating biological cells, e.g. neuron
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Provided is a novel storage device. According to the present invention, each of a gate of a first transistor, an output terminal of a first buffer, and a first terminal of a second transistor is connected to a word line, a first terminal of a third transistor is connected to a first power supply terminal of the first buffer, a first terminal of a fourth transistor is connected to a second power supply terminal of the first buffer, a gate of the second transistor is connected to an output terminal of an inverter, a gate of the third transistor is connected to an output terminal of a second buffer, a gate of the fourth transistor is connected to the output terminal of the inverter, and the inverter has a function that outputs a signal obtained by inverting a logical value of a signal outputted from the second buffer.
The present invention provides a transistor that can handle large currents. The present invention provides a storage device in which transistors can be densely arranged. This semiconductor device has first and second semiconductor layers, first to third conductive layers, and a first insulating layer. The first conductive layer and the second conductive layer are provided apart from each other. A first lateral surface of the first conductive layer and a second lateral surface of the second conductive layer have first groove parts and second groove parts, respectively. The first semiconductor layer fits into a pair of the first groove parts, and the second semiconductor layer fits into a pair of the second groove parts. Between the first conductive layer and the second conductive layer, the third conductive layer surrounds the upper surface, the lower surface, and the pair of lateral surfaces of each of the first semiconductor layer and the second semiconductor layer. The first insulating layer has a portion located between the first semiconductor layer and the third conductive layer and a portion located between the second semiconductor layer and the third conductive layer.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
H10D 1/68 - Capacitors having no potential barriers
A semiconductor device that can be easily miniaturized is provided. A semiconductor device with reduced parasitic capacitance is provided. The semiconductor device includes a transistor, first and second insulating layers, and a wiring. The transistor includes first to third conductive layers, a semiconductor layer, and a third insulating layer. The first insulating layer includes a first opening reaching the first conductive layer. The semiconductor layer is in contact with the second conductive layer over the first insulating layer and a side surface of the first insulating layer and a top surface of the first conductive layer in the first opening. The second insulating layer includes a second opening that is in a position overlapping with the first opening and reaches the semiconductor layer. The third insulating layer is in contact with a side surface of the second insulating layer in the second opening and the semiconductor layer in the first opening. The third conductive layer is embedded in the second opening and the first opening. The wiring is positioned over the second insulating layer, is in contact with the third conductive layer, and includes a portion overlapping with the semiconductor layer or the second conductive layer with the second insulating layer therebetween.
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
H10K 59/121 - Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
68.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device that can be easily miniaturized is provided. The semiconductor device includes a first insulating layer, a second insulating layer, and a transistor. The transistor includes a first conductive layer, a second conductive layer, a first semiconductor layer, a third insulating layer, and a third conductive layer. The first insulating layer is over the first conductive layer and includes a slit reaching the first conductive layer. The second conductive layer is over the first insulating layer. The first semiconductor layer includes a first portion in contact with the second conductive layer, a second portion along a side surface of the slit, and a third portion in contact with a top surface of the first conductive layer in the slit. The third conductive layer includes a portion facing a second portion of the first semiconductor layer with the third insulating layer therebetween. The second insulating layer includes a portion facing the second portion of the first semiconductor layer with the third insulating layer and the third conductive layer of the first semiconductor layer therebetween and a portion overlapping with the top surface with the third portion of the first conductive layer therebetween.
An organic compound with high heat resistance is provided. A novel organic compound that can be used for a light-emitting device that emits red light or near-infrared light is provided. An organic compound represented by General Formula (G0) is provided. In General Formula (G0), Q represents oxygen or sulfur, Ar1 represents a substituted or unsubstituted fused aromatic ring, R1 and R2 each independently represent hydrogen or a group with 1 to 100, inclusive, carbon atoms in total, and at least one of R1 and R2 has a hole-transport skeleton or a fused ring.
An organic compound with high heat resistance is provided. A novel organic compound that can be used for a light-emitting device that emits red light or near-infrared light is provided. An organic compound represented by General Formula (G0) is provided. In General Formula (G0), Q represents oxygen or sulfur, Ar1 represents a substituted or unsubstituted fused aromatic ring, R1 and R2 each independently represent hydrogen or a group with 1 to 100, inclusive, carbon atoms in total, and at least one of R1 and R2 has a hole-transport skeleton or a fused ring.
A system for supporting specification preparation having a function of receiving a summary of an invention, generating a first prompt including a content for preparing a first specification corresponding to the summary, obtaining the first specification from a language model as an answer to the first prompt, displaying the first specification, classifying the first specification into chapters, generating a second prompt including a content for obtaining data related to a first chapter that is classified from a second component and a content for creating a second chapter by revising the first chapter in accordance with the data, obtaining the second chapter as an answer to the second prompt from the language model, displaying the first chapter and the second chapter, comparing the first chapter and the second chapter to select the one which is suitable for the summary, and preparing a second specification including the selected chapter is provided.
A thin optical device having high light utilization efficiency and less chromatic aberration and a small electronic device including the optical device are provided. The thin optical device includes a first reflective polarizing plate, a lens, an optical rotator, a retardation plate, and a second reflective polarizing plate. The optical device can be a thin optical device by rotation of the polarization plane of linearly polarized light with the optical rotator and utilization of a property of selectively reflecting circularly polarized light of the second reflective polarizing plate. Furthermore, the optical device does not use a half mirror and thus has a property of high light utilization efficiency. When the second reflective polarizing plate has a layered structure, chromatic aberration of an optical system can be reduced.
G16H 10/20 - ICT specially adapted for the handling or processing of patient-related medical or healthcare data for electronic clinical trials or questionnaires
G06F 3/0482 - Interaction with lists of selectable items, e.g. menus
G06F 16/955 - Retrieval from the web using information identifiers, e.g. uniform resource locators [URL]
G16H 10/60 - ICT specially adapted for the handling or processing of patient-related medical or healthcare data for patient-specific data, e.g. for electronic patient records
An organometallic complex having an emission peak in a long wavelength region (a visible region having a wavelength of 700 nm or greater or a near-infrared region) is provided. The organometallic complex has a structure represented by General Formula (G1), in which a ligand having a quinoxaline skeleton is coordinated to a central metal, and an electron-withdrawing group (e.g., fluorine, a cyano group, a trifluoromethyl group, a trifluoromethylsulfonyl group, or a pentafluorosulfanyl group) is included as a substituent at at least one substitutable position of the benzene ring of the quinoxaline skeleton of the ligand.
An organometallic complex having an emission peak in a long wavelength region (a visible region having a wavelength of 700 nm or greater or a near-infrared region) is provided. The organometallic complex has a structure represented by General Formula (G1), in which a ligand having a quinoxaline skeleton is coordinated to a central metal, and an electron-withdrawing group (e.g., fluorine, a cyano group, a trifluoromethyl group, a trifluoromethylsulfonyl group, or a pentafluorosulfanyl group) is included as a substituent at at least one substitutable position of the benzene ring of the quinoxaline skeleton of the ligand.
Semi conductor Energy Laboratory Co., Ltd. (Japan)
Inventor
Seo, Satoshi
Seo, Hiromi
Takahashi, Tatsuyoshi
Ishisone, Takahiro
Abstract
A multicolor light-emitting element using fluorescence and phosphorescence, which has a small number of manufacturing steps owing to a relatively small number of layers to be formed and is advantageous for practical application can be provided. In addition, a multicolor light-emitting element using fluorescence and phosphorescence, which has favorable emission efficiency is provided. A light-emitting element which includes a light-emitting layer having a stacked-layer structure of a first light-emitting layer exhibiting light emission from a first exciplex and a second light-emitting layer exhibiting phosphorescence is provided.
H10K 50/11 - OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
H10K 50/13 - OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers specially adapted for multicolour light emission, e.g. for emitting white light comprising stacked EL layers within one EL unit
An authentication system for an electronic device with a high security level is provided. The authentication system includes a data retention means that accumulates first data related to a state of the electronic device being used by a first user registered in advance and generates a first data group, a first authentication means that authenticates a second user operating the electronic device as the first user and releases a locked state, a data acquisition means that acquires second data related to a state of the electronic device being used by the second user in a state where the locked state is released, and a second authentication means that authenticates the second user as the first user on the basis of the first data group and the second data and sets the electronic device to the locked state when the second user is not authenticated. The data retention means has a function of deleting the oldest first data of the plurality of pieces of the first data included in the first data group.
Provided are: an information processing system excellent in convenience and usefulness; and an operation method for the same. The information processing device has functions of: receiving a divisional examination instruction; acquiring patent family data corresponding to application information input by the divisional examination instruction; creating claim classification data in which claim data included in the patent family data is classified into one or more claim groups; and outputting, as a division candidate group, a claim group without an application in a divisional examination country in the claim classification data.
The present invention provides a display device having a narrow bezel area. Provided is a flexible display device. The display device has first and second areas. The first area includes an area where content can be displayed. The second area includes an area where the display device can be folded. The second area includes an area lacking a release layer. The lack of a release layer allows for a reduction in the thickness of the folded portion. This means that a smaller radius of curvature can be achieved when said portion is folded. With this arrangement, the bezel area of the display device can be made narrower.
G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
77.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
Provided is a highly reliable semiconductor device. The semiconductor device has a trench capacitor. The semiconductor device has an insulating layer provided with an opening. A first electrode of the capacitor is provided along a side surface of the opening of the insulating layer. An upper end surface of the first electrode has a lower height from a reference surface than an upper surface of the insulating layer. A ferroelectric layer containing oxygen is provided so as to have a region in contact with the first electrode in the opening. A region of the first electrode in contact with the ferroelectric layer becomes an oxide region. A second electrode of the capacitor is provided on the ferroelectric layer so as to have a region facing the first electrode across the ferroelectric layer in the opening.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
The present invention provides a semiconductor device that suppresses variations in calculation results. The semiconductor device includes a voltage generation circuit, a drive circuit, and an arithmetic cell. The voltage generation circuit has a plurality of first output terminals. The drive circuit has a first selector circuit, a transistor, and a switch. The first selector circuit has a plurality of first input terminals, a plurality of second input terminals, and a second output terminal. The voltage generation circuit generates a plurality of analog potentials by a resistance voltage division method, and gives each of the plurality of analog potentials to the plurality of first input terminals. Due to the fact that digital data is given to each of the plurality of second input terminals, the first selector circuit establishes an electrically conductive state between one of the plurality of first input terminals and the second output terminal in accordance with the digital data, and applies the analog potential of the selected first input terminal to the gate of the transistor. The first transistor generates a first current in an amount corresponding to one of the analog potentials applied to the gate and provides the first current to the arithmetic cell.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
A memory device that can be miniaturized or highly integrated is provided. A transistor includes a first conductor including a columnar region, a first insulator including a first region of a tubular shape, a second conductor including an opening penetrated by the first conductor, a first semiconductor positioned over the second conductor and including a second region of a tubular shape, and a third conductor over the first semiconductor. The first region of the first insulator surrounds the columnar region of the first conductor. The first conductor includes a third region positioned above the opening of the second conductor. The third region of the first conductor is surrounded by the second region of the first semiconductor with the first region of the first insulator therebetween.
A display apparatus with high display quality is provided. A high-resolution display apparatus is provided. The display apparatus includes a plurality of pixels, and the pixels each include a light-emitting device, a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. One electrode of the light-emitting device is electrically connected to one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, and one electrode of the first capacitor. A gate of the second transistor is electrically connected to the other electrode of the first capacitor, one of a source and a drain of the third transistor, and one of a source and a drain of the fourth transistor. One frame period of each of the pixels includes a period in which the first transistor and the fourth transistor are each in a conduction state.
A high-definition liquid crystal display device is provided. A liquid crystal display device with a high aperture ratio is provided. A liquid crystal display device with a high contrast ratio and display quality is provided. A liquid crystal display device capable of being driven at a low voltage is provided. The display device includes, between a pair of substrates, a pixel electrode, a first common electrode, a second common electrode, and a liquid crystal layer. The pixel electrode and the first common electrode are positioned between the liquid crystal layer and one of the substrates. The second common electrode is positioned between the liquid crystal layer and the other substrate. The same potential is supplied to the first common electrode and the second common electrode. The first common electrode includes a portion overlapping with the second common electrode between the display regions of two adjacent subpixels that exhibit different colors. At least one of the pixel electrode and the first common electrode includes a portion that does not overlap with the second common electrode in the display region of the subpixel.
The present invention provides a transistor capable of carrying large currents or having a small footprint. Provided is a semiconductor device including the following. A pair of first spacer layers are spaced apart and located above a first insulating layer. A first semiconductor layer is located above the pair of first spacer layers and has a region that does not overlap the pair of first spacer layers. A pair of first conductive layers are spaced apart and have a portion located above the first semiconductor layer. A third insulating layer has a portion located on the pair of first conductive layers, a portion in contact with a lateral surface of the pair of first conductive layers, and a portion in contact with the first insulating layer. A second insulating layer has a portion in contact with an upper surface, a lower surface, and a lateral surface in the region of the first semiconductor layer that does not overlap the pair of first spacer layers. A second conductive layer has a portion surrounding the upper surface, the lower surface, and the lateral surface of the first semiconductor layer, with the second insulating layer interposed therebetween.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
Provided is a storage device with a novel configuration. A sense circuit, a first sense amplifier section, a second sense amplifier section, a word-line–side drive circuit section, a sense amplifier drive circuit section, and a controller section are included. A sense amplifier drive block control signal is a signal for setting a state in which a plurality of sense amplifier drive blocks control sense amplifier blocks. A word-line–side drive block control signal is a signal for setting a state in which a plurality of word-line–side drive blocks output a word signal to a memory cell connected to the first sense amplifier blocks and output a sense circuit control signal to the sense circuit connected to the memory cell. The memory cell and the sense circuit each have a first transistor. The first transistor has a first semiconductor layer having an oxide semiconductor in a channel formation region.
Provided is a semiconductor device that allows for miniaturization and a high level of integration. In this semiconductor device, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer are laminated, in that order. The third insulating layer, the second conductive layer, and the second insulating layer have an opening reaching the first conductive layer. A semiconductor layer has a portion covering each of an upper surface of the first conductive layer, a lateral surface of the opening in the second insulating layer, a lateral surface of the opening in the second conductive layer, and a lateral surface of the opening in the third insulating layer. The semiconductor layer is processed using, as a mask, a first layer formed so as to fill in the opening. The height of the upper surface of the first layer is lower than the height of the upper surface of the third insulating layer.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
H10B 99/00 - Subject matter not provided for in other groups of this subclass
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
88.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a semiconductor device having a high operating speed. This semiconductor device comprises: a semiconductor layer; a first conductive layer and a second conductive layer spaced apart from each other on the semiconductor layer; a first insulating layer disposed on the first conductive layer and the second conductive layer and having a first opening; a second insulating layer having a second opening and disposed in contact with a part of the upper surface of the first conductive layer and a part of the upper surface of the second conductive layer at a position overlapping the first opening; a third insulating layer in contact with a side surface of the first conductive layer in the second opening; a fourth insulating layer in contact with a side surface of the second conductive layer in the second opening; a fifth insulating layer disposed in the first opening and in contact with a part of the upper surface of the semiconductor layer, a side surface of the third insulating layer, a side surface of the fourth insulating layer, and a part of the upper surface of the second insulating layer; and a third conductive layer disposed on the fifth insulating layer in the first opening and having a region overlapping the semiconductor layer via the fifth insulating layer.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes a transistor, a first interlayer insulating layer, and a second interlayer insulating layer over the first interlayer insulating layer. The transistor includes a first conductive layer functioning as one of a source electrode and a drain electrode and a second conductive layer functioning as the other of the source electrode and the drain electrode, and the first and second interlayer insulating layers are provided between the first conductive layer and the second conductive layer. An opening portion reaching the first conductive layer is provided in the first and second interlayer insulating layers and the second conductive layer, and a semiconductor layer, a first gate insulating layer, and a first gate electrode are provided in this order to include regions positioned in the opening portion. A second gate electrode is provided between the first interlayer insulating layer and the second interlayer insulating layer to cover a side surface of the semiconductor layer. The second gate electrode includes an oxide region including a region in contact with the semiconductor layer. The oxide region functions as a second gate insulating layer.
A lithium-ion secondary battery with high discharge capacity and favorable rate characteristics is provided. The lithium-ion secondary battery includes a positive electrode, a negative electrode, and a first electrolyte solution, in which the positive electrode includes a positive electrode active material; the positive electrode active material has an olivine crystal structure and includes lithium, manganese, iron, aluminum, phosphorus, and oxygen; an atomic ratio of manganese to the sum of manganese, iron, and aluminum (Mn/(Mn+Fe+Al)) in the positive electrode active material is greater than 0.5; and an atomic ratio of aluminum to the sum of manganese, iron, and aluminum (Al/(Mn+Fe+Al)) in the positive electrode active material is greater than or equal to 0.01 and less than 0.1.
c/o Semiconductor Energy Laboratory Co., Ltd. (Japan)
Inventor
Inoue, Hiroki
Yoneda, Seiichi
Abstract
A semiconductor device that level-shifts a negative voltage and/or a positive voltage is provided. The semiconductor device includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, an input terminal, and an output terminal. A first terminal of the first transistor is electrically connected to a first terminal of the second transistor and the output terminal. A second terminal of the second transistor is electrically connected to a first terminal of the third transistor. A first terminal of the fourth transistor is electrically connected to a gate of the second transistor and a first terminal of the first capacitor, and a second terminal of the first capacitor is electrically connected to the input terminal. The first transistor, the second transistor, the third transistor, and the fourth transistor are of the same polarity.
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
92.
METHOD FOR PRODUCING POSITIVE ELECTRODE ACTIVE MATERIAL, METHOD FOR PRODUCING SECONDARY BATTERY, METHOD FOR PRODUCING POROUS CARBON, POSITIVE ELECTRODE ACTIVE MATERIAL, AND SECONDARY BATTERY
Provided are a high-capacity lithium-ion secondary battery, and a positive electrode active material used for the same. Also provided is a porous carbon that can be used in the positive electrode active material. Provided is a method for producing a positive electrode active material, in which a porous carbon and sulfur are mixed and subjected to a heat treatment at from 120°C to 160°C for from 1 to 10 hours. The porous carbon is obtained by: mixing a spherical resin, a base having a weight of from 1.0 to 2.0 times a weight of the spherical resin, and water; subjecting the mixture to a first heat treatment performed in an inert atmosphere at from 700°C to 1000°C for from 1 to 20 hours; and then washing, performing a treatment with an acidic solution, washing, and crushing. The volume of pores of the porous carbon having a pore diameter of 2.0 nm or less as calculated by an MP method is from 0.70 to 1.2 cm3/g.
H01M 4/58 - Selection of substances as active materials, active masses, active liquids of inorganic compounds other than oxides or hydroxides, e.g. sulfides, selenides, tellurides, halogenides or LiCoFySelection of substances as active materials, active masses, active liquids of polyanionic structures, e.g. phosphates, silicates or borates
C01B 32/318 - Preparation characterised by the starting materials
H01M 4/36 - Selection of substances as active materials, active masses, active liquids
H01M 4/38 - Selection of substances as active materials, active masses, active liquids of elements or alloys
The purpose of the present invention is to provide a lithium-ion battery having a large discharge capacity and good rate characteristics. This lithium-ion battery has a positive electrode, a negative electrode, and a first electrolyte. The positive electrode has a positive electrode active material. The positive electrode active material has an olivine-type crystal structure, and has lithium, manganese, iron, zinc, phosphorus, and oxygen, where the atomic ratio of manganese to the sum of manganese, iron, and zinc contained in the positive electrode active material (Mn/(Mn + Fe + Zn)) exceeds 0.5, and the atomic ratio of zinc in the sum of manganese, iron, and zinc contained in the positive electrode active material (Zn/(Mn + Fe + Zn)) is 0.01 or more and less than 0.05.
H01M 4/58 - Selection of substances as active materials, active masses, active liquids of inorganic compounds other than oxides or hydroxides, e.g. sulfides, selenides, tellurides, halogenides or LiCoFySelection of substances as active materials, active masses, active liquids of polyanionic structures, e.g. phosphates, silicates or borates
The purpose of the present invention is to provide an electronic apparatus which is small in size and light in weight and has a high light utilization efficiency. An electric apparatus according to the present invention has a display device, reflective polarization plates (41, 44), and an optical rotator (43), and can constitute a catadioptric system (30) having a high light utilization efficiency without using a half mirror. A display panel (31) capable of time division emission of R (red light), G (green light), and B (blue light) light is used as the display device, and a Faraday rotator having the function of changing the magnetic flux density of a generated magnetic field is used as the optical rotator (43). Accordingly, the rotation angle with respect to the polarized light of each of R, G, and B can be controlled, and the rotation angle of the light of each wavelength can be aligned.
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
G09F 9/35 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being liquid crystals
The present invention provides a semiconductor device having reduced power consumption. This semiconductor device includes a first inverter, a second inverter, a first analog switch, a first transistor, and a capacitive element. In particular, the first inverter has a second transistor and a third transistor. Each of the first transistor and the second transistor is an IO transistor, and the third transistor is an Si transistor. An output terminal of the second inverter is connected to a first terminal of the first transistor, and a second terminal of the first transistor is connected to a first terminal of the capacitive element and an input terminal of the first inverter. An output terminal of the first inverter is connected to a first terminal of the first analog switch, and a second terminal of the first analog switch is connected to an input terminal of the second inverter. A gate of the first transistor is connected to a first interconnect, and a p-channel–side control terminal of the first analog switch is connected to the first interconnect.
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/70 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
H10B 99/00 - Subject matter not provided for in other groups of this subclass
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
96.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
The present invention provides a semiconductor device having a transistor with high field-effect mobility. The semiconductor device has a semiconductor layer, a first conductive layer, and a first insulating layer. The first insulating layer is located on the semiconductor layer. The first conductive layer has a region overlapping the semiconductor layer with the first insulating layer interposed therebetween. The semiconductor layer contains crystalline indium oxide. The semiconductor layer is between 1 nm and 10 nm thick, inclusive. The semiconductor layer contains crystal grains. The grain size of the crystal grains is 0.3 μm or larger. The semiconductor layer preferably has a first region and a second region that do not overlap the first conductive layer. Preferably, the first region and the second region each contain a first element. The first element is preferably one or more of hydrogen, boron, and phosphorus.
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
H01L 21/363 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using physical deposition, e.g. vacuum deposition, sputtering
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
The present invention provides a lithium-ion secondary cell with good charge–discharge cycle characteristics. The lithium-ion secondary cell has a positive electrode and a negative electrode. The positive electrode has positive electrode active material particles containing magnesium, fluorine, and lithium cobalt oxide. In XPS analysis of the positive electrode active material particles, the atomic ratio Mg/Co of magnesium and cobalt is 1.00 or more, and when the Mg1s peak is analyzed, the O-Mg-F bond–derived peak component is 10% or more. When the positive electrode active material particles are analyzed by STEM-EDX, there is a region of a surface layer portion where the magnesium concentration is 7 atomic percent or more.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
A semiconductor device having high storage density is provided. The semiconductor device includes a first layer and a second layer above the first layer. The first layer includes first to fourth conductors, first to fifth insulators, and a first semiconductor, and the second layer includes fifth to seventh conductors, sixth and seventh insulators, and a second semiconductor. The first insulator, the second conductor, the second insulator, and the third conductor are formed in this order over the first conductor, and a first opening having a bottom surface of the first conductor is provided in the first insulator, the second insulator, and the third conductor. In the first opening, a first semiconductor, the fourth insulator, and the fourth conductor are formed in this order. The third insulator is positioned on a side surface of the third conductor and a top surface of the second insulator. The fifth conductor is positioned on a top surface of the fourth conductor and a top surface of the fifth insulator. The sixth insulator and the sixth conductor are formed in this order over the fifth conductor, and a second opening with a bottom surface of the fifth conductor is provided in the sixth insulator and the sixth conductor. In the second opening, a second semiconductor, a seventh insulator, and a seventh conductor are formed in this order.
To reduce power consumption and suppress display degradation of a liquid crystal display device. To suppress display degradation due to an external factor such as temperature. A transistor whose channel formation region is formed using an oxide semiconductor layer is used for a transistor provided in each pixel. Note that with the use of a high-purity oxide semiconductor layer, off-state current of the transistor at a room temperature can be 10 aA/μm or less and off-state current at 85° C. can be 100 aA/μm or less. Consequently, power consumption of a liquid crystal display device can be reduced and display degradation can be suppressed. Further, as described above, off-state current of the transistor at a temperature as high as 85° C. can be 100 aA/μm or less. Thus, display degradation of a liquid crystal display device due to an external factor such as temperature can be suppressed.
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
G06F 3/041 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
G06F 3/044 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
G06F 3/045 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using resistive elements, e.g. a single continuous surface or two parallel surfaces put in contact
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
The secondary battery includes a positive electrode active material which exhibits a broad peak at around 4.55 V in a dQ/dVvsV curve obtained when the charge depth is increased. The secondary battery includes a positive electrode active material which, even when the charge voltage is greater than or equal to 4.6 V and less than or equal to 4.8 V and the charge depth is greater than or equal to 0.8 and less than 0.9, does not have the H1-3 type structure and can maintain a crystal structure where a shift in CoO2 layers is inhibited. The broad peak at around 4.55 V in the dQ/dVvsV curve indicates that a change in the energy necessary for extraction of lithium at around the voltage is small and a change in the crystal structure is small.
H01M 4/58 - Selection of substances as active materials, active masses, active liquids of inorganic compounds other than oxides or hydroxides, e.g. sulfides, selenides, tellurides, halogenides or LiCoFySelection of substances as active materials, active masses, active liquids of polyanionic structures, e.g. phosphates, silicates or borates
H01M 4/38 - Selection of substances as active materials, active masses, active liquids of elements or alloys
