An electric field sensor includes a gas cell having a first terminal and a second terminal. A ground plane is proximate the gas cell. A transmitter has an input and an output. The transmitter's output is communicatively coupled to the first terminal of the gas cell. A receiver has an input and an output. The receiver's input is communicatively coupled to the second terminal. A processing circuit has a processing circuit input and a processing circuit output. The processing circuit input is coupled to the output of the receiver, and the processing circuit output is coupled to the input of the transmitter.
An apparatus an apparatus includes a light source and freeform optics optically coupled to the light source. The apparatus also includes a spatial light modulator (SLM) optically coupled to the freeform optics and a prism optically coupled between the freeform optics and the SLM. Additionally, the apparatus includes eyepiece optics optically coupled to the prism.
Various examples disclosed herein relate to controlling access to non-volatile memory devices. In an example embodiment, a device is provided. The device includes a memory security controller configured to operate in a first functional safety mode or a second functional safety mode, a security mode selection controller coupled to the memory security controller, and a memory interface controller coupled to the memory security controller and the security mode selection controller and configured to couple to a non-volatile memory. The security mode selection controller is configured to determine a number of pending access requests associated with the memory security controller, determine a number of incoming responses from the non-volatile memory to the memory security controller, and select between the first functional safety mode and the second functional safety mode based on at least one of the number of pending access requests or the number of incoming responses.
This invention is a technique for coordinate multi-point wireless transmission between a plurality of geographically separated transmission points (TP) and at least one user equipment (UE).
H04L 5/00 - Arrangements affording multiple use of the transmission path
H04B 7/024 - Co-operative use of antennas at several sites, e.g. in co-ordinated multipoint or co-operative multiple-input multiple-output [MIMO] systems
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
5.
REDUCING SLICE HEADER PARSING OVERHEAD IN VIDEO CODING
A method for encoding a picture of a video sequence in a bit stream that reduces slice header parsing overhead is provided. The method includes determining weighting factors that may be used for weighted prediction in encoding at least one slice of the picture, wherein a total number of the weighting factors is constrained to not exceed a predetermined threshold number of weighting factors, wherein the threshold number is less than a maximum possible number of weighting factors, and signaling weighted prediction parameters including the weighting factors in a slice header in the bit stream.
H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
H04N 19/159 - Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
H04N 19/174 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
H04N 19/196 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding being specially adapted for the computation of encoding parameters, e.g. by averaging previously computed encoding parameters
H04N 19/23 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video object coding with coding of regions that are present throughout a whole video segment, e.g. sprites, background or mosaic
H04N 19/46 - Embedding additional information in the video signal during the compression process
H04N 19/503 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
6.
Method and System for FOTA Update for Higher Performance MCU with External Flash
Systems and methods for updating firmware may include using wait states to reduce or eliminate polling by an executing firmware component. An example includes dedicated firmware update hardware logic components, including a firmware update processing unit that executes firmware update code. The firmware update code may be paused between request of a hardware event and completion of a hardware event and under control of one or more of the hardware logic components. Once a hardware event has been completed, a hardware logic component may determine completion and, in response, restart execution of the firmware update code.
A semiconductor device (100) includes a heterojunction bipolar transistor (HBT) (104) having a collector (106), a base, and an emitter (130). The base includes a monocrystalline base layer (124), including silicon-germanium, on the collector (106), and an extrinsic base layer (112), including polycrystalline silicon, extending partway over the monocrystalline base layer (124). The base further includes a base link (126), including polycrystalline silicon-germanium, connecting the monocrystalline base layer (124) to the extrinsic base layer (112). An emitter spacer (122), of dielectric material, laterally separates the emitter (130) from the extrinsic base layer (112). The HBT (104) has a spacer-extrinsic base vertical offset (136) between a bottom of the emitter spacer (122) and a bottom surface of the extrinsic base layer (112) adjacent to the emitter spacer (122). The emitter spacer (122) has a bottom width (138) at a bottom of the emitter spacer (122). A sum of the spacer-extrinsic base vertical offset (136) and the bottom width (138) of the emitter spacer (122) is greater than the thickness (140) of the monocrystalline base layer (124).
An example apparatus includes: class D amplifier circuitry (130) having a first input, a second input, a third input, and an output, the first input of the class D amplifier circuitry (130) coupled to the output of the class D amplifier circuitry (130); and class AB amplifier circuitry (140) having a first input, a second input, a third input, and an output, the first input of the class AB amplifier circuitry (140) coupled to the first input of the class D amplifier circuitry (130) and the output of the class D amplifier circuitry (130), the second and third inputs of the class AB amplifier circuitry (140) coupled to the second and third inputs of the class D amplifier circuitry (130), and the output of the class AB amplifier circuitry (140).
An electronic device includes a first resonator electrode (235 A) and a second resonator electrode (235B) in an interconnect stack (210) over a semiconductor substrate (201). The first resonator electrode includes a first lower resonator electrode (220A), a first upper resonator electrode (225 A) and a first plurality of vias (215 A) between the first lower resonator electrode and the first upper resonator electrode. The second resonator electrode includes a second lower resonator electrode (220B), a second upper resonator electrode (225B), and a second plurality of vias (215B) between the second lower resonator electrode and the second upper resonator electrode. A cavity (230) in the interconnect stack is bounded by the first resonator electrode and the second resonator electrode. An electron emitter (205) extends from the semiconductor surface between the first and second resonator electrodes and is configured to direct electrons into the cavity. The electronic device may be operated to produce short wavelength radiation, e.g. x-rays.
A voltage-to-delay converter includes a first reset transistor (402P) having a first terminal coupled to a power supply terminal, a gate terminal receiving a reset signal (CLK_RST), and a second terminal coupled to a top plate of a first integrating capacitor (404P), and a second reset transistor (402M) having a first terminal coupled to a power supply terminal, a gate terminal receiving the reset signal (CLK_RST), and a second terminal coupled to a top plate of a second integrating capacitor (404M). First and second input transistors (412P, 412M) receive first and second input voltages (INP, INM), and are coupled between the top plate of the first and second integrating capacitors, respectively, and a first current source (410). A discharge current source (406) is coupled to bottom plates of the first and second integrating capacitors. A pulse generator (330) has first and second inputs coupled to the top plate of the first and second integrating capacitors, respectively.
An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem including a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller configured to receive a read request from the L1 controller as a single transaction. Read request includes a read address, a first indication of an address and a coherence state of a cache line A to be moved from the L1 main cache to the L1 victim cache to allocate space for data returned in response to the read request, and a second indication of an address and a coherence state of a cache line B to be removed from the L1 victim cache in response to the cache line A being moved to the L1 victim cache.
G06F 12/0817 - Cache consistency protocols using directory methods
G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
G06F 12/084 - Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
G06F 12/0895 - Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
G06F 12/128 - Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
A method of branch prediction includes determining that a processor is to execute at least a portion of a first set of instructions. An address associated with a sequentially first instruction of the first set of instruction is determined, and a branch prediction index is determined based on the address and a branch history. A table is queried based on the branch prediction index to determine a predicted exit point of the first set of instructions. The processor fetches a subset of the first set of instructions based on the predicted exit point.
Systems and methods for servicing read requests may include receiving a transaction from a processing unit while mirroring contents from an external memory to an on-chip RAM. Such systems and methods may monitor a progress of the mirroring and, based on the monitoring, access code or data values for the transaction from either the external memory or the on-chip RAM. Such systems and methods may further provide the code or data values to the processing unit according to the transaction. Such systems and methods may allow for execution of software before software has been fully downloaded to internal memory.
An ADC includes a comparator to provide a comparator output responsive to an input voltage of the ADC and a DAC output voltage; a SAR circuit including a SAR that stores an n-bit digital code that is initialized at a beginning of a conversion phase of the ADC, where the SAR circuit is to update the digital code responsive to the comparator output, where an ADC output is responsive to the digital code at an end of the conversion phase; and a DAC to provide the DAC output voltage responsive to the digital code and a reference voltage. The DAC includes an m-bit CDAC and an (n-m)-bit RDAC to provide an intermediate voltage responsive to the n-m least-significant bits of the digital code and the reference voltage. The CDAC provides the DAC output voltage responsive to the m most-significant bits of the digital code, the intermediate voltage, and reference voltage.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
H03M 1/20 - Increasing resolution using an n bit system to obtain n + m bits, e.g. by dithering
In some examples, a semiconductor package comprises a semiconductor die; an operational component on an active surface of the semiconductor die; and a cover coupled to the active surface of the semiconductor die and covering the operational component. The cover comprises a monolithic structure including a vertical portion and a horizontal portion. A hollow area is between the cover and the operational component. The package also includes a mold compound covering the semiconductor die and the cover.
A second transistor couples to a first transistor at a switch terminal. A third transistor couples to an auxiliary inductor terminal, and the third transistor also couples to the switch terminal. A logic circuit has a switch terminal, a first, a second, and a third input and first and second outputs. The first output couples to a control input of the third transistor. The second output couples to the second transistor. A configurable delay circuit has modulation, switch terminal, and voltage inputs and first, second, and third outputs. The switch terminal input couples to the switch terminal. The first output of a configurable delay circuit couples to the first input of the logic circuit. The second output of the configurable delay circuit couples to the second input of the logic circuit. The third output of the configurable delay circuit couples to the control input of the first transistor.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
In described examples, an integrated circuit (IC) (100) includes multiple subcircuits, The subcircuits include a first subcircuit (104 and 136) that receives a current and sinks a portion of the current that is responsive to a threshold. In response to the current being greater than the threshold, the first subcircuit (104 and 136) provides a difference between the current and the portion to a second subcircuit (106 and 142) and asserts a signal corresponding to an ordinality of the first subcircuit (104 and 136).
An electronic device includes a first resonator electrode and a second resonator electrode in an interconnect stack over a semiconductor substrate. The first resonator electrode includes a first lower resonator electrode, a first upper resonator electrode and a first plurality of vias between the first lower resonator electrode and the first upper resonator electrode. The second resonator electrode includes a second lower resonator electrode, a second upper resonator electrode, and a second plurality of vias between the second lower resonator electrode and the second upper resonator electrode. A cavity in the interconnect stack is bounded by the first resonator electrode and the second resonator electrode. An electron emitter extends from the semiconductor surface between the first and second resonator electrodes and is configured to direct electrons into the cavity. The electronic device may be operated to produce short wavelength radiation, e.g. x-rays.
A circuit includes a compensation terminal, a current feedback terminal, a voltage feedback terminal, a reference voltage terminal, a modulator, an error amplifier, and average current balancing circuitry. A first input of the modulator is coupled to the current feedback terminal. A first input of the error amplifier is coupled to the voltage feedback terminal. A second input of the error amplifier is coupled to the reference voltage terminal. An output of the error amplifier is coupled to the compensation terminal. A first input of the average current balancing circuitry is coupled to the output of the error amplifier and the compensation terminal. A second input of the average current balancing circuitry is coupled to the current feedback terminal. An output of the average current balancing circuitry is coupled to a second input of the modulator.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
In examples, a package comprises a semiconductor die, a gullwing conductive terminal coupled to the semiconductor die, and a mold compound covering the semiconductor die and the conductive terminal. The conductive terminal extends outward from the mold compound. The conductive terminal includes a top surface and a bottom surface opposing the top surface, the conductive terminal includes a first bend and a second bend more distal from the mold compound than the first bend, and the bottom surface includes a first cavity extending along a width of the conductive terminal at the first bend. The top surface includes a second cavity extending along the width of the conductive terminal at the second bend.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
21.
INTEGRATED CIRCUIT (IC) WITH CORRUGATED CHANNEL STRUCTURE
An integrated circuit (IC) device including one or more corrugated channel structures formed in a top portion of a semiconductor substrate, where a corrugated channel structure includes a first sidewall, a second sidewall and an upper portion. In an example, the corrugated channel structure is provided with a substantially uniform distribution profile of a dopant across a horizontal plane from the first sidewall to the second sidewall.
H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A test load board includes a PCB (printed circuit board) with pads for a probe of a tester. The test load board also includes a contactor that includes contact points for connecting leads of a DUT (device under test). The test load board further includes an RFID (radio frequency identification) tag affixed to the PCB. The RFID tag is loaded with a unique identifier (ID) of the test load board.
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips
23.
INTEGRATED CIRCUIT PACKAGE WITH INTEGRATED HEAT SINK
A packaged integrated circuit (IC) includes a package substrate and an IC on the package substrate. A first material is on the package substrate and encapsulates the IC. An inductor is coupled to the package substrate. A heat sink includes a second material. The heat sink is coupled to the IC. A third material is on the first material and encapsulates the inductor and at least part of the heat sink. The second material has a higher thermal conductivity than the first and third materials.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/373 - Cooling facilitated by selection of materials for the device
24.
DIFFERENTIAL WIDEBAND QUADRATURE SIGNAL GENERATION USING OVER-COUPLED DIRECTIONAL COUPLER
Embodiments disclosed herein relate to quadrature signal generation, and more particularly, to wideband differential quadrature signal generation at millimeter-wave frequencies using over-coupled directional couplers. In an example, a quadrature signal generation sub-circuit includes two conductive strips arranged in parallel with respect to each other on different layers of a metal interconnect of a substrate (i.e., during a complementary metal-oxide semiconductor (CMOS) fabrication process) that form a directional coupler. Each conductive strip has a length and a width configured such that an input end of the first conductive strip and a coupled end of the second conductive strip, that are electromagnetically coupled together, produce an over-coupling factor. The input end may be configured to couple to a local oscillator, and the coupled end may be configured to couple to a mixer. The directional coupler may provide, to the mixer, an output of a desired bandwidth based on the over-coupling factor.
H01P 5/18 - Conjugate devices, i.e. devices having at least one port decoupled from one other port consisting of two coupled guides, e.g. directional couplers
H03F 3/19 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
In an example, a system includes a loop filter including one or more integrators. The system includes a ramp generator. The system includes a comparator having a first input coupled to an output of the loop filter, a second input coupled to an output of the ramp generator, and having an output. The system includes a mute loop coupled to an input of the loop filter and the output of the comparator. The system includes a power stage having an input coupled to the output of the comparator, and having an output. The system includes a main loop coupled to the output of the power stage and the input of the loop filter. The system includes an integrated error detector having an input coupled to the loop filter, and having an output. The system includes a dual comparator having an input coupled to the output of the integrated error detector.
An IC (integrated circuit) package include an interconnect having a die attach pad and lead. The IC package also includes a die with a first side mounted on the die attach pad and a second side opposing the first side. The second side having a planar region. The planar region having selective polyimide structures between contact points of a connection pad. The IC package also includes a clip coupled to the connection pad and to a lead of the leads.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
27.
SEMICONDUCTOR DEVICE PACKAGE WITH INTERNAL MAGNETIC SHIELD FOR HALL SENSOR
A described example includes: a heat slug coupled to a package substrate, the heat slug configured to conduct a current between terminals of the package substrate; a first magnetic shield mounted to a top surface of the package substrate, the first magnetic shield including a die mount area; a semiconductor die flip chip mounted to the die mount area; a second magnetic shield mounted to the package substrate, the second magnetic shield having a cantilever portion extending over a portion of the semiconductor die including a Hall element; electrical connections of wire bonds or ribbon bonds between bond pads of the semiconductor die and leads on the package substrate; and mold compound covering the electrical connections, the semiconductor die, the first magnetic shield, and the second magnetic shield, while a portion of the heat slug is exposed forming a thermal pad for a semiconductor device package.
G01R 15/20 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
A semiconductor device includes a heterojunction bipolar transistor (HBT) having a collector, a base, and an emitter. The base includes a monocrystalline base layer, including silicon-germanium, on the collector, and an extrinsic base layer, including polycrystalline silicon, extending partway over the monocrystalline base layer. The base further includes a base link, including polycrystalline silicon-germanium, connecting the monocrystalline base layer to the extrinsic base layer. An emitter spacer, of dielectric material, laterally separates the emitter from the extrinsic base layer. The HBT has a spacer-extrinsic base vertical offset between a bottom of the emitter spacer and a bottom surface of the extrinsic base layer adjacent to the emitter spacer. The emitter spacer has a bottom width at a bottom of the emitter spacer. A sum of the spacer-extrinsic base vertical offset and the bottom width of the emitter spacer is greater than the thickness of the monocrystalline base layer.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
In described examples, a frequency modulated continuous wave (FMCW) radar includes a reference clock, a phase locked loop (PLL), a pulse generator, a counter, a chirp ramp control circuit, and a synchronization state machine. The reference clock generates a reference clock signal. The PLL generates a feedback clock signal in response to the reference clock signal, and an output signal in response to the feedback clock signal. The pulse generator outputs a chirp start pulse in response to the reference clock signal. The counter increments a count in response to the feedback clock signal. The synchronization state machine provides a chirp ramp signal to a chirp ramp control circuit in response to the reference clock signal, the feedback clock signal, the chirp start pulse, and the count. The chirp ramp control circuit causes the PLL to ramp a frequency of the output signal in response to the chirp ramp signal.
G01S 13/32 - Systems for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated
The present disclosure generally relates to semiconductor processing for a self-aligned gate structure and corresponding semiconductor device. In an example, a semiconductor device includes a semiconductor substrate, a semiconductor gate layer, an offset dielectric layer, and a gate metal contact. The semiconductor gate layer is over the semiconductor substrate. The offset dielectric layer is over the semiconductor gate layer. The gate metal contact is over the offset dielectric layer and is through an opening through the offset dielectric layer. The gate metal contact contacts the semiconductor gate layer through the opening through the offset dielectric layer. A first sidewall of the semiconductor gate layer, a second sidewall of the offset dielectric layer, and a third sidewall of the gate metal contact are vertically aligned over the semiconductor substrate.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
An example apparatus includes: a first transistor having a first terminal and a control terminal; a second transistor having a first terminal and a control terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor; a third transistor having a first terminal and a control terminal; a fourth transistor having a first terminal and a control terminal, the first terminal of the fourth transistor coupled to the first terminal of the third transistor; feedback circuitry coupled to the first transistor, the second transistor, the third transistor and the fourth transistor; current source circuitry having a first terminal and a second terminal, the first terminal of the current source circuitry coupled to the feedback circuitry; slew assist circuitry coupled to the first transistor, the second transistor, the third transistor and the fourth transistor, the feedback circuitry and the current source circuitry.
A microelectronic device includes a hybrid component. The microelectronic device has a substrate including silicon semiconductor material. The hybrid component includes a silicon portion in the silicon, and a wide bandgap (WBG) structure on the silicon. The WBG structure includes a WBG semiconductor material having a bandgap energy greater than a bandgap energy of the silicon. The hybrid component has a first current terminal on the silicon, and a second current terminal on the WBG semiconductor structure. The microelectronic device may be formed by forming the silicon portion of the hybrid component in the silicon, and subsequently forming the WBG structure on the silicon.
A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.
G06F 12/128 - Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
G06F 12/0806 - Multiuser, multiprocessor or multiprocessing cache systems
G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
G06F 12/0817 - Cache consistency protocols using directory methods
G06F 12/0853 - Cache with multiport tag or data arrays
G06F 12/0855 - Overlapped cache accessing, e.g. pipeline
G06F 12/0864 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
G06F 12/0884 - Parallel mode, e.g. in parallel with main memory or CPU
G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
G06F 12/0895 - Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
G06F 12/1027 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F 12/121 - Replacement control using replacement algorithms
G06F 12/126 - Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
G06F 12/127 - Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning using additional replacement algorithms
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
G11C 29/44 - Indication or identification of errors, e.g. for repair
34.
HARDWARE PROTECTION OF INLINE CRYPTOGRAPHIC PROCESSOR
A real time, on-the-fly data encryption system is operable to encrypt and decrypt data flow between a secure processor and an unsecure external memory systen. Multiple memory segments are supported, each with its own separate encryption capability, or no encryption at all. Data integrity is ensured by hardware protection from code attempting to access data across memory segment boundaries. Protection is also provided against dictionary attacks by monitoring multiple access attempts to the same memory location.
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
G06F 12/14 - Protection against unauthorised use of memory
An example apparatus includes: a pullup circuit coupled to a first USB terminal; a first pulldown circuit coupled to the first USB terminal; a second pulldown circuit coupled to a second USB terminal; a third pulldown circuit coupled to a third USB terminal; a fourth pulldown circuit coupled to a fourth USB terminal; a high-speed termination detection circuit including: a current source including a first supply terminal and a second supply terminal, the first supply terminal coupled to the first USB terminal, the second supply terminal coupled to the second USB terminal; a first comparator including a first comparator terminal and a second comparator terminal, the first comparator terminal coupled to the first USB terminal; and a second comparator including a third comparator terminal and a fourth comparator terminal, the third comparator terminal coupled to the second USB terminal; and a controller including a first control terminal and a second control terminal, the first control terminal coupled to the second comparator terminal, the second control terminal coupled to the fourth comparator terminal.
Methods for operating two or more analog-to-digital converters (ADCs) are presented herein. The method may be implemented in an integrated circuit. The integrated circuit may include a first ADC and a second ADC disposed on a single semiconductor die. The integrated circuit may also include logic circuitry operably coupled to the first and second ADCs. For a digital value obtained by conversion, by the first ADC, of a first analog signal sampled by the first ADC during a period of time overlapping with another period of time during which a second analog signal is being converted by the second ADC, the logic circuitry may be configured to cause the digital value to be marked as noisy.
In some examples, a method includes determining a first clock data recovery (CDR) code of a CDR circuit at a first time and determining a second CDR code of the CDR circuit at a second time after the first time. The method also includes generating, by a clock generator, a sampling clock for sampling a received data signal according to the first CDR code while the CDR circuit is active and determining, by an offset circuit, a clock offset based on the first CDR code and the second CDR code. Additionally, the method includes generating, by the clock generator, the sampling clock according to the clock offset responsive to disabling of the CDR circuit.
H04L 7/00 - Arrangements for synchronising receiver with transmitter
G06F 1/12 - Synchronisation of different clock signals
H04L 7/06 - Speed or phase control by synchronisation signals the synchronisation signals differing from the information signals in amplitude, polarity, or frequency
38.
TRANSMIT AND RECEIVE CIRCUITS WITH MULTIPLE INTERFACES
A method includes transmitting first data with a first priority through a first dedicated interface on a transmit side of a PCIe system. The method also includes transmitting second data with a second priority through a second dedicated interface on the transmit side of the PCIe system. The method includes transmitting the first data and the second data to a receive side of the PCIe system using two or more virtual channels over a PCIe link, where the first data uses a first virtual channel and the second data uses a second virtual channel.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
A method and apparatus for sub-picture based raster scanning coding order. The method includes dividing an image into even sub-pictures, and encoding parallel sub-pictures on multi-cores in raster scanning order within sub-pictures, wherein from core to core, coding of the sub-picture is independent around sub-picture boundaries, and wherein within a core, coding of a sub-picture is at least one of dependent or independent around sub-picture boundaries.
H04N 19/129 - Scanning of coding units, e.g. zig-zag scan of transform coefficients or flexible macroblock ordering [FMO]
H04N 19/119 - Adaptive subdivision aspects e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
H04N 19/174 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
H04N 19/433 - Hardware specially adapted for motion estimation or compensation characterised by techniques for memory access
H04N 19/436 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
A wafer chip scale package (WCSP) (104) comprises first and second dies (200, 202) in differing voltage domains and an isolation material (204) between the first and second dies and contacting multiple surfaces of each of the first and second dies. The package also comprises a first resin material (206) contacting multiple surfaces of the isolation material, with the isolation material between the resin material and the first and second dies. The package also comprises a fiberglass material (208) contacting a surface of the resin material and a second resin material (210) contacting a surface of the fiberglass material. The package also comprises first and second conductive structures (230, 226) coupled to the first and second dies, respectively. The package also includes a passivation material (224) contacting the first and second dies and the first and second conductive structures.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
41.
SEMICONDUCTOR PACKAGE WITH SHUNT AND PATTERNED METAL TRACE
A semiconductor package includes a first layer including a semiconductor die and a shunt embedded within a first dielectric substrate layer, and metal pillars extending therethrough. The semiconductor package further includes a second layer stacked on the first layer, the second layer including a metal trace patterned on the first dielectric substrate layer, and a second dielectric substrate layer over the metal trace. The metal trace electrically connects a first portion of the shunt to a first metal pillar of the metal pillars and electrically connects a second portion of the shunt to a second metal pillar of the metal pillars. The semiconductor package further includes a base layer opposite the second layer relative the first layer, the base layer forming exposed electrical contact pads for the semiconductor package, the electrical contact pads providing electrical connections to the shunt, the metal pillars, and the semiconductor die.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
42.
METHODS AND APPARATUS TO MODULATE SIGNALS USING MULTI-CLASS MODULATION CIRCUITRY
An example apparatus includes: class D amplifier circuitry having a first input, a second input, a third input, and an output, the first input of the class D amplifier circuitry coupled to the output of the class D amplifier circuitry; and class AB amplifier circuitry having a first input, a second input, a third input, and an output, the first input of the class AB amplifier circuitry coupled to the first input of the class D amplifier circuitry and the output of the class D amplifier circuitry, the second and third inputs of the class AB amplifier circuitry coupled to the second and third inputs of the class D amplifier circuitry, and the output of the class AB amplifier circuitry.
An example circuit includes a substrate including a first transistor of a gate driver output stage, the substrate including a first well region; a diode circuit including a first terminal and a second terminal, the first terminal coupled to a first tap of the first well region; and a second transistor including a first terminal, a second terminal, and a body, the first terminal of the second transistor coupled to a switching voltage terminal, and the second terminal and the body of the second transistor coupled to the first tap of the first well region and to the first terminal of the diode circuit.
H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
An electronic device includes opposite first and second sides, opposite third and fourth sides spaced apart along a first direction, and opposite fifth and sixth sides spaced apart along a second direction orthogonal to the first direction, the first and second sides being spaced apart along a third direction orthogonal to the first and second directions. The electronic device includes a molded package, first leads exposed outside the molded package along the first side, and the first leads extending outward from the molded package along a respective one of the third and fourth sides, and second leads exposed outside the molded package along the first side, the second leads having a lateral side exposed outside the molded package along a respective one of the fifth and sixth sides, and the lateral side of the individual second leads being flush with a respective side of the molded package.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
In an example, a method includes transmitting a plurality of wake-up frames on a transmission channel from a first node having a first priority. The method also includes pausing the wake-up frames from the first node and listening to the transmission channel after a predetermined number of wake-up frames are transmitted from the first node. The method also includes receiving, at the first node, a wake-up frame from a second node on the transmission channel, wherein the second node has a second priority.
H04W 72/566 - Allocation or scheduling criteria for wireless resources based on priority criteria of the information or information source or recipient
An acoustic device is provided which comprises an audio system including: a microphone having a microphone output, and a processing circuit having a wakeup input, an audio input, and an audio output, the audio input coupled to the microphone output. In at least one example, the acoustic device further comprises an acoustic sensor separate from the microphone, the acoustic sensor having a sensor output. In at least one example, the acoustic device further comprises a wakeup circuit having a sensor input and a wakeup output, the sensor input coupled to the sensor output, wherein the wakeup output is coupled to the wakeup input.
An electronic device includes a package structure having opposite first and second sides, opposite third and fourth sides spaced along a first direction, opposite fifth and sixth sides spaced along an orthogonal second direction, the first and second sides spaced along a third direction orthogonal to the first and second directions, and an opening extending into the first side along the third direction, a first semiconductor die having a first side exposed in the opening of the package structure and an opposite second side partially enclosed by the package structure, and a second semiconductor die electrically connected to the first semiconductor die, the second semiconductor die enclosed by the package structure and laterally spaced apart from the first semiconductor die.
A device comprises a U-shaped cell configured to contain a quantum gas, a first waveguide coupled to an inlet of the U-shaped cell, and a second waveguide coupled to an outlet of the U-shaped cell. The device also comprises a multi-layer substrate including transmitter and receiver antennas that are aligned with the first and second waveguides, respectively, the substrate including a network of metal layers coupled to the transmitter and receiver antennas. The device also includes transmitter and receiver dies coupled to the transmitter and receiver antennas, respectively, by way of the network of metal layers, the substrate positioned between the U-shaped cell and the transmitter and receiver dies.
A wafer chip scale package (WCSP) comprises first and second dies in differing voltage domains and an isolation material between the first and second dies and contacting multiple surfaces of each of the first and second dies. The package also comprises a first resin material contacting multiple surfaces of the isolation material, with the isolation material between the resin material and the first and second dies. The package also comprises a fiberglass material contacting a surface of the resin material and a second resin material contacting a surface of the fiberglass material. The package also comprises first and second conductive structures coupled to the first and second dies, respectively. The package also includes a passivation material contacting the first and second dies and the first and second conductive structures.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A package comprises a semiconductor die having a device side in which circuitry is formed and first and second metal members coupled to and extending away from the device side. The package also comprises a passivation layer contacting the device side, at least a portion of the passivation layer positioned between the first and second metal members, the passivation layer including a top surface facing away from the semiconductor die. The package further comprises multiple passivation layer protrusions (PLPs) coupled to and extending away from the top surface, the multiple PLPs having heights ranging from 0.5 microns to 50 microns.
A package comprises a semiconductor die including a device side having circuitry formed therein. The package includes a metal member coupled to the device side and a nanotwin copper member having a bottom surface coupled to the metal member, the nanotwin copper member comprising a twin boundary separating a first region having a first grain structure from a second region having a second grain structure. The package also comprises a wire bond coupled directly to a top surface of the nanotwin copper member, the wire bond contacting multiple regions of the nanotwin copper member. The package also comprises a mold compound covering the die, the metal member, the nanotwin copper member, and the wire bond.
A package comprises a semiconductor die including a device side having circuitry formed therein and a first metal member on the device side of the die and having a top surface facing away from the die. The first metal member includes a group of dielectric members, each dielectric member in the group of dielectric members extending at least partially through a thickness of the first metal member. The package also comprises solder material contacting the top surface of the first metal member and top surfaces of the dielectric members in the group of dielectric members. The package also includes a second metal member coupled to the solder material and to a conductive terminal of the package, the conductive terminal exposed to an exterior of the package.
An integrated circuit comprises a charge pump connected to a power source terminal and to a ground terminal, the charge pump having a charge pump output terminal; and a switch matrix having a plurality of switch matrix inputs and a plurality of switch matrix outputs, wherein pairs of the plurality of switch matrix outputs are connected to respective ones of a respective plurality of output terminals, and wherein the charge pump output terminal is connected to a first subset comprising at least three of the plurality of switch matrix inputs.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 1/32 - Means for protecting converters other than by automatic disconnection
A voltage-to-delay converter includes a first reset transistor having a first terminal coupled to a power supply terminal, a gate terminal receiving a reset signal, and a second terminal coupled to a top plate of a first integrating capacitor, and a second reset transistor having a first terminal coupled to a power supply terminal, a gate terminal receiving the reset signal, and a second terminal coupled to a top plate of a second integrating capacitor. First and second input transistors receive first and second input voltages, and are coupled between the top plate of the first and second integrating capacitors, respectively, and a first current source. A discharge current source is coupled to bottom plates of the first and second integrating capacitors. A pulse generator has first and second inputs coupled to the top plate of the first and second integrating capacitors, respectively.
A system for prefetching program code from flash memory that includes processing circuitry configured to execute program code and prefetch circuitry coupled to the processing circuitry. In an implementation, the prefetch circuitry is configured to analyze branch logic within the program code to identify a block of code to prefetch from flash memory. Once identified, the prefetch circuitry causes the block of code to be prefetched from flash memory and loaded to a memory buffer. In another implementation, the prefetch circuitry is further configured to receive a request to supply the processing circuitry with the block of code. Upon receiving the request, the prefetch circuitry determines that the block of code has already been fetched and loaded in the memory buffer. Once identified in the memory buffer, the prefetch circuitry causes the block of code to be supplied to the processing circuitry.
Described examples include a semiconductor device having a first p-channel field effect transistor (p-FET). The first p-FET includes: a first gate dielectric layer on a surface of a substrate; a first gate structure on the first gate dielectric layer; and first silicon-germanium (SiGe) regions disposed in the substrate, on both sides of the first gate structure, the first SiGe regions extended to a first depth from the surface of the substrate. The semiconductor device also has a second p-FET. The second p-FET includes a second gate dielectric layer on the surface of the substrate; a second gate structure on the second gate dielectric layer; and second SiGe regions disposed in the substrate, on both sides of the second gate structure, the second SiGe regions extended to a second depth from the surface of the substrate, the second depth different than the first depth.
Various examples disclosed herein relate to deterministically controlling interconnect operations to provide dynamic power gating for a system. In an example, a microcontroller unit (MCU) is provided that includes a group of processing devices, a group of target resources, interconnect circuitry, and clock control circuitry. The interconnect circuitry connects the group of processing devices to the group of target resources. The clock control circuitry is coupled to the interconnect circuitry. The clock control circuitry is configured to identify an upcoming occurrence of a communication between a pair of devices comprised of one of the processing devices and one of the target resources, and prior to the occurrence of the communication, enable a clock associated with a path through the interconnect circuitry between the pair of devices.
In described examples, an integrated circuit (IC) includes multiple subcircuits. The subcircuits include a first subcircuit that receives a current and sinks a portion of the current that is responsive to a threshold. In response to the current being greater than the threshold, the first subcircuit provides a difference between the current and the portion to a second subcircuit and asserts a signal corresponding to an ordinality of the first subcircuit. The second subcircuit is configured to repeat the actions with respect to the first subcircuit, with the second subcircuit in place of the first subcircuit and a third subcircuit in place of the second subcircuit, and with the difference in place of the current, in response to the IC comprising the third subcircuit.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
59.
ELECTROSTATIC DISCHARGE DEVICES WITH METALLIZED DIES
In examples, a method for manufacturing a package comprises depositing a metal contact layer on a surface of a wafer, the wafer including first and second diodes; positioning the wafer on an expandable tape coupled to a carrier; dicing the wafer to produce first and second dies, the first die including the first diode and the second die including the second diode; wire bonding the first die to the second die using a bond wire; covering the first and second dies and the bond wire with a mold compound to produce a molded structure; decoupling the molded structure from the expandable tape; and sawing the molded structure to produce the package.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/00 - Details of semiconductor or other solid state devices
60.
INTEGRATED DEEP TRENCH CAPACITOR HAVING HIGH CAPACITANCE DENSITY AND VOLTAGE LINEARITY
An integrated circuit including an integrated trench capacitor in a substrate. The trench capacitor includes a plurality of deep trenches extending into the substrate, the trenches filled with a conductive trench-fill material. A first subset of the trenches located in an N-type well and a second subset of the trenches located in a P-type well. A first capacitor terminal connects the conductive trench-fill material in the first subset of trenches and the conductive trench-fill material in the second subset of trenches. A second capacitor terminal connects the N-type well and the P-type well.
H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
An example apparatus includes: a wire bond tool including a bond wire capillary having a central opening configured for receiving a bond wire in the central opening; a first laser path formed in the capillary configured to focus a first laser beam on the end of the bond wire to form a free air ball; and a second laser path formed in the capillary configured to focus a second laser beam on a bonding location beneath the capillary.
In described examples, a device includes a non-transitory memory and a processor. The memory stores a first instruction. The processor receives the first instruction from the memory. Executing the first instruction causes the processor to perform the following actions. The processor receives a position vector corresponding to a sum of a first component in a first dimension and a second component in a second dimension. The processor compares a magnitude of the first component to a magnitude of the second component, and compares the first component or the second component to zero. And the processor determines a sector in which the position vector is located responsive to the compare actions and a sector layout. In some examples, execution of additional instructions causes the processor to operate a rotational system in response to the determined sector.
An example apparatus includes: driver circuitry having a terminal; a capacitor having a terminal; diode circuitry having a first terminal and a second terminal; a transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the transistor coupled to the first terminal of the diode circuitry, the control terminal of the transistor coupled to the terminal of the capacitor and the second terminal of the diode circuitry; and current mirror circuitry having a first terminal and second terminal, the first terminal of the current mirror circuitry coupled to the terminal of the driver circuitry, the second terminal of the current mirror circuitry coupled to the second terminal of the transistor.
H02P 7/28 - Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual DC dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices using semiconductor devices
H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
In an example, a method includes transmitting a plurality of wake-up frames (418) on a transmission channel from a first node (402) having a first priority. The method also includes pausing the wake- up frames (418) from the first node (402) and listening to the transmission channel after a predetermined number of wake-up frames (418) are transmitted from the first node (402). The method also includes receiving, at the first node (402), a wake-up frame (420) from a second node (406) on the transmission channel, wherein the second node (406) has a second priority.
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
B60L 58/10 - Methods or circuit arrangements for monitoring or controlling batteries or fuel cells, specially adapted for electric vehicles for monitoring or controlling batteries
G01R 31/36 - Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
H02J 13/00 - Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the networkCircuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network
An electronic device (100) includes a package structure (108) having opposite first and second sides (101, 102), opposite third and fourth sides (103, 104) spaced along a first direction (X), opposite fifth and sixth sides (105, 106) spaced along an orthogonal second direction (Y), the first and second sides (101, 102) spaced along a third direction (Z) orthogonal to the first and second directions (X, Y), and an opening (120) extending into the first side (101) along the third direction (Z), a first semiconductor die (111) having a first side (121) exposed in the opening (120) of the package structure (108) and an opposite second side (122) partially enclosed by the package structure (108), and a second semiconductor die (112) electrically connected to the first semiconductor die (111), the second semiconductor die (112) enclosed by the package structure (108) and laterally spaced apart from the first semiconductor die (111).
A method for adapting a continuous time equalizer (CTE) includes determining a gain of a discrete time equalizer (DTE) and determining whether the gain has increased or decreased by more than the threshold amount. Responsive to determining that the gain has increased or decreased by more than the threshold amount, the method includes sequentially configuring the CTE for multiple CTE settings such that gain of the CTE is caused to increase or decrease in a same direction with the change in gain of the DTE. The method also includes determining a separate figure of merit (FOM) for each of the multiple CTE settings and selecting a new CTE setting from the multiple CTE settings based on the FOM for each of the multiple CTE settings.
In some examples, an integrated circuit comprises: a TDI input, a TDO output, a TCK input and a TMS input; a TAP state machine (TSM) having an input coupled to the TCK input, an input coupled to the TMS input, an instruction register control output, a TSM data register control (DRC) output, and a TSM state output; an instruction register having an input coupled to the TDI input, an output coupled to the TDO output, and a control input coupled to the instruction register control output of the TAP state machine; router circuitry including a TSM DRC input coupled to the TSM DRC output, a control DRC input coupled to the TSM state output, and a router DRC output; and a data register having an input coupled to the TDI input, an output coupled to the TDO output, and a data register DRC input coupled to the router DRC output.
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
H10K 50/814 - Anodes combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
H10K 50/816 - Multilayers, e.g. transparent multilayers
An integrated circuit, comprising an instruction pipeline that includes instruction fetch phase circuitry, instruction decode phase circuitry, and instruction execution circuitry. The instruction execution circuitry includes transformation circuitry for receiving an interleaved dual vector operand as an input and for outputting a first natural order vector including a first set of data values from the interleaved dual vector operand and a second natural order vector including a second set of data values from the interleaved dual vector operand.
An example method includes generating a first interleave instruction based on compilation of a source file configured for execution by the first processor; generating a predication instruction to mask lane(s) of a first source register and a second source register of the second processor, in which the first source register stores a first vector and the second source register stores a second vector, based on translation of the source file; and generating a second interleave instruction based on compilation of the translated source file. The method further includes, based on the predication instruction and the second interleave instruction, reading respective portions of the first and second vectors from unmasked lanes of the first and second source registers, and interleaving the read portions to produce a third vector, which is then stored in a destination register of the second processor.
In one example, a method comprises providing first data to a machine learning model to generate second data. The method further comprises determining errors based on the second data and target second data; determining loss gradients based on the errors. The method further comprises updating running sums of prior loss gradients by adding the gradients to the running sums; and updating model parameters of the machine learning model based on the updated running sums.
In an example, a method includes communicating between a first BLUETOOTH device and a second BLUETOOTH device via a first channel within a channel set at a first connection event using first channel specific parameters. The method also includes determining, by the first BLUETOOTH device, one or more channel cluster operation parameters for a second channel within the channel set at a second connection event using second channel specific parameters. The method includes communicating over the second channel during the second connection event from the first BLUETOOTH device to the second BLUETOOTH device using renegotiated second channel specific parameters.
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
H04W 76/15 - Setup of multiple wireless link connections
Various systems and methods are provided. One such system includes first and second inputs of first and second types, respectively; a data controller, including a context mapper coupled to the first and second inputs. The data controller includes a context mapper that provides a processing identifier and a storage identifier to each item of data received from the first and second inputs; and a set of processing components, each coupled to the context mapper, and each associated with a respective processing identifier for processing each item of data having the corresponding processing identifier. The system further includes a memory coupled to the context mapper, the memory having multiple storage locations each associated with a respective storage identifier for storing each item of data having the corresponding storage identifier; and first and second outputs of the first and second types, respectively, coupled to the data controller.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
A semiconductor device has a deep trench in a semiconductor substrate of the semiconductor device, with linear trench segments extending to a trench intersection. Adjacent linear trench segments are connected by connector trench segments that surround a substrate pillar in the trench intersection. Each connector trench segment has a width at least as great as widths of the linear trench segments connected by the connector trench segment. The deep trench includes a trench filler material. The deep trench may have three linear trench segments extending to the trench intersection, connected by three connector trench segments, or may have four linear trench segments extending to the trench intersection, connected by four connector trench segments.
Current balancing techniques. In an example, a circuit includes a synchronization terminal, an error amplifier, and a clock generator. The error amplifier is configured to generate a first control voltage signal based on a reference voltage and a power converter output voltage. The clock generator is configured to produce an outgoing clock signal having an outgoing clock frequency. The circuit further includes an encoder, a frequency detector, and a decoder. The encoder is coupled to the clock generator and synchronization terminal, and configured to encode the outgoing clock signal based on the first control voltage signal to provide, at synchronization terminal, an outgoing encoded clock signal. The frequency detector is coupled to synchronization terminal and configured to derive, from an incoming encoded clock signal, an incoming clock frequency. The decoder is coupled to synchronization terminal and configured to derive, from the incoming encoded clock signal, a second control voltage signal.
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
Current regulation circuits and techniques. In one example, a circuit includes a voltage regulator circuit, current sensing circuitry, and a current control loop. The voltage regulator circuit is coupled to an output terminal of a DC-DC power converter and configured to produce a regulation signal based on a voltage at a regulator input terminal. The current sensing circuitry is coupled to a switching terminal of the DC-DC power converter and configured to produce a pulse signal based on a voltage at the switching input terminal and a threshold set by the regulation signal. The current control loop is coupled to control terminals of switching transistors of the DC-DC power converter and configured to generate switching control signals, based on the pulse signal, to control the switching transistors to drive an average value of a current flowing through the switching terminal to a target average current value corresponding to the threshold.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
Systems, methods, and computer program products provide for time critical packet transmission. An electronic device may include a transceiver and a processor that is configured to receive or transmit, via the transceiver, a plurality of packets having respective headers conforming to a layer below a network layer, and the first header of a first packet of the plurality of packets may include a source address and a hop limit field. The packet may be transmitted according to the layer below the network layer, thereby providing a smaller packet.
An example apparatus includes: first circuitry configured to verify a set of reference voltages is stable; and second circuitry including a first transistor, a second transistor, a first number of parallel transistors, and a second number of parallel transistors, the second circuitry configured to, in response to the verification: produce a trip voltage based on: a comparison of a threshold voltage of the first transistor and a threshold voltage of the second transistor; and a reference voltage selected from the set and provided to a control terminal of the first transistor; and adjust the value of the trip voltage based on a comparison between a first current mirror having a first number of parallel transistors and a second current mirror connected to a second number of parallel transistors.
An example radar system includes transmit, receive and processing circuitry. In operation, the radar system transmits first and second sets of chirp signals in which each chirp signal of the first set of chirp signals has an induced phase shift, receives reflected signals based on the transmitted first and second sets of chirp signals, and generates respective first and second sets of digital signals. Fourier Transform (FT) operations are performed on the first and second sets of digital signals to generate first and second arrays, respectively. The radar system identifies a first peak in the first array and a second peak in the second array representing an object in a field of view. The first and second peaks are at corresponding positions in the first and second arrays, respectively. The radar system then compares the phases of the first and second peaks to determine an actual phase shift for the induced phase shift.
Systems, methods, and computer program products provide for time critical packet transmission. An electronic device may include a transceiver and a processor that is configured to receive or transmit, via the transceiver, a plurality of packets having respective headers (610) conforming to a layer below a network layer, and the first header of a first packet of the plurality of packets may include a source address (625) and a hop limit field (623). The packet may be transmitted according to the layer below the network layer, thereby providing a smaller packet.
Systems and methods determine whether to switch to a second communication protocol from a first communication protocol based on energy detection. The energy detection may be used to indicate use of a channel defined by the second communication protocol. Energy detection on that channel may be accompanied by energy detection on an adjacent or close-by channel. If energy is detected on the channel and on an adjacent or a close-by channel, then that may indicate interference by a third communication protocol rather than by use of the channel on the second communication protocol. However, if energy is detected on the channel and not on the adjacent or close-by channel, then that may be an indication of use of the channel rather than interference.
H02J 50/80 - Circuit arrangements or systems for wireless supply or distribution of electric power involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
An integrated circuit includes a first transistor coupled between a power input and a power output, the first transistor being an N-type transistor and having a first transistor control input; a first amplifier stage having a reference input, a feedback input, and a first amplifier output, the feedback input coupled to the power output; a second amplifier stage having an amplifier input and a second amplifier output, the amplifier input coupled to the first amplifier output, and the second amplifier output coupled to the first transistor control input; and a first biasing circuit coupled to the first transistor control input, the first biasing circuit having an electrical control input coupled to the power output.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G05F 1/563 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including two stages of regulation, at least one of which is output level responsive, e.g. coarse and fine regulation
G05F 1/595 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load semiconductor devices connected in series
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
An example cascode voltage regulator circuit includes a first transistor coupled to an input voltage terminal and configured as a source follower to provide an output voltage at a source terminal, a second transistor coupled in series between the source terminal of the first transistor and an output terminal, the second transistor configured as a current limiter, and a current mirror coupled between respective first and second control terminals of the first and second transistors, the current mirror configured to receive a first current indicative of a source follower current flowing through the first transistor and to turn off the second transistor by coupling the first and second control terminals together responsive to the source follower current exceeding a threshold. In an example, the first transistor is a drain-extended NMOS device and the second transistor is a drain-extended PMOS device.
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
G05F 1/573 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overcurrent detector
A circuit includes a first transistor and a second transistor. The circuit also includes a third transistor and a fourth transistor. Additionally, the circuit includes a switch network coupled to the first transistor, to the second transistor, to the third transistor, and to the fourth transistor. Also, the circuit includes a first buffer having an input and an output, where the output is coupled to the second transistor and a second buffer having an input and an output, where the output is coupled to the first transistor. Additionally, the circuit includes a third buffer having an input and an output, the input coupled to the input of the first buffer and the output coupled to the third transistor; and a fourth buffer having an input and an output, where the input is coupled to the input of the second buffer and the output is coupled to the fourth transistor.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/44 - Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
84.
DISTRIBUTED MECHANISM FOR FINE-GRAINED TEST POWER CONTROL
An example circuit, e.g., an integrated circuit, comprises processor cores, each of which includes multiple memory blocks; power control circuits respectively coupled to the processor cores; isolation circuits respectively coupled to the processor cores; and controller circuitry coupled to each of the processor cores, to each of the power control circuits, and to each of the isolation circuits. The controller circuitry is configured to select a subset of processor cores of the processor cores and a subset of memory blocks of the subset of processor cores for testing; and cause non-selected memory blocks of the processor cores to be at least one of power gated, clock gated, and isolated from the selected subset of memory blocks.
In some examples, a device comprises: a substrate having a cavity, the cavity having a bottom surface; a die pad in the cavity; and a semiconductor die in the cavity and having a first segment coupled to the die pad and a second segment suspended over and facing the bottom surface.
Described embodiments include a charger circuit with a charge pump having a charge pump input and a charge pump output. The charge pump input is coupled to an input voltage terminal. A current sink is coupled between the charge pump output and a ground terminal, and has a current sink control terminal. A transistor is coupled between the input voltage terminal and an output voltage terminal, and has a control terminal. A driver circuit has a driver input, a driver output, a positive rail input, and a negative rail input. The driver output is coupled to the control terminal. The positive rail input is coupled to the charge pump output. The negative rail input is coupled to the output voltage terminal.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
87.
ELECTROSTATIC DISCHARGE PROTECTION DEVICES WITH LOW CAPACITANCE
Diodes for ESD protection devices are described. The diodes have low capacitance. In an example, a semiconductor device includes a substrate, an n-type epitaxial layer on the n-type substrate in a first region of the n-type substrate, and a p-type epitaxial layer on the n-type epitaxial layer with an interface between the n-type and p-type epitaxial layers. The p-type epitaxial layer has a first concentration of p-type dopants throughout the p-type epitaxial layer. Also, the semiconductor device includes a p-type dopant distribution straddling across the interface, the p-type dopant distribution having a first peak concentration of p-type dopants greater than the first concentration, and an n-type dopant distribution straddling across the interface, the n-type dopant distribution having a second peak concentration of n-type dopants. The second peak concentration is substantially same as the first peak concentration.
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
In a described example, a semiconductor wafer can include a first monitor structure in a scribe line adjacent to a die, the first monitor structure including a first source region, a first drain region, and a first gate region. The first gate region can include a first elongated finger extending longitudinally between the first source region and the first drain region, as viewed from a top plan view. The semiconductor wafer can include a second monitor structure in the scribe line, the second monitor structure including one or more second source regions, one or more second drain regions, and a plurality of second gate regions. The second gate regions can include a second elongated finger extending longitudinally over a respective region of the die between the one or more second source regions and the one or more second drain regions, as viewed from the top plan view.
In examples, a semiconductor package comprises a semiconductor die, and an inductor coupled to the semiconductor die. The inductor comprises a first metal coil having a first end coupled to the semiconductor die and a second end; a second metal coil vertically spaced from the first metal coil and having a third end coupled to the second end and a fourth end coupled to the semiconductor die; a magnetic mold compound (MMC) between the first and second metal coils, the MMC including conductive ions; and an insulative layer between the first and metal coils.
H01F 27/32 - Insulating of coils, windings, or parts thereof
H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformersApparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
Systems and methods may perform sequential automatic test pattern generation (on parallel memory units. In one example, an array of logic gates (330-335) may output enable signals to cause multiple memory units (360, 361) to be enabled in parallel. Test pattern generation and test control logic (210) may perform forward path testing, backward path testing, and any other appropriate testing on the enabled memory units (360, 361). The systems and methods may then move on to another group of memory units, which are enabled in parallel and tested in parallel.
One example includes a bulk bin system. The system includes a bin receptable comprising a first poka-yoke mating feature and a bulk bin configured to accommodate storage of bulk components. The bulk bin can be configured to rest on the bin receptacle and includes a second poka-yoke mating feature extending from an inner surface of the bulk bin. The second poka-yoke mating feature can be configured to engage with the first poka-yoke mating feature when the bulk bin is provided in the bin receptacle. The system further comprises a cover plate that is secured to the bulk bin via a securing feature. The cover plate includes a cover portion that extends along and is approximately aligned with the inner surface of the bulk bin to cover the second poka-yoke mating feature.
An example multiphase power converter circuit includes a first power stage is configured to provide a first phase output signal at a first switching output based on a first control signal. The first power stage includes first open fault detection circuitry configured to disable detecting and/or reporting of an open fault condition responsive to the first control signal. A second power stage is configured to provide a second phase output signal at a second switching output based on a second control signal. The second power stage includes second open fault detection circuitry configured to enable detecting and/or reporting of the open fault condition responsive to the second control signal having a value to turn off the second power stage. The second open fault detection circuitry is further configured to detect the open fault condition based on a voltage at the second switching output.
H02H 7/12 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for convertersEmergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for rectifiers for static converters or rectifiers
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
The present disclosure generally relates to a semiconductor device having a slanted field plate. In an example, a semiconductor device includes a semiconductor substrate, a gate, a drain contact, a source contact, and a field plate. The gate is on a surface of the semiconductor substrate. The drain contact and a source contact are on the semiconductor substrate. The field plate is over the surface of the semiconductor substrate and extends from one side of the gate towards the drain contact. The field plate includes multiple field plate portions. Each of the multiple field plate portions has a uniform respective slope with respect to the surface, and the multiple field plate portions have different slopes.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A method of manufacturing an electronic device includes forming a shallow trench isolation (STI) structure on or in a semiconductor surface layer and forming a mask on the semiconductor surface layer, where the mask exposes a surface of a dielectric material of the STI structure and a prospective local oxidation of silicon (LOCOS) portion of a surface of the semiconductor surface layer. The method also includes performing an oxidation process using the mask to oxidize silicon in an indent in the dielectric material of the STI structure and to grow an oxide material on the exposed LOCOS portion of the surface of the semiconductor surface layer.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
An example device comprising: first clock divider circuitry to be coupled to a first clock; first counter circuitry configured to be coupled to the first clock divider circuitry, the first counter circuitry configured to increment based on the first clock and a second clock; second clock divider circuitry to be coupled to a third clock; second counter circuitry configured to be coupled to the second clock divider circuitry, the second counter circuitry configured to increment based on the third clock and the second clock; and comparison circuitry coupled to the first and second counter circuitry.
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G06F 1/12 - Synchronisation of different clock signals
G06F 11/16 - Error detection or correction of the data by redundancy in hardware
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
H03K 5/26 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
A circuit includes a microcontroller having a clock output and a data output. The microcontroller includes a serial-peripheral interface (SPI) circuit, a pulse-width modulation (PWM) generator, and a central processing unit (CPU). The SPI circuit is configured to provide an SPI clock signal and an SPI data signal to the data output. The PWM generator is configured to provide a continuous PWM signal to the clock output. The CPU is coupled to the SPI circuit and the PWM generator, and the CPU has executable instructions configured to synchronize the PWM signal to the SPI clock signal.
A method comprises: forming a die including a cavity; coupling an anchor to the die; coupling a first resonator to a side of the anchor, in which the first resonator is suspended over the cavity and is operable to bend towards or away from a bottom of the cavity; and coupling a second resonator to the side of the anchor, in which the second resonator is suspended over the cavity, at least a part of the first resonator is laterally between the side of the anchor and a part of the second resonator, and the first resonator is operable to bend in an opposite direction from the second resonator.
H03H 3/007 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
A method includes receiving, by a MMU for a processor core, an address translation request from the processor core and providing the address translation request to a TLB of the MMU; generating, by matching logic of the TLB, an address transaction that indicates whether a virtual address specified by the address translation request hits the TLB; providing the address transaction to a general purpose transaction buffer; and receiving, by the MMU, an address invalidation request from the processor core and providing the address invalidation request to the TLB. The method also includes, responsive to a virtual address specified by the address invalidation request hitting the TLB, generating, by the matching logic, an invalidation match transaction and providing the invalidation match transaction to one of the general purpose transaction buffer or a dedicated invalidation buffer.
Methods, apparatus, systems and articles of manufacture to facilitate atomic compare and swap in cache for a coherent level 1 data cache system are disclosed. An example system includes a cache storage; a cache controller coupled to the cache storage wherein the cache controller is operable to: receive a memory operation that specifies a key, a memory address, and a first set of data; retrieve a second set of data corresponding to the memory address; compare the second set of data to the key; based on the second set of data corresponding to the key, cause the first set of data to be stored at the memory address; and based on the second set of data not corresponding to the key, complete the memory operation without causing the first set of data to be stored at the memory address.
A programmable switch converter controller for a power stage with a switch, an inductor, and a diode, includes a pulse-width modulator. The pulse-width modulator is configured to: generate an on-time interval (Ton) that is fixed or proportional to a demand signal proportional to a load adapted to be coupled to an output of the power stage; generate an off-time interval (Toff) that is inversely proportional to the product of a voltage across the inductor while the switch is off and a demand signal proportional to the load; initiate Ton when Toff elapses; and initiate Ton responsive to an external trigger signal.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
