The present disclosure relates to layout recommendations and, more particularly, to dynamic layout optimization systems, processes and methods of use. The method includes: determining mismatches between design notes and layout data of an integrated circuit; generating suggestions to correct the mismatches between the design notes and the layout data of the integrated circuit; providing an output of the mismatches between the design notes and the layout data of the integrated circuit including the suggestions; and saving the mismatches and suggestions to a log file.
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
G06F 119/02 - Reliability analysis or reliability optimisationFailure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
2.
SEMICONDUCTOR RING SURROUNDING VERTICAL DIODE AND RELATED METHODS
The disclosure provides a semiconductor ring surrounding a vertical diode, and related methods. Structures according to the disclosure include a vertical diode over a substrate. A semiconductor ring is over the substrate and horizontally surrounds the vertical diode. A spacer material is horizontally adjacent the semiconductor ring and separates the semiconductor ring from the vertical diode.
Disclosed are a word line (WL) driver and a memory structure including a WL driver system with multiple WL drivers. The WL driver includes a write WL voltage (VWL) control node, a read VWL control node, and an output node. First and second transistors are connected in series between the write VWL control node and the output node. Third and fourth transistors are connected in parallel between the read VWL control node and the output node. The first, second, and third transistors are P-type field effect transistors (PFETs) and the fourth transistor is an N-type field effect transistor (NFET). Additional NFETs are connected between the output node and ground and, optionally, between the gate and source of the second transistor. All transistors are the same gate dielectric type.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
4.
BIPOLAR TRANSISTOR STRUCTURES WITH SEMICONDUCTOR BASE FILM WITHIN ISOLATION LAYER, AND RELATED METHODS
The disclosure provides bipolar transistor structures with a semiconductor base film within an opening of an isolation layer, and related methods. A structure according to the disclosure includes a semiconductor base film on a collector terminal. The semiconductor base film includes a first portion within an opening of an isolation layer. The first portion includes an intrinsic semiconductor. A second portion of the semiconductor base film is on the first portion. The second portion includes a sidewall adjacent the isolation layer and a lower surface on the isolation layer. A semiconductor film is on an upper surface of the first portion of the isolation layer and adjacent a sidewall of the second portion of the isolation layer. An emitter is on the semiconductor film.
A laterally diffused field effect transistor (LDFET) and a related method are disclosed. The LDFET includes a substrate having a fin region and a planar region adjacent to the fin region. The LDFET also includes a source region in the fin region, a drain region in the planar region, a channel gate over the fin region and the planar region, and a drain extension region in the planar region between the source region and the drain region. The use of a substrate with a fin region for the source region and the channel of the channel gate and a planar region for the drain region and the drain extension region provides many of the benefits of both types of substrates for the LDFET.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Structures for a photonic chip that include a waveguide and methods of forming such structures. The structure comprises a first waveguide core, a second waveguide core adjacent to the first waveguide core, and a first layer between the first waveguide core and the second waveguide core. The structure further comprises a second layer adjacent to the first waveguide core, and a third layer adjacent to the second waveguide core. The first layer comprises an electro-optic material, and the second and third layers comprise a metal.
G02F 1/035 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on ceramics or electro-optical crystals, e.g. exhibiting Pockels or Kerr effect in an optical waveguide structure
The present disclosure relates to semiconductor structure and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a sub-collector region; a collector region over the sub-collector region, the collector region having a first semiconductor material comprising polysilicon material and single crystalline semiconductor material which is over the sub-collector region, and a second semiconductor material on the single crystalline semiconductor material; diffusion regions in the first semiconductor material; an emitter region over the collector region; and a base region adjacent to the emitter region.
Structures including a phase shifter and methods of forming such structures. The structure comprises a dielectric layer, a heater on the dielectric layer, a back-end-of-line stack on the dielectric layer and the heater, a substrate, and a second back-end-of-line stack on the substrate. The second back-end-of-line stack adjoins the first back-end-of-line stack along a bonding interface. The structure further comprises a waveguide core on the dielectric layer. The waveguide core includes a section that overlaps with the heater.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
The present disclosure relates to semiconductor structures and, more particularly, to capacitor structures and methods of manufacture. The structure includes: a gate structure over an active region of a semiconductor substrate; a source region on a first side of the gate structure; a drain region on a second side of the gate structure; a first contact structure shorting the drain region to the source region by; and a second contact structure connecting to the gate structure over the active region.
The present disclosure relates to semiconductor structures and, more particularly, to body contacted transistors and methods of manufacture. The structure includes: an active gate structure on a semiconductor substrate; at least one body contact extending through the active gate structure and connecting to a body region that contains a channel of the active gate which is under the active gate structure; and insulator material isolating the at least one body contact from the active gate structure.
Structures for a phase shifter and methods of forming such structures. The structure comprises a first waveguide core, a second waveguide core laterally adjacent to the first waveguide core, and a third waveguide core laterally adjacent to the second waveguide core. The second waveguide core and the first waveguide core are separated by a first slot, and the third waveguide core and the second waveguide core are separated by a second slot. The structure further comprises a layer that overlaps with respective portions of the first waveguide core, the second waveguide core, and the third waveguide core. The layer comprises a first electro-optic material.
G02F 1/035 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on ceramics or electro-optical crystals, e.g. exhibiting Pockels or Kerr effect in an optical waveguide structure
G02F 1/025 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction in an optical waveguide structure
12.
RESISTIVE RANDOM-ACCESS MEMORY STRUCTURE AND METHOD
Disclosed are a memory structure and an operating method. The structure includes: bit cells in columns and rows with all bit cells; source lines (SLs) and bit lines (BLs) for the columns; word lines (WL) for the rows; and peripheral circuitry to facilitate memory operations in a bit cell located in a selected column and a selected row. The peripheral circuitry includes a BL biasing circuit that applies an appropriate BL voltage to the BL for a selected column to achieve a desired memory operation and applies a positive unselected BL voltage to BLs for all unselected columns at least during write operations. The peripheral circuitry also includes a SL biasing circuit that applies an appropriate SL voltage to the SL for the selected column to achieve the desired memory operation and applies a positive unselected SL voltage to the SLs for all unselected columns at least during write operations.
Structures for a photonics chip that include a photonic component and methods of forming such structures. The structure may comprise a photodetector on a substrate and a waveguide core. The photodetector includes a light-absorbing layer having a longitudinal axis, a first sidewall, and a second sidewall adjoined to the first sidewall at an interior angle. The first sidewall is slanted relative to the longitudinal axis, and the second sidewall is oriented transverse to the longitudinal axis. The waveguide core includes a tapered section adjacent to the first sidewall and the second sidewall of the light-absorbing layer.
Structures for a thermo-optic phase shifter and methods of forming such structures. The structure comprises a waveguide core, a heater, a first plurality of segments positioned between a portion of the waveguide core and the heater, and a second plurality of segments positioned between the portion of the waveguide core and the heater. The first plurality of segments comprise a first material, the second plurality of segments comprise a second material, and the second plurality of segments alternate with the first plurality of segments.
G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02F 1/21 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference
G02F 1/225 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure
H05B 3/14 - Heating elements characterised by the composition or nature of the materials or by the arrangement of the conductor characterised by the composition or nature of the conductive material the material being non-metallic
Disclosed is a charge/discharge circuit structure for an output node (e.g., of a device, such as a charge pump in a memory structure, such as in a resistive random access memory (RRAM) structure). The circuit structure includes, among other components: a positive supply voltage node at a positive supply voltage level; a first input node connected to an output node of a device (e.g., a charge pump) to receive a variable output voltage (Vout); and an N-type field effect transistor (NFET) and a first P-type field effect transistor (PFET) connected in series between the positive supply voltage node and the first input node. The gate of the NFET can be connected to the drain region of the first PFET (and thereby also the first input node). Thus, the NFET functions as a source follower NFET switch controlled by feedback from the drain region of the first PFET.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
16.
RESISTIVE RANDOM ACCESS MEMORY (RRAM) STRUCTURE AND MULT-STEP MEMORY OPRERATION WITH ALL WORD LINES ACTIVATED
Disclosed is a memory structure including: an array of resistive random access memory cells (bit cells) in columns and rows; word lines (WLs) connected to the rows; and source line (SL)-bit line (BL) pairs connected to the columns. The structure is configured to perform a multi-step operation (e.g., a multi-step forming operation) during which: all WLs receive a low WL voltage; all BLs and SLs (except for the SL connected to a selected column) are discharged to ground; and the SL connected to the selected column receives a SL voltage (VSL) that starts high and decreases with each step. The operation concurrently and progressively changes the resistance states of resistors in bit cells of the selected column from an initial resistance state to a lower operational resistance state. Throughout the operation, BL current (IBL) on the BL of the selected column is monitored and, when a threshold IBL is reached, the next step is initiated.
Structures for a micro-ring resonator filter and methods of forming a structure for a micro-ring resonator filter. The structure comprises a bus-ring coupling section including a first Mach-Zehnder interferometer, and a micro-ring resonator section including a ring resonator coupled to the first Mach-Zehnder interferometer. The ring resonator includes a second Mach-Zehnder interferometer.
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/13 - Integrated optical circuits characterised by the manufacturing method
18.
POWER AMPLIFIER WITH VARIABLE POWER SUPPLY VOLTAGE
Disclosed is a circuit structure including a power amplifier and a temperature-dependent power supply system for the power amplifier. The power supply system includes a first voltage generator, which generates a reference voltage that is variable and depends on the operating temperature. In some embodiments, this first voltage generator employs a combination of proportional-to-absolute-temperature and constant-to-absolute temperature current sources to achieve the desired relationship between the operating temperature and the reference voltage. In other embodiments, a look-up table is employed to achieve the desired relationship between the operating temperature and the reference voltage. In any case, the power supply system also includes a second voltage generator, which is connected to receive the reference voltage and which generates (and outputs to the power amplifier) a power supply voltage that is dependent on the reference voltage.
H03F 3/213 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
The present disclosure relates to semiconductor structures and, more particularly, to multi-finger semiconductor devices with dummy gate structures and methods of manufacture. The structure includes: a plurality of active gate structures over a semiconductor substrate; a shared diffusion region in the semiconductor substrate between adjacent active gate structures of the plurality of gate structures; and a gate structure shorted to the shared diffusion region.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
A word line charge pump circuit of a memory device includes a clock driver configured to drive a clock signal using a first voltage and output a buffered clock signal with a swing level corresponding to a level of the first voltage, and a charge pump configured to receive a bit line voltage and generate a word line voltage by boosting the bit line voltage using the buffered clock signal.
Structures for a high-electron-mobility transistor and methods of forming such structures. The structure comprises a device structure that includes a gate and an ohmic contact, and one or more active blocks that are laterally positioned between the gate and the ohmic contact. The one or more active blocks are configured to receive a supply voltage that is different from ground.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
Structures for a photonic chip that include a grating and a light source, as well as methods of forming such structures. The structure comprises a grating that includes segments. The grating comprises a material having a refractive index that is variable in response to a stimulus, such as an applied bias voltage. The structure further comprises a waveguide core that includes a section adjacent to the segments of the grating. The structure may further include a light source adjacent to the grating.
G02F 1/03 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on ceramics or electro-optical crystals, e.g. exhibiting Pockels or Kerr effect
G02B 6/132 - Integrated optical circuits characterised by the manufacturing method by deposition of thin films
23.
STRUCTURE FOR POLARIZATION-INDEPENDENT COARSE WAVELENGTH DIVISION DEMULTIPLEXING
Disclosed are embodiments of a structure for polarization-independent coarse wavelength division demultiplexing. The structure includes a polarization splitter-rotator (PSR), which receives a dual polarization mode multi-wavelength optical signal and outputs a single polarization mode multi-wavelength optical signal. The structure includes a wavelength division demultiplexer (WDD) and a thermo-optic phase-shifter (TOPS), which is coupled to the PSR and either coupled to the input section of the WDD or integrated into the input section of the WDD. The structure includes at least one photodetector and a thermal control system (TCS). The photodetector is coupled to an unused end of a waveguide in either the TOPS or WDD (depending on the embodiment). The TCS monitors output current from the photodetector, and based thereon, sets heating voltage(s) applied to heating element(s) in the TOPS, ensuring that single wavelength optical signals output from output sections of the WDD are at desired wavelengths and power levels.
G02B 6/42 - Coupling light guides with opto-electronic elements
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
H04J 14/02 - Wavelength-division multiplex systems
24.
STRUCTURE WITH PORTIONS HAVING DIFFERENT GERMANIUM CONCENTRATIONS AND RELATED METHODS
The disclosure provides a structure base portions having different germanium concentrations, and related methods. A structure of the disclosure includes a base region including a first portion on a first emitter/collector (E/C) terminal and including germanium (Ge). A Ge concentration in the first portion varies with respect to distance from the first E/C terminal. A second portion is on the first portion and includes Ge. A third portion is between the second portion and a second E/C terminal and includes Ge. A Ge concentration in the third portion varies with respect to distance between the second portion and the second E/C terminal.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/15 - Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
Disclosed structures and methods include a chip including a transistor between an insulator layer and dielectric material layers. The transistor includes: within an active device region, source and drain regions and stacked body and channel regions laterally between the source and drain regions; and a gate structure on a surface of the active device region adjacent to and between the channel region and the dielectric material layers. Alternatively, the transistor includes: within an active device region, a source region laterally between drain and stacked body and channel regions laterally between the source region and each drain region; and gate structures on a surface of the active device region adjacent to and between the channel regions, respectively, and the dielectric material layers. In any case, a local interconnect adjacent to another surface of the active device region opposite the gate structure(s) electrically couples the body region to the source region(s).
The present disclosure relates to a memory sense amplifier and, more particularly, to a non-volatile memory sense amplifier and methods of use. The structure includes: a first stage amplifier comprising a plurality of non-volatile memory cells connecting to a bit line; a second stage amplifier connecting to the first stage amplifier and a common reference node; and a reference unity gain amplifier connecting to the second stage amplifier through the common reference node and receiving a voltage bias from the first stage amplifier, wherein the reference unity gain amplifier is connected to provide a reference voltage to the second stage amplifier.
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 7/14 - Dummy cell managementSense reference voltage generators
27.
STRUCTURE AND RELATED METHOD FOR SOURCE/DRAIN TERMINAL WITHIN SUBCOLLECTOR
The disclosure provides structures and related methods to provide a source/drain (S/D) terminal within a subcollector. A structure according to the disclosure includes a field effect transistor (FET) structure having a source/drain (S/D) terminal within a semiconductor layer, and a gate structure on the semiconductor layer. A bipolar transistor (BT) structure is on the FET structure and includes a subcollector within the semiconductor layer, and a collector-base-emitter stack on the subcollector and above the semiconductor layer.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a plurality of active devices in a layout, the plurality of active devices comprising semiconductor material with a first dopant type; a protective film; and a fill shape covering the protective film and comprising the semiconductor material with the first dopant type.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/161 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group
Structures for a photonic receiver and methods of forming a photonic receiver. The structure comprises a photodetector including a pad with a side edge and a semiconductor layer configured to absorb light. The structure further comprises a plurality of waveguide core segments. Each waveguide core segment extends outwardly from a respective portion of the side edge of the pad.
The present disclosure relates to semiconductor structures and, more particularly, to resistor trimming structures and methods of use. The structure includes: a set of resistors each of which include an increasing resistance value; and a set of switches each of which are connected to a respective resistor of the set of resistors and each of which comprise a decreasing width dimension for each resistor of increasing resistance value.
H01C 17/22 - Apparatus or processes specially adapted for manufacturing resistors adapted for trimming
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
31.
BIPOLAR TRANSISTOR STRUCTURES WITH SEMICONDUCTOR FILM AND RELATED METHODS
The disclosure provides bipolar transistor structures with a semiconductor film, and related methods. A structure of the disclosure includes an intrinsic base on a collector. The collector has a first doping type. A semiconductor film is on the intrinsic base and horizontally surrounds the intrinsic base. The semiconductor film horizontally encapsulates the intrinsic base. An emitter having the first doping type is on a first portion of the semiconductor film. An extrinsic base having a second doping type is on a second portion of the semiconductor film.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A multi-phase circuit includes a plurality of phases respectively corresponding to a plurality of clock phases. To balance respective output currents from the phases, for each phase: in response to an occurrence of a sampling time of that phase, a measurement signal corresponding to a value at the sampling time of the current for that phase is produced using a sampling circuit and provided to the other phases, other measurement signals from the other phases are received, an indicator signal according to whether the measurement signal is greater than an average of the other measurement signals is produced using a comparator circuit, and the output current of the phase is adjusted according to the indicator signal. The plurality of phases may include three or more phases.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
33.
CHIP INCLUDING SILICON DEVICE AND III-V SEMICONDUCTOR DEVICE ON III-V SEMICONDUCTOR LAYER
Disclosed semiconductor structures include a stack of III-V semiconductor layers and a III-V semiconductor device and a silicon device on the stack. The III-V semiconductor device includes, among other components, a barrier layer above and immediately adjacent to a III-V semiconductor surface at the top of the stack in a first area. The silicon device includes, among other components, a silicon-based layer above and immediately adjacent to the same III-V semiconductor surface at the top of the stack in a second area. Thus, the barrier layer and the silicon-based layer are at the same level above the substrate. Optionally, an isolation well can be within the stack adjacent to the III-V semiconductor surface in the second area (e.g., to electrically isolate the III-V semiconductor device from the silicon device). Also disclosed are methods of forming the semiconductor structures.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/8252 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
Disclosed is a dual-antifuse (DAF) device with two electrically isolated antifuses. The DAF device includes a gate structure including a dielectric layer lining a recess in a semiconductor layer between first and second conductive regions and a conductor layer on the dielectric layer. A gate cut isolation structure extends through the conductor layer, dividing the conductor layer into first and second conductor sections. As a result, the device includes a first antifuse (i.e., the first conductor section, the first conductive region, and the dielectric layer therebetween) and a second antifuse (i.e., a second conductor section, the second conductive region, and the dielectric layer therebetween), which is isolated from the first antifuse. Thus, the two antifuses are independently programable. Also disclosed herein are memory structure embodiments, which include DAF devices (either with or without electrically isolated antifuses) integrated into the cells of an array and which are configured for improved reliability.
H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
A disclosed D flip-flop includes first and second stages. The first stage includes a first intermediate node. The second stage includes second and third intermediate nodes and a pair of transistors connected in series to the second intermediate node. The first and third intermediate nodes are connected to the gates of different ones of the transistors in the pair in order to provide feedforward and feedback paths for maintaining the voltage level of a signal on the second intermediate node when a clock signal is static and the second intermediate node is floating. Optionally, the second stage can also include a feedback loop (including an inverter and a multiphase clock-controlled tri-state logic device connected in series from and back to the third intermediate node) for maintaining the voltage level of a signal on the third intermediate node when the clock signal is static and the third intermediate node is floating.
Disclosed are predecoders and structures including the predecoders. Each predecoder includes, among other components, first and second latches controlled by write and read clock signals, respectively, and a multiplexer-enabled write logic bypass path. During a write, an address signal is latched by the first latch and propagated through logic downstream of the first latch (including through a write logic block) to the second latch (which is transparent). During a read, the write logic bypass path is activated so the address signal bypasses the first latch and the write logic block and is instead propagated only through logic downstream of the write logic block to the second latch (which periodically latches the received signal). In both operations, a predecoded address signal is output but, due to activation of the write logic bypass path during the read, the time between receiving the address signal and outputting the predecoded address signal is reduced.
A multi-domain RC clamp circuit. A circuit is provided that includes a first power domain having a first RC clamp with a first transistor arranged to bypass a first resistor of the first RC clamp; and a second power domain having a second RC clamp with a second transistor arranged to bypass a second resistor of the second RC clamp, wherein the second transistor is controlled by a first input from the first power domain and the first transistor is controlled by a second input from the second power domain.
The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a semiconductor substrate; a collector region over the semiconductor substrate; an intrinsic base over the collector region; an electrically insulating heat dissipative material at a junction of the collector region and the intrinsic base; an extrinsic base over the intrinsic base; and an emitter region adjacent to the extrinsic base.
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
Structures for a photonic chip that include a photodetector and methods of forming such structures. The structure comprises a photodetector including a pad, a semiconductor layer on the pad, and a metal layer that extends into the pad. The semiconductor layer may be configured to absorb light of a given wavelength.
H01L 31/105 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
Structures for a photonic phase shifter and methods of forming such structures. The structure comprises a device structure including a source, a drain, a body, a gate over the body, and a well laterally between the source and the drain. The structure further comprises a waveguide core including a portion that overlaps with the well. A dielectric layer is positioned between the well and the portion of the waveguide core.
G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour
41.
NANOSHEET FIELD-EFFECT TRANSISTORS DEPOPULATED OF NANOSHEET CHANNEL LAYERS
Structures for a nanosheet field-effect transistor and methods of forming a structure for a nanosheet field-effect transistor. The structure comprises a field-effect transistor including a first source/drain region, a second source/drain region, a nanosheet channel layer, a gate conductor layer, a first inner spacer, and a second inner spacer. The nanosheet channel layer extends laterally from the first source/drain region to the second source/drain region. The gate conductor layer includes a section positioned in a space above the nanosheet channel layer. The first inner spacer adjoins the second inner spacer, and the first and second inner spacers are positioned laterally between the section of the gate conductor layer and the first source/drain region.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
The present disclosure relates to a structure including a first curvature compensation circuit which includes a first set of transistors, and a second curvature compensation circuit which includes a second set of transistors. A voltage reference (VREF) signal output from a bandgap voltage reference core with the second curvature compensation circuit is received as an input to the first curvature compensation circuit.
Structures and methods with a switchable voltage divider and a related method are disclosed. A structure of the disclosure includes a plurality of voltage nodes each receiving one of a plurality of voltages from the charge pump. A switchable voltage divider couples the plurality of voltage nodes to an output amplifier. The switchable voltage divider includes a common node and a plurality of first stages each coupled to one of the plurality of voltage node. Each first stage includes at least one first resistor, a first PFET, and a second PFET connected in series between a corresponding one of the plurality of voltage nodes and the common node, and a third PFET connected to a junction between the first PFET and the second PFET. A second stage includes multiple second resistors and an NFET connected in series between the common node and ground.
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
The present disclosure relates to semiconductor structures and, more particularly, to diode triggered silicon controlled rectifiers and methods of manufacture. The structure includes: a vertical silicon controlled rectifier (SCR) having a doped semiconductor material region over a semiconductor substrate; and at least one vertical triggering diode electrically connected to the SCR in series, and having a doped semiconductor material region over a doped region in the semiconductor substrate.
H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
A disclosed structure includes a FET with a gate structure (e.g., a RMG structure) having a scaled effective gate length proximal to a channel region and a large conductor surface distal to the channel region. The gate structure includes a first portion within a lower region of a gate opening proximal to the channel region and a second portion within a wider upper region. In this case, the gate structure can include a conformal gate dielectric layer that lines the gate opening and a gate conductor layer thereon. Alternatively, the gate structure includes a first portion including a short gate dielectric layer proximal to the channel region and a second portion (including a conformal gate dielectric layer and gate conductor layer) on the lower portion in a gate opening. Optionally, the structure also includes an additional FET without the scaled effective gate length. Also disclosed are associated methods.
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
46.
ILLUSTRATION GENERATOR FOR INTEGRATED CIRCUIT DESIGN AND METHOD
Disclosed are a method, system, and software application (referred to herein as an illustration generator) for generating two or three dimensional (2D or 3D) digital illustrations of user-selected areas of integrated circuit (IC) layouts. The illustration generator can include a program of instructions executable by processor to cause the processor to perform a method. This method includes: generating a database of IC component regions (e.g., using a technology file, and a design manual); comparing a user-selected area of an IC layout to the database in order to identify specific IC component regions included within the user-selected area; and generating a 2D or 3D digital illustration of the area. The digital illustration can include representations of different structural features within the area including at least some of the previously identified specific integrated circuit component regions.
Structures for a polarization splitter and methods of forming such structures. The structure comprises a multimode interference structure including a first multimode interference region, a second multimode interference region, a first waveguide core adjoined to a first portion of the first multimode interference region at a first acute angle, a second waveguide core adjoined to a second portion of the first multimode interference region at a second acute angle, and a third waveguide core adjoined to a third portion of the first multimode interference region. The second multimode interference region has an overlapping relationship with the first multimode interference region.
G02B 6/126 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind using polarisation effects
A deadtime generator configured to output a pair of non-overlapping clock signals. A circuit is provide that includes an input node for receiving a clock signal; a first signal path coupled to the input node and having a first output node for outputting a first modified clock signal, wherein the first signal path includes a feedback node coupled to an input of a feedback inverter; a second signal path coupled to the input node and having a second output node for outputting a second modified clock signal, wherein second signal path includes a Low-to-High skewed inverter; and a feedback signal path coupled to second signal path and having a High-to-Low skewed inverter with an output coupled to a gate of at least one transistor, wherein an output of the at least one transistor is coupled to the feedback node.
Personal test units and methods of using a personal health unit for performing a health-monitoring test. The structure comprises a housing including a first interior chamber and a second interior chamber. The first interior chamber is configured to removably receive a sensor chip, and the second interior chamber is configured to removably receive a module that includes a plurality of reservoirs each containing a fluid. A microfluidic circuit is configured to couple the plurality of reservoirs to a plurality of sensing devices on the sensor chip. The structure may optionally include a light source that is disposed inside the housing. The light source may include a laser and a plurality of optical fibers configured to transfer light from the laser to the sensing devices on the sensor chip.
Structures for a photonic chip that include a photodetector and a grating coupler, and methods of forming such structures. The structure comprises a photodetector including a semiconductor layer, and a grating coupler adjacent to the semiconductor layer of the photodetector. The structure further comprises a waveguide core including a portion that is laterally spaced from the grating coupler.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
51.
PHOTONIC CHIP INCLUDING ELECTRICAL INTERCONNECTIONS WITH A DUAL-LOBED PILLAR
Structures for a photonic chip and associated methods. The structure comprises a photonic chip including a bond pad and forming an electrical interconnection that includes a pillar positioned on the bond pad. The pillar includes a first lobed section, a second lobed section spaced from the first lobed section by a gap, and a connecting section extending across a portion of the gap to connect the first lobed section to the second lobed section.
G02B 6/42 - Coupling light guides with opto-electronic elements
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
52.
CAPACITIVE ELEMENT AND CIRCUIT STRUCTURE INCLUDING CAPACITIVE ELEMENT(S)
Disclosed are a capacitive element (CE) and a circuit structure including CE(s). The CE includes series-connected first, second, and third transistors (dual-gate n-type field effect transistors). Shared source/drain regions between the second and first transistors and between the first and third transistors are connected to capacitors, respectively. The first transistor is larger than the second and third transistors. The front gate of the first transistor and back gates of all three transistors receive a first control voltage (VC1). The front gates of the second and third transistors receive a second control voltage (VC2). VC1 and VC2 are concurrently switchable to concurrently switch the three transistors between on and off states. High and low voltage levels of VC1 are at a first positive voltage level and at ground. High and low voltage levels of VC2 are at the first positive voltage level and at a second positive voltage level.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
53.
FinFET WITH RECESSED TRENCH ISOLATIONS AT SIDEWALLS OF FIN
A structure for a FinFET, a FinFET and an LDMOS device are disclosed. The structures include a trench isolation adjacent a semiconductor fin and configured to increase a height of the semiconductor fin without increasing the footprint. The fin has junction and gate regions, and the trench isolation is adjacent a lower region the fin. The FinFET includes a first recess in the trench isolation adjacent the gate region of the fin, and a second recess in the trench isolation adjacent the junction region of the fin. The first recess is at least partially filled with a high dielectric constant (high-K) layer and a gate metal, and the second recess is at least partially filled with a low dielectric constant (low-K) layer. The trench isolation includes an upper portion and a lower portion that include materials of different compositions, e.g., a dopant in the upper portion.
Structures for a Mach-Zehnder interferometer and methods of forming a structure for a Mach-Zehnder interferometer. The structure comprises a first waveguide core including a first phase delay arm, and a second waveguide core including a second phase delay arm. The first phase delay arm includes a first taper, a second taper, and a plurality of segments between the first and second tapers.
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
G02B 1/00 - Optical elements characterised by the material of which they are madeOptical coatings for optical elements
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/28 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals
55.
MEMORY CELL INCLUDING DUAL-ANTIFUSE DEVICE, MEMORY STRUCTURE, AND OPERATING METHOD
Disclosed is a memory cell including a dual-antifuse device between a first pass-gate transistor and a second pass-gate transistor. The dual-antifuse device includes first and second antifuses having a common terminal and each also having an additional terminal opposite the common terminal. The first pass-gate transistor is connected between a first bitline and the additional terminal of the first pass-gate transistor. The second pass-gate transistor is connected between a second bitline and the additional terminal of the second pass-gate transistor. The common terminal of the first and second antifuses and gates of the first and second pass-gate transistors are connected to a wordline. Also disclosed is a memory structure including an array of such memory cells and an associated operating method. Within the array, different wordline and bitline bias conditions can be employed in order to reliably perform programming or read operations of a selected antifuse in a selected cell.
H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
Structures for a thermo-optic phase shifter and methods of forming such structures. The structure comprises a waveguide core, and a heater that includes a heating element, a first extension that projects from the first heating element, and a second extension that projects from the heating element. The heating element overlaps with a portion of the waveguide core, and the portion of the waveguide core is positioned laterally between the first extension and the second extension.
G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour
57.
SEMICONDUCTOR DEVICES AND METHODS OF FORMING SEMICONDUCTOR DEVICES USING LATERAL SOLID-PHASE EPITAXY
A semiconductor device includes a semiconductor substrate, a channel disposed over the semiconductor substrate and extending in a specific direction, a drain disposed at a first end of the channel, a source disposed at a second end of the channel, and a gate disposed over the channel and configured to control a current through the channel. The gate, or the channel, or both include a semiconductor material that is monocrystalline.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
58.
MULTIPLE-WIDTH DELAY ARMS FOR A WAVELENGTH-DIVISION-MULTIPLEXING FILTER
Structures for a wavelength-division-multiplexing filter and methods of forming a structure for a wavelength-division-multiplexing filter. The structure comprises a first waveguide core including a first phase delay arm and a second waveguide core including a second phase delay arm. The first phase delay arm has a first section and a second section connected to the first section. The first section of the first phase delay arm and the second section of the first phase delay arm are asymmetrical.
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
G02B 6/28 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals
G02B 6/30 - Optical coupling means for use between fibre and thin-film device
59.
Voltage level shifters and output driver including voltage level shifters for low power reset and hold
Disclosed are voltage level shifters and an output driver including them. Each voltage level shifter includes an input section with first and second intermediate nodes and an output section connected thereto. Each voltage level shifter is configured to achieve desired outputs particularly when a voltage rail in a high voltage domain is powering up but a voltage rail in a low voltage domain is at 0.0V or when the voltage rail in the high voltage domain is powered up and the voltage rail in the low voltage domain is powering down. To achieve the desired outputs, the output section includes, among other components, two output stabilizing transistors series-connected to the second intermediate node and having gates connected to the first intermediate node and a feedback node, respectively. The input section includes, among other components, a pull-down transistor connected to the first intermediate node and controlled by the second intermediate node.
The disclosure provides a method for the manufacture and layout adjustment of integrated circuits (ICs) with margin analysis. The method includes identifying a design rule applicable to two adjacent structures represented in an integrated circuit (IC) layout. The method also includes predicting, via a machine learning module and an associated library of training data for the IC layout, a margin for the two adjacent structures based on the design rule. From the predicting, the method determines whether the predicted margin is below a threshold margin. In cases where the predicted margin is below the threshold margin, the method includes manufacturing a device from the IC layout. In some implementations, the method includes modifying the IC layout.
Structures for a phase shifter and methods of forming such structures. The structure comprises a phase shifter including a first section, a second section, and a strip laterally between the first section and the second section. The structure further comprises a waveguide core including a portion laterally between the first section and the second section of the phase shifter, and a dielectric layer between the waveguide core and the phase shifter. The strip is laterally offset relative to the portion of the waveguide core toward the first section of the phase shifter.
The disclosure provides a method for modifying integrated circuit (IC) layouts in compliance with design rules. Methods of the disclosure include identifying, within an integrated circuit (IC) layout, a structure having a physical parameter compliant with a design rule for the layout and exceeding the design rule by a threshold amount. The method includes determining whether modifying the physical parameter for the structure to be less than the threshold amount maintains compliance with the design rule. In response to determining that modifying the physical parameter maintains compliance with the design rule, the method includes modifying the IC layout and transmitting the modified IC layout to a manufacturing device.
Disclosed are a system, method, and computer program product for developing and evaluating a prototype parameterized cell (P-PCELL) for a specific integrated circuit component. The P-PCELL is developed using multiple graphic design system (GDS) files for the component and a mapping file. Optionally, P-PCELL development is performed using a first machine learning model. Optionally, the P-PCELL is also evaluated based on test feedback acquired through user-testing including, for example, design rule checking (DRC) errors. Updates (e.g., design manual and/or parameter range updates) can be developed given the DRC errors. Optionally, development of the updates is performed using a second machine learning model. P-PCELL evaluation can further include determining P-PCELL code functionality, de-bugging the P-PCELL code, detecting any irregularities in the P-PCELL (e.g., based on a comparison of user-customized configurations with specifications and the GDS files) and correcting such irregularities.
The present disclosure relates to semiconductor structures and, more particularly, to vertical heterojunction bipolar transistors and methods of manufacture. The structure includes: a sub-collector region; a collector region above the sub-collector region; a base region above the collector region; an emitter region over a portion of the base region; and an undercut region bounded vertically and laterally by the base region and adjacent to the emitter region.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
A combined low noise amplifier (LNA), mixer, and voltage-controlled oscillator (VCO) circuit (i.e., an LMV cell) includes four dual-gate transistors. These four transistors include series-connected first and second transistors between a ground rail and a first local oscillator signal node and series-connected third and fourth transistors between the ground rail and a second local oscillator signal node. The first and third transistors are LNA components. The second and fourth transistors are cross-coupled VCO components. Front and back gates of the transistors are biased with different combinations of an RF input signal and complementary local oscillator signals generated on the first and second local oscillator nodes. This front and back gate biasing effectively mixes the RF input signal with each of the complementary local oscillator signals to generate complementary intermediate frequency output signals at output nodes between the first and second transistors and between the third and fourth transistor, respectively.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
A negative voltage level shifter. A circuit is provided that includes a first input path that couples an input node to a gate of a first n-type metal-oxide semiconductor (NMOS) transistor, wherein the first NMOS transistor has a drain coupled to a zero volt supply and a source coupled to a gate of a second NMOS transistor, wherein the second NMOS transistor incudes a source coupled to a negative power supply of −V volts and a drain coupled to an output node; and a second input path that couples the input node to a gate of a third NMOS transistor via an inverter, wherein the third NMOS transistor has a drain coupled to the zero volt supply and a source coupled to the output node.
A device and method for generating a common bias for a device component having a first circuit powered by a first power supply and a second circuit powered by a second power supply. A method includes: arranging a circuit path in a ring oscillator to replicate a logic depth of both the first circuit and the second circuit, wherein the ring oscillator is controlled by the common bias and a first portion of the circuit path is powered by the first power supply and a second portion of the circuit path is powered by the second power supply; outputting an oscillating signal from the ring oscillator; computing common bias voltages based on the oscillating signal; and applying the common bias voltages to the device component.
The present disclosure relates to semiconductor structures and, more particularly, to vertical heterojunction bipolar transistors and methods of manufacture. The structure includes: a collector region above a semiconductor substrate; a base region above the collector region; an emitter region adjacent to the base region; and an undercut structure above the semiconductor substrate and adjacent to the collector region.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
Structures for a photonic chip that include a photonic component and delay lines and methods of forming such structures. The structure comprises a photonic component, a first waveguide core including a section coupled to the photonic component, and a second waveguide core including a section coupled to the photonic component. The section of the first waveguide core has a first length, and the section of the second waveguide core having a second length that is greater than the first length.
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/13 - Integrated optical circuits characterised by the manufacturing method
Structures including an edge coupler and methods of forming such structures. The structure comprises an edge coupler including a first portion and a second portion between the first portion and a semiconductor substrate, a first coupling-assistance feature adjacent to the first portion of the edge coupler, and a second coupling-assistance feature adjacent to the first portion of the edge coupler. The first portion of the edge coupler is positioned in a lateral direction between the first coupling-assistance feature and the second coupling-assistance feature.
Structures including an inductor and methods of forming such structures. The structure comprises a semiconductor substrate including a first plurality of sealed cavities and a back-end-of-line stack on the semiconductor substrate. Each sealed cavity includes an air gap, and the back-end-of-line stack includes an inductor having a winding that overlaps with the sealed cavities.
Structures for a photonic chip that include an optical signal blocker and methods of forming such structures. The structure comprises a semiconductor substrate, an optical signal blocker including a metal sheet and a plurality of openings in the first metal sheet, and a waveguide core between the semiconductor substrate and the optical signal blocker. The waveguide core includes a portion that is overlapped by the optical signal blocker.
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
73.
Voltage level down-shifting circuit structure with input stage pull-down capacitor
A voltage level shifter includes an input stage with series-connected first and second N-type field effect transistors (NFETs) and an output stage with an inverter connected to an intermediate node between the first and second NFETs. Gates of the first and second NFETs are connected to an output node of the inverter and an input node, respectively. An input voltage signal on the input node toggles between a first voltage and ground. An intermediate voltage signal on the intermediate node toggles between a second voltage (lower than the first voltage) and ground. An output voltage signal on the output node toggles between the second voltage and ground. A capacitor in the input stage is connected between the input and intermediate nodes so that, when the input voltage switches to ground, the intermediate voltage signal is pulled to ground to facilitate switching of the output voltage signal to the second voltage.
Structures for an integrated circuit having a watermark and related methods. The structure comprises a first semiconductor structure including at least one feature with a variation relative to a second semiconductor structure including the at least one feature without the variation. The variation provides a watermark for identifying a Process Design Kit used to form the first semiconductor structure.
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Disclosed are a structure and method for generating a reference voltage (VREF) that remains essentially constant in response variations in temperature and/or variations in a positive supply voltage. The structure can include a VREF generation circuit with a first stage for generating a first complementary-to-absolute temperature voltage (V_CTAT1), a second stage for generating a second complementary-to-absolute temperature voltage (V_CTAT2) higher than but exhibiting the same temperature-dependent rate of change as V_CTAT1, and an output stage for generating VREF as a function of the difference between V_CTAT2 and V_CTAT1 (e.g., VREF can be approximately equal to V_CTAT2 minus V_CTAT1). In this structure, the same bias voltage (VBIAS) is employed for each stage and all transistors can be metal oxide semiconductor field effect transistors (MOSFETs). With the disclosed configuration, a more stable VREF across a wider temperature range and/or VDD range is achievable and the structure may consume less chip area.
G05F 3/24 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations wherein the transistors are of the field-effect type only
G05F 1/567 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
76.
BIPOLAR TRANSISTOR STRUCTURES WITH SLOPED BASE SIDEWALLS AND RELATED METHODS
The disclosure provides bipolar transistor structures with sloped base sidewalls and related methods to form the same. A structure according to the disclosure includes an intrinsic base on a collector and having an emitter thereon. A first extrinsic base is on the intrinsic base, and the first extrinsic base includes a sloped sidewall substantially aligned with a sloped sidewall of the intrinsic base. A first extrinsic includes a sloped sidewall substantially aligned with a sloped sidewall of the intrinsic base. A second extrinsic base has a sloped sidewall on and adjacent the sloped sidewall of the intrinsic base.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/43 - Electrodes characterised by the materials of which they are formed
Structures for a memory device and methods of forming a structure for a memory device. The structure comprises a first transistor including a first gate structure and a first source/drain region, a second transistor including a second gate structure and a second source/drain region, and a capacitor including a first capacitor plate directly coupled to the first source/drain region, a second capacitor plate, and a capacitor dielectric layer between the first capacitor plate and the second capacitor plate.
A word line driver includes all low voltage transistors including a low voltage, word line voltage-controlled, protection transistor. The word line driver receives input signals including: a first power supply signal that toggles between a programmable first voltage and a first voltage-dependent second voltage; an input voltage signal that toggles between the second voltage and the first voltage; a second power supply signal at the second voltage; a third power supply signal at a first voltage-dependent third voltage; and a fourth power supply signal at a fixed fourth voltage. In response, the word line driver outputs a word line voltage signal that toggles between the first voltage and ground. The particular voltage levels of the input signals in combination with the inclusion of the protection transistor prevent safe operating area violations.
G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices
A diode device includes a first well in a semiconductor substrate, a second well in the semiconductor substrate surrounding the first well, and a low-doped region between the first well and the second well in the semiconductor substrate. The first well and the second well have opposite conductivity types, creating a PIN diode. The diode device also includes a field plate structure over the low-doped region between the wells. The field plate structure includes a single crystal semiconductor over a first dielectric layer and/or a polyconductor gate over a second dielectric layer. The field plate structure provides high voltage isolation resulting in increased breakdown voltage for the PIN diode at reduced costs compared to conventional processes. In certain embodiments, the diode device may have a breakdown voltage of greater than 35 Volts.
Disclosed are a resistive random access memory (RRAM) structure and operating method. The RRAM structure includes RRAM cells arranged in columns and rows with all cells in a column connected between source and bit lines for the column and with all cells in a row connected to a word line for the row. The RRAM structure also includes peripheral circuitry enabling all memory operations to be performed without selective source line biasing. For example, during a reset operation, the following voltage conditions can be applied: a low positive voltage (e.g., of +1.8V) to the word line of the row containing the selected RRAM cell; a low negative voltage (e.g., of −1.8V) to all other word lines; and another low negative voltage (e.g., of −1.6V) to the bit line of the column containing the selected RRAM cell. All source lines and all other bit lines can be discharged to ground.
Disclosed is a photonic integrated circuit (PIC) structure including a scattering light-based monitor with photodetectors (e.g., PIN and/or avalanche photodiodes) placed adjacent to one or both sides of an end portion (i.e., a coupler) of a waveguide core at an optical interface with another optical device. The photodetectors are placed in such a way as to enable sensing of scattering light emitted from the end portion as light signals are received (e.g., either from the optical device for propagation to the main body of the waveguide core or from the main body for transmission to the optical device). Also disclosed are a monitoring system and method including the PIC chip structure with the above-described scattering light-based monitor. The system and method assess the optical interface using electric signals generated by the photodetectors.
The present disclosure relates to a fixture and, more particularly, to a fixture for the transport and storage of wafers and methods of use. The fixture includes: a frame having a mounting space provided between a top section, a bottom section and rails extending between the top section and the bottom section; and a clamp slidably mounted to the rails, the clamp including a locking mechanism that locks the clamp to the frame at different heights of the rails.
A radio frequency (RF) circuit and associated method include a mixer configured for independent second order intercept point (IP2) calibration. The mixer includes three ports and multiple dual-gate transistors interconnected therebetween for down-converting an RF input signal to a lower frequency baseband output signal. To optimize performance, front gates of the transistors are biased with a front gate bias voltage (Vfg). To adjust second order non-linearity, back gates of the transistors are biased using a first back gate bias voltage (Vbgp) for half of the transistors of the mixer and a second back gate bias voltage (Vbgm) for a different half of the transistors. The circuit can also include a front gate bias voltage generator for generating Vfg and a back gate bias voltage generator (including a digital-to-analog converter (DAC) with multiple DAC units) for generating Vbgp and Vbgm independent of Vfg.
H03D 7/12 - Transference of modulation from one carrier to another, e.g. frequency-changing by means of semiconductor devices having more than two electrodes
The present disclosure relates to a fixture and, more particularly, to a fixture which holds a radio frequency identification tag and methods of use. The structure includes a cage comprising a top portion, a bottom portion attached to the top portion and a storage space between the top portion and the bottom portion; a moveable linkage system extending within the storage space; a door attached to a first end of the linkage system, the door being moveable between an open position and a closed position; and a cam mechanism comprising structures with surfaces that permit the door to move from the closed position to the open position and to prevent the door from closing when in the closed position.
Structures for an edge coupler and methods of forming such structures. The structure comprises a waveguide core including a facet, a first tapered section, a second tapered section, and a longitudinal axis. The first tapered section is positioned along the longitudinal axis between the second tapered section and the facet. The first tapered section has a first width dimension that varies non-linearly with position along the longitudinal axis. The second tapered section has a second width dimension that varies non-linearly with position along the longitudinal axis.
Structures for an electrical interconnection and methods of forming a structure for an electrical interconnection. The structure comprises a bond pad and an electrical interconnection including a pillar positioned on a portion of the bond pad. The pillar includes a first section and a second section between the first section and the portion of the bond pad. The second section has a cross section with a perimeter having a non-round closed shape, and the second section is positioned acentric relative to the first section.
A design is schematically displayed using a three-dimensional (3D) graphical user interface (GUI) by displaying, via the 3D GUI, a first plane extending along a first axis and a second axis different from the first axis, including displaying symbols corresponding to a set of first-level components of a first level of the design disposed on the first plane; and a second plane extending along the first axis and second axis, including displaying symbols corresponding to a first set of second-level components of a second level of the design disposed on the second plane. The two planes are displayed simultaneously, and respectively disposed at first and second positions along a third axis different from the first and second axes. Each level of the design may correspond to a respective level of a hierarchy of the design, a respective substrate the design will be implemented on, or a combination thereof.
G06F 3/04815 - Interaction with a metaphor-based environment or interaction object displayed as three-dimensional, e.g. changing the user viewpoint with respect to the environment or object
Disclosed are a high-density stacked capacitor and an associated formation method. The high-density stacked capacitor includes: first and second terminals; and a stack of parallel-connected capacitors between the terminals. The stack includes a first capacitor (e.g., a planar transistor-type capacitor) including: a channel region positioned laterally between source/drain regions, which are connected to the first terminal; and front and back gates, which are above and below the channel region and connected to the second terminal. The stack also includes at least one additional capacitor (e.g., a metal-oxide-metal capacitor (MOMCAP)) aligned above the front gate of the first capacitor in a back end of the line (BEOL) metal level. Optionally, the capacitor includes multiple additional capacitors aligned above the front gate and stacked vertically one above the other in different BEOL metal levels. Each additional capacitor includes interdigitated first and second capacitor plates connected to the first and second terminals, respectively.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS
A semiconductor device includes a semiconductor substrate, a gate structure on the semiconductor substrate, the gate structure comprising a source region, a drain region, and a gate electrode, and at least one thermally conductive electrical insulator pillar in contact with the gate structure, wherein the at least one thermally conductive electrical insulator pillar extends from the gate structure to a back end of line (BEOL) layer of the semiconductor device.
Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an intrinsic base including a first semiconductor layer, a collector including a second semiconductor layer, and an emitter including a third semiconductor layer. The first semiconductor layer, which comprises silicon-germanium, includes a first portion and a second portion adjacent to the first portion. The second semiconductor layer includes a portion on the first portion of the first semiconductor layer, and the third semiconductor layer includes a portion on the second portion of the first semiconductor layer. The structure further comprises a dielectric spacer laterally between the portion of the second semiconductor layer and the portion of the third semiconductor layer.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
The disclosure provides a method for analysis and manufacture of curved features for integrated circuits. The method includes identifying, within an IC layout, a curved feature including a first endline and a second endline each having at least a threshold length and a curvilinear interval connecting the first endline to the second endline. The method also includes calculating a feature angle and a radius of the curvilinear interval between the first endline and the second endline. Further processing includes determining, based on the feature angle and the radius, whether the curvilinear interval is divisible into a plurality of linear segments each having a same orientation differential relative to the first endline and the second endline. The method additionally includes manufacturing an IC from the layout based on the curvilinear interval and the plurality of linear segments in response to curvilinear interval being divisible into the plurality of linear segments.
G05B 19/18 - Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
Structures for a quantum sensor and methods of forming such structures. The structure comprises a first waveguide core, a second waveguide core, and a sensor layer laterally between the first waveguide core and the second waveguide core. The first waveguide core is laterally coupled to the sensor layer, the second waveguide core is laterally coupled to the sensor layer, and the sensor layer comprises a material including a plurality of defect centers capable of photoluminescence.
The disclosure relates to a PIC structure including a photonic component on a semiconductor substrate. The photonic component includes an optical absorber including a spiral waveguide body and a linear input waveguide coupled to the spiral waveguide body. A plurality of discrete optical guard elements are in proximity to the photonic component. The plurality of discrete optical guard elements are composed of a light absorbing material and surround the spiral waveguide body and the linear input waveguide.
The present disclosure relates to semiconductor structures and, more particularly, to a device triggered silicon control rectifier (SCR) and methods of manufacture. the structure includes: a vertical silicon controlled rectifier having a diffusion region in a well of a semiconductor substrate; a vertical triggering device sharing the diffusion region with the vertical silicon controlled rectifier; and a body contact adjacent to the vertical triggering device and electrically connecting to the well.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
A structure includes a first layer having inductor windings. An inner area of the first layer is at least partially enclosed by the inductor windings and an outer area of the first layer is separated from the inner area by the inductor windings. This structure further includes a second layer having structural fill elements. The first layer and the second layer are parallel, and the second layer is relatively below the first layer in a direction perpendicular to the first layer. The density of the structural fill elements aligned below the inner area is less than the density of the structural fill elements aligned below the outer area.
The disclosure provides an isolation stack for a bipolar transistor (BT), and related methods. A structure of the disclosure includes a first isolation layer on a subcollector. A first air gap is between the first isolation layer and a collector of a BT. A second isolation layer is on the first isolation layer and adjacent an intrinsic base of the BT. A third isolation layer is on the second isolation layer, vertically between the second isolation layer and an extrinsic base of the BT. A second air gap is adjacent the third isolation layer and below the extrinsic base.
The present disclosure relates to structures including charge pump structures and related methods of operating such structures. A structure of the disclosure includes a first charge pump stage including first branches each connected between an input voltage and ground. The first branches each include first capacitors (C1, C2) connected between first intermediate nodes (Q1, Q1_B) and additional first intermediate nodes (V1, V1_B), respectively. A second charge pump stage includes second branches each connected between second intermediate nodes and additional second intermediate nodes, respectively.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
98.
STRUCTURE WITH DOPED WELL BETWEEN PHOTODETECTOR AND OPTICAL INTERFACE OF SEMICONDUCTOR LAYER
The disclosure provides a structure with a doped well between a photodetector and an optical interface of a semiconductor layer. A structure of the disclosure includes a semiconductor layer having a first surface configured for optically interfacing with incident radiation, and a second surface opposite the first surface. A photodetector is within the semiconductor layer and on the second surface thereof. A doped well is within the semiconductor layer between the photodetector and the first surface. The doped well has a same conductivity type as the semiconductor layer and a higher dopant concentration than the semiconductor layer.
Disclosed are a semiconductor structure and method of forming the semiconductor structure. The semiconductor structure includes a high-density stacked capacitor and, particularly, a stack of capacitors connected in parallel between two nodes. The stack includes a diode-type capacitor (also referred to herein as a PN junction capacitor) within a semiconductor substrate. In different embodiments, the diode-type capacitor has different in-substrate well configurations. The stack also includes a transistor-type capacitor (e.g., a metal oxide semiconductor capacitor (MOSCAP)) on an insulator layer aligned above the diode-type capacitor. Optionally, the stack also includes at least one additional capacitor (e.g., at metal-oxide-metal capacitor (MOMCAP)) on a dielectric layer aligned above the transistor-type capacitor (e.g., in one or more back end of the line (BEOL) metal levels).
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS
100.
ELECTRO-OPTIC BRIDGE CHIPS FOR CHIP-TO-CHIP COMMUNICATION
Structures including a photonic chip and methods of forming and using such structures. The structure comprises a first substrate, a photonic chip attached to a first portion of the first substrate, and an optical connector including a second substrate and a plurality of piezoelectric actuators disposed between a second portion of the first substrate and the second substrate. The second substrate includes a plurality of waveguide cores disposed adjacent to an interface for light transfer between the waveguide cores and the photonic chip, and the piezoelectric actuators are configured to change an alignment of the waveguide cores at the interface relative to the photonic chip.
patents
