Structures for a Mach-Zehnder interferometer and methods of forming a structure for a Mach-Zehnder interferometer. The structure comprises a Mach-Zehnder interferometer including a first directional coupler, a second directional coupler, a first delay arm between the first and second directional couplers, and a second delay arm between the first and second directional couplers. The first delay arm includes a portion with a U-shape that surrounds a pocket, and the second delay arm includes a portion with a U-shape that extends into the pocket.
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
G02F 1/21 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference
G02F 1/225 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure
2.
STRUCTURE WITH SPACER ON INTRINSIC BASE PEDESTAL AND RELATED METHODS
The disclosure provides a structure with a spacer on an intrinsic base pedestal, and related methods. A structure of the disclosure includes an intrinsic base pedestal on a collector and adjacent a dielectric layer. A spacer is over the intrinsic base pedestal. The spacer extends vertically upward from and horizontally beyond the intrinsic base pedestal. An emitter is horizontally adjacent the spacer. An extrinsic base includes a first portion vertically between the intrinsic base pedestal and the spacer, and a second portion on the dielectric layer. A vertical thickness of the second portion is less than a vertical thickness of the first portion.
Structures for a high-electron-mobility transistor and methods of forming such structures. The structure comprises a dielectric layer including an opening and a recess adjacent to the first opening. The opening extends fully through the dielectric layer, and the recess extends partially through the dielectric layer. The structure further comprises a device structure including a gate that has a portion inside the opening.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 62/852 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP
H10D 84/86 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of Schottky-barrier gate FETs
The present disclosure relates to an integrated photonic device, specifically an optical interlink structure. An optical interlink structure includes conjoined optical components, wherein each component includes one or cascaded multimode interferometer(s) (MMIs) on two distinct optical chip regions, wherein the conjoined arrangement enables efficient optical transmission between the interlink components.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
A system and method for classifying changes between graphic design system (GDS) files using a machine learning (ML) model. A disclosed method includes: inputting a first GDS file and a second GDS file into a GDSXOR comparator to generate a differences file, wherein the differences file includes a plurality of changes between the first GDS file and a second GDS file; using the ML model to process changes in the differences file, wherein the ML model evaluates each change and outputs a probability that a change is at least one of expected or unexpected; and comparing the probability to a threshold and classifying the change as at least one of expected or unexpected in response to the threshold being met.
The disclosure provides an electrical biasing circuit with a current limiter, e.g., for biasing of amplifiers. A structure of the disclosure includes an operational transconductance amplifier (OTA). The OTA includes first input terminal connected to a reference signal output node to receive a reference voltage, a second input terminal connected to a bias signal output node to receive a bias voltage, and an output terminal. A first transistor is connected between a positive supply voltage rail and the bias signal output node. The first control terminal of the first transistor is connected to the output terminal of the OTA.
The present disclosure relates to semiconductor structures and, more particularly, to a lateral transistor and methods of manufacture. The structure includes: an extrinsic base within a semiconductor material; an emitter having a semiconductor material with a single crystalline orientation, the emitter being above the extrinsic base and comprising a faceted sidewall; a collector having the semiconductor material with the single crystalline orientation, the collector being above the extrinsic base and comprising a faceted sidewall; and a spacer between the emitter and the collector.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
Structures for a photonic chip that include a modulator and methods of forming such structures. The structure comprises a first waveguide core, a second waveguide core that overlies the first waveguide core, and a first layer between the first waveguide core and the second waveguide core. The structure further comprises a second layer adjacent to the first layer, and a third layer adjacent to the first layer. The first layer is positioned in a lateral direction between the second layer and the third layer, the first layer comprises an electro-optic material, and the second and third layers comprise a metal.
G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour
9.
OPTICAL COMPONENTS INCLUDING A METAMATERIAL STRUCTURE AND METHODS OF FORMING THEREOF
A structure for a photonics chip includes a substrate and an optical component over the substrate. The optical component includes a metamaterial structure, the metamaterial structure including a plurality of elements in series and a dielectric material surrounding the plurality of elements. Each element has a first end surface and a second end surface opposite to the first end surface. The second end surface of each element includes a first end surface portion and a second end surface portion along a lateral position on the second end surface, the second end surface portion having a different orientation from the first end surface portion.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 1/00 - Optical elements characterised by the material of which they are madeOptical coatings for optical elements
G02B 6/13 - Integrated optical circuits characterised by the manufacturing method
The present disclosure relates to risk prediction automation and, more particularly, to systems and processes of optical proximity correction weak point risk prediction automation in use with semiconductor fabrication processes. The method includes: obtaining, by the computing device, feature variables of a design pattern associated with a design layout; determining, by the computing device, a risk rating value of selected feature variables of the feature variables for the design pattern; and generating, by the computing device, a waiverable disposition score using a machine learning model based on a combination of the risk rating value of the selected feature variables of the design pattern of the design layout.
The present disclosure relates to an integrated photonic device, specifically an efficient fiber-chip coupling structure or arrangement in which an optical fiber has at least two facet cuts that are made or configured to efficiently transmit an optical field from/to an optical chip. The efficient fiber-chip coupling arrangement may be part of an optical coupling setup used in, for example, optical wafer level testing applications. The optical fiber may optionally include an additional facet cut that is made or configured to provide improved visualisation of an optical alignment edge of the optical fiber during alignment with the optical chip or other elements.
The present disclosure relates to a monitoring tool and, more particularly, to a monitoring tool and method of use. The method includes: obtaining, by a computing device, an image of a tool used in processing equipment; comparing, by the computing device, a first side of the tool to a second side of the tool; determining, by the computing device, whether there is an asymmetry between the first side of the tool and the second side of the tool; and providing, by the computing device, a notification that there is the asymmetry between the first side of the tool and the second side of the tool.
The present disclosure relates to an optical fiber positioning device and, more particularly, to an optical fiber positioning device and a method for attaching a fiber optic array to a photonic integrated circuit (PIC). The structure includes: a body having a first end and a second end; a dome shaped indicator provided on the body; a first positioning mark associated with the dome shaped indicator; and a second positioning mark under the first positioning mark and associated with the dome shaped indicator.
A photodetector assembly comprises: a stacked structure having a cladding layer, a buried oxide layer, a semiconductor substrate, wherein the cladding layer includes a first side and a second opposed side which abuts a first side of the buried oxide layer, wherein the semiconductor substrate includes a first side which abuts a second opposed side of the buried oxide layer and further includes a second opposed side; a photodetector device embedded in the stacked structure; an inductor operably coupled to the photodetector device, wherein the inductor is arranged on the first side of the cladding structure and at least partially traverses the stacked structure; a signal electrode operably coupled to the photodetector device by using the inductor; and at least one ground electrode operably coupled to the photodetector device, wherein the signal electrode and the ground electrode are arranged on the first side of the cladding layer.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
Disclosed are embodiments of structure including: a chip with an embedded magnetic random access memory (eMRAM) or other on-chip component susceptible to magnetic field-induced performance degradation; and magnetic shield(s) for protecting the chip. In some embodiments, a magnetic shield includes abutting magnetic layers having different magnetic properties. In other embodiments, a magnetic shield includes abutting magnetic layers (of the same or different magnetic materials) having offset patterns of openings (e.g., through-holes or mesh). In any case, the chip can be mounted on a board and contained in a package. Such magnetic shields can be located on the package (opposite the board) and/or on the board (opposite the chip) depending upon the expected location of a potentially adverse magnetic field.
Structures for an electro-absorption modulator and methods of forming a structure for an electro-absorption modulator. The structure comprises a first metal layer and a second metal layer adjacent to the multiple-layer structure, a waveguide core, and a multiple-layer structure on a portion of the waveguide core. The multiple-layer structure comprises a first plurality of layers and a second plurality of layers that alternate with the first plurality of layers. The first plurality of layers comprise a first material, and the second plurality of layers comprise a second material. The multiple-layer structure is positioned in a lateral direction between the first metal layer and the second metal layer.
G02F 1/015 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction
17.
DUAL-OXIDE ACCESS TRANSISTORS FOR A RESISTIVE RANDOM-ACCESS MEMORY DEVICE
Structures including an access transistor and a resistive memory element, and methods of forming such structures. The structure comprises an access transistor including a semiconductor layer, a first source/drain region, a second source/drain region, a gate dielectric layer on the semiconductor layer, and a gate electrode overlapped with the gate dielectric layer. The gate dielectric layer has a first portion with a first thickness adjacent to the first source/drain region and a second portion with a second thickness adjacent to the second source/drain region, and the first thickness is greater than the second thickness. The structure further comprises a resistive memory element that is coupled to the first source/drain region of the access transistor.
An in-memory computing circuit structure can include an array of bit cells. Each bit cell includes: a first transistor and a first variable resistor series-connected between end nodes; and a second transistor and a second variable resistor series-connected between the end nodes. Within the columns, bit cells are series-connected in bit cell stacks, sense nodes are on the bit cell stacks, and analog-to-digital converters (ADCs) are connected to the sense nodes. Concurrent read operations are performed to sum resistances of selected variable resistors in the bit cells of the columns, respectively. The resulting currents on the sense nodes are provided as analog input signals to the ADCs. Each ADC for a column outputs a digital output signal indicating how close bit values stored in bit cells of the column are to matching input data signals applied to the rows. A content addressable memory (CAM) can include such a structure.
G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
G11C 7/16 - Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
The present disclosure relates to semiconductor structures and, more particularly, to low leakage decoupling capacitor structures and methods of manufacture. The structure includes: a first gate structure comprising a gate dielectric region with a first thickness; and a second gate structure adjacent to the first gate structure, the second gate structure comprising a gate dielectric region with a second thickness different from the gate dielectric region with the first thickness.
H10D 1/68 - Capacitors having no potential barriers
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
20.
THREE-DIMENSIONAL INTEGRATED CIRCUIT WITH TOP CHIP INCLUDING SCHOTTKY DIODE BODY CONTACT
Disclosed structures and methods include a top chip flipped relative to a bottom chip and bonded thereto. On the top chip, dielectric material layers separate a transistor from the bottom chip. The transistor includes source and drain regions, a body region on a channel region between the source and drain regions, and a gate structure adjacent to and between the channel region and the dielectric material layers. An insulator layer is on the transistor opposite the dielectric material layers and includes an opening extending to the body region. Optionally, a semiconductor layer is at the bottom of the opening. A contact extends into the opening to the body region (or to the semiconductor layer thereon, if applicable).
Structures for a photonic component and methods of forming a structure for a photonic component. The photonic structure comprises a semiconductor substrate, a first waveguide core including a first plurality of segments, and a second waveguide core including a second plurality of segments. The second plurality of segments are positioned between the first plurality of segments and the substrate.
A structure includes at least one single-photon avalanche diode (SPAD), at least one dome-shaped lens over each SPAD, and a metal guard ring surrounding each SPAD. A front-side illuminated SPAD photodetector and a method of forming the structure is also provided. The dome-shaped lens(es) with the metal guard ring improve SPAD efficiency in terms of photo detection probability (PDP) and light absorption with minimal increase in area.
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
23.
HIGH-ELECTRON-MOBILITY TRANSISTORS WITH FIELD PLATE
The present disclosure relates to semiconductor structures and, more particularly, to high-electron-mobility transistors with field plates and methods of manufacture. The structure includes: a gate structure on a semiconductor substrate; a passivation layer adjacent to the gate structure and above the semiconductor substrate; an insulator material over the passivation layer; and a field plate comprising a first portion contacting the passivation layer and a second portion being separated from the passivation layer by the insulator material.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/824 - Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
24.
STRUCTURE WITH EMITTER CONTACT WIDER THAN EMITTER TERMINAL AND RELATED METHOD
The disclosure provides a structure with an emitter contact wider than an emitter terminal, and related methods. A structure of the disclosure includes an emitter contact within an inter-level dielectric (ILD) layer and on an emitter terminal of a bipolar transistor, wherein a horizontal width of the emitter contact is greater than a horizontal width of the emitter terminal thereunder.
Structures for a phase shifter and methods of forming such structures. The structure comprises a first layer comprising a first electro-optic material, a second layer comprising a second electro-optic material, and a third layer between the first layer and the second layer. The third layer comprises a dielectric material that is an electrical insulator. A waveguide core is positioned on a portion of the first layer.
G02F 1/21 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference
G02F 1/225 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure
26.
BIT CELL, IN-MEMORY COMPUTING CIRCUIT FOR MAJORITY FUNCTIONS, AND IN-MEMORY COMPUTING METHOD
A bit cell (BC) includes: a variable resistor and a first transistor connected in series between two end nodes; and a second transistor also connected between the two end nodes. Gates of the first and second transistors are connected to first and second word lines (WLs), respectively, for a row. A circuit includes an array of BCs. In each column, BCs are connected in a stack between a sense amplifier (SA) and footer device (FD). During a read operation, FDs connect the stacks to ground. Additionally, first and second WL voltages on first and second WLs for each row are such that, for any selected row, first transistors of BCs are on and second transistors are off and, for any unselected row, first transistors of BCs are off and second transistors are on. SAs compare sense currents from the stacks to a mid-level reference current to concurrently compute majority functions.
A structure includes: a first latch, which is powered on during a normal operating mode and powered off during a data retention mode; a second latch, which is continuously powered on regardless of the mode; and a switch (e.g., a transmission gate) connected between the two latches. The first latch includes a data retention structure (including a combination of feedforward and feedback paths) configured to avoid data loss when a clock signal that controls flip-flop operation is static for some extended period of time. The second latch includes a keeper loop configured to avoid data loss when the first voltage domain is powered off during the data retention mode. The first latch is controlled, in part, by a single-phase clock signal. The second latch is controlled, in part, by either a dual-phase clock signal or combination of a single-phase clock signal and an intermediate signal from the first latch.
Structures for a photonic chip that include a waveguide core and methods of forming such structures. The structure comprises a waveguide core including a slot and a dielectric layer inside the slot. The waveguide core comprises a material having a first refractive index, and the dielectric layer comprises a dielectric material having a second refractive index that is less than the first refractive index.
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
Disclosed is an electrostatic discharge (ESD) protection structure for a circuit component connected to a first pad by an interconnect. The structure includes: a trigger circuit; a trigger circuit disconnect switch connected between the interconnect and trigger circuit; and a discharge circuit connected to a trigger voltage output node of the trigger circuit and to the interconnect. The switch enables the interconnect to be disconnected from the trigger circuit during testing of the circuit component (e.g., during wafer level testing to assess gate integrity) and to otherwise be continuously connected to the trigger circuit to facilitate ESD protection. The switch can be a depletion mode high electron mobility transistor (HEMT) with a gate connected to a second pad, which is connected to receive a negative voltage during testing and which is otherwise left floating. Also disclosed are a package chip including the ESD protection structure and associated methods.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
30.
SINGLE PHOTON AVALANCHE DIODE WITH SHARED CONDUCTIVE LINE
A single-photon avalanche diode (SPAD) device includes a first deep trench isolation (DTI) structure on a first side of the SPAD device, a first vertical doped region over a side of the first DTI structure, a second DTI structure on a second side of the SPAD device, a second vertical doped region over a side of the second DTI structure, a deep well coupled between the first vertical doped region and the second vertical doped region, and a shallow trench structure over the second DTI structure, the shallow trench structure comprising insulating sidewalls and a first conductive line between the insulating sidewalls, wherein the first conductive line is coupled to the second vertical doped region.
H10F 77/00 - Constructional details of devices covered by this subclass
H10F 30/221 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier being a PN homojunction
H10F 30/225 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier working in avalanche mode, e.g. avalanche photodiodes
A pad isolation switch for a resistive random-access memory (RRAM) device. The switch includes: a first pair of transistors arranged in series between an external pad node and an internal node, the first pair of transistors coupled together with a connector node; a second pair of transistors arranged in series between a supply voltage and the connector node; a first high voltage selection circuit having a pair of inputs coupled to the external pad node and VDDW; and a first level shifter having an output coupled to a gate of the first transistor and an input coupled to an output of the first high voltage selection circuit.
A charge pump structure and integrated circuit device. The charge pump structure includes a first stage charge pump unit implemented with low voltage devices that raises an input voltage using a system clock signal; and a plurality of second stage charge pump units, each implemented with low voltage devices that raise an output voltage of a prior charge pump unit using one of a series of boosted clock signals.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
The present disclosure relates to a structure which includes at least one gate structure over semiconductor material, the at least one gate structure comprising an active layer, a gate metal extending from the active layer and a sidewall spacer on sidewalls of the gate metal; and a field plate aligned with the at least one gate structure and isolated from the gate metal by the sidewall spacer.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
Embodiments of the disclosure provide a circuit structure and method with a resistor for reducing a discharged pad voltage. A structure of the disclosure includes a resistor having a first end connected to a pad and a second end opposite the first end. A trigger circuit is connected between the pad and ground. A discharge circuit is connected between the second end of the resistor and ground. The discharge circuit is connected to an output node of the trigger circuit.
G05F 1/63 - Regulating voltage or current wherein it is irrelevant whether the variable actually regulated is AC or DC using variable impedances in series with the load as final control devices
G05F 1/652 - Regulating voltage or current wherein it is irrelevant whether the variable actually regulated is AC or DC using variable impedances in parallel with the load as final control devices
35.
OPTO-ELECTRONIC CIRCUITS FOR OPTICAL POWER LIMITING
A structure includes: a photonic integrated circuit (PIC) with power detection and reduction photonic elements coupled to a waveguide near input and output ports, respectively; and an electronic integrated circuit (EIC) between the power detection and reduction photonic elements to reduce the power level of the optical signal near the output port when an over-power condition is detected. In some embodiments, the PIC includes first and second PIN photodiodes coupled to a waveguide near input and output ports, respectively. The first PIN photodiode is reverse biased, generating a sense current (Isen). The EIC receives Isen, detects when Isen is greater than a reference current (Iref) indicating detection of the over-power condition and, in response to the over-power condition, applies a bias voltage to forward bias the second PIN photodiode. Such forward biasing injects current into the waveguide near the output port and reduces the power level of the optical signal.
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a first transistor having an intrinsic base, an extrinsic base and an emitter; and a second transistor having an intrinsic base, an extrinsic base and an emitter. The extrinsic base of the first transistor and the extrinsic base of the second transistor have a common extrinsic base layer with a first dopant type for the first transistor and a second dopant type for the second transistor.
A gain cell memory device includes a semiconductor device layer of a silicon on insulator (SOI) substrate comprising an active region, a storage transistor over the active region of the semiconductor device layer, an isolation structure between a gate electrode of the storage transistor and a source/drain region adjacent to the storage transistor, the isolation structure extending through the active region such that a first portion of the active region is isolated from a second portion of the active region, and a capacitor coupled to the storage transistor. A bottom plate of the capacitor comprises the first portion of the active region, a gate dielectric layer of the storage transistor is an insulator of the capacitor, and a top plate of the capacitor comprises the gate electrode of the storage transistor and a metal structure over the gate electrode.
The embodiments herein relate to semiconductor devices including voids having different depths and methods of forming the same. The semiconductor device includes a device layer, a first metal layer over the device layer, a second metal layer over the first metal layer, a first void, and a second void. The device layer may include an active component. The first void is vertically over the active component and arranged through the first metal layer and the second metal layer. The second void is adjacent to the first void and has an upper portion at a same level as an upper portion of the first void.
The present disclosure generally relates to trench isolation structures for semiconductor devices. More particularly, the present disclosure relates to trench isolation structures with varying depths for electrically isolating integrated circuit (IC) components in semiconductor devices. The present disclosure provides a structure including a substrate, a first trench, a second trench, and a third trench in the substrate. The first, second, and third trenches have respective bottoms located at different depths. The structure may also include first, second, and third dielectric layers and a semiconductor layer in the trenches. The third dielectric layer is of a different material from the second dielectric layer. The second dielectric layer is of a different material from the first dielectric layer.
Structures for a high-electron-mobility transistor and methods of forming such structures. The structure comprises a layer stack including an active region, and a dielectric layer on the active region of the layer stack. The active region has a perimeter. The dielectric layer includes an opening and portions between the opening and the perimeter of the active region. The structure further comprises a source/drain region inside the opening in the dielectric layer.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H01L 21/76 - Making of isolation regions between components
H10D 62/852 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP
H10D 64/62 - Electrodes ohmically coupled to a semiconductor
41.
SILICON CONTROLLED RECTIFIER (SCR), INTEGRATED CIRCUIT (IC) CHIP INCLUDING SCR, AND METHODS OF FORMING SCR
A silicon controlled rectifier (SCR) includes a first well, a second well, a first well contact formed in the first well, a second well contact formed in the second well, a first junction contact raised compared to the first well contact, and a second junction contact raised compared to the second well contact.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
A radio frequency (RF) circuit and associated operating method include a mixer configured for independent second order intercept point (IP2) calibration. The mixer includes three ports and multiple dual-gate transistors interconnected therebetween for down-converting an RF input signal to a lower frequency baseband output signal. To optimize performance, front gates of the transistors are biased with a front gate bias voltage (Vfg). To adjust second order non-linearity, back gates of the transistors are biased using a first back gate bias voltage (Vbgp) for half of the transistors of the mixer and a second back gate bias voltage (Vbgm) for a different half of the transistors. The circuit can also include a front gate bias voltage generator for generating Vfg and a back gate bias voltage generator (including a digital-to-analog converter (DAC) with multiple DAC units) for generating Vbgp and Vbgm independent of Vfg.
H03D 7/12 - Transference of modulation from one carrier to another, e.g. frequency-changing by means of semiconductor devices having more than two electrodes
Structures for a phase shifter and methods of forming such structures. The structure comprises a waveguide core and a metamaterial structure laterally adjacent to the waveguide core. The metamaterial structure includes a first plurality of portions and a second plurality of portions that alternate with the first plurality of portions. The waveguide core comprises an electro-optic material, the first plurality of portions comprise a first material having a first refractive index, and the second plurality of portions comprise a second material having a second refractive index that is less than the first refractive index.
G02F 1/035 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on ceramics or electro-optical crystals, e.g. exhibiting Pockels or Kerr effect in an optical waveguide structure
44.
BODY CONTACT IN SOI DEVICE AND METHOD FOR FORMING THE SAME
A semiconductor device includes a semiconductor substrate including a buried oxide layer and a semiconductor layer over the buried oxide layer, a gate dielectric over the semiconductor layer, a gate electrode over the gate dielectric, a source region on a first side of the gate electrode, the source region including a first doped layer doped with a first type of impurities and a second doped layer above the first doped layer and doped with a second type of impurities, and a PN junction between the first doped layer and the second doped layer, a drain region on a second side of the gate electrode, a body of the semiconductor layer between the source region and the drain region, and a source silicide layer in the source region, the source silicide layer including an edge portion that contacts the first doped layer.
H10D 62/00 - Semiconductor bodies, or regions thereof, of devices having potential barriers
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
45.
VERTICAL HALL DEVICE, SENSING APPARATUS, AND METHODS OF FORMING VERTICAL HALL DEVICE
A vertical Hall device includes a substrate, an epitaxial layer disposed over the substrate, a first terminal including a dopant region and a Deep Trench Isolation (DTI) structure, and a second terminal including a first contact. The dopant region is disposed in the substrate, the DTI structure passes through the epitaxial layer and is coupled to the dopant region, and the first contact is disposed in the epitaxial layer.
A bonded semiconductor device includes a lower semiconductor device, an upper semiconductor device face bonded to the lower semiconductor device, and a nanopillar structure in an insulation layer of at least one of the lower semiconductor device and the upper semiconductor device, the nanopillar structure comprising a base layer and a plurality of nanopillars that contact the base layer. The nanopillar structure is electrically isolated from conductive structures of the lower semiconductor device and the upper semiconductor device.
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
47.
METHOD AND CIRCUIT FOR BIT READ DURING NON-VOLATILE MEMORY POWER-ON-RESET
Embodiments of the present disclosure provide a memory circuit, including: a non-volatile memory; a one-time-programmable memory; a sense amplifier coupled to the non-volatile memory and the one-time-programmable memory; a digital register coupled to an output of the sense amplifier for storing reference resistance bits; control logic coupled to an output of the digital register; a decoder coupled to an output of the control logic; and a controller for outputting a control signal to the control logic to select a first reference resistance for the sense amplifier from the decoder for a reading of bits from the one-time-programmable memory, and to select a second reference resistance for the sense amplifier from the decoder for a reading of bits from the non-volatile memory.
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
48.
SEMICONDUCTOR DISLOCATION-BASED PHYSICALLY UNCLONABLE FUNCTION AND METHOD
A cell structure for a physically unclonable function (PUF) includes a field effect transistor (FET) with an active semiconductor region having opposing sides. One side is linear and the other is stepped or curved so the active semiconductor region has a first portion with a first width and a second portion with a greater second width. The FET also includes a gate with first and second gate fingers electrically connected and traversing the first and second portions, respectively. Optionally, the cell structure includes semiconductor fill material region(s) adjacent to at least one end and/or at least one side. Optionally, the cell structure includes a pair of mirror-image FETs. Various dimensions within the cell structure are predetermined to achieve an approximately random likelihood that the off-state drain current (Idoff) will be at any particular Idoff level within a relatively large range of possible Idoff levels, due to random occurrence of dislocation(s).
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
49.
SEMICONDUCTOR STRUCTURES INCLUDING A CONDUCTOR LAYER AND MULTIPLE ISOLATION LAYERS
Semiconductor structures that include a conductor layer and multiple dielectric layers, as well as methods of forming such semiconductor structures. The structure comprises a first dielectric layer, a second dielectric layer, and a conductor layer including a first section and a second section between the first dielectric layer and the second dielectric layer. The structure further comprises a semiconductor layer including a first section that overlaps with the first section of the conductor layer and a second section that overlaps with the second section of the conductor layer, and a trench isolation region including a first portion laterally between the first section of the conductor layer and the second section of the conductor layer.
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
Photonic structures including ring resonators and methods of forming such structures. The photonic structure comprises first, second, and third waveguide cores, and a first ring resonator arranged between a first portion of the first waveguide core and a portion of the second waveguide core. The photonic structure further comprises a second ring resonator arranged between a second portion of the first waveguide core and a portion of the third waveguide core.
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
51.
ELECTRICAL FUSE HAVING FUSE LINK ALONG SIDEWALL(S) OF INACTIVE GATE STRUCTURE
An electronic fuse includes an inactive gate structure over a substrate, and a fuse link along at least one sidewall of the inactive gate structure. A first terminal is at a first end of the fuse link, and a second terminal is at a second of the fuse link. The fuse link takes the form of a conductive metal spacer along at least one sidewall of the inactive gate structure and can be formed without a silicide process. Although the e-fuse can be used with any semiconductor device, it is advantageous for use with, for example, III-IV semiconductor devices. The method of making the e-fuse does not require any additional masks and provides a fuse link having a sub-photolithographic width dimension.
An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).
The present disclosure relates to layout recommendations and, more particularly, to dynamic layout optimization systems, processes and methods of use. The method includes: determining mismatches between design notes and layout data of an integrated circuit; generating suggestions to correct the mismatches between the design notes and the layout data of the integrated circuit; providing an output of the mismatches between the design notes and the layout data of the integrated circuit including the suggestions; and saving the mismatches and suggestions to a log file.
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
G06F 119/02 - Reliability analysis or reliability optimisationFailure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
54.
SEMICONDUCTOR RING SURROUNDING VERTICAL DIODE AND RELATED METHODS
The disclosure provides a semiconductor ring surrounding a vertical diode, and related methods. Structures according to the disclosure include a vertical diode over a substrate. A semiconductor ring is over the substrate and horizontally surrounds the vertical diode. A spacer material is horizontally adjacent the semiconductor ring and separates the semiconductor ring from the vertical diode.
Disclosed are a word line (WL) driver and a memory structure including a WL driver system with multiple WL drivers. The WL driver includes a write WL voltage (VWL) control node, a read VWL control node, and an output node. First and second transistors are connected in series between the write VWL control node and the output node. Third and fourth transistors are connected in parallel between the read VWL control node and the output node. The first, second, and third transistors are P-type field effect transistors (PFETs) and the fourth transistor is an N-type field effect transistor (NFET). Additional NFETs are connected between the output node and ground and, optionally, between the gate and source of the second transistor. All transistors are the same gate dielectric type.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
56.
BIPOLAR TRANSISTOR STRUCTURES WITH SEMICONDUCTOR BASE FILM WITHIN ISOLATION LAYER, AND RELATED METHODS
The disclosure provides bipolar transistor structures with a semiconductor base film within an opening of an isolation layer, and related methods. A structure according to the disclosure includes a semiconductor base film on a collector terminal. The semiconductor base film includes a first portion within an opening of an isolation layer. The first portion includes an intrinsic semiconductor. A second portion of the semiconductor base film is on the first portion. The second portion includes a sidewall adjacent the isolation layer and a lower surface on the isolation layer. A semiconductor film is on an upper surface of the first portion of the isolation layer and adjacent a sidewall of the second portion of the isolation layer. An emitter is on the semiconductor film.
A laterally diffused field effect transistor (LDFET) and a related method are disclosed. The LDFET includes a substrate having a fin region and a planar region adjacent to the fin region. The LDFET also includes a source region in the fin region, a drain region in the planar region, a channel gate over the fin region and the planar region, and a drain extension region in the planar region between the source region and the drain region. The use of a substrate with a fin region for the source region and the channel of the channel gate and a planar region for the drain region and the drain extension region provides many of the benefits of both types of substrates for the LDFET.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
The present disclosure relates to semiconductor structures and, more particularly, to a defect free bipolar transistor and methods of manufacture. The structure includes: a collector region; an emitter region over the base region; and an extrinsic base region adjacent to the emitter region, the extrinsic base region comprising a raised wing extension at a perimeter thereof.
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
Structures for a photonic chip that include a waveguide and methods of forming such structures. The structure comprises a first waveguide core, a second waveguide core adjacent to the first waveguide core, and a first layer between the first waveguide core and the second waveguide core. The structure further comprises a second layer adjacent to the first waveguide core, and a third layer adjacent to the second waveguide core. The first layer comprises an electro-optic material, and the second and third layers comprise a metal.
G02F 1/035 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on ceramics or electro-optical crystals, e.g. exhibiting Pockels or Kerr effect in an optical waveguide structure
The present disclosure relates to semiconductor structure and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a sub-collector region; a collector region over the sub-collector region, the collector region having a first semiconductor material comprising polysilicon material and single crystalline semiconductor material which is over the sub-collector region, and a second semiconductor material on the single crystalline semiconductor material; diffusion regions in the first semiconductor material; an emitter region over the collector region; and a base region adjacent to the emitter region.
Structures including a phase shifter and methods of forming such structures. The structure comprises a dielectric layer, a heater on the dielectric layer, a back-end-of-line stack on the dielectric layer and the heater, a substrate, and a second back-end-of-line stack on the substrate. The second back-end-of-line stack adjoins the first back-end-of-line stack along a bonding interface. The structure further comprises a waveguide core on the dielectric layer. The waveguide core includes a section that overlaps with the heater.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
The present disclosure relates to semiconductor structures and, more particularly, to capacitor structures and methods of manufacture. The structure includes: a gate structure over an active region of a semiconductor substrate; a source region on a first side of the gate structure; a drain region on a second side of the gate structure; a first contact structure shorting the drain region to the source region by; and a second contact structure connecting to the gate structure over the active region.
The present disclosure relates to semiconductor structures and, more particularly, to body contacted transistors and methods of manufacture. The structure includes: an active gate structure on a semiconductor substrate; at least one body contact extending through the active gate structure and connecting to a body region that contains a channel of the active gate which is under the active gate structure; and insulator material isolating the at least one body contact from the active gate structure.
Structures for a phase shifter and methods of forming such structures. The structure comprises a first waveguide core, a second waveguide core laterally adjacent to the first waveguide core, and a third waveguide core laterally adjacent to the second waveguide core. The second waveguide core and the first waveguide core are separated by a first slot, and the third waveguide core and the second waveguide core are separated by a second slot. The structure further comprises a layer that overlaps with respective portions of the first waveguide core, the second waveguide core, and the third waveguide core. The layer comprises a first electro-optic material.
G02F 1/035 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on ceramics or electro-optical crystals, e.g. exhibiting Pockels or Kerr effect in an optical waveguide structure
G02F 1/025 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction in an optical waveguide structure
65.
RESISTIVE RANDOM-ACCESS MEMORY STRUCTURE AND METHOD
Disclosed are a memory structure and an operating method. The structure includes: bit cells in columns and rows with all bit cells; source lines (SLs) and bit lines (BLs) for the columns; word lines (WL) for the rows; and peripheral circuitry to facilitate memory operations in a bit cell located in a selected column and a selected row. The peripheral circuitry includes a BL biasing circuit that applies an appropriate BL voltage to the BL for a selected column to achieve a desired memory operation and applies a positive unselected BL voltage to BLs for all unselected columns at least during write operations. The peripheral circuitry also includes a SL biasing circuit that applies an appropriate SL voltage to the SL for the selected column to achieve the desired memory operation and applies a positive unselected SL voltage to the SLs for all unselected columns at least during write operations.
Structures for a photonics chip that include a photonic component and methods of forming such structures. The structure may comprise a photodetector on a substrate and a waveguide core. The photodetector includes a light-absorbing layer having a longitudinal axis, a first sidewall, and a second sidewall adjoined to the first sidewall at an interior angle. The first sidewall is slanted relative to the longitudinal axis, and the second sidewall is oriented transverse to the longitudinal axis. The waveguide core includes a tapered section adjacent to the first sidewall and the second sidewall of the light-absorbing layer.
Structures for a thermo-optic phase shifter and methods of forming such structures. The structure comprises a waveguide core, a heater, a first plurality of segments positioned between a portion of the waveguide core and the heater, and a second plurality of segments positioned between the portion of the waveguide core and the heater. The first plurality of segments comprise a first material, the second plurality of segments comprise a second material, and the second plurality of segments alternate with the first plurality of segments.
G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02F 1/21 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference
G02F 1/225 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure
H05B 3/14 - Heating elements characterised by the composition or nature of the materials or by the arrangement of the conductor characterised by the composition or nature of the conductive material the material being non-metallic
Disclosed is a charge/discharge circuit structure for an output node (e.g., of a device, such as a charge pump in a memory structure, such as in a resistive random access memory (RRAM) structure). The circuit structure includes, among other components: a positive supply voltage node at a positive supply voltage level; a first input node connected to an output node of a device (e.g., a charge pump) to receive a variable output voltage (Vout); and an N-type field effect transistor (NFET) and a first P-type field effect transistor (PFET) connected in series between the positive supply voltage node and the first input node. The gate of the NFET can be connected to the drain region of the first PFET (and thereby also the first input node). Thus, the NFET functions as a source follower NFET switch controlled by feedback from the drain region of the first PFET.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
69.
RESISTIVE RANDOM ACCESS MEMORY (RRAM) STRUCTURE AND MULT-STEP MEMORY OPRERATION WITH ALL WORD LINES ACTIVATED
Disclosed is a memory structure including: an array of resistive random access memory cells (bit cells) in columns and rows; word lines (WLs) connected to the rows; and source line (SL)-bit line (BL) pairs connected to the columns. The structure is configured to perform a multi-step operation (e.g., a multi-step forming operation) during which: all WLs receive a low WL voltage; all BLs and SLs (except for the SL connected to a selected column) are discharged to ground; and the SL connected to the selected column receives a SL voltage (VSL) that starts high and decreases with each step. The operation concurrently and progressively changes the resistance states of resistors in bit cells of the selected column from an initial resistance state to a lower operational resistance state. Throughout the operation, BL current (IBL) on the BL of the selected column is monitored and, when a threshold IBL is reached, the next step is initiated.
Structures for a micro-ring resonator filter and methods of forming a structure for a micro-ring resonator filter. The structure comprises a bus-ring coupling section including a first Mach-Zehnder interferometer, and a micro-ring resonator section including a ring resonator coupled to the first Mach-Zehnder interferometer. The ring resonator includes a second Mach-Zehnder interferometer.
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/13 - Integrated optical circuits characterised by the manufacturing method
71.
POWER AMPLIFIER WITH VARIABLE POWER SUPPLY VOLTAGE
Disclosed is a circuit structure including a power amplifier and a temperature-dependent power supply system for the power amplifier. The power supply system includes a first voltage generator, which generates a reference voltage that is variable and depends on the operating temperature. In some embodiments, this first voltage generator employs a combination of proportional-to-absolute-temperature and constant-to-absolute temperature current sources to achieve the desired relationship between the operating temperature and the reference voltage. In other embodiments, a look-up table is employed to achieve the desired relationship between the operating temperature and the reference voltage. In any case, the power supply system also includes a second voltage generator, which is connected to receive the reference voltage and which generates (and outputs to the power amplifier) a power supply voltage that is dependent on the reference voltage.
H03F 3/213 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
An avalanche photodiode device includes a first doped layer having a first doping type, a second doped layer having a second doping type, a third doped layer having the first doping type, a first PN junction between the first doped layer and the second doped layer, a second PN junction between the second doped layer and the third doped layer, a first vertical conductive structure coupled to the first doped layer and the third doped layer, and a second vertical conductive structure coupled to the second doped layer.
H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
H01L 31/072 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
73.
LDMOS TRANSISTOR WITH SPLIT GATE FIELD PLATE TAPERED TOWARD DRAIN REGION AND RELATED METHOD
An LDMOS transistor includes a semiconductor substrate, a channel gate over the semiconductor substrate, a source region to a first side of the channel gate, and a drain region to a second, opposite side of the channel gate. The LDMOS transistor also includes a split gate field plate over the semiconductor substrate where the split gate field plate has a tapered surface that is thinner toward the drain region. In certain embodiments, the split gate field plate has no lateral overlap with the channel gate and an L-shaped gate dielectric separates the split gate field plate from the channel gate and the semiconductor substrate. The split gate field plate can be shorted to the source region to reduce gate-to-drain region (Miller) parasitic capacitance. The LDMOS transistor split gate field plate can be formed with no additional masks.
The present disclosure relates to semiconductor structures and, more particularly, to multi-finger semiconductor devices with dummy gate structures and methods of manufacture. The structure includes: a plurality of active gate structures over a semiconductor substrate; a shared diffusion region in the semiconductor substrate between adjacent active gate structures of the plurality of gate structures; and a gate structure shorted to the shared diffusion region.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
A single photon avalanche diode (SPAD) device includes a semiconductor substrate, a central source/drain, an outer source/drain, and a shallow trench isolation (STI) structure between the central source/drain and the outer source/drain at an incident surface of the substrate, wherein a width of the STI structure is at least one third of a width of the central source/drain. The SPAD device may have superior dark current rate compared to conventional devices.
H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
H01L 31/0352 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
76.
WORD LINE CHARGE PUMP CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
A word line charge pump circuit of a memory device includes a clock driver configured to drive a clock signal using a first voltage and output a buffered clock signal with a swing level corresponding to a level of the first voltage, and a charge pump configured to receive a bit line voltage and generate a word line voltage by boosting the bit line voltage using the buffered clock signal.
Structures for a high-electron-mobility transistor and methods of forming such structures. The structure comprises a device structure that includes a gate and an ohmic contact, and one or more active blocks that are laterally positioned between the gate and the ohmic contact. The one or more active blocks are configured to receive a supply voltage that is different from ground.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
The present disclosure relates to semiconductor structures and, more particularly, to a transistor with a field plate and methods of manufacture. The structure includes: a gate structure on a semiconductor substrate; a source region on a first side of the gate structure; a drain region on a second side of the gate structure; and a field plate extending over the gate structure from the source region to the drain region, the field plate including at least one via structure extending toward the drain region.
Structures for a photonic chip that include a grating and a light source, as well as methods of forming such structures. The structure comprises a grating that includes segments. The grating comprises a material having a refractive index that is variable in response to a stimulus, such as an applied bias voltage. The structure further comprises a waveguide core that includes a section adjacent to the segments of the grating. The structure may further include a light source adjacent to the grating.
G02F 1/03 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on ceramics or electro-optical crystals, e.g. exhibiting Pockels or Kerr effect
G02B 6/132 - Integrated optical circuits characterised by the manufacturing method by deposition of thin films
80.
STRUCTURE FOR POLARIZATION-INDEPENDENT COARSE WAVELENGTH DIVISION DEMULTIPLEXING
Disclosed are embodiments of a structure for polarization-independent coarse wavelength division demultiplexing. The structure includes a polarization splitter-rotator (PSR), which receives a dual polarization mode multi-wavelength optical signal and outputs a single polarization mode multi-wavelength optical signal. The structure includes a wavelength division demultiplexer (WDD) and a thermo-optic phase-shifter (TOPS), which is coupled to the PSR and either coupled to the input section of the WDD or integrated into the input section of the WDD. The structure includes at least one photodetector and a thermal control system (TCS). The photodetector is coupled to an unused end of a waveguide in either the TOPS or WDD (depending on the embodiment). The TCS monitors output current from the photodetector, and based thereon, sets heating voltage(s) applied to heating element(s) in the TOPS, ensuring that single wavelength optical signals output from output sections of the WDD are at desired wavelengths and power levels.
G02B 6/42 - Coupling light guides with opto-electronic elements
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
H04J 14/02 - Wavelength-division multiplex systems
81.
STRUCTURE WITH PORTIONS HAVING DIFFERENT GERMANIUM CONCENTRATIONS AND RELATED METHODS
The disclosure provides a structure base portions having different germanium concentrations, and related methods. A structure of the disclosure includes a base region including a first portion on a first emitter/collector (E/C) terminal and including germanium (Ge). A Ge concentration in the first portion varies with respect to distance from the first E/C terminal. A second portion is on the first portion and includes Ge. A third portion is between the second portion and a second E/C terminal and includes Ge. A Ge concentration in the third portion varies with respect to distance between the second portion and the second E/C terminal.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/15 - Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
GlobalFoundries Dresden Module One Limited Liability Company & Co. KG (Germany)
Inventor
John, Peter
Herrmann, Grit
Lederer, Ulf
Maschke, Stefan
Wagenbreth, Frank
Werner, Martin
Vargason, Troy
Anne, Gopala Krishna
Balakrishnan, Ramaguru
Alagarsamy Muthukrishnan, Sabha Krishnan
Leucke, Uwe
Abstract
The present disclosure relates to energy consumption of tools and, more particularly, to modeling energy consumption in semiconductor tools. The method includes: obtain, by a computing device, a state history of a tool over a predetermined period of time; model, by the computing device, the state history of the tool using machine learning to provide a predicted energy usage of the tool; compare, by the computing device, predicted energy usage obtained from the machine learning model to an actual energy usage of the tool; and determine, by the computing device, a deviation between the actual energy usage and the predicted energy usage of the tool to maintain energy consumption efficiency of the tool.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
83.
THREE-DIMENSIONAL INTEGRATED CIRCUIT WITH TOP CHIP INCLUDING LOCAL INTERCONNECT FOR BODY-SOURCE COUPLING
Disclosed structures and methods include a chip including a transistor between an insulator layer and dielectric material layers. The transistor includes: within an active device region, source and drain regions and stacked body and channel regions laterally between the source and drain regions; and a gate structure on a surface of the active device region adjacent to and between the channel region and the dielectric material layers. Alternatively, the transistor includes: within an active device region, a source region laterally between drain and stacked body and channel regions laterally between the source region and each drain region; and gate structures on a surface of the active device region adjacent to and between the channel regions, respectively, and the dielectric material layers. In any case, a local interconnect adjacent to another surface of the active device region opposite the gate structure(s) electrically couples the body region to the source region(s).
The present disclosure relates to a memory sense amplifier and, more particularly, to a non-volatile memory sense amplifier and methods of use. The structure includes: a first stage amplifier comprising a plurality of non-volatile memory cells connecting to a bit line; a second stage amplifier connecting to the first stage amplifier and a common reference node; and a reference unity gain amplifier connecting to the second stage amplifier through the common reference node and receiving a voltage bias from the first stage amplifier, wherein the reference unity gain amplifier is connected to provide a reference voltage to the second stage amplifier.
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 7/14 - Dummy cell managementSense reference voltage generators
85.
Structure and related method for source/drain terminal within subcollector
The disclosure provides structures and related methods to provide a source/drain (S/D) terminal within a subcollector. A structure according to the disclosure includes a field effect transistor (FET) structure having a source/drain (S/D) terminal within a semiconductor layer, and a gate structure on the semiconductor layer. A bipolar transistor (BT) structure is on the FET structure and includes a subcollector within the semiconductor layer, and a collector-base-emitter stack on the subcollector and above the semiconductor layer.
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 84/40 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or with at least one component covered by groups or , e.g. integration of IGFETs with BJTs
The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a plurality of active devices in a layout, the plurality of active devices comprising semiconductor material with a first dopant type; a protective film; and a fill shape covering the protective film and comprising the semiconductor material with the first dopant type.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/161 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group
Structures for a photonic receiver and methods of forming a photonic receiver. The structure comprises a photodetector including a pad with a side edge and a semiconductor layer configured to absorb light. The structure further comprises a plurality of waveguide core segments. Each waveguide core segment extends outwardly from a respective portion of the side edge of the pad.
The embodiments herein relate to transistors having varying thicknesses of gate dielectric layers. The transistor includes a gate dielectric layer between a gate electrode and a substrate. The gate dielectric layer includes a first dielectric portion on the substrate, a second dielectric portion at least partially in the substrate, and a third dielectric portion partially in the substrate between the first and second dielectric portions. The second dielectric portion is thicker than the first dielectric portion. The third dielectric portion is thicker than the first dielectric portion and thinner than the second dielectric portion.
The disclosed subject matter relates generally to structures in semiconductor devices and integrated circuit (IC) chips. More particularly, the present disclosure relates to a metal-dielectric-metal capacitor having electrically inactive metal layers arranged in an interconnect level that is below another interconnect level containing two sets of metal lines interdigitated with each other.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
A contactless current sensing circuit for sensing current in a conductive wire on a dielectric substrate of a printed circuit board (PCB) includes a plurality of magnetic tunneling junction (MTJ) structures including first and second MTJ structures on a first side of the conductive wire, and third and fourth MTJ structures on a second side of the conductive wire opposite to the first side. The MTJ structures are located within the H-field induced by a current flowing through the conductive wire.
The present disclosure relates to semiconductor structures and, more particularly, to resistor trimming structures and methods of use. The structure includes: a set of resistors each of which include an increasing resistance value; and a set of switches each of which are connected to a respective resistor of the set of resistors and each of which comprise a decreasing width dimension for each resistor of increasing resistance value.
H01C 17/22 - Apparatus or processes specially adapted for manufacturing resistors adapted for trimming
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
92.
BIPOLAR TRANSISTOR STRUCTURES WITH SEMICONDUCTOR FILM AND RELATED METHODS
The disclosure provides bipolar transistor structures with a semiconductor film, and related methods. A structure of the disclosure includes an intrinsic base on a collector. The collector has a first doping type. A semiconductor film is on the intrinsic base and horizontally surrounds the intrinsic base. The semiconductor film horizontally encapsulates the intrinsic base. An emitter having the first doping type is on a first portion of the semiconductor film. An extrinsic base having a second doping type is on a second portion of the semiconductor film.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A multi-phase circuit includes a plurality of phases respectively corresponding to a plurality of clock phases. To balance respective output currents from the phases, for each phase: in response to an occurrence of a sampling time of that phase, a measurement signal corresponding to a value at the sampling time of the current for that phase is produced using a sampling circuit and provided to the other phases, other measurement signals from the other phases are received, an indicator signal according to whether the measurement signal is greater than an average of the other measurement signals is produced using a comparator circuit, and the output current of the phase is adjusted according to the indicator signal. The plurality of phases may include three or more phases.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
94.
CHIP INCLUDING SILICON DEVICE AND III-V SEMICONDUCTOR DEVICE ON III-V SEMICONDUCTOR LAYER
Disclosed semiconductor structures include a stack of III-V semiconductor layers and a III-V semiconductor device and a silicon device on the stack. The III-V semiconductor device includes, among other components, a barrier layer above and immediately adjacent to a III-V semiconductor surface at the top of the stack in a first area. The silicon device includes, among other components, a silicon-based layer above and immediately adjacent to the same III-V semiconductor surface at the top of the stack in a second area. Thus, the barrier layer and the silicon-based layer are at the same level above the substrate. Optionally, an isolation well can be within the stack adjacent to the III-V semiconductor surface in the second area (e.g., to electrically isolate the III-V semiconductor device from the silicon device). Also disclosed are methods of forming the semiconductor structures.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/8252 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
Disclosed is a dual-antifuse (DAF) device with two electrically isolated antifuses. The DAF device includes a gate structure including a dielectric layer lining a recess in a semiconductor layer between first and second conductive regions and a conductor layer on the dielectric layer. A gate cut isolation structure extends through the conductor layer, dividing the conductor layer into first and second conductor sections. As a result, the device includes a first antifuse (i.e., the first conductor section, the first conductive region, and the dielectric layer therebetween) and a second antifuse (i.e., a second conductor section, the second conductive region, and the dielectric layer therebetween), which is isolated from the first antifuse. Thus, the two antifuses are independently programable. Also disclosed herein are memory structure embodiments, which include DAF devices (either with or without electrically isolated antifuses) integrated into the cells of an array and which are configured for improved reliability.
H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
A disclosed D flip-flop includes first and second stages. The first stage includes a first intermediate node. The second stage includes second and third intermediate nodes and a pair of transistors connected in series to the second intermediate node. The first and third intermediate nodes are connected to the gates of different ones of the transistors in the pair in order to provide feedforward and feedback paths for maintaining the voltage level of a signal on the second intermediate node when a clock signal is static and the second intermediate node is floating. Optionally, the second stage can also include a feedback loop (including an inverter and a multiphase clock-controlled tri-state logic device connected in series from and back to the third intermediate node) for maintaining the voltage level of a signal on the third intermediate node when the clock signal is static and the third intermediate node is floating.
Disclosed is a circuit including a transistor with integrated circuitry for protection against damage due to an electrostatic discharge (ESD) event or other drain voltage (Vd) overstress condition. The transistor is an N-type field effect transistor (NFET) and includes a drain region, a source region connected to ground, and a gate connected to a first node. The first node is connected to receive an externally-generated gate bias voltage. A resistor-capacitor (RC)-triggered voltage clamp is connected in parallel with the transistor. Specifically, a resistor is connected between the source region and a second node and a capacitor is connected between the second node and the drain region. A first diode or series-connected first diodes is/are connected between the second node and the first node. Optionally, a resistor-diode (RD)-triggered voltage clamp is also connected in parallel with the transistor and shares the resistor and second node with the RC-triggered voltage clamp.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
98.
Predecoders with write logic bypass path and memory structure including predecoders
Disclosed are predecoders and structures including the predecoders. Each predecoder includes, among other components, first and second latches controlled by write and read clock signals, respectively, and a multiplexer-enabled write logic bypass path. During a write, an address signal is latched by the first latch and propagated through logic downstream of the first latch (including through a write logic block) to the second latch (which is transparent). During a read, the write logic bypass path is activated so the address signal bypasses the first latch and the write logic block and is instead propagated only through logic downstream of the write logic block to the second latch (which periodically latches the received signal). In both operations, a predecoded address signal is output but, due to activation of the write logic bypass path during the read, the time between receiving the address signal and outputting the predecoded address signal is reduced.
A multi-domain RC clamp circuit. A circuit is provided that includes a first power domain having a first RC clamp with a first transistor arranged to bypass a first resistor of the first RC clamp; and a second power domain having a second RC clamp with a second transistor arranged to bypass a second resistor of the second RC clamp, wherein the second transistor is controlled by a first input from the first power domain and the first transistor is controlled by a second input from the second power domain.
A semiconductor structure including an active region and an isolation region adjacent to the active region and a gate arranged over the active region and the isolation region is provided. A first gate contact and a second gate contact is arranged over the gate. The first gate contact overlaps the active region and the second gate contact overlaps the isolation region. A metal line extends over the first gate contact and the second gate contact.
