Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise source, drain and gate finger electrodes on active regions of a plurality of sections of a multi-section transistor, and a contact structure comprising source and drain contact areas, e.g. drain and source pads extending over active regions of each section, interconnected by conductive micro-vias to respective underlying drain and source finger electrodes. Alternatively, source contact areas comprise parts of a source bus which runs over inactive regions. For reduced gate loop inductance, the source bus may be routed over or under the gate bus. The pad structure and the micro-via interconnections are configured to reduce current density in self-supported widths of the drain finger electrodes. Example CUP device structures provide for higher current carrying capability and reduced drain-source resistance.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 64/00 - Electrodes of devices having potential barriers
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
2.
APPARATUS, SYSTEMS AND METHODS FOR LOAD-ADAPTIVE 3D WIRELESS CHARGING
Apparatus, systems and methods for load-adaptive 3D wireless charging are disclosed. In a 3D charging system of an example embodiment, features comprise a 3D coil design that provides magnetic field distribution coverage for a 3D charging space, e.g. hemi-spherical space/volume; a push-pull class EF2 PA with EMI filter and transmitter circuitry that provides constant current to the 3D coil, with current direction, phase and timing control capability to adapt to load conditions; reactance shift detection circuitry comprising a voltage sensor, current sensor and phase detector and hardware for fast, real-time, computation of reactance and comparison to upper and lower limits for load-adaptive reactance tuning and for auto-protection; and a switchable tuning capacitor network arrangement of shunt and series capacitors configured for auto-tuning of input impedance, e.g. in response to a X detection trigger signal, which enables both coarse-tuning and uniform fine-tuning steps over an extended reactance range.
H02J 50/12 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
H02J 50/80 - Circuit arrangements or systems for wireless supply or distribution of electric power involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
H02J 50/90 - Circuit arrangements or systems for wireless supply or distribution of electric power involving detection or optimisation of position, e.g. alignment
H03F 3/20 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
Pulsed laser drivers are disclosed comprising Gallium Nitride (GaN) power transistors for driving diode laser systems requiring high current and fast pulses, such as laser drivers for LIDAR (Light Detection and Ranging) systems. Drivers are capable of delivering pulses with peak current ≥100A, e.g. 170A to provide high peak power, fast pulses with nanosecond rise times and nanosecond pulse duration, for driving multi-channel laser diode arrays with 40A per channel for 120W output per channel for a combined peak output of 480W. For lower duty cycle, example driver circuits are disclosed comprising a high current power transistor for direct drive with drive assist. For higher duty cycle, example resonant driver circuits are disclosed comprising two high current power transistors. Implementation of resonant driver circuits with GaN technology provides fast charging for short pulse operation at higher repetition rates or for pulse code modulation.
A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.
H01L 21/30 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/00 - Details of semiconductor or other solid state devices
C01B 21/06 - Binary compounds of nitrogen with metals, with silicon, or with boron
H05B 33/08 - Circuit arrangements for operating electroluminescent light sources
C01G 15/00 - Compounds of gallium, indium, or thallium
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
8.
GaN-on-Si semiconductor device structures for high current/ high voltage lateral GaN transistors and methods of fabrication thereof
A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and also over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 23/528 - Layout of the interconnection structure
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
Embedded packaging for devices and systems comprising lateral GaN power transistors is disclosed. The packaging assembly is suitable for large area, high power GaN transistors and comprises an assembly of a GaN power transistor and package components comprising a three level interconnect structure. In preferred embodiments, the three level interconnect structure comprises an on-chip metal layer, a copper redistribution layer and package metal layers, in which there is a graduated or tapered contact area sizing through the three levels for dividing/applying current on-chip and combining/collecting current off-chip, with distributed contacts over the active area of the GaN power device. This embedded packaging assembly provides a low inductance, low resistance interconnect structure suitable for devices and systems comprising large area, high power GaN transistors for high voltage/high current applications.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/28 - Encapsulation, e.g. encapsulating layers, coatings
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
13.
POWER SWITCHING SYSTEMS COMPRISING HIGH POWER E-MODE GAN TRANSISTORS AND DRIVER CIRCUITRY
Driver circuitry for switching systems comprising enhancement mode (E-Mode) GaN power transistors with low threshold voltage is disclosed. An E-Mode high electron mobility transistor (HEMT) D3 has a monolithically integrated GaN driver, comprising smaller E- Mode GaN HEMTs D1 and D2, and a discrete dual-voltage pre-driver. D1 provides the gate drive voltage to the gate of the GaN switch D3, D2 clamps the gate of the GaN switch D3, an internal source-sense connection closely couples the source of D3 and the source of D1. An additional source-sense connection is provided for the pre-driver. Boosting the drive voltage to the gate of D1 produces firm and rapid pull-up of D1 and D3 for improved switching performance at higher switching speeds. High current handling components of the driver circuitry are integrated with the GaN switch and closely coupled to reduce inductance, while the discrete pre-driver can be thermally separated from the GaN chip.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H01L 27/085 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
14.
FAULT TOLERANT DESIGN FOR LARGE AREA NITRIDE SEMICONDUCTOR DEVICES
A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighbouring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 29/41 - Electrodes characterised by their shape, relative sizes or dispositions
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
15.
DEVICES AND SYSTEMS COMPRISING DRIVERS FOR POWER CONVERSION CIRCUITS
An electronic switching system and device comprising driver circuits for power transistors are disclosed, with particular application for MOSFET driven, normally-on gallium nitride (GaN) power transistors. Preferably, a low power, high speed CMOS driver circuit with an integrated low voltage, lateral MOSFET driver is series coupled, in a hybrid cascode arrangement, to a high voltage GaN HEMT and provides for improved control of noise and voltage transients. Monitoring and control functions, including latching and clamping, are based on monitoring of Vcc conditions for shut-down and start-up conditioning to enable safer operation, particularly for high voltage and high current switching. Preferred embodiments also provide isolated, self-powered, high speed driver devices, with reduced input losses.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
A semiconductor device in provided having a substrate and a semiconductor layer formed on a main surface of the substrate. A plurality of first island electrodes and a plurality of second island electrodes are placed over the semiconductor layer. The plurality of first island electrodes and second island electrodes are spaced apart from each other so as to be alternatively arranged to produce two-dimensional active regions in all feasible areas of the semiconductor layer. Each side of the first island electrodes is opposite a side of the second island electrodes. The semiconductor device can also include a plurality of strip electrodes that are formed in the regions between the first island electrodes and the second island electrodes. The strip electrodes serve as the gate electrodes of a multi-island transistor. The first island electrodes serve as the source electrodes of the multi -island transistor. The second island electrodes serve as the drain electrodes of the multi-island transistor. A plurality of connections to the gate electrodes are provided at each interstice defined by corners of the first island electrodes and the second island electrodes.
H01L 29/41 - Electrodes characterised by their shape, relative sizes or dispositions
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
H01L 29/201 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds
23.
HIGH DENSITY GALLIUM NITRIDE DEVICES USING ISLAND TOPOLOGY
A Gallium Nitride (GaN) series of devices - transistors and diodes are disclosed - that have greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The devices also include a simpler and superior flip chip connection scheme and a means to re-duce the thermal resistance. A simplified fabrication process is disclosed and the layout scheme which uses island electrodes rather than finger electrodes is shown to increase the active area density by two to five times that of conventional interdigitated structures. Ultra low on resistance transistors and very low loss diodes can be built using the island topology. Specifically, the present disclosure provides a means to enhance cost/effective performance of all lateral GaN structures.
24.
HIGH DENSITY GALLIUM NITRIDE DEVICES USING ISLAND TOPOLOGY
A Gallium Nitride (GaN) series of devices - transistors and diodes are disclosed - that have greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The devices also include a simpler and superior flip chip connection scheme and a means to reduce the thermal resistance. A simplified fabrication process is disclosed and the layout scheme which uses island electrodes rather than finger electrodes is shown to increase the active area density by two to five times that of conventional interdigitated structures. Ultra low on resistance transistors and very low loss diodes can be built using the island topology. Specifically, the present disclosure provides a means to enhance cost/effective performance of all lateral GaN structures.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H01L 27/085 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
25.
ISLAND MATRIXED GALLIUM NITRIDE MICROWAVE AND POWER SWITCHING TRANSISTORS
A gallium nitride (GaN) device that has greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The layout scheme, which uses island electrodes rather than finger electrodes, is shown to increase the active area density over that of conventional interdigitated structures. Ultra low on resistance transistors can be built using the island topology. Specifically, the present invention, which uses conventional GaN lateral technology and electrode spacing, provides a means to enhance cost/effective performance of all lateral GaN structures.
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 64/20 - Electrodes characterised by their shapes, relative sizes or dispositions
