Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface; a material on the surface of the glass layer, the material including a positive-type photo-imageable dielectric (PID) material; a via including a conductive material, wherein the via extends through the glass layer and through the material on the surface of the glass layer, and wherein the via has a first diameter through the material on the surface, a second diameter at the surface of the glass layer, and the first diameter is equal to the second diameter plus 1 micron or minus 1 micron; and a dielectric layer on the material at the surface of the glass layer, the dielectric layer including a conductive pathway electrically coupled to the via.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
2.
LOW Z-HEIGHT SEPARABLE LIQUID METAL BASED ELECTRICAL INTERCONNECT
Embodiments disclosed herein include an interconnect structure. In an embodiment, the interconnect structure is an apparatus that comprises a substrate with a well through a thickness of the substrate. In an embodiment, the substrate comprises a polymer foam. In an embodiment, a liquid metal is in the opening, and the liquid metal comprises voids.
Integrated circuit structures having varied internal spacers and epitaxial source or drain structures are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure between first internal spacers having a maximum lateral width. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure between second internal spacers having a maximum lateral width greater than the maximum lateral width of the first internal spacers.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Techniques for instruction prefix encoding for cryptographic computing capability data types are described. In an embodiment, an apparatus includes an instruction decoder to decode a first instruction including a first prefix; and cryptography circuitry to perform a cryptographic operation on data, the cryptographic operation to be based at least in part on the first prefix and a relative enumeration in a pointer to the data.
Integrated circuit structures having varied etch-stop for epitaxial source or drain structures are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure having a lateral width, and the first epitaxial source or drain structure beneath a first etch-stop layer. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure having a lateral width greater than the lateral width of the first epitaxial source or drain structure, and the second epitaxial source or drain structure beneath a combination of the first etch stop layer and a second etch-stop layer.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
Network apparatus, communicatively coupled to a provider of services, that includes gateway circuitry to receive application programming interface (API) request data from a computing device that indicates a requested service. The gateway circuitry is to (1) select, based upon the API request data, at least one of the services corresponding to the requested service, and (2) generate, based upon mapping of the API request data to the at least one of the services, corresponding request data specifically for use in invoking the at least one of the services. The gateway circuitry is to (1) generate the corresponding request data by performing at least one programmable transformation, (2) be used in association with at least one proxy-related operation, (3) register the services for use in association with service discovery, and (4) verify the API request data and an identity associated with the computing device.
Physical therapy assistant-as-a-service (PTaaS) enables the automatic evaluation of a patient's performance of physical therapy exercises and the automatic provision of feedback to the patient on their exercise performance in real-time. A patient device can provide real-time patient exercise video to a PTaaS backend that performs checks prior to the patient performing the exercise (pre-checks) and checks during patient performance of the exercise (live checks). If any of the checks fail, the PTaaS can provide feedback to the patient, such as if the patient is in an incorrect starting pose or has a body part at an incorrect angle before beginning the exercise or if the patient's form or posture during performance of the exercise needs to be adjusted. The PTaaS can automatically generate exercise metrics, reports, and physical therapy insights that a physical therapy clinician can access from a clinician portal.
G16H 20/30 - ICT specially adapted for therapies or health-improving plans, e.g. for handling prescriptions, for steering therapy or for monitoring patient compliance relating to physical therapies or activities, e.g. physiotherapy, acupressure or exercising
8.
LOCAL DENSITY CONTROL FOR METAL CAPACITANCE REDUCTION
An integrated circuit structure includes a plurality of interconnect lines and a plurality of dummy lines that are co-planar with the plurality of interconnect lines, where a ratio of line length to end-to-end spacing of the dummy lines varies inversely with a density of the interconnect lines within each of a plurality of regions. The regions are of approximately equal area within a rectangular grid array.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Particular embodiments described herein provide for an electronic device that is configured to receive audio data related to a conference call from a network conference engine, sample the audio data at a frame rate, determine an amount of missing samples of audio data for a predetermined amount of time, and communicate, to the network conference engine, a notification when the amount of missing samples of audio data for the predetermined amount of time is greater than a lost sample threshold. The electronic device can also be configured to receive visual content and visual content verification data from the network conference engine and use the visual content verification data to determine if visual content to be rendered on a display of the electronic device is the same or similar to the received visual content from the network conference engine.
Described herein is a graphics processor having processing resources with configurable thread and register configurations. Program code can configure a number of registers and accumulators that will be used by hardware threads during execution of the program code by the graphics processor. Processing resources within the graphics processor can be configured to assign different numbers of registers and accumulators to hardware threads based on the configuration requested by program code to be executed by the processing resource.
Gate-all-around integrated circuit structures having asymmetric source and drain contact structures, and methods of fabricating gate-all-around integrated circuit structures having asymmetric source and drain contact structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a fin. A gate stack is over the vertical arrangement of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. A first conductive contact structure is coupled to the first epitaxial source or drain structure. A second conductive contact structure is coupled to the second epitaxial source or drain structure. The second conductive contact structure is deeper along the fin than the first conductive contact structure.
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A computing apparatus, including: a hardware computing platform; and logic to operate on the hardware computing platform, configured to: receive a microservice instance registration for a microservice accelerator, wherein the registration includes a microservice that the microservice accelerator is configured to provide, and a microservice connection capability indicating an ability of the microservice instance to communicate directly with other instances of the same or a different microservice; and log the registration in a microservice registration database.
This disclosure describes systems, methods, and devices related to control frames status. A device may receive a control frame from a station (STA) at a beginning of a transmission opportunity (TxOP) that includes availability and unavailability information. The device may acknowledge the availability and unavailability information of the STA based on fields within the control frame, including unavailability target start time field and unavailability duration field. The device may adjust a transmission schedule to avoid transmitting to the STA during its indicated unavailability period. The device may initiate a TxOP with an initial control frame that includes updated availability and unavailability information based on the control frame from the STA.
Various approaches to efficiently allocating and utilizing hardware resources in data centers while maintaining compliance with a service level agreement are described. In various embodiments, an application-level service level objective (SLO) specified for a computational workload is translated into a hardware-level SLO to facilitate direct enforcement by the hardware processor, e.g., using a feedback control loop or model-based mapping of the hardware-level SLO to allocations of microarchitecture resources of the processor. In some embodiments, a computational model of the hardware behavior under resource contention is used to predict the application performance (e.g., as measured in terms of the hardware-level SLO) to be expected under certain contention scenarios. Scheduling of workloads among the compute nodes within the data center may be based on such predictions. In further embodiments, configurations of microservices are optimized to minimize hardware resources while meeting a specified performance goal.
Embodiments attempt to solve challenges in a wireless communications system. Embodiments describe various techniques, systems, and devices to support various measurement and interruption criteria for access nodes and user equipment in a 3GPP 5G NR or 6G system, among other wireless communications systems. Other embodiments are described and claimed.
This disclosure describes systems, methods, and devices for supporting protocol data unit (PDU) set-level quality of service (QoS) handling. Processing circuitry of an application function (AF), of a user plane function (UPF), and of a session management function (SMF) may provide, by the AF, protocol description information for PDU set-level QoS handling to the UPF, the PUD set-level QoS handling indicative of PDU set-level information; identify, by the SMF, the protocol description information; provide, by the SMF, the protocol description information to the UPF; identify, by the UPF, a PSI of a detected downlink packet either based on matching the protocol description metadata received by the UPF; encapsulate, by the UPF, the downlink packet in a general packet radio service tunneling protocol for user plane (GTP-U) header.
Various aspects may provide a molding system. The molding system may include a molding unit which includes a first mold panel and a second mold panel. The first mold panel and the second mold panel may include a mold cavity which surrounds a semiconductor workpiece along a side surface of the semiconductor workpiece, with the first mold panel and the second mold panel engaged with the semiconductor workpiece. Various aspects may also provide a molding method which utilize the molding system.
B29C 45/14 - Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mouldApparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles
Methods and device to implement the use of proximity sensor data and time-averaging specific absorption rate methods in determining whether to apply or remove a power back-off to a radio frequency transmitter. The methods and devices may be configured to detect whether a body is proximately located based on obtained proximity sensor data; define an upper threshold for a radio frequency (RF) transmit power and a lower threshold for the RF transmit power; calculate an average power of an RF transmitter over a fixed time period; and based on whether the body is detected, the average power, and a comparison of the average power to the upper threshold or the lower threshold, determine whether to apply or remove a power back-off to the RF transmitter.
H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets
19.
OFDMA TRIGGER BASED PEER TO PEER OPERATIONS WITH DUAL-STAGE TRIGGERING
A station (STA) may operate as a first peer-to-peer (P2P) client (P2P1) for P2P operations with dual-stage triggering. The STA may decode a primary frame trigger frame (TF) from an access point (AP) operating as a coordinator. The primary TF may allocate resources in an initial portion of a time-duration allocation to the P2P1 for the P2P operations with one or more other peer stations, including a second P2P client (P2P2) and a third P2P client (P2P3). The primary TF may further allocate resources in a subsequent portion of the time-duration allocation to the P2P2 for the P2P operations. The STA may also encode a first secondary TF for transmission within the initial portion of the time-duration allocation. The first secondary TF may allocate specific resource units (RUs) to the one or more other peer stations. The STA may also decode a TB physical layer protocol data unit (TB PPDU) encoded in accordance with a multi-user orthogonal frequency division multiple access (MU OFDMA) frame format. The TB PPDU may be received concurrently within the initial portion of the time-duration allocation from the one or more other peer stations in accordance with an uplink OFDMA technique.
Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface; a material on the surface of the glass layer, the material including a polyimide or a dielectric material; a via including a conductive material, wherein the via extends through the glass layer and through the material on the surface of the glass layer, and wherein the via has a first diameter through the material on the surface, a second diameter at the surface of the glass layer, and the first diameter is equal to the second diameter plus 1 micron or minus 1 micron; and a dielectric layer on the material at the surface of the glass layer, the dielectric layer including a conductive pathway electrically coupled to the via.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
21.
CHANNEL ACCESS SENSING AND FREQUENCY INTERLACING FOR SIDELINK COMMUNICATION
Various embodiments herein provide techniques for sidelink communication, e.g., in an unlicensed frequency band. For example, embodiments may relate to channel access sensing procedures, e.g., in association with a listen-before-talk (LBT) procedure for unlicensed spectrum. Embodiments may further relate to a frequency interlaced physical structure for sidelink communication. Other embodiments may be described and claimed.
Various aspects provide a transceiver and a communication device including the transceiver. In an example, the transceiver includes an amplifier circuit including an amplifier stage with an adjustable degeneration component, the amplifier stage configured to amplify a received input signal with an adjustable gain, an adjustable feedback component coupled to the amplifier stage; and a controller coupled to the amplifier stage and to the adjustable feedback component and configured to adjust the adjustable feedback component based on an adjustment of the adjustable degeneration component.
A computer-readable storage medium stores instructions to configure one or more processors of a Further Reduced Capacity (F-RedCap) UE for operation in a 5G NR network, and to cause the F-RedCap UE to perform operations including decoding a PBCH to obtain a numerology parameter. A maximum resource block (RB) allocation is determined for a bandwidth associated with the numerology parameter. The maximum RB allocation is adjusted based on a reduced bandwidth associated with the F-RedCap UE to obtain an adjusted RB allocation. A maximum data rate is determined based on the numerology parameter and the adjusted RB allocation. Data is encoded for an uplink (UE) transmission to a base station. The UE transmission uses the maximum data rate.
The disclosure provides an apparatus, method, device and medium for 3D dynamic sparse convolution. The method includes: receiving an input feature map of a 3D data sample; performing input feature map partition to divide the input feature map into a plurality of disjoint input feature map groups; performing a shared 3D dynamic sparse convolution to the plurality of disjoint input feature map groups respectively to obtain a plurality of output feature maps corresponding to the plurality of disjoint input feature map groups, wherein the shared 3D dynamic sparse convolution comprises a shared 3D dynamic sparse convolutional kernel; and performing output feature map grouping to sequentially stack the plurality of output feature maps to obtain an output feature map corresponding to the input feature map. (FIG. 2).
Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.
Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack structure of a quantum dot device, wherein the quantum well stack structure includes an insulating material to define multiple rows of quantum dot formation regions; and a gate that extends over multiple ones of the rows.
B82Y 10/00 - Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
B82Y 40/00 - Manufacture or treatment of nanostructures
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H10D 30/40 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
H10D 48/00 - Individual devices not covered by groups
H10D 62/81 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wellsSemiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures having periodic or quasi-periodic potential variation
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
A computing device includes last level cache (LLC) for processing cores and a separate input/output (I/O) LLC for use in facilitating data transfers between the computing device and one or more I/O devices. The I/O LLC is configured to include a set of partitions corresponding to a set of classes. Usage of the partitions in the set of partitions is monitored and the set of partitions is dynamically adjusted based on the usage. A process in a particular one of the classes makes a data request and a particular one of the partitions associated with the particular class is used in the data request.
A wavelength multiplexing optical fiber transmitter, receiver, or transceiver where multiple emitters and/or photodetectors of different center wavelengths are coupled to a single optical fiber core terminus through multiple waveguides, which may be directly printed in free space. The optical assemblies described are suitable for optical data link applications, for example, to reduce a number of optical fibers needed for a given bandwidth or increase the bandwidth of a give number of optical fibers. Bidirectional fiber termination may also be implemented with an emitter and a photodetector pair coupled to a single optical fiber core terminus through multiple waveguides.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
H04J 14/02 - Wavelength-division multiplex systems
29.
INTEGRATED CIRCUIT STRUCTURE WITH VARIED EPITAXIAL SOURCE OR DRAIN STRUCTURES
Integrated circuit structures having varied epitaxial source or drain structures are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure having a lateral width. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure having a lateral width greater than the lateral width of the first epitaxial source or drain structure.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Various embodiments herein provide techniques related to hybrid automatic repeat request (HARQ) feedback of a new radio (NR) sidelink (SL) transmission. Specifically, in embodiments, a user equipment (UE) may perform, in a first slot of a plurality of slots, a listen before talk (LBT) procedure related to a NR SL transmission. The UE may further identify a subset of two or more candidate slots of the plurality of slots for transmission of a HARQ message related to the LBT procedure. The UE may further transmit the HARQ message in a candidate slot of the two or more candidate slots. Other embodiments may be described and/or claimed.
A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
Embodiments are generally directed to selective packing of patches for immersive video. An embodiment of a processing system includes one or more processor cores; and a memory to store data for immersive video, the data including a plurality of patches for multiple projection directions. The system is to select the patches for packing, the selection of the patches based at least in part on which of the multiple projection directions is associated with each of the patches. The system is to encode the patches into one or more coded pictures according to the selection of the patches.
Integrated circuit (IC) packages having a through-via interposer with an embedded die, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC package may include a through-via interposer with an embedded die, the through-via connections having front to back conductivity. In some embodiments, a die may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the embedded die. In some embodiments, a second IC package in a package-on-package (POP) arrangement may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the conductive vias.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
34.
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH VERTICAL SIDEWALLS
Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.
Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
36.
APPROXIMATING ACTIVATION FUNCTIONS IN NEURAL NETWORKS WITH PROGRAMMABLE LOOK-UP TABLE
An activation function in a neural network may be approximated by one or more linear functions. A linear function may correspond to a segment of the input range of the activation function, e.g., a linear segment. A programmable look-up table may store slopes and intercepts of linear functions. A post processing engine (PPE) array executing the activation function may determine that an input data element of the activation function falls into the linear segment and compute an output of the linear function using the input data element. The output of the linear function may be used as the approximated output of the activation function. Alternatively, the PPE array may determine that the input data element is in a saturation segment and use a fixed value associated with the saturation segment as the approximated output of the activation function.
Tensor multiplication operations in a deep neural network (DNN) may be performed at multiple precision levels. Various precision levels may be selected for various DNN layers to achieve a desired accuracy of the DNN with minimized consumption of computational resource. A precision level may be selected from a plurality of predetermined precision levels for a layer. The layer may include a tensor multiplication operation on an activation tensor and a weight tensor. An activation in the activation tensor may be converted to lower-precision activations. A weight in the weight tensor may be converted to lower-precision weights. An algorithm determined based on the selected precision level may be used to compute an approximate product of an activation and weight using the lower-precision activations and lower-precision weights. A different precision level may be selected for a different layer, and a different algorithm may be used to compute products in the different layer.
Described herein are IC devices include tight-pitched patterned metal layers, such as metal gratings, and processes for forming such patterned metal layers. The processes include subtractive metal patterning, where portions of a metal layer are etched and replaced with an insulator to form the metal grating. Masks for etching portions of the metal layer are generated using directed self-assembly (DSA). In some examples, multiple etching steps are performed, e.g., to generate metal lines at a first pitch, and to add additional lines at half of the first pitch. In some examples, additive metal patterning is performed in addition to subtractive metal patterning.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
Camera tuning process is a time consuming and labor-intensive process. To address this issue, camera tuning system including a multi-modal large language model and a retrieval-augmented generation system can be implemented to intelligently and efficiently handle a camera tuning task in real-time. The multi-modal large language model can evaluate image quality and can be finetuned using high-quality labeled data and synthetically generated labeled data. The retrieval-augmented generation system can incorporate camera configuration knowledge into a vector database and can leverage a retrieved context to generate a configuration solution that addresses image quality issues identified by the multi-modal large language model. The resulting camera tuning system is a unified process that can identify image quality issues and provide configuration solutions that address both technical and aesthetic image quality concerns.
Examples include techniques to implement mutual authentication for confidential computing. Examples are described of implementing mutual authentication for confidential computing that includes use of local attestation.
Techniques for low power indoor/outdoor detection are disclosed. In the illustrative embodiment, an integrated sensor hub receives data from an accelerometer. The sensor hub processes the accelerometer data to determine an activity of the user. Depending on the activity of the user, the sensor hub may determine whether the compute device is indoors or outdoors or may receive data from additional sensors, such as a magnetometer, a gyroscope, or an ambient light sensor. The additional sensor data may be used to determine whether the compute device is inside or outside.
G05B 13/02 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric
G01J 1/42 - Photometry, e.g. photographic exposure meter using electric radiation detectors
G01P 15/00 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration
G01R 33/00 - Arrangements or instruments for measuring magnetic variables
Embodiments disclosed herein include a capacitor apparatus. In an embodiment, the apparatus comprises a first metal layer and a first plate above the first metal layer, where the first plate is electrically conductive. In an embodiment, a second plate is above the first plate, where the second plate is electrically conductive, and a third plate is above the second plate, where the third plate is electrically conductive. In an embodiment, a second metal layer is above the third plate, and a first via is between the first metal layer and the second metal layer, where the first via contacts the first plate and the third plate. In an embodiment, a second via is between the first metal layer and the second metal layer, where the second via contacts the second plate, and a third via is between the first metal layer and the first plate.
H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
43.
PACKAGE ARCHITECTURE WITH THERMAL ENHANCEMENTS FOR VERTICALLY ORIENTED INTEGRATED CIRCUIT DIES
Embodiments of a microelectronic assembly comprise: a first set comprising one or more of first integrated circuit (IC) dies; a second set comprising another one or more of the first IC dies; a plate between, and in direct contact with, the first set and the second set; and a second IC die coupled to the first set, the second set, and the plate. Each IC die comprises a substrate of semiconductor material and an interconnect region including metallization in interlayer dielectric (ILD), the substrate and the interconnect region share a planar interface, and the first IC dies and the second IC die are arranged with the planar interfaces of the first IC dies parallel to each other and orthogonal to the planar interface of the second IC die.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/467 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing gases, e.g. air
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
44.
INTEGRATED CIRCUIT DEVICES WITH BACKSIDE SEMICONDUCTOR STRUCTURES
An IC device may include a semiconductor structure and a backside semiconductor structure over the semiconductor structure. The semiconductor structure and backside semiconductor structure may constitute the source or drain region of a transistor. The backside semiconductor structure may be closer to the backside of a substrate of the IC device than the semiconductor structure. The backside semiconductor structure may be formed at a lower temperature than the semiconductor structure. The backside semiconductor structure may have one or more different materials from the semiconductor structure. For instance, a semiconductor material in the backside semiconductor structure may have a different crystal direction from a semiconductor material in the semiconductor structure. As another example, the backside semiconductor structure may have one or more different chemical compounds from the semiconductor structure. The backside semiconductor structure may be over a backside via that can couple the backside semiconductor structure to a backside metal layer.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
An apparatus includes a host interface; a network interface; hardware storage to store a flow table; and programmable circuitry comprising processors to implement network interface functionality and to: implement a hash table and an age context table, wherein the hash table and the age context table are to reference flow rules maintained in the flow table; process a synchronization packet for a flow by adding a flow rule for the flow to the flow table, adding a hash entry corresponding to the flow rule to the hash table, and adding an age context entry for the flow to the age context table; and process subsequent packets for the flow by performing a first lookup at the hash table to access the flow rule at the flow table and by performing a second lookup at the age context table to apply aging rules to the flow rule in the flow table.
Disclosed embodiments are relate to heat transfer devices or heat exchangers for computing systems, and in particular, to heat pipes for improved thermal performance at a cold plate interface. A thermal exchange assembly includes a heat pipe (HP) directly coupled to a cold plate. The HP includes a window, which is a recessed or depressed portion of the HP. The window is attached to the cold plate at a window section of the cold plate. The cold plate is configured to be placed on a semiconductor device that generates heat during operation. The cold plate transfers the heat to the HP with less thermal resistance than existing HP solutions. Other embodiments may be described and/or claimed.
A processor of an aspect includes a decode unit to decode a matrix multiplication instruction. The matrix multiplication instruction is to indicate a first memory location of a first source matrix, is to indicate a second memory location of a second source matrix, and is to indicate a third memory location where a result matrix is to be stored. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the matrix multiplication instruction, is to multiply a portion of the first and second source matrices prior to an interruption, and store a completion progress indicator in response to the interruption. The completion progress indicator to indicate an amount of progress in multiplying the first and second source matrices, and storing corresponding result data to the third memory location, that is to have been completed prior to the interruption.
A component of a system, including: processor circuitry; and a non-transitory computer-readable storage medium including instructions that, when executed by the processing circuitry, cause the processor circuitry to: receive image data of an object captured by a camera; analyze a visual feature of the object based on the received image data; generate illumination patterns based on the analyzed visual feature; and control arrays of light sources integrated into a plurality of fingers of a robotic gripper to project the illumination patterns within a grasp volume defined by the plurality of fingers during object manipulation to enhance detection of the visual feature of the object, wherein each light source in the arrays of light sources is individually controllable.
B25J 13/08 - Controls for manipulators by means of sensing devices, e.g. viewing or touching devices
B25J 19/00 - Accessories fitted to manipulators, e.g. for monitoring, for viewingSafety devices combined with or specially adapted for use in connection with manipulators
49.
HUMAN-ROBOT INTERFACE SYSTEM WITH BIDIRECTIONAL HAPTIC FEEDBACK
A bidirectional haptic feedback system, including: a flexible membrane configured to be mounted on a handheld controller; sensor-actuator units arranged on the flexible membrane, the sensor-actuator units respectively including a damping mechanism configured to mechanically isolate vibrations between adjacent sensor-actuator units; a control system configured to: generate vibration signals within selected frequency bands within a proximity to a natural resonant frequency range of the sensor-actuator units to drive the actuators of the sensor-actuator units to deliver haptic feedback to a user based on a state of the robot; simultaneously detect user grasp contact and pressure through analysis of back electromotive force (EMF) signals generated by the sensor-actuator units; and adjust robot control parameters dynamically in response to the detected grasp contact and pressure.
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H10B 10/00 - Static random access memory [SRAM] devices
H10D 1/47 - Resistors having no potential barriers
H10D 30/62 - Fin field-effect transistors [FinFET]
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
Various embodiments herein provide techniques related to measurements in a testing scenario by a user equipment (UE) that is configured to use a pre-configured measurement gap (pre-MG). In embodiments, the UE may be configured to perform one or more measurements with the pre-MG disabled. The pre-MG may then be enabled and the UE may perform additional measurements. In this way, a plurality of parameters related to the UE and/or the pre-MG may be identified based on the testing scenario. Other embodiments may be described and/or claimed.
A UE configured for operating in a 5G NR network may decode signalling that schedules two physical downlink shared channels (PDSCHs) in a same time slot. When the UE is a reduced-bandwidth (RBW) reduced-capacity (RedCap) UE (RBW-RedCap UE), the UE may determine if a total number of allocated PRBs in an OFDM symbol for the two scheduled PDSCHs exceed a predetermined value when the two scheduled PDSCHs either partially or fully overlap in time in non-overlapping PRBs. The UE may also prioritize decoding of one of the two scheduled PDSCHs when the total number of allocated PRBs exceed the predetermined value and when the two scheduled PDSCHs either partially or fully overlap in time in non-overlapping PRBs. If a first of the two scheduled PDSCHs is a unicast PDSCH and a second of the two scheduled PDSCHs is a broadcast PDSCH, the UE may prioritize decoding of the unicast PDSCH.
H04W 72/1273 - Mapping of traffic onto schedule, e.g. scheduled allocation or multiplexing of flows of downlink data flows
H04W 72/0446 - Resources in time domain, e.g. slots or frames
H04W 72/51 - Allocation or scheduling criteria for wireless resources based on terminal or device properties
H04W 72/566 - Allocation or scheduling criteria for wireless resources based on priority criteria of the information or information source or recipient
53.
Method and device for post-quantum secure shared secret generation with forward secrecy
A method and device for generating a shared session secret with forward secrecy between a first device and a second device. The first and second devices perform mutual authentication. The first and second devices establish a first shared secret using a key encapsulation mechanism with a long-term cryptographic key pair of the devices. The first and second devices generate an ephemeral cryptographic key pair comprising an ephemeral public key and an ephemeral private key, respectively, and transfer the ephemeral public key of the device to the other device using the first shared secret. The first and second devices then establish a second shared secret using the key encapsulation mechanism with the ephemeral public keys of the first device and the second device. The second shared secret is used as a temporary shared session secret.
Embodiments of the present disclosure are directed to applying the higher effective isotropic radiated power (EIRP) limits that are set to subordinate devices to client devices that meet indoor constrains to form their own networks concurrently to operate as a client under the control of indoor access point (AP). Other embodiments may be described and claimed.
H04W 52/34 - TPC management, i.e. sharing limited amount of power among users or channels or data types, e.g. cell loading
H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets
H04W 88/10 - Access point devices adapted for operation in multiple networks, e.g. multi-mode access points
55.
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH REDUCED CAP
Self-aligned gate endcap (SAGE) architectures with reduced or removed caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with reduced or removed caps, are described. In an example, an integrated circuit structure includes a first gate electrode over a first semiconductor fin. A second gate electrode is over a second semiconductor fin. A gate endcap isolation structure is between the first gate electrode and the second gate electrode, the gate endcap isolation structure having a higher-k dielectric cap layer on a lower-k dielectric wall. A local interconnect is on the first gate electrode, on the higher-k dielectric cap layer, and on the second gate electrode, the local interconnect having a bottommost surface above an uppermost surface of the higher-k dielectric cap layer.
H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.
A multi-slot connector having reduced DIMM-to-DIMM pitch distances can support up to 64 memory channels for next generation DDR (double data rate) technology, including DDR6. To support the increase in memory channels, while compensating for limited form factor motherboards, the multi-slot connector includes two or more slots for devices, such as DIMMs, to connect to a motherboard or other platform. Reduced pitch distances between the DIMMs, shortened connector pins, thinner contacts, and complementary reduced pitch distances in a ball grid array (BGA) used to connect to the motherboard or other platform, provides a compact multi-slot connector that can support up to 64 memory channels with improved performance characteristics. An optional cooling device can be employed between the slots as needed to maintain optimal performance.
A method comprises fetching, by fetch circuitry, an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded XOR3PP instruction to generate a decoded XOR3PP instruction; and executing, by execution circuitry, the decoded XOR3PP instruction to determine a first rotational value and a second rotational value, perform a rotate operation on at least a portion of the first value based on the first rotational value to generate a rotated third value, perform an XOR operation on at least a portion of the first value, at least a portion of the second value, and the rotated third value to generate an XOR result, perform a rotate operation on the XOR result based on the second rotational value to generate a rotated XOR; and store the rotated XOR result.
An IC device with one or more transistors may also include one or more vias and jumpers for delivering power to the transistors. For instance, a via may be coupled to a power plane. A jumper may be connected to the via and an electrode of a transistor. With the via and jumper, an electrical connection is built between the power plane and the electrode. The via may be self-aligned. The IC device may include a dielectric structure at a first side of the via. A portion of the jumper may be at a second side of the via. The second side opposes the first side. The dielectric structure and the portion of the jumper may be over another dielectric structure that has a different dielectric material from the dielectric structure. The via may be insulated from another electrode of the transistor, which may be coupled to a ground plane.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A fabrication method and associated integrated circuit (IC) structures and devices that include one or more conductive vias is described herein. In one example, a conductive via is formed from one side of the integrated circuit, and then a portion of the conductive via is widened from a second side of the IC structure opposite the first side. In one example, a resulting IC structure includes a first portion having a first width, a second portion having a second width, and a third portion having a third width, wherein the third portion is between the first portion and the second portion, and the third width is smaller than the first width and the second width. In one such example, the conductive via tapers from both ends towards the third portion between the ends.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
The present disclosure is directed to a high-voltage magnetron sputtering tool with an enhanced power source including a vacuum chamber containing a magnetron cathode with a magnet array, a target, and an anode, as well as the enhanced power source that includes high-power DC power source and controller that produces a pulsed output. In an aspect, the enhanced power source may include a standard power source that is retrofitted a supplemental high-power DC power source and controller, and alternatively, a high-power DC power source and controller that replaces the standard power source. In addition, the present disclosure is directed to methods for depositing a hydrogen-free diamond-like carbon film on a semiconductor substrate using the high-voltage magnetron sputtering tool. In an aspect, the hydrogen-free diamond-like carbon film may be an etch mask having a sp3 carbon bonding that is greater than 60 percent.
Disclosed herein is a method for automatically routing a circuit layout of a metal layer of an interposer is provided. The method may include identifying anchor points of the metal layer; sorting the anchor points by location; determining neighbouring anchor points of a same supply net from the location of the anchor points; and creating vertical straps on the circuit layout plan through the neighbouring anchor points of the same supply net.
Examples described herein relate to a network interface device. In some examples, the network interface device includes a host interface; a direct memory access (DMA) circuitry; a network interface; and circuitry. The circuitry can be configured to: apply, for a tunnel packet, a single match-action rule that comprises a value of the encapsulation header of the tunnel packet and a value of the encapsulated header, wherein the single match-action rule is based on two or more match-action rules.
An apparatus, computer-implemented method, and system for prioritizing a plurality of applications based on memory bandwidth utilization. The apparatus includes memory circuitry, machine-readable instructions, and processor circuitry to determine a bandwidth threshold based on the plurality of applications, wherein the bandwidth threshold is a percentage of total memory bandwidth utilization. The apparatus further receives a hint from the processor circuitry when the bandwidth threshold is exceeded. The apparatus then applies a prioritization policy to the plurality of applications while the bandwidth threshold is exceeded.
Embodiments herein relate to a system which predicts the frequency or phase offset of a primary clock signal relative to a stable reference such as an atomic clock based on the frequency or phase offsets, respectively, of secondary clock signals relative to the frequency or phase, respectively, of the primary clock signal. The system can include a neural network which is trained to learn a correspondence between the offset of the primary clock signal relative to the stable reference and the offsets of the secondary clock signals relative to the primary clock signal. The training can include varying environmental conditions such as temperature, vibration, pressure, humidity or magnetic field. Once trained, the neural network can be used to provide a stable output clock signal based on the primary clock signal and its predicted offset.
H03B 5/04 - Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
H03B 5/32 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
Embodiments herein relate to a clock distribution network (CDN) which has an adjustable path length and therefore an adjustable resonant frequency. In one approach, the CDN includes first and second transmission lines to distribute first and second differential clocks to one or more data lanes. Each transmission line includes a signal conductor and a return conductor. Each data lane can receive a clock signal from respective tap points on the signal conductors of the transmission lines. The return conductors include switch points at different positions along the length of the return conductors which are coupled to respective switches. When a selected switch is closed, the return conductors are short-circuited to one another to reduce their effective length and therefore the resonant frequency of the CDN.
Solder materials and microelectronic devices and systems deploying the solder materials are discussed. The solder material includes a bulk material of tin and bismuth and particles interspersed in the tin and bismuth bulk material. The particles are a metal other than tin and bismuth, and an intermetallic compound is formed around the particles. The intermetallic compound includes the metal of the particles and tin or bismuth. The solder materials are deployed as interconnect structures to interconnect components, such as electrically coupling an integrated circuit package to a motherboard.
An apparatus to facilitate barrier state save and restore for preemption in a graphics environment is disclosed. The apparatus includes processing resources to execute a plurality of execution threads that are comprised in a thread group (TG) and mid-thread preemption barrier save and restore hardware circuitry to: initiate an exception handling routine in response to a mid-thread preemption event, the exception handling routine to cause a barrier signaling event to be issued; receive indication of a valid designated thread status for a thread of a thread group (TG) in response to the barrier signaling event; and in response to receiving the indication of the valid designated thread status for the thread of the TG, cause, by the thread of the TG having the valid designated thread status, a barrier save routine and a barrier restore routine to be initiated for named barriers of the TG.
Systems, apparatus, articles of manufacture, and methods are disclosed to implement personalized skin tone adaptation for images and video. An example apparatus disclosed herein obtains an initial skin tone group distribution for an identified user depicted in an input image. The example apparatus also determines, based on the input image, a plurality of skin tone measurements associated respectfully with a plurality of skin tone groups corresponding to the initial skin tone group distribution. The example apparatus further outputs a revised skin tone group distribution based on the skin tone measurements, the initial skin tone group distribution, and a transition model.
G06V 10/84 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using probabilistic graphical models from image or video features, e.g. Markov models or Bayesian networks
G06T 7/90 - Determination of colour characteristics
G06T 11/60 - Editing figures and textCombining figures or text
G06V 10/56 - Extraction of image or video features relating to colour
70.
MICROELECTRONIC ASSEMBLIES HAVING TOPSIDE POWER DELIVERY STRUCTURES
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate, having a surface, including a first conductive pathway electrically coupled to a power source; a first microelectronic component, having an active side electrically coupled to the surface of the package substrate and an opposing back side, surrounded by an insulating material; a second microelectronic component, having an active side electrically coupled to the surface of the package substrate and an opposing back side, surrounded by the insulating material and including a through-substrate via (TSV) electrically coupled to the first conductive pathway; and a redistribution layer (RDL), on the insulating material, including a second conductive pathway electrically coupling the TSV, the second surface of the second microelectronic component, and the second surface of the first microelectronic component.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
71.
ORTHOGONAL COLD PLATE FOR USE IN ACTIVE LIQUID IMMERSION COOLING
A cold plate comprises a plurality of fins. The individual fins have an opening, and the openings collectively define a first channel through the plurality of fins. During operation of an integrated circuit component attached to the cold plate, coolant is pumped through the cold plate. The coolant flows in a first direction through the first channel and then in a second through second channels located between the fins. The first direction is substantially orthogonal to the second direction. The first channel can comprise a tube that has openings that direct coolant to flow into the second channels. The first channel is located close to the base plate of the cold plate so that there is a high degree of heat transfer between an integrated circuit component attached to the cold plate and coolant flowing through the cold plate.
An electronic device is provided that implements thermally conductive plastic supports that may replace the typical use of “feet” used in conventional electronic devices. The thermally conductive supports may extend through the bottom chassis cover (e.g. the “D cover”) of the electronic device, and be mechanically and thermally coupled to a heat pipe that is in turn coupled to a heat source for which thermal regulation is utilized. The thermally conductive plastic supports may provide a heat path from the heat source to the bottom chassis cover and, when the electronic device is disposed on a surface, an additional heat path may be provided from the heat source to this surface.
Integrated circuit structures having cut metal gates, and methods of fabricating integrated circuit structures having cut metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on but not through the STI structure. The gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.
Self-aligned gate endcap (SAGE) architectures with improved caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with improved caps, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first gate structure and the second gate structure. The gate endcap isolation structure has a higher-k dielectric cap layer on a lower-k dielectric wall. The higher-k dielectric cap layer includes hafnium and oxygen and has 70% or greater monoclinic crystallinity.
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
75.
FRAMEWORK FOR OPTIMIZATION OF MACHINE LEARNING ARCHITECTURES
The present disclosure is related to framework for automatically and efficiently finding machine learning (ML) architectures that are optimized to one or more specified performance metrics and/or hardware platforms. This framework provides ML architectures that are applicable to specified ML domains and are optimized for specified hardware platforms in significantly less time than could be done manually and in less time than existing ML model searching techniques. Furthermore, a user interface is provided that allows a user to search for different ML architectures based on modified search parameters, such as different hardware platform aspects and/or performance metrics. Other embodiments may be described and/or claimed.
Systems, apparatus, articles of manufacture, and methods are disclosed to partition a boot drive for two or more processor circuits. An example apparatus includes at least one first processor circuit to determine at least one first parameter for a first namespace and at least one second parameter for a second namespace to be configured for a non-volatile memory (NVM) boot drive, cause a first controller of the NVM boot drive to create the first namespace based on the at least one first parameter, and cause the first controller to create the second namespace based on the at least one second parameter. Also, the example at least one first processor circuit is to attach the first namespace to the first controller of the NVM boot drive, attach the second namespace to a second controller of the NVM boot drive, and attach the second controller to a bootloader of a second processor circuit.
A transport system, including: a plurality of self-lifting wheel units individually controllable and mounted to a transport platform; one or more sensors mounted to the transport platform and configured to detect a floor obstacle, floor elevation change, or floor surface irregularity; a control system operatively connected to the plurality of self-lifting wheel units and the one or more sensors, wherein the control system is configured to: receive floor obstacle, elevation change, or surface irregularity detection data from the one or more sensors; plan and control the plurality of self-lifting wheel units to selectively lift or lower to maintain stability of the transport platform when traversing the floor obstacle, the floor elevation change, or the floor surface irregularity; and regulate movement of the transport platform to traverse the floor obstacle, the floor elevation change, or the floor surface irregularity based the plan and control.
B60G 17/0165 - Resilient suspensions having means for adjusting the spring or vibration-damper characteristics, for regulating the distance between a supporting surface and a sprung part of vehicle or for locking suspension during use to meet varying vehicular or surface conditions, e.g. due to speed or load the regulating means comprising electric or electronic elements characterised by their responsiveness, when the vehicle is travelling, to specific motion, a specific condition, or driver input to an external condition, e.g. rough road surface, side wind
G01S 17/08 - Systems determining position data of a target for measuring distance only
G01S 17/931 - Lidar systems, specially adapted for specific applications for anti-collision purposes of land vehicles
This disclosure describes systems, methods, and devices related to using padding bits for protecting trigger frames, block acknowledgement request frames, and block acknowledgement frames in Wi-Fi. A device may generate padding bits of a trigger frame, a block acknowledgment request frame, or a block acknowledgement frame; generate one or more fields signaling that the padding bits are present in the trigger frame, the block acknowledgement request frame, or the block acknowledgement frame; and cause to send the trigger frame, the block acknowledgement request frame, or the block acknowledgement frame to one or more STAs, the trigger frame, the block acknowledgement request frame, or the block acknowledgement frame including the one or more fields and the padding bits.
Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (Vt). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vt within the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
80.
PUBLISH-SUBSCRIBE CLASSIFICATION IN A CROSS-DOMAIN SOLUTION
A cross-domain device includes interfaces to couple to a first device, second device, and third device. The cross-domain device creates a first buffer in its shared memory to allow writes by the first device associated with a first software module and reads by the second device associated with a second software module, and creates a second buffer in the shared memory separate from the first buffer to allow writes by the first device associated with the first software module and reads by the third device associated with a third software module. The cross-domain device uses the first buffer to implement a first memory-based communication link between the first software module and the second software module, and uses the second buffer to implement a second memory-based communication link between the first software module and the third software module.
A cross-domain device includes a memory with a shared memory region. The device further includes a first interface to couple to a first device over a first interconnect, where the first device implements a first domain, and includes a second interface to couple to a second device over a second interconnect, where the second device implements a second domain, and the first domain is independent of the second domain. The cross-domain device is to create a buffer in the shared memory region to allow writes by a first software module in the first domain and reads by a second software module in the second domain, and use the buffer to implement a memory-based communication link between the first software module and the second software module.
Glass cores with embedded power delivery components are disclosed. An example apparatus includes a glass layer including an opening, a dielectric material within the opening, a first cluster of inductors extending through the dielectric material, and a second cluster of inductors extending through the dielectric material, the second cluster spaced apart from the first cluster, the dielectric material extending continuously from around the first cluster to around the second cluster.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
Porous liners for through-glass vias and associated methods are disclosed. An example apparatus includes a glass layer having a through-hole. The example apparatus further includes a conductive material within the through-hole. The example apparatus also includes a porous material between at least a portion of the conductive material and at least a portion of a sidewall of the through-hole.
An apparatus for a user equipment (UE) is configured for operation in a Next Generation Radio Access Network (RAN). The apparatus includes processing circuitry to encode a radio resource control (RRC) setup request message for transmission to a distributed unit (DU) function of a base station. The processing circuitry is to decode an RRC setup message received from the DU function. The RRC setup message is responsive to the RRC setup request message. The processing circuitry is to perform a selection of a public land mobile network (PLMN) based on the RRC setup message. The processing circuitry is to encode an RRC setup complete message for transmission to the DU function. The RRC setup complete message includes a global unique temporary identifier (GUTI) of the UE, an access and mobility management function (AMF) identification (ID) of a previously contacted AMF, and an ID of the PLMN.
Examples to determine a dynamic batch size of a layer are disclosed herein. An example apparatus to determine a dynamic batch size of a layer includes a layer operations controller to determine a layer ratio between a number of operations of a layer and weights of the layer, a comparator to compare the layer ratio to a number of operations per unit of memory size performed by a computation engine, and a batch size determination controller to, when the layer ratio is less than the number of operations per unit of memory size, determine the dynamic batch size of the layer.
Apparatus including speakers ported through keys of a keyboard are disclosed. An example electronic device includes a housing, and a keyboard carried by the housing. The keyboard includes a key having a keycap that covers an associated switch. The example electronic device further includes a speaker within the housing underneath the keyboard. The keycap includes an opening to define a port through which sound from the speaker is able to pass.
H01H 13/7065 - Switches having rectilinearly-movable operating part or parts adapted for pushing or pulling in one direction only, e.g. push-button switch having a plurality of operating members associated with different sets of contacts, e.g. keyboard with contacts carried by or formed from layers in a multilayer structure, e.g. membrane switches characterised by construction, mounting or arrangement of operating parts, e.g. push-buttons or keys characterised by the mechanism between keys and layered keyboards
This disclosure describes systems, methods, and devices related to enhanced service period updates. A device may receive, from a station (STA), a negotiation request that identifies a service period and one or more transmission and reception (Tx/Rx) parameters to be updated during the service period. The device may define the service period based on the received negotiation request, wherein the service period is determined using a target wake time (TWT) element. The device may adjust, based on the negotiation request, the one or more Tx/Rx parameters for operation during the service period, wherein the one or more Tx/Rx parameters include at least a maximum modulation and coding scheme (Max MCS). The device may transmit a confirmation to the STA after updating the one or more Tx/Rx parameters. The device may revert the one or more Tx/Rx parameters to default values outside the service period.
A cross-domain device includes a first interface to couple to a first device and a second interface to couple to a second device, where the first device is to implement a first component in a radio access network (RAN) system in a first computing domain, and the second device is to implement a second component in the RAN system in a second computing domain. The first component is to interface within the second component in a RAN processing pipeline. The cross-domain device further comprises hardware to implement a communication channel between the first device and the second device to pass data from the first component to the second component, where the communication channel enforces isolation of the first computing domain from the second computing domain.
A fabrication method and associated integrated circuit (IC) structures and devices that include one or more self-insulated vias is described herein. In one example, an IC structure includes a via surrounded by an insulator material and a layer of insulator material between a conductive material of the via and the surrounding insulator material. In one example, the layer of insulator material has one or more material properties that are different than the surrounding insulator material, including one or more of a different density, a different dielectric constant, and a different material composition.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
90.
INFRASTRUCTURE-BASED COLLABORATIVE AUTOMATED PARKING AND LOCATION MANAGEMENT
Systems and techniques for location management are described herein. In an example, a system may include at least one processor and at least one memory with instructions stored thereon that when executed by the processor, cause the processor to obtain data originating from one or more sensors proximate to the location. A trained activity-based detection model may identify an activity at the location and perform a determination of a service to be offered at the location based on the detected activity. The system may then send a message to a user offering the service to the user, and in response to receiving an authorization accepting the service from the user, cause the service to be implemented at the location, which may include classifying the service as a service type, matching the service type to a service provider, and sending a notification to the service provider.
B60L 53/36 - Means for automatic or assisted adjustment of the relative position of charging devices and vehicles by positioning the vehicle
B60L 53/63 - Monitoring or controlling charging stations in response to network capacity
B60L 55/00 - Arrangements for supplying energy stored within a vehicle to a power network, i.e. vehicle-to-grid [V2G] arrangements
G06Q 20/40 - Authorisation, e.g. identification of payer or payee, verification of customer or shop credentialsReview and approval of payers, e.g. check of credit lines or negative lists
Systems, apparatus, articles of manufacture, and methods are disclosed provide a trust assurance for GUI controls presented on client display. At least one non-transitory machine-readable medium includes machine-readable instructions to cause at least one processor circuit to at least: generate a graphical user interface; obtain an image associated with a destination for the graphical user interface; embed a first plurality of pixels of the image into at least one of a hue channel, a saturation channel, or a luminance channel of a second plurality of pixels of the graphical user interface to create an embedded graphical user interface; and cause the embedded graphical user interface to be sent to the destination.
Systems, apparatus, articles of manufacture, and methods are disclosed to implement seamless switching of dynamic range and/or refresh rate on display devices. An example apparatus disclosed herein causes a display to activate panel self refresh after a command to switch a graphics output from a first dynamic range to a second dynamic range, the graphics output provided to the display. The example apparatus also switches the graphics output from the first dynamic range to the second dynamic range after the panel self refresh is activated. The example apparatus further causes the display to deactivate the panel self refresh after the graphics output is switched to the second dynamic range.
Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.
Examples described herein relate to performing source routing of a packet to route the packet from a source to a destination through multiple routers by specification of a path of logical port identifiers through the multiple routers. In some examples, multiple routers are to translate the logical port identifiers into physical ports based on configurations. In some examples, the path of the packet through the multiple routers is based on a topology of the routers.
Methods and apparatus for DDR5 DIMM power fail monitor to prevent I/O reverse-bias current. An apparatus is configured to be implemented in a host system including a processor having an integrated memory controller (iMC) coupled to one or more DIMMs having an onboard Power Management Integrated Circuit (PMIC). The apparatus includes circuitry to monitor an operating state for a host voltage regulator (VR) providing input power to the processor and monitor an operating state of the PMIC for each of the one or more DIMMs. In response to detecting a fault condition of the host VR or a PMIC for a DIMM, the apparatus prevents reverse bias voltage in circuitry in at least one of the iMC and the one or more DIMMs. The apparatus may implement a finite state machine (FSN) having a plurality of defined states including a fault state used to indicate detection of the fault condition.
Examples described herein relate to processing packets. In some examples, based on receipt of a Hypertext Transfer Protocol (HTTP) packet at a network interface device, the HTTP packet comprising an HTTP body and HTTP header: provide the HTTP header, but not the HTTP body, for processing in user space; modify solely the HTTP header in user space; and in kernel space, combine the modified HTTP header and the HTTP body prior to transmission of the HTTP packet with modified HTTP header to a client.
Various approaches for configuring or operating a floating satellite network ground station on a ship or other marine vessel that transits among multiple geographic areas, are discussed. An example method for configuration includes: receiving configuration information for a compute node (e.g., mobile data center) to be operated as a temporary non-terrestrial network (NTN) ground station, with the compute node located on a marine vessel that has connectivity to the satellite NTN via a feeder link; configuring the compute node to operate as the temporary NTN ground station, based on the configuration information; and modifying the feeder link to perform data communications between the temporary NTN ground station and respective orbiting satellites of the satellite NTN. The feeder link is dynamically modified based on network usage and restrictions applicable to a geographic location of the marine vessel, such as an exclusion zone (EZ) defined for NTN communications.
In one embodiment, an apparatus comprises a log circuit to: identify an input associated with a logarithm operation, wherein the logarithm operation is to be performed by the log circuit using piecewise linear approximation; identify a first range that the input falls within, wherein the first range is identified from a plurality of ranges associated with a plurality of piecewise linear approximation (PLA) equations for the logarithm operation, and wherein the first range corresponds to a first equation of the plurality of PLA equations; compute a result of the first equation based on a plurality of operands associated with the first equation; and return an output associated with the logarithm operation, wherein the output is generated based at least in part on the result of the first equation.
In one embodiment, a matrix processor comprises a memory to store a matrix operand and a strided read sequence, wherein: the matrix operand is stored out of order in the memory; and the strided read sequence comprises a sequence of read operations to read the matrix operand in a correct order from the memory. The matrix processor further comprises circuitry to: receive a first instruction to be executed by the matrix processor, wherein the first instruction is to instruct the matrix processor to perform a first operation on the matrix operand; read the matrix operand from the memory based on the strided read sequence; and execute the first instruction by performing the first operation on the matrix operand.
Embodiments are directed to providing integrity-protected command buffer execution. An embodiment of an apparatus includes a computer-readable memory comprising one or more command buffers and a processing device communicatively coupled to the computer-readable memory to read, from a command buffer of the computer-readable memory, a first command received from a host device, the first command executable by one or more processing elements on the processing device, the first command comprising an instruction and associated parameter data, compute a first authentication tag using a cryptographic key associated with the host device, the instruction and at least a portion of the parameter data, and authenticate the first command by comparing the first authentication tag with a second authentication tag computed by the host device and associated with the command.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
