A memory device of an embodiment includes a stacked body including a plurality of insulating layers and a plurality of gate electrode layers alternately stacked in a first direction, a semiconductor layer provided in the stacked body and extending in the first direction, and a gate insulating layer provided between the semiconductor layer and the gate electrode layer, the gate insulating layer including a first region including a first oxide containing at least one of hafnium oxide or zirconium oxide, the first region including an orthorhombic crystal, and the first region including at least one first element selected from the group consisting of carbon (C), nitrogen (N), chlorine (Cl), boron (B), hydrogen (H), fluorine (F), helium (He), and argon (Ar).
H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
2.
MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
According to one embodiment, when a command executed in a nonvolatile memory is an erase/program command and when a cumulative weight value satisfies a condition that a first input is selected as an input of high priority, a memory system suspends execution of the erase/program command by transmitting a suspend command to the nonvolatile memory. The memory system repeats executing an operation of starting the execution of one read command of the first input and an operation of updating the cumulative weight by using the weight associated with the read command until read command no longer exists in the first input or until the condition that the cumulative weight is larger than the first value is not satisfied, and resumes the execution of the suspended erase/program command.
A semiconductor device according to the present embodiment includes a first pad, a second pad, a third pad, a first bonding wire joined to the first pad, a second bonding wire provided on the second pad with a second stud bump in between, and a third bonding wire joined to the third pad. The second pad is positioned between the first and third pads. The second bonding wire includes a second ball portion and a second wire portion, the second ball portion being joined to the second stud bump, the second wire portion extending from the second ball portion.
According to one embodiment, a semiconductor device includes a device. The device includes a decoder, a generation circuit, a register, and a modifier. The decoder analyzes a command of a received packet. The generation circuit generates a unique device number in accordance with information in the packet. The register holds the generated unique device number. The modifier updates and outputs the packet. When a packet issued by a host is a command packet, among broadcast packets which return to the host through one or more devices, for determining the unique device number, the command packet includes parameters of an initial value and final value of device number.
G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computerOutput arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
According to one embodiment, a memory card includes a nonvolatile memory and a controller. The controller performs initialization of an interface, determines a maximum performance that can be supported from among a plurality of performance predetermined for stream recording, based on a bus configuration of the interface determined at the interface initialization and a maximum allowable power consumption set during the interface initialization, and generates a data set stored in a power state register specified by an NVMe™ standard, which is a power state set in which each of all performance smaller than the determined maximum performance among the plurality of performance corresponds to a power state, to indicate a list of the performance which can be supported for a host.
According to one embodiment, there is provided a nonvolatile memory including a memory cell array, an input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.
According to one embodiment, a host interface circuit includes a physical layer that performs communication with a host, and a protocol control circuit that determines a transfer rate between the physical layer and the host. When a temperature detected by a temperature sensor becomes equal to or higher than a first temperature, the protocol control circuit changes the transfer rate from a first transfer rate to a second transfer rate. The protocol control circuit transitions to a first mode in which a change of the transfer rate based on a first request from the host is prohibited.
A semiconductor device includes a conductive film containing molybdenum and a metal element. The metal element has a melting point lower than the melting point of molybdenum and forms a complete solid solution with molybdenum. The metal element as a material for composing the conductive film is at least one selected from the group consisting of, for example, titanium, vanadium, and niobium.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H03M 13/03 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
H03M 13/35 - Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
10.
MULTI-BIT WRITING AND VERIFICATION IN SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a memory string and a control circuit. The memory string includes a first memory cell connected to a first word line and a second memory cell adjacent to the first memory cell and connected to a second word line. The control circuit is configured to perform a multi-bit-data writing with respect to each of the first and second memory cells. The multi-bit-data writing includes, in order, a first programming to program the first memory cell, the first programming with respect to the second memory cell, a reading of first data from the first memory cell, a second programming to program the second memory cell, and a verification of data programmed in the second memory cell. The control circuit is configured to set a verify voltage to be applied to the second word line during the verification based on the first data.
A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
12.
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor memory device includes first and second memory devices arranged in a first direction, and a plurality of first bump electrodes disposed between the first and the second memory devices. Each of the first and the second memory devices includes a first chip including a memory cell array and a plurality of first electrodes, a second chip including a peripheral circuit and a plurality of second electrodes, and a plurality of second bump electrodes disposed between the first and the second chips. The plurality of first bump electrodes electrically connect the plurality of first electrodes to the plurality of second electrodes. The plurality of second bump electrodes electrically connect the memory cell array to the peripheral circuit in the first and the second memory devices.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
In one embodiment, a semiconductor storage device includes a string that has one end electrically connected to a bit line, and another end electrically connected to a source line, and includes a plurality of memory cells. An operation of writing data to each of a plurality of adjacent first memory cells among the plurality of memory cells is sequentially performed in a direction from a first memory cell on a side of the source line to a first memory cell on a side of the bit line. An operation of reading data from each of the plurality of adjacent first memory cells is performed to allow a current to flow through the string in a first direction from the source line to the bit line.
A memory system includes an interface circuit configured to connect to a host device, a controller electrically connected to the interface circuit, and a nonvolatile semiconductor memory electrically connected to the controller. The controller is configured to transmit a first response in response to a power supplied from the host device via the interface circuit, upon receipt of a first command from the host device after transmitting the first response, determine a status of data stored in the nonvolatile semiconductor memory, and transmit to the host device a second response including the determined status of the data stored in the nonvolatile semiconductor memory.
Various examples, controllers and methods are disclosed relating to parity checking. One controller can perform a plurality of read operations to read first data from the local non-volatile memory and at least one second storage device. The controller further can determine at least one first intermediate parity based on performing at least one first XOR operation of the first data, the at least one first intermediate parity. The controller further can retrieve at least one second intermediate parity of second data from at least one remote buffer of at least one third storage device. The controller further can determine at least one partial parity based on performing at least one second XOR operation of the at least one first intermediate parity and the at least one second intermediate parity. The controller further can store the at least one partial parity in at least one fourth storage device.
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
16.
NON-VOLATILE STORAGE DEVICE OFFLOADING IN A MULTI-DATA NODE ENVIRONMENT
Various examples, controllers and methods are disclosed relating to parity checking. One controller can receive a plurality of data segments from a compute node via an interface. Further, the controller can determine at least one intermediate parity based on performing at least one XOR operation of the plurality of data segments, the at least one intermediate parity being stored in at least one device buffer of the first storage device. Further, the controller can transmit the at least one intermediate parity of the at least one device buffer to at least one parity storage device, wherein the at least one intermediate parity corresponds to one of a plurality of intermediate parities used to determine at least one partial parity of a redundant array of independent disk (RAID) volume. Further, the controller can store the plurality of data segments in at least the first storage device and a second storage device.
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
According to one embodiment, a semiconductor memory device includes: a semiconductor layer arranged above a substrate in a first direction; a first interconnect layer between the substrate and the semiconductor layer; a second interconnect layer arranged adjacent to the first interconnect layer in a second direction; a plurality of memory pillars; and a first member between the first interconnect layer and the second interconnect layer. The semiconductor layer has, on a side of a second surface facing a first surface in contact with the first member, a first projecting portion projecting in the first direction and overlapping a part of an area in the first direction, the area being provided with the first interconnect layer and the first member.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
18.
MEMORY DEVICE WITH MEMORY STRINGS USING VARIABLE RESISTANCE MEMORY REGIONS
A memory device includes a memory cell and a first select transistor. The memory cell includes a variable resistance memory region, a first semiconductor layer in contact with the variable resistance memory region, a first insulating layer in contact with the first semiconductor layer, and a first voltage application electrode in contact with the first insulating layer. The first select transistor includes a second semiconductor layer, a second insulating layer in contact with the second semiconductor layer, and a second voltage application electrode extending in the second direction and being in contact with the second insulating layer.
A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
According to one embodiment, a memory system includes a nonvolatile memory, a first write buffer, a second write buffer having a capacity smaller than that of the first write buffer and a bandwidth larger than that of the first write buffer, and a controller. When the write speed of the first group is less than a first value, the controller loads unloaded data among first data into the first write buffer, and after an amount of the first data reaches or exceeds a minimum write size, writes the first data to a first write destination block. When the write speed of the second group is greater than or equal to the first value, the controller loads second data having the minimum write size into the second write buffer and writes the second data to the second write destination block.
Various implementations relate to receiving, by a first non-volatile memory device from a host, a host command including device context information of a plurality of non-volatile memory devices. The device context includes an address of a buffer of each of the plurality of non-volatile memory devices, in response to receiving the host command. The first non-volatile memory device divides portions of host data corresponding to the host command among the plurality of non-volatile memory devices. The first non-volatile memory device sends to the host a transfer request indicating transfer of each of the portions of the host data to a respective one of the plurality of non-volatile memory devices. The first non-volatile memory device sends to each of the plurality of non-volatile memory devices other than the first non-volatile memory device, a peer command based on the device context information.
According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
G11C 11/4094 - Bit-line management or control circuits
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/08 - Address circuitsDecodersWord-line control circuits
According to an embodiment, a memory system comprising: a non-volatile memory including a plurality of memory cells each capable of storing at least a first bit and a second bit, and configured to calculate third soft bit data based on a logical sum calculation using at least first soft bit data corresponding to the first bit and second soft bit data corresponding to the second bit; and a memory controller configured to restore the first soft bit data and the second soft bit data based on at least first hard bit data corresponding to the first bit, second hard bit data corresponding to the second bit, and the third soft bit data.
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
According to one embodiment, there is provided a semiconductor memory device including a first chip, a second chip and a third chip. In the first chip, plural first conductive layers are stacked via a first insulating layer. In the second chip, plural second conductive layers are stacked via a second insulating layer. A number of stack layers in the plural first conductive layers and a number of stack layers in the plural second conductive layers are different from each other.
G11C 16/26 - Sensing or reading circuitsData output circuits
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
25.
MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE AND METHOD FOR CREATING A LAYOUT THEREOF
A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
A memory device includes a substrate; first conductors aligned apart from each other in a first direction; a second conductor and a third conductor each extending in a second direction between the substrate and the first conductors, and being aligned apart from each other in the second direction; fourth conductors aligned apart from each other in the first direction on an opposite side of the substrate with respect to the first conductors; a fifth conductor extending in the second direction between the first conductors and the fourth conductors; and a first interconnect coupling between the fifth conductor and the substrate. The first interconnect includes a contact extending in the first direction and passing through the first conductors between the second and third conductors.
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
According to one embodiment, a controller, in a case where a first difference between a first number of times of erase and a second number is equal to or smaller than a second threshold, executes a copy operation in a first mode, the second number of times of erase is larger than the first number of times of erase. In a case where the first difference is larger than the second difference, the controller executes the copy operation in a second mode. A ratio of a copy amount to a cumulative data write amount in a first mode is smaller than a ratio of the copy amount to the cumulative data write amount in the second mode. The cumulative data write amount is an amount of data written to the nonvolatile memory based on write commands.
A semiconductor device of the embodiment includes a stacked body, a first insulating layer, first and second staircase portions 2, and a second insulating layer 46. The stacked body includes a first electrode layer 41 (WLDD) and a second electrode layer 41 (SGD). The first and second staircase portions 2 are provided in a first end portion 101 a second end region 102. The second insulating layer 46 extends in the X-direction. The second insulating layer divides the second electrode layer 41 (SGD) in the X-direction direction. A length L1 in the X-direction of the second insulating layer 46 is longer than a length L2 in the x-direction of the second electrode layer 41 (SGD) and shorter than a length L3 in the X-direction of the first electrode layer 41 (WLDD).
H01L 27/11568 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
According to one embodiment, a semiconductor device includes a first element isolating area, a first element area surrounding the first element isolating area, a second element isolating area surrounding the first element area a first gate electrode provided on and across the first element isolating area, the first element area, and the second element isolating area, and a second gate electrode isolated from the first gate electrode and provided on and across the first element isolating area, the first element area, and the second element isolating area.
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
According to one embodiment, a semiconductor memory device includes a housing and terminals. The housing has a first end edge extending in a first direction and a second end edge opposite to the first end edge. The terminals include signal terminals and include first terminals, second terminals, and third terminals. The first terminals are arranged in the first direction at a position close to the first end edge. The second terminals are arranged in the first direction with intervals at a position closer to the first end edge than the second end edge. The first plurality of terminals are closer to the first end edge than the second plurality of terminals are. The third terminals are arranged in the first direction with intervals at a position closer to the second end edge than the first end edge.
According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.
H03M 13/35 - Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 29/04 - Detection or location of defective memory elements
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
32.
SEMICONDUCTOR DEVICE WITH CONDUCTORS DISPOSED IN INSULATING FILMS AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes: a first insulating film; an interconnect disposed in the first insulating film and containing copper, cobalt, nickel, or manganese; a second insulating film that includes a first portion connected to the interconnect and that contains silicon and nitrogen; a third insulating film including a second portion connected to the first portion; a first conductor disposed in the first portion and in contact with the interconnect; a film covering a side surface of the second portion and containing a metal or containing silicon and nitrogen; and a second conductor disposed in the second portion and in contact with the film.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
33.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes first conductive layers, a width in a first direction thereof being a first width, a second conductive layer arranged with first conductive layers, a smaller one of a width in the first direction thereof and a width in a second direction thereof being a second width that is larger than the first width, a third conductive layer in contact with one end portion of at least one of first conductive layers, and a fourth conductive layer in contact with one end portion of the second conductive layer. The at least one of first conductive layers and the second conductive layer contain a first metal, a second metal, and oxygen (O). A concentration of the first metal of the at least one of first conductive layers is higher than a concentration of the first metal of the second conductive layer.
A semiconductor device includes a substrate having a first surface, a first adhesive disposed on the first surface, and a first semiconductor chip disposed on the first adhesive. The semiconductor device further includes a first insulating member disposed on the first surface so as to be in contact with at least a part of the first adhesive. In a first direction perpendicular to the first surface, an upper surface of the first insulating member is higher than or equal to an upper surface of the first adhesive.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A memory system includes a memory device and a memory controller. The memory device includes first to fourth pads to which respective first to fourth signals are sent from the memory controller, a memory cell array configured to store data, and a data input and output interface. The data input and output interface is configured to receive the first signal input to the first pad as a command based on a timing of a first rising edge of the fourth signal at the fourth pad after a rising edge of the second signal at the second pad, and to receive the first signal input to the first pad as an address in response to a second rising edge of the fourth signal at the fourth pad after a rising edge of the third signal at the third pad.
A semiconductor storage device includes a substrate having a memory region and a hook-up region arranged in a first direction and a plurality of memory structures arranged in a second direction intersecting the first direction. The plurality of memory structures include a plurality of conductive layers arranged in a third direction intersecting a surface of the substrate and extending in the first direction over the memory region and the hook-up region and a plurality of contact electrodes provided in the hook-up region and extending in the third direction to have an outer peripheral surface surrounded by a part of the plurality of conductive layers, each contact electrode being connected to any of the plurality of conductive layers. The hook-up region includes a first area and a second area arranged in the first direction. The first region includes a first contact electrode and a second contact electrode, and the second region includes a third contact electrode. A length of the third contact electrode in the third direction is larger than a length of the first contact electrode in the third direction, and is smaller than a length of the second contact electrode in the third direction.
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H01L 23/528 - Layout of the interconnection structure
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A memory system includes a nonvolatile memory and a memory controller. The memory controller is configured to: execute a first tracking process to determine a value of a first voltage in a patrol process that is carried out independently of a request from a host, execute a first data read process to read first data from the nonvolatile memory in response to receiving a read request from the host, cause the nonvolatile memory to execute a second tracking process using the first voltage when error correction of the first data fails, receive a value of a second voltage from the nonvolatile memory as a result of the second tracking process, and execute a second data read process using the second voltage to read second data from the nonvolatile memory.
According to an embodiment, a controller acquires a first temperature detection value and executes an acquisition operation on a first storage area. The controller converts a first voltage value into a second voltage value representing the read voltage in a temperature set value based on the first temperature detection value and records the second voltage value. The acquisition operation is an operation of determining, by using the read voltages, whether memory cells are ON or OFF and acquiring the first voltage value representing the read voltage for suppressing error bits. After that, the controller acquires a second temperature detection value and converts the second voltage value into a third voltage value representing the read voltage in the second temperature detection value. The controller reads data from the memory cells by using, as the read voltage, a voltage indicated by the third voltage value.
A semiconductor device includes a base body, a stacked body on the base body and a first columnar part. The base body includes a substrate, a first insulating film on the substrate, a first conductive film on the first insulating film, and a first semiconductor part on the first conductive film. The stacked body includes conductive layers and insulating layers stacked alternately in a stacking direction. The first columnar part is provided inside the stacked body and the first semiconductor part. The first columnar part includes a semiconductor body and a memory film between the semiconductor body and conductive layers. The semiconductor body extends in the stacking direction. The first columnar part has a first diameter and a second diameter in a first direction crossing the stacking direction. The first diameter inside the first semiconductor part is larger than the second diameter inside the stacked body.
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/528 - Layout of the interconnection structure
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 99/00 - Subject matter not provided for in other groups of this subclass
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
40.
SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor storage device includes: a stacked body having a plurality of insulating layers and a plurality of gate electrode layers alternately stacked in a first direction, the plurality of gate electrode layers including a first gate electrode layer and a second gate electrode layer, the second gate electrode layer adjacent to the first gate electrode layer in the first direction, and the plurality of insulating layers including a first insulating layer located between the first gate electrode layer and the second gate electrode layer; a semiconductor layer extending in the first direction; a first charge storage layer disposed between the semiconductor layer and the first gate electrode layer, the first charge storage layer including silicon and nitrogen; a second charge storage layer disposed between the semiconductor layer and the second gate electrode layer, the second charge storage layer sandwiching the first insulating layer with the first charge storage layer.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
According to one embodiment, a semiconductor device includes a base, a memory cell region on the base comprising a first plurality of conductive layers and a second plurality of insulating layers, wherein an insulating layer extends between, and separates, each two adjacent conductive layers of the first plurality of conductive layers. A first stacked body and a second stacked body are located on the base, and includes a plurality of insulating layers and a plurality of conductive layers fewer than the number of first conductive layers, and an insulating layer extends between, and separates, each two adjacent conductive layers of the plurality of conductive layers in each stacked body. The end portions of the stacked bodies include a stair portion having a stair-like shape wherein a surface of each of the conductive layers thereof is exposed.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
According to one embodiment, a memory system includes an array of memory cells that store two or more bits of data each, and a memory controller to control writing data into the memory cells and reading from the memory cells. When a first command is received from a host, the memory controller reads data designated by the first command from the array and then rewrites the read data back into the array using a writing method in which a lower number of bits per memory cell is written than the originally stored manner of the read data. When a read command designating the rewritten data is received from the host, the memory controller reads from the array and transfers it to the host.
A semiconductor storage device includes a first word line, a first insulating layer extending along the first word line, a first memory cell connected to the first word line, a second memory cell connected to the first word line, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, and a control circuit. The second memory cell is farther from the first insulating layer than the first memory cell. The control circuit is configured to apply a first voltage to the first bit line during a read operation of the first memory cell, and apply a second voltage to the second bit line during a read operation of the second memory cell. The second voltage is higher than the first voltage.
G11C 16/26 - Sensing or reading circuitsData output circuits
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body. The columnar semiconductor layer has a boundary of the first portion and the second portion, the boundary being close to the second insulating layer; and an average value of an outer diameter of the memory layer facing a side surface of the second insulating layer is larger than that of the memory layer facing a side surface of a lowermost layer of the first insulating layers in the second portion.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/26 - Sensing or reading circuitsData output circuits
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/23 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
The arrangements disclosed herein relate to systems, methods, non-transitory computer-readable media, and apparatuses including a non-volatile memory and a controller operatively coupled to the non-volatile memory. The controller is to determine information on a number of errors for at least a portion of a page for performing a sequential read operation of a plurality of pages of a block of a plurality of blocks of the non-volatile memory, where the data is read using a first read threshold. The controller is to determine a second read threshold based at least in part on read histogram for the sequential read operation and the information on the number of the errors for at least the portion of the page and the first read threshold.
The present disclosure relates to systems, apparatuses, methods, and non-transitory computer-readable media including a non-volatile memory and a controller operatively coupled to the non-volatile memory. The controller is to determine information on a number of errors for a page for reading data stored in the page of the non-volatile memory, and the data is read using a first read threshold. The controller is to determine a second read threshold based at least in part on the first read threshold and the number of page errors for the page and apply the second read threshold for subsequently reading data stored on the page according to a decision rule.
A memory device includes a first memory cell array and a controller. The first memory cell array includes a plurality of pages, with each of the plurality of pages including a plurality of memory cell transistors configured to store data of a K-value, and K being an integer of 1 or more. The controller writes data into a first page and a second page included in the plurality of pages of the first memory cell array without executing a verify read during a write operation in response to one command set including a write command and data.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/26 - Sensing or reading circuitsData output circuits
According to one embodiment, when a current consumption class supported by a removable memory device is another current consumption class different from a first current consumption class with a largest current consumption value among plural types of current consumption classes, the first current consumption value consumed from a first power by the removable memory device is smaller than or equal to a third permissible current value for a first power defined in the other current consumption class; and a second current consumption value consumed from a second power by the removable memory device is smaller than or equal to a fourth permissible current value for the second power defined in the other current consumption class.
G06F 1/3225 - Monitoring of peripheral devices of memory devices
G06F 1/3234 - Power saving characterised by the action undertaken
G06K 19/06 - Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
50.
SEMICONDUCTOR MEMORY DEVICE THAT INCLUDES A SEMICONDUCTOR COLUMN THAT PENETRATES A PLURALITY OF CONDUCTIVE LAYERS
A semiconductor memory device includes a substrate, a plurality of first conductive layers, a second conductive layer disposed at a position farther from or a position closer to the substrate than the plurality of first conductive layers, a first semiconductor column, a first electric charge accumulating film, a first wiring disposed at a position farther from or a position closer to the substrate than the plurality of first conductive layers and the second conductive layer, a first contact that is disposed between one end of the second conductive layer and the first semiconductor column and is electrically connected to the second conductive layer and the first wiring, and a second contact that is disposed between another end of the second conductive layer and the first semiconductor column and is electrically connected to the second conductive layer and the first wiring.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - Details of semiconductor or other solid state devices
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
A memory device includes a memory cell that includes a resistance change element and a switching element that are coupled in series between a first terminal of the memory cell and a second terminal of the memory cell, and a control circuit electrically connected to the first and second terminals of the memory cell. The control circuit is configured to alternately apply a first write pulse and a first recovery pulse having different polarities to the resistance change element during a first operation to set the resistance change element to have a first resistance state, and to alternately apply a second write pulse and a second recovery pulse having different polarities to the resistance change element during a second operation to set the resistance change element to have a second resistance state, with the first write pulse and the second write pulse having different polarities.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
52.
SYSTEM AND METHOD FOR IMPROVED ENDURANCE IN NON-VOLATILE MEMORY SYSTEMS
A system may include one or more processors. The one or more processors may be configured to determine, using first data relating to a sample set of non-volatile memory devices, one or more program parameters of each of a plurality of rows of cells of a non-volatile memory. The one or more processors may be configured to adjust, using the first data, the one or more program parameters of each of the plurality of rows by equalizing the one or more program parameters across the plurality of rows. The one or more processors may be configured to determine one or more programming voltages of each row based at least in part on the adjusted program parameters of the plurality of rows. The one or more processors may be configured to program a first row of the plurality of rows using the one or more programming voltages of the first row.
A memory system is connectable to a host. A memory system includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of blocks, each of which is a unit of an erase operation. The controller is electrically connected to the non-volatile memory and controls the non-volatile memory. The controller receives first data from the host. The controller generates third data from the first data by randomizing the first data using second data that has a different value each time the data erase operation is executed on a first block among the plurality of blocks. The controller writes the second data to the non-volatile memory and the third data to the first block.
A semiconductor memory device capable of improving the usage efficiency of a bus is provided. The semiconductor memory device includes a data storage unit, a data transfer circuit, and a control circuit. The data storage unit temporarily stores data read from a memory cell array. The data transfer circuit is provided between the data storage unit and an input/output pad, and transfers the data stored in the data storage unit to the input/output pad. When a predetermined time period elapses without the data transfer circuit starting data transfer to the memory controller through the input/output pad, the control circuit cuts off power supplied to the data transfer circuit. The predetermined time period can be changed according to an instruction from the memory controller.
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
55.
SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR STORAGE DEVICE
A semiconductor storage device according to one embodiment includes a multi-layered body and a first wiring. The multi-layered body includes a plurality of first layers and a plurality of second layers. The first wiring extends in a first direction within the multi-layered body. Each of the plurality of first layers includes a second wiring, a capacitor electrode, a semiconductor layer, and a first protruding portion. The second wiring extends in a second direction intersecting with the first direction. At least a part of the semiconductor layer is between the second wiring and the capacitor electrode. The first protruding portion protrudes from the second wiring in a third direction intersecting with the first direction and the second direction and covers at least a part of the semiconductor layer from one side in the first direction.
In one embodiment, a semiconductor device includes a substrate including one or more wiring layers, a first insulator provided on an upper face of a first wiring layer that is an uppermost layer among the one or more wiring layers, and a second insulator provided on a lower face of a second wiring layer that is a lowermost layer among the one or more wiring layers. The device further includes a semiconductor chip provided on the substrate. The first or second wiring layer includes a first wiring and a second wiring that extend from an opening provided in the first or second insulator, and a third wiring that is provided at a position facing the opening between the first wiring and the second wiring.
According to an embodiment, a memory system includes a memory chip including a first terminal group used for data and a second terminal group used for a packet, and a memory controller configured to transmit and receive the data to and from the memory chip and transmit the packet to the memory chip. In a case where a transfer operation of the data is performed once, the memory controller transmits to the memory chip a first packet indicating a start of data transfer and a second packet indicating end of the data transfer. In a case where the transfer operation of the data is successively performed twice, the memory controller transmits to the memory chip the first packet corresponding to a second data transfer between a first data transfer and the second data transfer, and does not transmit the second packet corresponding to the first data transfer.
According to one embodiment, a standard cell library has a first standard cell in which a first internal power supply wire is arranged, and a second standard cell in which a second internal power supply wire is arranged. When the first and the second standard cell are arranged adjacent in a second direction, the first and the second internal power supply wire are separated. The first standard cell has a first wiring region in which a first external power supply wire can be arranged, a first connectable position in which the first external power supply wire and the first internal power supply wire can be connected, a third wiring region in which a second external power supply wire can be arranged, and a third connectable position in which the second external power supply wire and the first internal power supply wire can be connected.
A semiconductor memory device comprises: a semiconductor substrate; conductive layers; pad electrodes; a first wiring and a second wiring provided between the semiconductor substrate and the conductive layers; and via contact electrodes. The pad electrodes include: a first pad electrode having a signal inputted/outputted thereto/therefrom; and a second pad electrode and a third pad electrode applied with voltages. The semiconductor substrate is provided with a first transistor, a second transistor, a first diode, a second diode, and a clamp circuit. A part of the via contact electrodes overlapping the second pad electrode and electrically connected to the first transistor, the first diode, or the clamp circuit are commonly connected to the first wiring. Another part of the via contact electrodes overlapping the third pad electrode and electrically connected to the second transistor, the second diode, or the clamp circuit are commonly connected to the second wiring.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
According to one embodiment, a transmitter device includes: a digital processing circuit generating n-phase first and second digital signals, the second digital signal shifted from the first digital signal by a first phase; a delay circuit generating an n-phase second clock signal shifted from an n-phase first clock signal by a second phase being 0 or more and being the first phase or less; a first multiplexer converting the first digital signal into a single-phase third digital signal based on the first clock signal; a second multiplexer converting the second digital signal into a single-phase fourth digital signal shifted from the third digital signal by a sum of the first phase and the second phase based on the second clock signal; and a first driver outputting a composite signal of first and second analog signals based on the third and fourth digital signals.
According to one embodiment, a memory device includes a first block including a first memory string having a first transistor at an end, a second transistor having a first end connected to a gate of the first transistor, first interconnect connected to a gate of the second transistor, a block decoder connected to one end of the first interconnect, a third transistor having a first end connected to the other end of the first interconnect, and a power supply connected to a second end of the third transistor.
A memory device according to one embodiment includes a plurality of memory cells, a word line, and a controller. Each of the memory cells is configured to store multiple-bit data according to which of a plurality of states having different threshold voltages each of the memory cells is included in. The word line is connected to the memory cells. The controller is configured to count a number of memory cells having threshold voltages on a higher state side among the states, and to execute a read operation for the memory cells as a target, by using a read voltage that is shifted based on a result of the counting.
A semiconductor memory device comprises memory blocks and a control circuit. The control circuit is configured capable of executing a first pre-charge operation and a first program operation, and uninterruptedly thereafter executing a second program operation, in a first-mode write operation. In the first pre-charge operation, a first word line is applied with a certain voltage. In the first program operation, a first select gate line is applied with a first voltage, the first word line is applied with a first program voltage, and a second word line is applied with a write pass voltage smaller than the first program voltage. In the second program operation, a second select gate line is applied with the first voltage, the first word line is applied with a second program voltage larger than the write pass voltage, and the second word line is applied with the write pass voltage.
A semiconductor device includes: a first wafer including die regions; conductive layers provided in a device region on the first wafer, and stacked in a stacking direction; and first layers provided in an edge region on the first wafer and arranged in the stacking direction. First die regions positioned within the device region include respective terrace regions in which a part of the conductive layers are provided. The number of the first layers arranged in the stacking direction at positions within second die regions corresponding to positions at which the first die regions include at least partial region of the terrace regions within a region in which the second die regions overlap with the edge region when viewed in the stacking direction is greater than the number of the conductive layers provided at the positions including the at least partial region of the terrace regions.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
In general, according to one embodiment, a semiconductor memory device includes: a plurality of second and third interconnect layers apart from each other in a first direction, wherein each of the second interconnect layers includes a plurality of first terrace portions, each of the third interconnect layers includes a plurality of second terrace portions overlapping the first terrace portions in the first direction, the second terrace portions include a plurality of third and fourth terrace portions provided at a same interconnect layer of the third interconnect layers are electrically insulated from each other; and a first contact passes through one of the fourth terrace portions, and is electrically coupled to one of the first terrace portions, wherein each of the third and fourth terrace portions is thicker in the first direction than a portion of the third interconnect layers where the third or fourth terrace portions are not provided.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
According to one embodiment, a semiconductor storage device includes a memory cell, a bit line electrically connected to the memory cell, a sense amplifier circuit electrically connected to the bit line, a first data wiring electrically connected to the sense amplifier circuit, a data latch circuit electrically connected to the first data wiring, and a second data wiring and a third data wiring electrically connected to the data latch circuit, for transferring mutually inverted data signals. The data latch circuit includes a first node that stores data and a second node that stores inverted data of the data. The second data wiring is electrically connected to the first node. The first data wiring and the third data wiring are electrically connected to the second node.
A focused ion beam apparatus includes a controller configured to: define an actual working space defined by a scanning point of an electron beam and a focusing distance of the electron beam; irradiate a sample with the electron beam using an electron beam column and acquire a plurality of electron microscope images of the sample with different observation orientations, respectively; create a three-dimensional model including real space information of the sample based on the plurality of electron microscope images; change an attitude of the sample; acquire, from the three-dimensional model, a two-dimensional image of the sample; determine a predetermined range to be irradiated with an ion beam using the two-dimensional image; and process the sample by irradiating the predetermined range with the ion beam using an ion beam column.
According to one embodiment, a semiconductor memory device includes a structural body including a stacked body in which conductive layers are stacked in a first direction, a plate-shaped structure extending in the first and second directions in the structural body, first and second pillar structures extending in the first direction in the stacked and structural body, respectively, and each of which a plurality of layers are stacked from an outer peripheral surface side toward an inner side. The second pillar structure does not function as a NAND string. Materials of the plurality of layers in the first and second pillar structures are respectively same. A part of a side surface of the plate-shaped structure is conformed to a part of a side surface of the second pillar structure.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
An evaluation method includes acquiring first information indicating a state of a defect of a defect of a semiconductor device; generating third information including a location of a failure and a type of the failure in the semiconductor device based on the first information and prestored second information, the prestored second information indicates that the location of the failure and the type of the failure are associated with the first information; controlling whether fourth information for specifying the type of the failure of the semiconductor device is returned to a control device for controlling the semiconductor device, based on an access request from the control device and the third information; and evaluating an operation of the control device after the fourth information is returned.
A power supply management circuit includes a terminal connectable to a plurality of power storage elements via a plurality of switches, respectively, a measurement circuit, and a step-up/down circuit. The power supply management circuit is configured to obtain a total capacity of a first group of the power storage elements that are in connected state, and obtain a total capacity of a second group of the power storage elements that are in connected state. The power supply management circuit is configured to obtain a capacity of a first power storage element among the plurality of power storage elements based on a difference between the total capacity of the first group of the power storage elements and the total capacity of the second group of the power storage elements.
A semiconductor integrated circuit includes a plurality of step-down circuits, a plurality of input switches, and a plurality of output switches. The plurality of step-down circuits are configured to step down a first voltage that is input and to output a first stepped-down voltage or to step down a second voltage that is input and to output a second stepped-down voltage. The plurality of input switches are connected to input terminals of the plurality of step-down circuits, respectively, and each of the input switches is configured to switch an input to the corresponding input terminal to either the first voltage or the second voltage. The plurality of output switches are connected to output terminals of the plurality of step-down circuits, respectively, and each of the output switches is configured to switch an output from the corresponding output terminal to either a first output node or a second output node.
An organic molecular memory includes a first electrode, a second electrode above the first electrode in a first direction, an organic molecule layer between the first and second electrodes and including a first molecule and a second molecule, the second molecule being closer to the second electrode than the first molecule, and a third electrode facing the second molecule. Each of the first and second molecules includes a metal complex or a fullerene derivative.
H10K 10/00 - Organic devices specially adapted for rectifying, amplifying, oscillating or switchingOrganic capacitors or resistors having potential barriers
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
According to one embodiment, a semiconductor memory device includes a first capacitor including a first electrode, a second electrode, and a first capacitor insulating film provided between the first electrode and the second electrode, and a first transistor including a first oxide semiconductor layer electrically connected to the second electrode and extending in a first direction, a first gate electrode provided next to the first oxide semiconductor layer, and a third electrode electrically connected to the first oxide semiconductor layer and provided on the opposite side of the second electrode. The second electrode includes a first portion, a second portion provided between the first portion and the first oxide semiconductor layer, and a third portion provided between the second portion and the first oxide semiconductor layer. A first width of the first portion in a second direction perpendicular to the first direction is smaller than a second width of the second portion in the second direction, and a third width of the third portion in the second direction is smaller than the second width.
A semiconductor device includes a substrate, a first region, a second region, and a first insulating layer and a metal oxide layer disposed farther from the substrate than the first region. The first region includes a first transistor containing Si and a second insulating layer disposed between the first insulating layer and the metal oxide layer and the first transistor. The second region includes a second transistor containing oxide semiconductor and a third insulating layer disposed between the first insulating layer and the metal oxide layer and the second transistor. The metal oxide layer contains at least one element selected from the group consisting of Al, Hf, Zr, La, and Y and contains oxygen (O). The second insulating layer and the third insulating layer contain Si and oxygen (O). A density of the third insulating layer is higher than a density of the second insulating layer.
A semiconductor device includes a first inductor including a first coil wiring located on a first plane, a second coil wiring of which at least a part is located on the first plane, and a drive circuit that supplies a common signal to the first coil wiring and the second coil wiring. A first region surrounded by the first coil wiring and a second region surrounded by the second coil wiring overlap each other in a direction that is perpendicular to the first plane.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
76.
SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes: a first conductor layer; a second conductor layer; an oxide semiconductor layer provided between the first conductor layer and the second conductor layer; a gate electrode provided next to the oxide semiconductor layer; and a gate insulating film provided between the gate electrode and the oxide semiconductor layer. The oxide semiconductor layer includes at least one of indium, gallium, zinc, aluminum, tin, titanium, silicon, germanium, copper, arsenic, and tungsten and oxygen and includes a first end and a second end. The first conductor layer includes indium, tin, oxygen, and a first element that is at least one of nitrogen, sulfur, selenium, tellurium, hafnium, tantalum, tungsten, rhenium, osmium, iridium, bismuth, lanthanum, yttrium, zinc, cadmium, and mercury. The first end of the oxide semiconductor layer is in contact with the first conductor layer.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
A first interconnect and the first insulator extend in a first direction. A second insulator extends in the second direction and penetrates the first interconnect and the first insulator. A second interconnect is provided around the second insulator, extends in the second direction, and penetrates the first interconnect and the first insulator. A first magneto-resistive effect element is provided in a ring-shape around the second interconnect between the first interconnect and the second interconnect, and includes a first ferromagnetic material between the second interconnect and the first interconnect, a first nonmagnetic material between the first ferromagnetic material and the first interconnect, and a second ferromagnetic material between the first nonmagnetic material and the first interconnect.
H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
A semiconductor memory device includes a semiconductor substrate, a plurality of transistors on the semiconductor substrate and arranged in a first and a second directions, a stacked body including a plurality of conductive layers arranged in a third direction, and a plurality of wiring layers disposed between the semiconductor substrate and the stacked body and connecting the conductive layers to the transistors. The wiring layers include a plurality of first wirings that connect the first conductive layers to the first transistors, and a plurality of second wirings that connect the second conductive layers to the second transistors. A first part of the first wirings extending in the first direction from the hook-up region to the first circuit region and a second part of the second wirings extending in the first direction from the hook-up region to the first circuit region are provided at positions different in the third direction.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
A semiconductor memory device includes: a substrate; a first via-wiring extending in a first direction; first semiconductor layers electrically connected to the first via-wiring; memory portions electrically connected to the first semiconductor layers; first gate electrodes opposed to the first semiconductor layers; first wirings extending in a second direction, and electrically connected to the first gate electrodes; second semiconductor layers electrically connected to the first wirings; second gate electrodes opposed to the plurality of second semiconductor layers; a second via-wiring extending in the first direction and electrically connected to the second gate electrodes; and a second wiring extending in the first direction, electrically connected to the second semiconductor layers, and arranged with the second semiconductor layers in a third direction.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10B 53/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the top-view layout
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
According to one embodiment, a magnetic memory device includes first, second and third magnetic layers having variable, fixed and fixed magnetization directions, respectively, a nonmagnetic layer, and a spacer layer. The second magnetic layer is between the first and third magnetic layers, the nonmagnetic layer is between the first and second magnetic layers, the spacer layer is between the second and third magnetic layers, the second magnetic layer includes a layer adjacent to the spacer layer and including a first layer portion formed of Co and a second layer portion containing N, the third magnetic layer includes a layer adjacent to the spacer layer and including a first layer portion formed of Co.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
A semiconductor memory includes memory cell groups storing first data; pairs of first wiring lines transmitting second data including bits; second wiring lines transmitting a signal corresponding to a product of one bit of the first data and a corresponding bit of the second data; sense amplifiers sensing the signal corresponding to the product transmitted from the second wiring lines; a third wiring line transmitting a signal corresponding to a value adding the products; and switches disposed between the second wiring lines and the third wiring line, each being in an off state in order to disconnect the second wiring lines and the third wiring line until data read to the second wiring lines from the memory cell groups and sensed by the sense amplifiers is rewritten to the memory cell groups, and turned on to connect the second wiring lines and the third wiring line.
A method for manufacturing a semiconductor memory device according to an embodiment includes: forming a first film, a second film, and a third film in a first direction of a single crystal silicon substrate; forming a first opening penetrating the third to first films reaching the single crystal silicon substrate; forming a first single crystal silicon layer in the first opening; forming a second opening penetrating the third and second films; etching the second film from a side face of the second opening to form a first recess reaching the first single crystal silicon layer; forming a second single crystal silicon layer in the first recess; forming a wiring layer in contact with a first portion of the second single crystal silicon layer; forming a capacitor in contact with a second portion of the second single crystal silicon layer; and forming a gate electrode layer facing a third portion.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
83.
WIRE BONDING APPARATUS, OPERATION METHOD, AND CONTROL METHOD
According to one embodiment, a controller of a wire bonding apparatus is configured to calculate a height of a bump based on a diameter of a ball-shaped portion detected by a diameter detecting part, a first position of a bonding tool detected by a position detecting part when a load sensor detects a load at a bonding point, and a second position of the bonding tool when the bonding tool is lowered most at the bonding point, and to bond a wire based on the calculated height of the bump. The controller is further configured to acquire a plurality of the first positions of a plurality of the bumps formed on a chip, and to calculate a relative positional relationship of the plurality of first positions.
H01L 23/00 - Details of semiconductor or other solid state devices
B23K 20/10 - Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating making use of vibrations, e.g. ultrasonic welding
According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
A semiconductor memory device includes: conductive layers including a first range and a second range; a first semiconductor layer opposed to the conductive layers in the first range; a second semiconductor layer opposed to the conductive layers in the second range; a first bit line electrically connected to one end of the first semiconductor layer; and a second bit line electrically connected to one end of the second semiconductor layer. When a sense time of the first bit line when a predetermined operation is performed on a first memory cell including a first electric charge accumulating portion is assumed to be a first operation parameter and a sense time of the second bit line when the predetermined operation is performed on a second memory cell including a second electric charge accumulating portion is assumed to be a second operation parameter, the second operation parameter differs from the first operation parameter.
A wireless communication system includes a host apparatus and a memory card connectable to the host apparatus. The memory card includes a memory device, a memory controller circuit to control reading and writing to the memory device in response to requests from the host apparatus, a communication module to perform a communication function, and an extension register to store information on an extension function. The memory controller circuit is connected to the memory device, the communication module, and the extension register. The memory card is able to receive from the host apparatus a first request for reading the information stored in the extension register. The communication function is a wireless communication function including a WiFi function and/or a Bluetooth function. The WiFi function and the Bluetooth function are respectively assigned to pages different from each other.
H04W 4/60 - Subscription-based services using application servers or record carriers, e.g. SIM application toolkits
87.
TEMPLATE WITH SACRIFICIAL LAYER, METHOD OF MANUFACTURING TEMPLATE WITH SACRIFICIAL LAYER, METHOD OF REMANUFACTURING TEMPLATE WITH SACRIFICIAL LAYER, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
According to one embodiment, a method of manufacturing a template includes forming a sacrificial layer on a substrate. A first pattern is formed on a surface of the sacrificial layer opposite to a surface of the sacrificial layer in contact with the substrate. A replication material layer is formed on a surface of the first pattern of the sacrificial layer. A surface of the replication material layer opposite to a surface of the replication material layer in contact with the sacrificial layer is bonded to a template substrate. The replication material layer is cured to form a replication portion having a second pattern corresponding to the first pattern. The substrate is removed from the sacrificial layer to provide the template including the template substrate and the replication portion.
B29C 43/36 - Moulds for making articles of definite length, i.e. discrete articles
B29C 33/38 - Moulds or coresDetails thereof or accessories therefor characterised by the material or the manufacturing process
B29C 43/02 - Compression moulding, i.e. applying external pressure to flow the moulding materialApparatus therefor of articles of definite length, i.e. discrete articles
B29L 31/34 - Electrical apparatus, e.g. sparking plugs or parts thereof
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
A storage device includes memory cells each including: a first layer, a second layer, a third layer between the first and second layers, a switching layer between the first and third layers, and a variable resistance layer between the second and third layers. The switching layer includes first and second regions. The first region includes: first and second elements. The second region includes: the first element, a third element, an atomic number of which is greater than that of the second element, and a fourth element. An atomic concentration of a fifth element in the second region is higher than an atomic concentration of the fifth element in the first region. The fifth element is selected from a group consisting of zinc, tin, gallium, indium, bismuth, magnesium, and calcium.
According to one embodiment, a memory system includes a nonvolatile memory, and a memory controller including first and second caches and a first controller. The first cache includes a first memory unit and a first control unit. The second cache includes a second memory unit and a second control unit. The first memory unit includes a plurality of entries each having a cache tag including a first field and a cache line. Upon receiving a first prefetch request for first data of a first logical address, the first control unit stores the first data in the cache line of a first entry included in the first memory unit, and stores a first value in the first field of the first entry. The first control unit maintains the first entry until receiving a read request or a write request for the first logical address from the host.
G06F 12/0895 - Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
A semiconductor wafer testing apparatus includes a stage configured to place a semiconductor wafer having a plurality of first coils, a probe card configured to hold a plurality of chip inductors having a plurality of second coils, a driver configured to move the probe card toward the stage, and a control circuit including a plurality of transmitting circuits or a plurality of receiving circuits connected to each of the plurality of chip inductors. The control circuit is configured to transmit signals to the plurality of first coils by magnetically coupling the plurality of first coils to each of the plurality of second coils.
According to one embodiment, an arithmetic circuit includes a matrix calculator and p or more evaluators. The matrix calculator calculates a matrix that corresponds to a linearized polynomial included in an affine polynomial obtained by decomposing an error locator polynomial. Each of the evaluators calculates a first multiplication result obtained by multiplying the matrix by a first multiplication value based on a substitution value to be substituted into the error locator polynomial, calculates, for each of one or more evaluation terms that are different from the linearized polynomial, a second multiplication result obtained by multiplying a second multiplication value based on the substitution value by a corresponding evaluation term, and outputs error position information based on a value obtained by adding the first multiplication result and the second multiplication result.
According to one embodiment, a semiconductor memory device includes a memory cell array; a member; and a conductor portion intersecting the member, wherein the memory cell array includes word lines on one side in a Z direction regarding a source line, the conductor portion is included in a same layer as the source line, includes a surface on an other side in the Z direction having a height substantially equivalent to a height of a surface on the other side of the source line, and the member includes a contact surrounding the word lines, and an insulating film covering a side surface of the contact from one end of the contact on the one side to a height on the one side regarding an other end of the contact.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
93.
SEMICONDUCTOR INTEGRATED CIRCUIT, RECEIVING DEVICE, AND RECEIVING METHOD
In general, according to one embodiment, a semiconductor integrated circuit includes the following configuration. A first converter samples a first digital value from an analog signal based on a first clock signal. A second converter samples a second digital value from the analog signal based on a second clock signal differing from the first clock signal by a first phase. A first processing circuit calculates phase shifts of the first and second clock signals based on the first and second digital values and using a first frequency of a third clock signal. A second processing circuit generates a control signal for correcting the phase shifts of the first and second clock signals based on the phase shifts calculated by the first processing circuit and using a second frequency of a fourth clock signal. The second frequency is 2m times the first frequency.
According to an embodiment, a non-volatile memory includes a plurality of memory cells; a word line; and a controller, wherein, in a read process, the controller reads data from the memory cells at a first timing, a second timing, and a third timing while a first voltage is applied to the word line, calculates a first difference based on the data at the first timing and the second timing, a second difference based on the data at the second timing and the third timing, and a first value subtracted the first difference from the second difference, and determines, based on the first value, one of the data at the first timing, the data at the second timing, and the data at the third timing as a plurality of first read data.
In one embodiment, a memory system includes a non-volatile memory including a plurality of memory cells; and a memory controller. The memory controller is configured to store first data read from the plurality of memory cells using a first voltage in a storage circuit, store second data read from a bit group including respective bits of the plurality of memory cells using a first read voltage group in a storage circuit, perform an error correction of the second data, and determine, if third data is obtained as a result of successful error correction of the second data, a second read voltage group based on the first data stored in the storage circuit, the second data, and the third data.
According to one embodiment, a memory device includes: a memory cell array including a plurality of memory cells; and a voltage generator that is supplied with a first external voltage and a second external voltage higher than the first external voltage and generates an operating voltage of the memory cell array. An operation mode of the voltage generator at a time of generating a first voltage value of the operating voltage includes a first mode including a first period and a second period after the first period, and the first mode of generating the operating voltage using the first external voltage in the first period and using the second external voltage in the second period.
A semiconductor memory device includes a memory cell array including memory cells, word lines connected to the cells, bit lines connected to the cells, and a control circuit configured to execute, in response to a command sequence for writing data into a first memory cell connected to a first word line, a loop one or more times, each loop including a program operation for writing data into the first memory cell and a verification operation for verifying the data. The sequence indicates a level of a threshold voltage to be set to a second memory cell connected to a second word line adjacent to the first word line. The control circuit is configured to, after exiting the loop, determine whether to execute an operation to adjust a threshold voltage of the first memory cell based on the level of the threshold voltage to be set in the second memory cell.
According to one embodiment, a controller of a wire bonding apparatus is configured to calculate a height of a bump based on a diameter of a ball-shaped portion detected by a diameter detecting part, a first position of a bonding tool detected by a position detecting part when a load sensor detects a load at a first bonding point, and a second position of the bonding tool when the bonding tool is lowered at the first bonding point, and to bond a wire based on the calculated height of the bump.
H01L 23/00 - Details of semiconductor or other solid state devices
B23K 20/10 - Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating making use of vibrations, e.g. ultrasonic welding
A semiconductor device includes: a substrate extending in a first direction; a gate electrode extending along the first direction above the substrate; an oxide semiconductor that extends in a second direction intersecting the first direction above the substrate and penetrates the gate electrode; a first electrode electrically connected to one end of the oxide semiconductor; a second electrode electrically connected to the other end of the oxide semiconductor; and a first insulating film made of a first insulating material. The first insulating film includes: a first film portion that covers an upper surface of the gate electrode, a second film portion that covers a lower surface of the gate electrode, and a third film portion that extends in the second direction between the gate electrode and the oxide semiconductor.
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
H10B 12/00 - Dynamic random access memory [DRAM] devices
100.
IMAGE CAPTURING DEVICE AND IMAGE GENERATION METHOD
An image capturing device includes a stage holding a subject; a detector including a first pixel layer, a second pixel layer, and a third pixel layer stacked on top of one another, with an insulating film interposed adjacent ones of the first to third pixel layers; an image formation optical member configured to form, on the detector, an image based on imaging light transmitted through the subject; and an image processor configured to reconstruct an image of the subject based on a detection intensity of the imaging light detected by the detector.
patents
