Abstract

The technical solution involves a board card including a storage component, an interface apparatus, a control component, and an artificial intelligence chip. The artificial intelligence chip is connected to the storage component, the control component, and the interface apparatus, respectively; the storage component is used to store data; the interface apparatus is used to implement data transfer between the artificial intelligence chip and an external device; and the control component is used to monitor a state of the artificial intelligence chip. The board card is used to perform an artificial intelligence operation.

IPC Classes  ?

• G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
• G06N 3/047 - Probabilistic or stochastic networks
• G06N 3/08 - Learning methods

Abstract

Provided in the present application are a data compression method and apparatus, and a device and a medium. The method comprises: firstly, acquiring a pose matrix and a distance matrix which are at the current moment, wherein the pose matrix represents the rotation angle and position of a Lidar scanner, and the distance matrix represents the value of the distance between a spatial point scanned by the Lidar scanner and the Lidar scanner; calling, from a historical pose matrix stored in a decoding end, a pose matrix which is at the previous moment, and calculating the difference between the pose matrix which is at the current moment and the pose matrix which is at the previous moment, so as to obtain a residual matrix; and encoding the residual matrix and the distance matrix which is at the current moment, and then transmitting same to the decoding end, such that the decoding end obtains, on the basis of the residual matrix and the pose matrix which is at the previous moment, the pose matrix which is at the current moment, and stores the pose matrix and the distance matrix which are at the current moment. In the present application, a residual matrix of a Lidar scanner in an autonomous driving system and a distance matrix between the surrounding environment and the Lidar scanner are compressed and transmitted, and the transmitted data is matrix data, such that the data volume of the transmitted data is greatly reduced, thereby improving the transmission efficiency.

IPC Classes  ?

• G01S 17/931 - Lidar systems, specially adapted for specific applications for anti-collision purposes of land vehicles
• G01S 17/08 - Systems determining position data of a target for measuring distance only
• G01S 7/48 - Details of systems according to groups , , of systems according to group

Abstract

Disclosed in the present disclosure are a method for adjusting parameters of an image signal processor, a data processing method, and a product. An electronic device of the present disclosure may be comprised in a computing processing device (602) of a combined processing device. The computing processing device may comprise one or more computing devices (610). The combined processing device may further comprise an interface device (604) and another processing device (606). The computing processing device (602) interacts with the another processing device (606) to jointly complete a computing operation specified by a user. The combined processing device may further comprise a storage device (608). The storage device (608) is separately connected to the computing processing device (602) and the another processing device (606), and is used for storing data of the computing processing device (602) and the another processing device (606). According to the solution of the present disclosure, data styles of learnable image signal processing models can be normalized to data styles of training domain data sets, thereby facilitating the improvement of the actual inference performance of a target network model.

IPC Classes  ?

• H04N 5/14 - Picture signal circuitry for video frequency region

Abstract

Provided in the present application are a video signal coding method, and a processing apparatus and a readable storage medium. The processing device comprises: a processor and a memory, wherein the memory stores a computer execution instruction, and the processor executes the computer execution instruction which is stored in the memory, to enable the processing device to execute a video signal coding method. By means of the embodiments of the present application, processing overheads can be reduced, the implementation complexity can be reduced, and the implementation cost of a processing apparatus can be reduced.

IPC Classes  ?

• H04N 19/182 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a pixel
• H04N 19/139 - Analysis of motion vectors, e.g. their magnitude, direction, variance or reliability

Abstract

A device for optimizing parameters of a deep neural network is included in an integrated circuit apparatus. The integrated circuit apparatus includes a general interconnection interface and other processing apparatus. A computing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The integrated circuit apparatus further includes a storage apparatus. The storage apparatus is connected to the computing apparatus and other processing apparatus, respectively. The storage apparatus is used for data storage of the computing apparatus and other processing apparatus.

IPC Classes  ?

• G06N 3/08 - Learning methods
• G06N 5/04 - Inference or reasoning models

Abstract

A system for fusing operators of a neural network is included in a combined processing apparatus. The combined processing apparatus includes an interface apparatus and other processing apparatus. A computing processing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus further includes a storage apparatus. The storage apparatus is connected to the apparatus and other processing apparatus, respectively. The storage apparatus is configured to store data of the apparatus and other processing apparatus. A solution of the present disclosure improves efficiency of various operations in data processing fields including, for example, an artificial intelligence field, thus reducing overall overheads and costs of the operations.

IPC Classes  ?

• G06N 3/04 - Architecture, e.g. interconnection topology

Abstract

Disclosed in the present application is a compilation method for a convolution operator. The compilation method is realized by means of a processing apparatus. The processing apparatus may be comprised in a combined processing apparatus, the combined processing apparatus comprising an interface apparatus and a computing apparatus, wherein the computing apparatus interacts with the processing apparatus to jointly complete a computing operation, which is specified by a user. The combined processing apparatus comprises a storage apparatus, the storage apparatus being respectively connected to the computing apparatus and the processing apparatus, and being used for storing data of the computing apparatus and the processing apparatus.

IPC Classes  ?

• G06N 3/0464 - Convolutional networks [CNN, ConvNet]
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Abstract

A compiling method for a computing graph is implemented by a processing apparatus, and a running method for a computing graph is implemented by a computing apparatus. The processing apparatus and the computing apparatus are included in a combined processing apparatus. The combined processing apparatus further includes an interface apparatus. The computing apparatus interacts with the processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus further includes a storage apparatus. The storage apparatus is respectively connected to the computing apparatus and the processing apparatus and is configured to store data of the computing apparatus and the processing apparatus. The compiling method and the running method for the computing graph may simplify user operations and improve optimization performance of the computing graph.

IPC Classes  ?

• G06N 3/10 - Interfaces, programming languages or software development kits, e.g. for simulating neural networks

Abstract

A method for executing an inter-chip communication task, a corresponding electronic device and a readable storage medium. An inter-chip communication task is described by means of a communication primitive queue, the communication primitive queue comprising a plurality of communication primitives, and the plurality of communication primitives comprising serial communication primitives which are serially connected. The method comprises: executing a search for a communication primitive queue to determine states of serial communication primitives in the communication primitive queue; and in response to having found an interrupted serial communication primitive, re-executing the communication primitive queue from the interrupted serial communication primitive.

IPC Classes  ?

• G06F 15/163 - Interprocessor communication

Abstract

Provided in the present disclosure are a method for controlling data retransmission in an application layer, and a related product, wherein the method can be realized in a combined processing apparatus. The method comprises: pre-sending data at a sending end, the data comprising a payload and a count value for the payload; in response to the data being in a pre-sent state, recording first sending-end information, the first sending-end information representing the first amount of pre-sent data; receiving and recording first receiving-end information, the first receiving-end information representing the second amount of data received and fed back by a receiving end, wherein the second amount is not greater than the first amount; and according to the first sending-end information and the first receiving-end information, determining whether to retransmit the data.

IPC Classes  ?

• H04L 1/1809 - Selective-repeat protocols

Abstract

A system for sorting data in a single-core processor and a multi-core processor is included in a combined processing apparatus. The combined processing apparatus further includes a general interconnection interface and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus further includes a storage apparatus. The storage apparatus is connected to the apparatus and other processing apparatus, respectively. The storage apparatus is configured to store data of the apparatus and other processing apparatus. A solution of the present disclosure improves efficiency of various operations in data processing fields including, for example, an artificial intelligence field, thus reducing overall overheads and costs of the operations.

IPC Classes  ?

• G06F 7/08 - Sorting, i.e. grouping record carriers in numerical or other ordered sequence according to the classification of at least some of the information they carry
• G06F 17/18 - Complex mathematical operations for evaluating statistical data

Abstract

A method is for optimizing a convolution operation of an on-chip system and related products. The on-chip system is included in a computing processing apparatus of a combined processing apparatus. The computing processing apparatus includes one or a plurality of integrated circuit apparatuses. The combined processing apparatus further includes an interface apparatus and other processing apparatus. The computing processing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus further includes a storage apparatus. The storage apparatus is connected to the apparatus and other processing apparatus, respectively. The storage apparatus is configured to store data of the apparatus and other processing apparatus.

IPC Classes  ?

• G06F 17/15 - Correlation function computation

Abstract

An automatic operator fusion method for a computational graph. The method comprises: determining control data affecting operator fusion performance; for hardware information of a computing device of a computational graph to be executed, generating different control data samples according to the control data; applying the control data samples to compute the fusion income of candidate fusion sub-graphs corresponding to different control data samples; determining an optimal fusion mode according to the fusion income, performing compilation optimization on the computational graph on the basis of the optimal fusion mode to obtain a corresponding binary instruction sequence, and allocating the binary instruction sequence to the computing device to execute a task corresponding to the computational graph.

IPC Classes  ?

• G06F 8/41 - Compilation
• G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
• G06F 16/901 - IndexingData structures thereforStorage structures
• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/08 - Learning methods

Abstract

Provided in the present disclosure are a task scheduling method and apparatus, and a device and a medium. The method comprises: after a task to be scheduled is determined, splitting, into a plurality of sub-tasks, the task to be scheduled, and dividing the plurality of sub-tasks according to the number of instances of consecutive scheduling, so as to obtain at least one interval task of the task to be scheduled; and for each interval task of the task to be scheduled, occupying, for the interval task, interval affinity resources from among the current visible resources for the task to be scheduled, and consecutively scheduling each sub-task in the interval task to an affinity resource corresponding to the sub-task, until the scheduling of all the sub-tasks in the interval task is completed. In the scheme, a plurality of sub-tasks are divided according to intervals, and the sub-tasks in the intervals are consecutively scheduled until the scheduling of all the sub-tasks in the intervals is completed, such that the locality of data used by all the sub-tasks in the intervals is improved, and the frequency of switching of data in a buffer is reduced, thereby improving the computation efficiency of a chip.

IPC Classes  ?

• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt

Abstract

An instruction control method and a data caching method. The instruction control method comprises: decoding an access and storage instruction, wherein the access and storage instruction is used for reading data from a source-end storage circuit and writing the data into a destination-end storage circuit; in response to there being only a dependency on the destination-end storage circuit between the access and storage instruction and a preamble instruction, transmitting the access and storage instruction in advance, so as to read the data from the source-end storage circuit and cache same in a data buffer; and sending, to the data buffer, a block signal for blocking the data which is read by the access and storage instruction.

IPC Classes  ?

• G06F 12/0842 - Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking

Abstract

The present disclosure provides a circuit, method and system for inter-chip communication. The method is implemented in a computation apparatus, where the computation apparatus is included in a combined processing apparatus, and the combined processing apparatus includes a general interconnection interface and other processing apparatus. The computation apparatus interacts with other processing apparatus to jointly complete a computation operation specified by a user. The combined processing apparatus also includes a storage apparatus. The storage apparatus is respectively connected to the computation apparatus and other processing apparatus and is used for storing data of the computation apparatus and other processing apparatus.

IPC Classes  ?

• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
• G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]

Abstract

The present disclosure discloses a method for performing a matrix multiplication on an on-chip system and related products. The on-chip system is included in a computing processing apparatus of a combined processing apparatus. The computing processing apparatus includes one or a plurality of integrated circuit apparatuses. The combined processing apparatus further includes an interface apparatus and other processing apparatus. The computing processing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus further includes a storage apparatus. The storage apparatus is connected to the apparatus and other processing apparatus, respectively. The storage apparatus is configured to store data of the apparatus and other processing apparatus. The solution of the present disclosure may reduce the amount of data transmission between an internal device and an external storage apparatus, thus reducing the I/O bottleneck caused by bandwidth limitations and then improving overall performance of an integrated circuit apparatus.

IPC Classes  ?

• G06F 17/16 - Matrix or vector computation
• G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit

Abstract

The present invention relates to a method for task scheduling and a related product, wherein the related product comprises a device and a computer-readable storage medium. The device may be comprised in a computing processing apparatus of a combined processing apparatus, wherein the computing processing apparatus may comprise one or more data processing apparatuses. The combined processing apparatus may further comprise an interface apparatus and other processing apparatuses. The computing processing apparatus interacts with the other processing apparatuses to jointly complete a computing operation specified by a user. The combined processing apparatus may further comprise a storage apparatus, wherein the storage apparatus is separately connected to the device and the other processing apparatuses and used for storing data of the device and the other processing apparatuses. By means of the solution of the present invention, a scheduling operation can be optimized, and the defects of exiting scheduling policies are effectively overcome.

IPC Classes  ?

• G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
• G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]

Abstract

A system on a chip, an instruction system, a compilation system, and a related product. The system on a chip may comprise a plurality of heterogeneous IP cores. By means of managing the heterogeneous IP cores as execution units in a hardware pipeline, the heterogeneity of the IP cores can be hidden, such that the programming efficiency and the utilization rate of hardware are improved.

IPC Classes  ?

• G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
• G06F 8/41 - Compilation
• G06F 8/30 - Creation or generation of source code

Abstract

An instruction execution method, a system controller and a related product. The method comprises: during transmission of mixed-scale instructions, checking whether a mixed-scale instruction to be transmitted may be discarded; and when it is determined that said mixed-scale instruction may be discarded, blocking transmission of a particular mixed-scale instruction to be transmitted subsequent to said mixed-scale instruction.

IPC Classes  ?

• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit

Abstract

Disclosed in the present disclosure are an instruction processing apparatus, an instruction execution method, a system-on-chip, and a board. The solution of the present disclosure can hide the heterogeneity of an execution unit by providing a unified hybrid-scale instruction, thereby improving programming efficiency and increasing the utilization rate of hardware.

IPC Classes  ?

• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Abstract

Disclosed in the present disclosure are an instruction execution method, and a system controller and a related product. In the solution in the present disclosure, in an MS instruction pipeline, a branch MS instruction is processed by means of static prediction, such that hardware resources can be saved on, and the solution adapts to CPI characteristics of the MS instruction with a large change range, thereby improving the efficiency of the pipeline. FIG. 14

IPC Classes  ?

• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Abstract

An artificial intelligence accelerator pipeline performance analysis method and an apparatus. A computing device (201) is comprised in an integrated circuit device, and the integrated circuit device comprises a universal interconnection interface and other processing devices. The computing device (201) interacts with other processing devices to jointly complete a computing operation specified by a user. The integrated circuit device may further comprise a storage device, and the storage device is connected to the computing device and the other processing devices, respectively, and is configured to store data of the computing device (201) and other processing devices.

IPC Classes  ?

• G06F 11/267 - Reconfiguring circuits for testing, e.g. LSSD, partitioning

Abstract

The present invention relates to a method and equipment for analyzing timeline performance on an assembly line of an artificial intelligence accelerator. A computing apparatus of the present invention is included in an integrated circuit apparatus, and the integrated circuit apparatus comprises a universal interconnection interface and another processing apparatus. The computing apparatus interacts with the another processing apparatus to jointly complete computing operations specified by a user. The integrated circuit apparatus may further comprise a storage apparatus, the storage apparatus being separately connected to the computing apparatus and the another processing apparatus, and being used for storage of data of the computing apparatus and the another processing apparatus.

IPC Classes  ?

• G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Abstract

A method for reading target data in data based on an instruction, and a computing apparatus (301). The computing apparatus (301) is comprised in an integrated circuit apparatus, and the integrated circuit apparatus comprises a universal interconnection interface and other processing apparatuses. The computing apparatus (301) is interacted with other processing apparatuses to jointly complete a user-specified computing operation. The integrated circuit apparatus further comprises a storage apparatus, wherein the storage apparatus is separately connected to the computing apparatus (301) and other processing apparatuses, and is used for data storage of the computing apparatus (301) and other processing apparatuses.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A data storage method, a data access method, a data computing method, a data storage device, a computing device (201), a chip (101), and a printed circuit board (10). The computing device (201) is comprised in a combined processing device (20), and the combined processing device (20) further comprises an interface device (102) and other processing devices. The computing device (201) interacts with the other processing devices to jointly complete a computing operation specified by a user. The combined processing device (20) further comprises a storage device (204), and the storage device (204) is separately connected to the computing device (201) and the other processing devices and is used for storing data of the computing device (201) and the other processing devices. An efficient storage method and access method are provided for unconventional types of data, and thus, the storage space and the transmission bandwidth are effectively saved.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

The present disclosure discloses a data processing apparatus, a data processing method, and related products. The data processing apparatus is used as a computing apparatus and is included in a combined processing apparatus. The combined processing apparatus further includes an interface apparatus and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus further includes a storage apparatus. The storage apparatus is respectively connected to the computing apparatus and other processing apparatus and is used to store data of the computing apparatus and other processing apparatus. The solution of the present disclosure takes full advantage of parallelism among different storage units to improve utilization of each functional component.

IPC Classes  ?

• G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
• G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal

Abstract

Disclosed in embodiments of the present application are a data acquisition method and apparatus, a device, and a system. The data acquisition device comprises: a processor and a memory, the processor being connected to the memory, the memory being configured to store program code, and the processor being configured to invoke the program code. The solution greatly reduces the data collection cost, and provides data support for an ISP learnable novel perception network architecture. In addition, the solution may significantly shorten the algorithm iteration time, avoid heavy labeling work, and quickly iterate the algorithm version.

IPC Classes  ?

• G06T 3/00 - Geometric image transformations in the plane of the image
• G06T 5/00 - Image enhancement or restoration
• G06V 10/774 - Generating sets of training patternsBootstrap methods, e.g. bagging or boosting

Abstract

The present disclosure provides a processing device including: a coarse-grained pruning unit configured to perform coarse-grained pruning on a weight of a neural network to obtain a pruned weight, an operation unit configured to train the neural network according to the pruned weight. The coarse-grained pruning unit is specifically configured to select M weights from the weights of the neural network through a sliding window, and when the M weights meet a preset condition, all or part of the M weights may be set to 0. The processing device can reduce the memory access while reducing the amount of computation, thereby obtaining an acceleration ratio and reducing energy consumption.

IPC Classes  ?

• G06N 3/08 - Learning methods
• G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
• G06N 3/04 - Architecture, e.g. interconnection topology

Abstract

Disclosed are a general machine learning model generation method and apparatus, and a computer device and a storage medium. The method comprises: acquiring task parameters of a machine learning task (S1201); performing classification processing on the task parameters to obtain task instructions and model parameters (S1202); aggregating the task instructions and the model parameters according to a data type to obtain stack data and heap data (S1203); and integrating the stack data and the heap data to obtain a general machine learning model (S1204). By means of the method, compiled results of a corresponding general model in the running of an algorithm can be directly executed, which avoids repetitive compilation, thus greatly improving the efficiency of machine learning algorithm implementation and shortening the time from compilation to obtaining execution results.

IPC Classes  ?

• G06N 20/00 - Machine learning
• G06F 8/35 - Creation or generation of source code model driven
• G06F 8/41 - Compilation
• G06F 8/10 - Requirements analysisSpecification techniques

Abstract

A packaging frame for a chip, a processing method, and a related product. In an artificial intelligence training scenario, an integrated circuit apparatus can comprise a printed circuit board, wherein a packaging substrate can be disposed on the printed circuit board, and a first system-on-chip chip and a first memory chip can be further disposed on the packaging substrate. The first system-on-chip chip can be communicatively connected to the first memory chip by means of the packaging substrate.

IPC Classes  ?

• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

The technical solution involves a board card including a storage component, an interface apparatus, a control component, and an artificial intelligence chip. The artificial intelligence chip is connected to the storage component, the control component, and the interface apparatus, respectively; the storage component is used to store data; the interface apparatus is used to implement data transfer between the artificial intelligence chip and an external device; and the control component is used to monitor a state of the artificial intelligence chip. The board card is used to perform an artificial intelligence operation.

IPC Classes  ?

• G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
• G06N 3/047 - Probabilistic or stochastic networks
• G06N 3/08 - Learning methods

Abstract

The present application discloses a data processing device and method, and related products. The data processing device comprises a first-level storage unit, a second-level storage unit and a processing unit, wherein the second-level storage unit is divided into a plurality of storage areas, to configure a data-level pipeline comprising the first-level storage unit, the second-level storage unit and the processing unit, so as to support parallel processing between the first-level storage unit and the second-level storage unit and parallel processing between the processing unit and the first-level storage unit and/or the second-level storage unit.

IPC Classes  ?

• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

Abstract

Embodiments of the present disclosure relate to a method and an apparatus for processing data, and related products. The embodiments of the present disclosure relate to a board card, which includes a storage component, an interface apparatus, a control component, and an artificial intelligence chip. The artificial intelligence chip is connected to the storage component, the control component, and the interface apparatus respectively. The storage component is used to store data, the interface apparatus is used to realize data transmission between the artificial intelligence chip and an external device; and the control component is used to monitor a state of the artificial intelligence chip. The board card may be used to perform artificial intelligence computations.

IPC Classes  ?

• G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow
• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/08 - Learning methods

Abstract

The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.

IPC Classes  ?

• G06F 21/85 - Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
• G06F 13/40 - Bus structure
• G06F 30/327 - Logic synthesisBehaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• G06N 3/04 - Architecture, e.g. interconnection topology

Abstract

The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system, and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.

IPC Classes  ?

• G06F 13/40 - Bus structure
• G06N 3/04 - Architecture, e.g. interconnection topology

Abstract

A neural network operation module, which comprises a storage unit that stores output neurons, weight precision and output neuron gradient precision of a multi-layer neural network; a controller unit that obtains an average value Y1 of the absolute value of the output neuron before fixed-point and an average value Y2 of the absolute value of the output neuron after fixed-point; if Y1/Y2 is greater than a preset threshold K, obtaining the output neuron gradient precision of adjacent two layers of the multi-layer neural network, and obtaining an estimation value An of error transfer precision; when An is greater than a preset precision Ar, the output neuron gradient precision and weight precision of the adjacent two layers are increased; and an operation unit that represents the output neuron gradient and weight of the adjacent two layers according to the increased precision.

IPC Classes  ?

• G06N 3/04 - Architecture, e.g. interconnection topology

Abstract

The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.

IPC Classes  ?

• G06F 13/40 - Bus structure
• G06N 3/04 - Architecture, e.g. interconnection topology

Abstract

The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system, and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.

IPC Classes  ?

• G06F 13/40 - Bus structure
• G06N 3/04 - Architecture, e.g. interconnection topology

Abstract

The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.

IPC Classes  ?

• G06F 13/40 - Bus structure
• G06N 3/04 - Architecture, e.g. interconnection topology

Abstract

The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.

IPC Classes  ?

• G06F 13/40 - Bus structure
• G06N 3/04 - Architecture, e.g. interconnection topology

Abstract

The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.

IPC Classes  ?

• G06F 13/40 - Bus structure
• G06N 3/04 - Architecture, e.g. interconnection topology

Abstract

The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.

IPC Classes  ?

• G06F 13/40 - Bus structure
• G06N 3/04 - Architecture, e.g. interconnection topology

Abstract

The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.

IPC Classes  ?

• G06F 13/40 - Bus structure
• G06N 3/04 - Architecture, e.g. interconnection topology

Abstract

Embodiments of the present disclosure relate to a method and an apparatus for processing data, and related products. The embodiments of the present disclosure relate to a board card including a storage component, an interface apparatus, a control component, and an artificial intelligence chip, where the artificial intelligence chip is connected to the storage component, the control component and the interface apparatus respectively. The storage component is used to store data; the interface apparatus is used to realize data transmission between the artificial intelligence chip and the external device. The control component is used to monitor a state of the artificial intelligence chip. The board card may be used to perform artificial intelligence computations.

IPC Classes  ?

• G06N 3/04 - Architecture, e.g. interconnection topology
• G06K 9/62 - Methods or arrangements for recognition using electronic means

Abstract

Embodiments of the present disclosure relate to a method and an apparatus for processing data, and related products. The embodiments of the present disclosure provide a board card including a storage component, an interface device, a control component, and an artificial intelligence chip. The artificial intelligence chip is connected to the storage component, the control component, and the interface device, respectively; the storage component is configured to store data; the interface device is configured to implement data transfer between the artificial intelligence chip and external equipment; and the control component is configured to monitor a state of the artificial intelligence chip. The board card is configured to perform artificial intelligence operations.

IPC Classes  ?

• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
• G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers

Abstract

There is provides an operation module, which includes a memory, a register unit, a dependency relationship processing unit, an operation unit, and a control unit. The memory is configured to store a vector, the register unit is configured to store an extension instruction, and the control unit is configured to acquire and parse the extension instruction, so as to obtain a first operation instruction and a second operation instruction. An execution sequence of the first operation instruction and the second operation instruction can be determined, and an input vector of the first operation instruction can be read from the memory. The operation unit is configured to convert an expression mode of the input data index of the first operation instruction and to screen data, and to execute the first and second operation instruction according to the execution sequence, so as to obtain an extension instruction.

IPC Classes  ?

• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
• G06F 17/16 - Matrix or vector computation
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Abstract

The present disclosure provides a neural network model splitting method and related products. The scheme provided by the present disclosure splits an operator into a plurality of smaller-scale sub-operators, so that a compute library under a single-core architecture can be called directly, which helps to avoid the extra work caused by re-implementation.

IPC Classes  ?

• G06N 3/04 - Architecture, e.g. interconnection topology

Abstract

The present disclosure relates to a method, a device, and related products for processing data. In an embodiment of the present disclosure, when processing data related to a neural network, an optimal truncation threshold value for a plurality of pieces of data is determined. The data is truncated through the truncation data threshold, and the plurality of pieces of data is quantized from a high-precision format to a low-precision format. The method in the present disclosure can ensure the precision of data processing as high as possible while reducing the amount of data processing. In addition, the method also helps to significantly reduce the amount of data transmission, thereby greatly accelerating the data exchange among a plurality of computing devices.

IPC Classes  ?

• G06N 20/00 - Machine learning
• G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/045 - Combinations of networks
• H03M 7/30 - CompressionExpansionSuppression of unnecessary data, e.g. redundancy reduction

Abstract

The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system, and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.

IPC Classes  ?

• G06F 40/205 - Parsing
• G06F 13/40 - Bus structure
• G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
• G06N 3/04 - Architecture, e.g. interconnection topology

Abstract

The present disclosure provides a data normalization processing method, a storage medium, and a computer device. According to the technical solution provided in the present disclosure, by adopting the method of data scaling and operator splicing, the input data in the deep learning neural network is normalized, which reduces the complexity of the normalization operation in the existing deep learning neural network, effectively prevents the data overflow in the process of data processing, and improves the operation speed of the deep learning neural network.

IPC Classes  ?

• G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
• G06F 7/552 - Powers or roots

Abstract

A computing apparatus, an integrated circuit chip, a board, and a method for executing arithmetic operations using the described computing apparatus. The computing apparatus may be included in a combined processing apparatus, and the combined processing apparatus may further comprise a universal interconnecting interface and other processing apparatuses. The computing apparatus interacts with the other processing apparatuses to jointly complete a computing operation designated by a user. The combined processing apparatus may further comprise a storage apparatus, and the storage apparatus is respectively connected to a device and the other processing apparatuses and is used for storing data of the device and the other processing apparatuses.

IPC Classes  ?

• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Abstract

A calculation apparatus, an integrated circuit chip, a board card, and a method for executing an arithmetic operation by using the calculation apparatus. The calculation apparatus may be included in a combined processing apparatus, and the combined processing apparatus may further comprise a universal interconnect interface and other processing apparatuses. The calculation apparatus interacts with other processing apparatuses, to jointly complete a calculation operation specified by a user. The combined processing apparatus can further comprise a storage apparatus, and the storage apparatus is respectively connected to a device and other processing apparatuses, and is configured to store data of the device and other processing apparatuses.

IPC Classes  ?

• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Abstract

A computing apparatus, an integrated circuit chip, a board card, and a method for executing an arithmetic operation by using the computing apparatus. The computing apparatus may be comprised in a combined processing apparatus, and the combined processing apparatus may further comprise a universal interconnection interface and other processing apparatuses. The computing apparatus and the other processing apparatuses interact with each other, so as to jointly complete a computing operation specified by a user. The combined processing apparatus may further comprise a storage apparatus, and the storage apparatus is respectively connected to a device and the other processing apparatuses and is used for storing data of the device and the other processing apparatuses.

IPC Classes  ?

• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Abstract

A computing apparatus, an integrated circuit chip, a board card, an electronic device, and a method for executing a computing operation by using the computing apparatus. The computing apparatus comprises a master processing circuit (102) and at least one slave processing circuit (104, 106, 108). The method comprises: configuring a master processing circuit to execute a master computation operation in response to a master instruction, and configuring a slave processing circuit to execute a slave computation operation in response to a slave instruction, wherein the master computation operation comprises a pre-processing operation and/or a post-processing operation for the slave computation operation, and the master instruction and the slave instruction are obtained by parsing a computing instruction received by the computing apparatus. By means of the method, a master instruction and a slave instruction related to a master computation operation and a slave computation operation can be efficiently executed, so as to accelerate the execution of the computation operations. The master computation operation and the slave computation operation are combined, such that the computing apparatus can support more types of computations and operations. A computing instruction can be flexibly configured on the basis of a pipeline computation arrangement, so as to meet a computing requirement.

IPC Classes  ?

• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/08 - Learning methods
• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Abstract

Provided are a computing apparatus, an integrated circuit chip, a board, and a method for executing arithmetic operations using the computing apparatus. The computing apparatus (1210) is included in a combined processing apparatus, and the combined processing apparatus further comprises a universal interconnecting interface and other processing apparatuses (1206). The computing apparatus (1210) interacts with the other processing apparatuses (1206) to jointly complete computing operations designated by a user. The combined processing apparatus further comprises a storage apparatus (1208), and the storage apparatus (1208) is respectively connected to a device and the other processing apparatuses (1206), and is configured to store data of the device and the other processing apparatuses (1206).

IPC Classes  ?

• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Abstract

An integrated computing apparatus, an integrated circuit chip, a board card, and a method for executing an arithmetic operation using the integrated computing apparatus. The integrated computing apparatus may be included in a combined processing apparatus, and the combined processing apparatus may further comprise a general interconnection interface and other processing apparatuses. The integrated computing apparatus interacts with the other processing apparatuses to jointly complete a user-specified computing operation. The combined processing apparatus may further comprise a storage apparatus, the storage apparatus respectively being connected to a device and the other processing apparatuses, and being used to store data of the device and the other processing apparatuses.

IPC Classes  ?

• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

Abstract

Disclosed are a computing apparatus, an integrated circuit chip, a board card, and a method for executing a computing operation by using the computing apparatus. The computing apparatus can be included in a combined processing apparatus. The combined processing apparatus further includes a universal interconnect interface and other processing apparatuses. The computing apparatus and other processing apparatuses interact with each other to joint complete a user-specified computing operation. The combined processing apparatus further includes a storage apparatus respectively connected to a device and other processing apparatuses and configured to store data in the device and other processing apparatuses. The solution can improve the operation efficiency of various data processing fields, such as artificial intelligence, thereby reducing overall operation overhead and cost. (Abstract drawing: Fig. 12)

IPC Classes  ?

• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Abstract

A computing apparatus, an integrated circuit chip, a board card, and a method for executing a computing operation by using the computing apparatus. The computing apparatus can be included in a combined processing apparatus. The combined processing apparatus further includes a universal interconnect interface and other processing apparatuses. The computing apparatus and other processing apparatuses interact with each other to joint complete a user-specified computing operation. The combined processing apparatus further includes a storage apparatus respectively connected to a device and other processing apparatuses and configured to store data in the device and other processing apparatuses.

IPC Classes  ?

• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

Abstract

A computing apparatus, an integrated circuit chip, a board card and a method for performing an arithmetic operation by using the computing apparatus. The computing apparatus may be included in a combined processing apparatus, and the combined processing apparatus may further comprise a universal interconnection interface and other processing apparatuses. The computing apparatus interacts with other processing apparatuses to jointly complete a computing operation specified by a user. The combined processing apparatus may further comprise a storage apparatus, and the storage apparatus is respectively connected to a device and the other processing apparatuses and used for storing data of the device and other processing apparatuses.

IPC Classes  ?

• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Abstract

A computing apparatus, an integrated circuit chip, a board card, an electronic device, and a method of executing an arithmetic operation using said computing apparatus. The computing apparatus may be comprised in a combined processing apparatus, the combined processing apparatus may further comprise a universal interconnection interface and other processing apparatuses. The computing apparatus interacts with other processing apparatuses to jointly complete a computing operation specified by a user. The combined processing apparatus may further comprise a storage apparatus. The storage apparatus is connected to the device and other processing apparatuses, respectively, and used for storing data of the device and other processing apparatuses.

IPC Classes  ?

• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

Abstract

The present disclosure provides a computation device. The computation device is configured to perform a machine learning computation, and includes an operation unit, a controller unit, and a conversion unit. The storage unit is configured to obtain input data and a computation instruction. The controller unit is configured to extract and parse the computation instruction from the storage unit to obtain one or more operation instructions, and to send the one or more operation instructions and the input data to the operation unit. The operation unit is configured to perform operations on the input data according to one or more operation instructions to obtain a computation result of the computation instruction. In the examples of the present disclosure, the input data involved in machine learning computations is represented by fixed-point data, thereby improving the processing speed and efficiency of training operations.

IPC Classes  ?

• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
• G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow

Abstract

The present disclosure provides a signal processing device, including a signal collector, an instruction converter, and a processor. Examples of the present disclosure may achieve precise recognition of users' intentions and bring operational conveniences to users.

IPC Classes  ?

• G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
• G06N 20/00 - Machine learning
• G06F 40/30 - Semantic analysis
• G06N 3/06 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
• G10L 15/22 - Procedures used during a speech recognition process, e.g. man-machine dialog
• G10L 15/26 - Speech to text systems
• G06V 40/20 - Movements or behaviour, e.g. gesture recognition

Abstract

The present disclosure relates to a neural network quantization parameter determination method and related products. A board card in the related products includes a memory device, an interface device, a control device, and an artificial intelligence chip, in which the artificial intelligence chip is connected with the memory device, the control device, and the interface device respectively. The memory device is configured to store data, and the interface device is configured to transmit data between the artificial intelligence chip and an external device. The control device is configured to monitor the state of the artificial intelligence chip. The board card can be used to perform an artificial intelligence computation.

IPC Classes  ?

• G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
• G06N 3/08 - Learning methods
• G06N 3/047 - Probabilistic or stochastic networks

Abstract

Disclosed are an information processing method and a terminal device. The method comprises: acquiring first information, wherein the first information is information to be processed by a terminal device; calling an operation instruction in a calculation apparatus to calculate the first information so as to obtain second information; and outputting the second information. By means of the examples in the present disclosure, a calculation apparatus of a terminal device can be used to call an operation instruction to process first information, so as to output second information of a target desired by a user, thereby improving the information processing efficiency. The present technical solution has advantages of a fast computation speed and high efficiency.

IPC Classes  ?

• G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/08 - Learning methods
• G06T 5/20 - Image enhancement or restoration using local operators
• G06T 5/50 - Image enhancement or restoration using two or more images, e.g. averaging or subtraction
• G06T 7/20 - Analysis of motion
• G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
• G06T 1/60 - Memory management
• G06T 3/40 - Scaling of whole images or parts thereof, e.g. expanding or contracting
• G06F 40/58 - Use of machine translation, e.g. for multi-lingual retrieval, for server-side translation for client devices or for real-time translation
• G06F 40/263 - Language identification
• G06N 3/02 - Neural networks
• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
• G06F 9/445 - Program loading or initiating
• G10L 15/00 - Speech recognition
• G06V 10/94 - Hardware or software architectures specially adapted for image or video understanding
• G06V 10/70 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning
• G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
• G06N 3/082 - Learning methods modifying the architecture, e.g. adding, deleting or silencing nodes or connections
• G06N 3/084 - Backpropagation, e.g. using gradient descent

Abstract

The present application discloses an on-chip code breakpoint debugging method, an on-chip processor, and a chip breakpoint debugging system. The on-chip processor starts and executes an on-chip code, and an output function is set at a breakpoint position of the on-chip code. The on-chip processor obtains output information output by the output function, and stores the output information into an off-chip memory. In one embodiment, according to the output information, output by the output function and stored in the off-chip memory, the on-chip processor can obtain execution conditions of the breakpoints of the on-chip code in real time, achieve the purpose of debugging multiple breakpoints in the on-chip code concurrently, and improve debugging efficiency.

IPC Classes  ?

• G06F 11/36 - Prevention of errors by analysis, debugging or testing of software

Abstract

Disclosed are an information processing method and a terminal device. The method comprises: acquiring first information, wherein the first information is information to be processed by a terminal device; calling an operation instruction in a calculation apparatus to calculate the first information so as to obtain second information; and outputting the second information. By means of the examples in the present disclosure, a calculation apparatus of a terminal device can be used to call an operation instruction to process first information, so as to output second information of a target desired by a user, thereby improving the information processing efficiency. The present technical solution has advantages of a fast computation speed and high efficiency.

IPC Classes  ?

• G06T 3/40 - Scaling of whole images or parts thereof, e.g. expanding or contracting
• G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
• G06T 1/60 - Memory management
• G06K 9/46 - Extraction of features or characteristics of the image

Abstract

Disclosed are an information processing method and a terminal device. The method comprises: acquiring first information, wherein the first information is information to be processed by a terminal device; calling an operation instruction in a calculation apparatus to calculate the first information so as to obtain second information; and outputting the second information. By means of the examples in the present disclosure, a calculation apparatus of a terminal device can be used to call an operation instruction to process first information, so as to output second information of a target desired by a user, thereby improving the information processing efficiency. The present technical solution has advantages of a fast computation speed and high efficiency.

IPC Classes  ?

• G06F 40/58 - Use of machine translation, e.g. for multi-lingual retrieval, for server-side translation for client devices or for real-time translation
• G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
• G06F 9/445 - Program loading or initiating
• G06F 40/263 - Language identification
• G06N 3/02 - Neural networks
• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/08 - Learning methods
• G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
• G06T 1/60 - Memory management
• G06T 3/4046 - Scaling of whole images or parts thereof, e.g. expanding or contracting using neural networks
• G06T 3/4053 - Scaling of whole images or parts thereof, e.g. expanding or contracting based on super-resolution, i.e. the output image resolution being higher than the sensor resolution
• G06T 5/20 - Image enhancement or restoration using local operators
• G06T 5/50 - Image enhancement or restoration using two or more images, e.g. averaging or subtraction
• G06T 7/20 - Analysis of motion
• G06V 10/70 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning
• G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
• G06V 10/94 - Hardware or software architectures specially adapted for image or video understanding
• G10L 15/00 - Speech recognition
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
• G06N 3/082 - Learning methods modifying the architecture, e.g. adding, deleting or silencing nodes or connections
• G06N 3/084 - Backpropagation, e.g. using gradient descent

Abstract

Disclosed are an information processing method and a terminal device. The method comprises: acquiring first information, wherein the first information is information to be processed by a terminal device; calling an operation instruction in a calculation apparatus to calculate the first information so as to obtain second information; and outputting the second information. By means of the examples in the present disclosure, a calculation apparatus of a terminal device can be used to call an operation instruction to process first information, so as to output second information of a target desired by a user, thereby improving the information processing efficiency. The present technical solution has advantages of a fast computation speed and high efficiency.

IPC Classes  ?

• G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
• G06F 9/445 - Program loading or initiating
• G06F 40/263 - Language identification
• G06F 40/58 - Use of machine translation, e.g. for multi-lingual retrieval, for server-side translation for client devices or for real-time translation
• G06N 3/02 - Neural networks
• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/08 - Learning methods
• G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
• G06T 1/60 - Memory management
• G06T 5/20 - Image enhancement or restoration using local operators
• G06T 5/50 - Image enhancement or restoration using two or more images, e.g. averaging or subtraction
• G06T 7/20 - Analysis of motion
• G06V 10/70 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning
• G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
• G06V 10/94 - Hardware or software architectures specially adapted for image or video understanding
• G10L 15/00 - Speech recognition
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
• G06N 3/082 - Learning methods modifying the architecture, e.g. adding, deleting or silencing nodes or connections
• G06N 3/084 - Backpropagation, e.g. using gradient descent

Abstract

Disclosed are an information processing method and a terminal device. The method comprises: acquiring first information, wherein the first information is information to be processed by a terminal device, calling an operation instruction in a calculation apparatus to calculate the first information so as to obtain second information, and outputting the second information. By means of the examples in the present disclosure, a calculation apparatus of a terminal device can be used to call an operation instruction to process first information, so as to output second information of a target desired by a user, thereby improving the information processing efficiency. The present technical solution has advantages of a fast computation speed and high efficiency.

IPC Classes  ?

• G06F 16/9535 - Search customisation based on user profiles and personalisation
• G06F 18/20 - Analysing
• G06F 18/21 - Design or setup of recognition systems or techniquesExtraction of features in feature spaceBlind source separation
• G06F 18/2431 - Multiple classes
• G06F 18/40 - Software arrangements specially adapted for pattern recognition, e.g. user interfaces or toolboxes therefor
• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/08 - Learning methods
• G06Q 30/0601 - Electronic shopping [e-shopping]
• G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
• G06T 3/4046 - Scaling of whole images or parts thereof, e.g. expanding or contracting using neural networks
• G10L 15/16 - Speech classification or search using artificial neural networks
• G10L 17/00 - Speaker identification or verification techniques
• G10L 17/18 - Artificial neural networksConnectionist approaches

Abstract

The present application relates to an operation device and an operation method. The operation device includes a plurality of operation modules. The plurality of operation modules complete an operation of a network model by executing corresponding computational sub-commands in parallel. Each operation module includes at least one operation unit configured to execute a first computational sub-command using first computational sub-data; and a storage unit configured to store the first computational sub-data. The first computational sub-data includes data needed for executing the first computational sub-command. The embodiments of the present application reduces bandwidth requirements for data access and reduces computation and equipment costs.

IPC Classes  ?

• G06N 5/02 - Knowledge representationSymbolic representation
• G06F 7/57 - Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups or for performing logical operations

Abstract

Disclosed are a general-purpose machine learning model generation method and apparatus, and a computer device and a storage medium. The method comprises: acquiring task parameters of a machine learning task (S1201), performing classification processing on the task parameters to obtain task instructions and model parameters (S1202), aggregating the task instructions and the model parameters according to a data type to obtain stack data and heap data (S1203), and integrating the stack data and the heap data to obtain a general-purpose machine learning model (S1204). By means of the method, compiled results of a corresponding general-purpose model in the running of an algorithm can be directly executed, which avoids repetitive compilation, thus greatly improving the efficiency of machine learning algorithm implementation and shortening the time from compilation to obtaining execution results.

IPC Classes  ?

• G06N 20/00 - Machine learning
• G06F 8/10 - Requirements analysisSpecification techniques
• G06F 8/35 - Creation or generation of source code model driven
• G06F 8/41 - Compilation

Abstract

Disclosed are a general machine learning model generation method and apparatus, and a computer device and a storage medium. The method comprises: acquiring task parameters of a machine learning task (S1201); performing classification processing on the task parameters to obtain task instructions and model parameters (S1202); aggregating the task instructions and the model parameters according to a data type to obtain stack data and heap data (S1203); and integrating the stack data and the heap data to obtain a general machine learning model (S1204). By means of the method, compiled results of a corresponding general model in the running of an algorithm can be directly executed, which avoids repetitive compilation, thus greatly improving the efficiency of machine learning algorithm implementation and shortening the time from compilation to obtaining execution results.

IPC Classes  ?

• G06F 8/41 - Compilation
• G06N 20/00 - Machine learning
• G06F 8/35 - Creation or generation of source code model driven
• G06F 8/10 - Requirements analysisSpecification techniques

Abstract

Disclosed are a general machine learning model generation method and apparatus, and a computer device and a storage medium. The method comprises: acquiring task parameters of a machine learning task (S1201); performing classification processing on the task parameters to obtain task instructions and model parameters (S1202); aggregating the task instructions and the model parameters according to a data type to obtain stack data and heap data (S1203); and integrating the stack data and the heap data to obtain a general machine learning model (S1204). By means of the method, compiled results of a corresponding general model in the running of an algorithm can be directly executed, which avoids repetitive compilation, thus greatly improving the efficiency of machine learning algorithm implementation and shortening the time from compilation to obtaining execution results.

IPC Classes  ?

• G06F 8/41 - Compilation
• G06N 20/00 - Machine learning
• G06F 8/35 - Creation or generation of source code model driven
• G06F 8/10 - Requirements analysisSpecification techniques

Abstract

Disclosed are a general machine learning model generation method and apparatus, and a computer device and a storage medium. The method comprises: acquiring task parameters of a machine learning task (S1201); performing classification processing on the task parameters to obtain task instructions and model parameters (S1202); aggregating the task instructions and the model parameters according to a data type to obtain stack data and heap data (S1203); and integrating the stack data and the heap data to obtain a general machine learning model (S1204). By means of the method, compiled results of a corresponding general model in the running of an algorithm can be directly executed, which avoids repetitive compilation, thus greatly improving the efficiency of machine learning algorithm implementation and shortening the time from compilation to obtaining execution results.

IPC Classes  ?

• G06N 20/00 - Machine learning
• G06F 8/35 - Creation or generation of source code model driven
• G06F 8/41 - Compilation
• G06F 8/10 - Requirements analysisSpecification techniques

Abstract

Disclosed are a general machine learning model generation method and apparatus, and a computer device and a storage medium. The method comprises: acquiring task parameters of a machine learning task (S1201); performing classification processing on the task parameters to obtain task instructions and model parameters (S1202); aggregating the task instructions and the model parameters according to a data type to obtain stack data and heap data (S1203); and integrating the stack data and the heap data to obtain a general machine learning model (S1204). By means of the method, compiled results of a corresponding general model in the running of an algorithm can be directly executed, which avoids repetitive compilation, thus greatly improving the efficiency of machine learning algorithm implementation and shortening the time from compilation to obtaining execution results.

IPC Classes  ?

• G06N 20/00 - Machine learning
• G06F 8/35 - Creation or generation of source code model driven
• G06F 8/41 - Compilation
• G06F 8/10 - Requirements analysisSpecification techniques

Abstract

Disclosed are an information processing method and a terminal device. The method comprises: acquiring first information, wherein the first information is information to be processed by a terminal device; calling an operation instruction in a calculation apparatus to calculate the first information so as to obtain second information; and outputting the second information. By means of the examples in the present disclosure, a calculation apparatus of a terminal device can be used to call an operation instruction to process first information, so as to output second information of a target desired by a user, thereby improving the information processing efficiency. The present technical solution has advantages of a fast computation speed and high efficiency.

IPC Classes  ?

• G10L 15/16 - Speech classification or search using artificial neural networks
• G06F 16/9535 - Search customisation based on user profiles and personalisation
• G06F 18/20 - Analysing
• G06F 18/21 - Design or setup of recognition systems or techniquesExtraction of features in feature spaceBlind source separation
• G06F 18/2431 - Multiple classes
• G06F 18/40 - Software arrangements specially adapted for pattern recognition, e.g. user interfaces or toolboxes therefor
• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/08 - Learning methods
• G06Q 30/0601 - Electronic shopping [e-shopping]
• G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
• G06T 3/4046 - Scaling of whole images or parts thereof, e.g. expanding or contracting using neural networks
• G10L 17/00 - Speaker identification or verification techniques
• G10L 17/18 - Artificial neural networksConnectionist approaches

Abstract

Disclosed are an information processing method and a terminal device. The method comprises: acquiring first information, wherein the first information is information to be processed by a terminal device; calling an operation instruction in a calculation apparatus to calculate the first information so as to obtain second information; and outputting the second information. By means of the examples in the present disclosure, a calculation apparatus of a terminal device can be used to call an operation instruction to process first information, so as to output second information of a target desired by a user, thereby improving the information processing efficiency. The present technical solution has advantages of a fast computation speed and high efficiency.

IPC Classes  ?

• G10L 17/00 - Speaker identification or verification techniques
• G06F 16/9535 - Search customisation based on user profiles and personalisation
• G06F 18/20 - Analysing
• G06F 18/21 - Design or setup of recognition systems or techniquesExtraction of features in feature spaceBlind source separation
• G06F 18/2431 - Multiple classes
• G06F 18/40 - Software arrangements specially adapted for pattern recognition, e.g. user interfaces or toolboxes therefor
• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/08 - Learning methods
• G06Q 30/0601 - Electronic shopping [e-shopping]
• G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
• G06T 3/4046 - Scaling of whole images or parts thereof, e.g. expanding or contracting using neural networks
• G10L 15/16 - Speech classification or search using artificial neural networks
• G10L 17/18 - Artificial neural networksConnectionist approaches

Abstract

An information processing method applied to a computation circuit is disclosed. The computation circuit includes a communication circuit and an operation circuit. The method includes controlling, by the computation circuit, the communication circuit to obtain a voice to be identified input by a user; controlling, by the computation circuit, the operation circuit to obtain and call an operation instruction to perform voice identification processing on the voice to be identified to obtain target text information corresponding to the voice to be identified. The operation instruction is a preset instruction for voice identification.

IPC Classes  ?

• G10L 15/16 - Speech classification or search using artificial neural networks
• G06F 16/9535 - Search customisation based on user profiles and personalisation
• G06F 18/20 - Analysing
• G06F 18/21 - Design or setup of recognition systems or techniquesExtraction of features in feature spaceBlind source separation
• G06F 18/2431 - Multiple classes
• G06F 18/40 - Software arrangements specially adapted for pattern recognition, e.g. user interfaces or toolboxes therefor
• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/08 - Learning methods
• G06Q 30/0601 - Electronic shopping [e-shopping]
• G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
• G06T 3/4046 - Scaling of whole images or parts thereof, e.g. expanding or contracting using neural networks
• G10L 17/00 - Speaker identification or verification techniques
• G10L 17/18 - Artificial neural networksConnectionist approaches

Abstract

Disclosed are an information processing method and a terminal device. The method comprises: acquiring first information, wherein the first information is information to be processed by a terminal device; calling an operation instruction in a calculation apparatus to calculate the first information so as to obtain second information; and outputting the second information. By means of the examples in the present disclosure, a calculation apparatus of a terminal device can be used to call an operation instruction to process first information, so as to output second information of a target desired by a user, thereby improving the information processing efficiency. The present technical solution has advantages of a fast computation speed and high efficiency.

IPC Classes  ?

• G10L 17/00 - Speaker identification or verification techniques
• G06F 16/9535 - Search customisation based on user profiles and personalisation
• G06F 18/20 - Analysing
• G06F 18/21 - Design or setup of recognition systems or techniquesExtraction of features in feature spaceBlind source separation
• G06F 18/2431 - Multiple classes
• G06F 18/40 - Software arrangements specially adapted for pattern recognition, e.g. user interfaces or toolboxes therefor
• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/08 - Learning methods
• G06Q 30/0601 - Electronic shopping [e-shopping]
• G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
• G06T 3/4046 - Scaling of whole images or parts thereof, e.g. expanding or contracting using neural networks
• G10L 15/16 - Speech classification or search using artificial neural networks
• G10L 17/18 - Artificial neural networksConnectionist approaches

Abstract

Disclosed are a general machine learning model generation method and apparatus, and a computer device and a storage medium. The method comprises: acquiring task parameters of a machine learning task (S1201); performing classification processing on the task parameters to obtain task instructions and model parameters (S1202); aggregating the task instructions and the model parameters according to a data type to obtain stack data and heap data (S1203); and integrating the stack data and the heap data to obtain a general machine learning model (S1204). By means of the method, compiled results of a corresponding general model in the running of an algorithm can be directly executed, which avoids repetitive compilation, thus greatly improving the efficiency of machine learning algorithm implementation and shortening the time from compilation to obtaining execution results.

IPC Classes  ?

• G06N 20/00 - Machine learning
• G06F 8/10 - Requirements analysisSpecification techniques
• G06F 8/35 - Creation or generation of source code model driven
• G06F 8/41 - Compilation

Abstract

A method and apparatus for processing data, and a related product, relating to a board. The PCB comprises: a memory device, an interface means, a control device, and an artificial intelligence chip. The artificial intelligence chip is separately connected to the memory device, the control device, and the interface means; the memory device is used for storing data; the interface means is used for implementing data transmission between the artificial intelligence chip and an external device; the control device is used for monitoring the state of the artificial intelligence chip. The board can be used for performing artificial intelligence operations.

IPC Classes  ?

• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 20/00 - Machine learning
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Abstract

Provided are a method and apparatus for processing data, and a related product. The method for processing data comprises the following steps: obtaining a group of data to be quantified for a machine learning model; respectively quantifying the group of data to be quantified by using multiple point positions to determine multiple groups of quantified data, each point position in the multiple point positions specifying a position of a decimal point in the multiple groups of quantified data; and selecting one point position from the multiple point positions for quantifying the group of data to be quantified on the basis of the difference between each group of quantified data in the multiple groups of quantified data and the group of data to be quantified.

IPC Classes  ?

• G06N 3/04 - Architecture, e.g. interconnection topology

Abstract

Embodiments of the present invention relate to a method and apparatus for processing data, and a related product. The embodiments of the present invention relate to a board. The board comprises: a storage device, an interface apparatus, a control device, and an artificial intelligence chip; wherein the artificial intelligence chip is separately connected to the storage device, the control device, and the interface apparatus; the storage device is used for storing data; the interface apparatus is used for implementing data transmission between the artificial intelligence chip and an external device; and the control device is used for monitoring a status of the artificial intelligence chip. The board can be used for performing artificial intelligence operation.

IPC Classes  ?

• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Abstract

Provided are a data processing method and a device, a computer apparatus, and a storage medium. The method comprises: determining a plurality of data to be quantized from target data according to the precision requirement of the target task and/or the terminal, wherein each of the data to be quantized is a subset of the target data, the target data is any data to be calculated and quantized in the layer to be quantized of the neural network, and the data to be calculated comprises at least one of input neurons, weights, biases and gradients (S4-11); respectively quantizing each of the data to be quantized according to a corresponding quantization parameter to obtain quantization data corresponding to each data to be quantized (S4-12); and obtaining a quantization result of the target data according to the quantization data corresponding to each of the data to be quantized, so that the layer to be quantized operates according to the quantization result of the target data (S4-13).

IPC Classes  ?

• G06N 3/04 - Architecture, e.g. interconnection topology

Abstract

The present disclosure relates to a data processing method and apparatus, and a related product. In an embodiment of the present disclosure, an optimal truncation threshold for multiple pieces of data is determined when data relating to a neural network is processed. The truncation data threshold is used for truncating data, and the multiple pieces of data are quantized from a high-precision format into a low-precision format. By means of the method in the present disclosure, the precision of data processing is guaranteed as much as possible while simultaneously reducing data processing volume. In addition, the described method also helps to significantly reduce the amount of data transmission, thereby greatly accelerating data exchange between multiple computing devices.

IPC Classes  ?

• G06N 3/04 - Architecture, e.g. interconnection topology
• G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers

Abstract

Aspect for storage device with fault tolerance capability for neural networks are described herein. The aspects may include a first storage unit of a storage device. The first storage unit is configured to store one or more first bits of data and the data includes floating point type data and fixed point type data. The first bits include one or more sign bits of the floating point type data and the fixed point type data. The aspect may further include a second storage unit of the storage device. The second storage unit may be configured to store one or more second bits of the data. In some examples, the first storage unit may include an ECC memory and the second storage unit may include a non-ECC memory. The ECC memory may include an ECC check Dynamic Random Access Memory and an ECC check Static Random Access Memory.

IPC Classes  ?

• G11C 11/419 - Read-write [R-W] circuits
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check

Abstract

A compiling method and device for deep learning algorithm and a related product, resulting in the improvement of computing efficiency of the related product when performing operations of a neural network model. The product comprises a controller unit, and the controller unit comprises an instruction cache unit, an instruction processing unit and a storage queue unit. The instruction cache unit is used for storing computing instructions correlated to artificial neural network operations; the instruction processing unit is used for parsing the computing instructions so as to obtain a plurality of operationinstructions; the storage queue unit is used for storing an instruction queue, the instruction queue comprising a plurality of operationinstructions or computing instructions to be executed according to the sequential order of the queue.

IPC Classes  ?

• G06F 8/41 - Compilation
• G06N 3/02 - Neural networks

Abstract

The present disclosure relates to a neural network quantization parameter determination method and related products. A board card in the related products includes a memory device, an interface device, a control device, and an artificial intelligence chip, in which the artificial intelligence chip is connected with the memory device, the control device, and the interface device respectively. The memory device is configured to store data, and the interface device is configured to transmit data between the artificial intelligence chip and an external device. The control device is configured to monitor the state of the artificial intelligence chip. The board card can be used to perform an artificial intelligence computation.

IPC Classes  ?

• G06N 3/084 - Backpropagation, e.g. using gradient descent
• G06F 17/18 - Complex mathematical operations for evaluating statistical data
• G06N 20/00 - Machine learning

Abstract

A quantization parameter determination method for a neural network, and a related product. A board in the related product comprises a storage device (390), an interface device (391), a control device (392), and an artificial intelligence chip (389). The artificial intelligence chip is separately connected to the storage device, the control device, and the interface device. The storage device is used for storing data. The interface device is used for implementing data transmission between the artificial intelligence chip and an external device. The control device is used for monitoring the state of the artificial intelligence chip. The board can be used for performing artificial intelligence operations.

IPC Classes  ?

• G06N 3/08 - Learning methods

Abstract

A method for determining a quantization parameter of a neural network, and a related product. The related product comprises a card, and the card comprises a storage device (390), an interface apparatus (391), a control device (392), and an artificial intelligence chip (389). The artificial intelligence chip (389) is respectively connected to the storage device (390), the control device (392), and the interface apparatus (391). The storage device (390) is used to store data, the interface apparatus (391) is used to transmit data between the artificial intelligence chip (389) and an external device, and the control device (392) is used to monitor the status of the artificial intelligence chip (389). The card can be used to perform artificial intelligence operations.

IPC Classes  ?

• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/08 - Learning methods

Abstract

The present disclosure relates to a neural network quantization parameter determination method and related products. A board card in the related products includes a memory device, an interface device, a control device, and an artificial intelligence chip, in which the artificial intelligence chip is connected with the memory device, the control device, and the interface device respectively. The memory device is configured to store data, and the interface device is configured to transmit data between the artificial intelligence chip and an external device. The control device is configured to monitor the state of the artificial intelligence chip. The board card can be used to perform an artificial intelligence computation.

IPC Classes  ?

• G06N 3/084 - Backpropagation, e.g. using gradient descent
• G06F 17/18 - Complex mathematical operations for evaluating statistical data
• G06N 20/00 - Machine learning

Abstract

A command processing method and apparatus, and related products, used for analyzing a compiled memory assignment command to obtain an operation code and an operation domain of the memory assignment command, and obtaining, according to the operation code and the operation domain, a storage address of a target tensor, the number of elements to be assigned in the target tensor, and target values, wherein the operation domain comprises the storage address of the target tensor, the number of said elements in the target tensor, and the target values, and the storage space directed to by the storage address of the target tensor is an on-chip storage space of a command processing apparatus; and using the target values as the values of said elements in the target tensor according to the storage address of the target tensor, the number of said elements in the target tensor, and the target values. The present application has a wide application range, and achieves a high command processing efficiency and a fast command processing speed.

IPC Classes  ?

• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Abstract

The present disclosure provides an adjusting method for quantization frequency of operational data and a related product. The method comprises adjusting the quantization frequency of a neural network. Thus, the present disclosure has the advantage of high calculation accuracy.

IPC Classes  ?

• G06N 3/08 - Learning methods

Abstract

An operation method and apparatus, and a related product. The product comprises a control module, and the control module comprises: an instruction caching unit, an instruction processing unit and a queue storage unit, wherein the instruction caching unit is used for storing computing instructions associated with an artificial neural network operation; the instruction processing unit is used for resolving the computing instructions to obtain a plurality of operation instructions; and the queue storage unit is used for storing instruction queues, the instruction queues comprising a plurality of operation instructions to be executed or computing instructions to be executed according to a sequential order of the queues. The operation efficiency, when an operation of a neural network model is performed, of a related product can be improved.

IPC Classes  ?

• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Abstract

A neural network operation module, which comprises a storage unit that stores output neurons, weight precision and output neuron gradient precision of a multi-layer neural network; a controller unit that obtains an average value Y1 of the absolute value of the output neuron before fixed-point and an average value Y2 of the absolute value of the output neuron after fixed-point; if Y1/Y2 is greater than a preset threshold K, obtaining the output neuron gradient precision of adjacent two layers of the multi-layer neural network, and obtaining an estimation value A nof error transfer precision according to the output neuron gradient precision and weight precision of the adjacent two layers; when Anrr, the output neuron gradient precision and weight precision of the adjacent two layers are increased; and an operation unit that represents the output neuron gradient and weight of the adjacent two layers according to the increased precision, and performs subsequent operation.

IPC Classes  ?

• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Abstract

The present disclosure relates to an operation method and device and a related product, the product comprising a controller unit, and the controller unit comprising: an instruction cache unit, an instruction processing unit and a queue-storing unit. The instruction cache unit is used to store computing instructions associated with an artificial neural network operation. The instruction processing unit is used to resolve the computing instructions to obtain a plurality of operation instructions. The queue-storing unit is used to store an instruction queue, which comprises: a plurality of operation instructions or computing instructions to be executed according to the front-to-rear sequence of the queue. By means of the described method, the present disclosure may improve the operation efficiency of the related product when carrying out a neural network model operation.

IPC Classes  ?

• G06N 3/02 - Neural networks

Abstract

Aspect for storage device with fault tolerance capability for neural networks are described herein. The aspects may include a first storage unit of a storage device. The first storage unit is configured to store one or more first bits of data and the data includes floating point type data and fixed point type data. The first bits include one or more sign bits of the floating point type data and the fixed point type data. The aspect may further include a second storage unit of the storage device. The second storage unit may be configured to store one or more second bits of the data. In some examples, the first storage unit may include an ECC memory and the second storage unit may include a non-ECC memory. The ECC memory may include an ECC check Dynamic Random Access Memory and an ECC check Static Random Access Memory.

IPC Classes  ?

• G11C 11/41 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• G11C 11/419 - Read-write [R-W] circuits
• G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect

Abstract

Provided are a neural network model splitting method and related products, wherein one operator is split into multiple smaller-scale sub-operators, for directly calling a computing library under a single-core architecture.

IPC Classes  ?

• G06N 3/08 - Learning methods

Abstract

The application provides a processing method and device. Weights and input neurons are quantized respectively, and a weight dictionary, a weight codebook, a neuron dictionary, and a neuron codebook are determined. A computational codebook is determined according to the weight codebook and the neuron codebook. Meanwhile, according to the application, the computational codebook is determined according to two types of quantized data, and the two types of quantized data are combined, which facilitates data processing.

IPC Classes  ?

• G06N 3/08 - Learning methods
• G06N 20/10 - Machine learning using kernel methods, e.g. support vector machines [SVM]
• G06K 9/62 - Methods or arrangements for recognition using electronic means
• G06N 5/04 - Inference or reasoning models
• G06N 3/084 - Backpropagation, e.g. using gradient descent
• G06N 5/046 - Forward inferencingProduction systems