A semiconductor structure includes: a logic device including a first power line and a second power line located on a same wiring layer, extending along a first direction and arranged in parallel along a second direction, the first direction and the second direction intersecting with each other and being parallel to a plane where the wiring layer is located; and a switch driving device, the switch driving device and the logic device being arranged in parallel along the first direction, the switch driving device including a first input line and a first output line located on the same wiring layer as the first power line, extending along the first direction and arranged in parallel along the second direction, the first output line being connected with the first power line or the second power line.
H03K 19/0948 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET using CMOS
A semiconductor structure and a memory are provided. The semiconductor structure includes multiple active regions, a column selector and multiple bit lines. The column selector includes a first gate, a second gate, a third gate, a fourth gate and a connection line. The first gate and the second gate intersect at a first node, the third gate and the fourth gate intersect at the second node, and the connection line connects the first node and the second node. Each of the multiple bit lines includes a first portion, a second portion and a connection portion. Each of the multiple bit lines is connected to a respective one of the multiple active regions, the active regions connected to different bit lines among the multiple bit lines are different.
A semiconductor structure includes: a bit line, a transistor structure, and a capacitor structure arranged in sequence in a first direction, the capacitor structure extending in the first direction, both the transistor structure and the capacitor structure including a portion of a semiconductor layer, and the semiconductor layer extending in the first direction; and a bit line contact layer on an end surface of the semiconductor layer that is away from the capacitor structure, the bit line contact layer and the semiconductor layer including the same semiconductor material, and the bit line covering an end surface of the bit line contact layer that is away from the semiconductor layer and covering at least a portion of a sidewall of the bit line contact layer that extends in the first direction.
A semiconductor structure is provided. The semiconductor structure includes: a substrate; a plurality of capacitors arranged in the substrate; and a plurality of active pillars arranged above the substrate. Each of the plurality of active pillars is arranged above a respective one of the plurality of capacitors, and a bottom portion of each of the plurality of active pillars is electrically connected to a top portion of the respective one of the plurality of capacitors therebelow.
Provided is a multi-dies stacking structure, which includes: a plurality of core dies stacked, wherein each core die comprises a first sub-core die and a second sub-core die vertically stacked; adjacent core dies are interconnected through micro-metal bumps, and the first sub-core die is interconnected with the second sub-core die through hybrid bonding members.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
Embodiments provide a semiconductor structure. The semiconductor structure includes: a substrate including a capacitor structure and a peripheral device structure; a first wiring layer including a first wiring sub-layer and a second wiring sub-layer, first conductive plugs being positioned between the first wiring layer and the peripheral device structures; a second wiring layer being positioned above the capacitor structures and the first wiring layer and second conductive plugs being positioned between the second wiring layer and the substrate, wherein a top surface of the first wiring layer is lower than the top surface of each of the capacitor structures, and heights of the first conductive plugs positioned between the first wiring sub-layer and the second wiring sub-layer are lower than heights of the first conductive plugs positioned between the first wiring sub-layer and the peripheral device structures.
A fabrication method for a semiconductor structure and a semiconductor structure are provided. The fabrication method for a semiconductor structure includes the steps as follows. A substrate is provided; multiple landing pad structures arranged at intervals are formed on an array region of the substrate, first conductive layers are formed on a peripheral region of the substrate, and a sacrificial spacer layer is formed on at least one side of each of the landing pad structures, where a gap exists between two adjacent ones of the landing pad structures; a dielectric layer is formed on the landing pad structures and the first conductive layers, where the dielectric layer covers an opening of the gap; the dielectric layer in the array region is removed and the gap is exposed; and the sacrificial spacer layer is removed to form air gaps.
Disclosed are a semiconductor structure, a memory and a method for operating the memory. The semiconductor structure includes: a substrate; a first gate structure and a second gate structure that are located on a surface of the substrate and have a same thickness smaller than a preset thickness; and a first doped area and a second doped area that are located in the substrate and are respectively located on two sides of the first gate structure. The first gate structure forms a selection transistor with the first and second doped areas; an orthographic projection of the second gate structure on the substrate is at least partially overlapped with the second doped area. The second gate structure and the second doped area form an antifuse bit structure. A breakdown state and a non-breakdown state of the antifuse bit structure are configured to represent different stored data.
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
9.
IMAGING SYSTEM HAVING MICROLENS AND PHOTO-ELECTRIC DEVICE AND MANUFACTURING METHOD
The present disclosure provides an imaging system having a microlens array, a photoelectric conversion device, and a manufacturing method. The microlens array includes a first microlens array and a first light-transmitting part, and the first light-transmitting part is disposed on the first microlens array, the refractive index of the first light-transmitting part is greater than the refractive index of the ambient medium. A first light-transmitting part with a high refractive index is arranged on the first microlens array to change the wavelength of the incident light, so that the light with a shorter wavelength is imaged by the first microlens array to form an object image with a smaller diameter in its image size, thereby increasing the resolution of the imaging system.
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
A memory circuit at least includes a plurality of memory banks, where each of the memory banks includes a first memory sub-bank, a second memory sub-bank and a third memory sub-bank sequentially arranged, the second memory sub-bank including a first memory section and a second memory section, the first memory sub-bank and the second memory section being configured to store upper bytes, and the first memory section and the third memory sub-bank being configured to store lower bytes.
A package substrate is provided. The package substrate includes a body and a plurality of conducive bridges. The body includes an opening region. The plurality of conductive bridges are disposed separately in the opening region, and the plurality of conductive bridges comprise: a first conductive bridge provided with at least two first through holes.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
12.
SEMICONDUCTOR STRUCTURE, ITS READ/WRITE CONTROLLING AND METHOD OF MAKING THE SAME
The disclosed semiconductor structure includes: a substrate and a data line on the substrate, the data line extends along a first direction; the first transistor and the second transistor located on the first transistor's side away from the data line; each of the first transistor and the second transistor includes: a semiconductor column, the semiconductor column is located on a part of the top surface of the data line and extends along the third direction; an isolation structure inside the semiconductor column; along the second direction, the thickness of the isolation structure in different regions in the third direction is different, and the isolation structure runs through the semiconductor columns, and two of the first, the second and the third directions intersect each other. This improves the sensitivity of the second transistor to the change in current in the first transistor while reducing the leakage current in the first transistor.
A semiconductor structure and method of manufacturing are disclosed. The semiconductor structure includes: a substrate having an adjacent array area and a peripheral region; a bit line extending along a first direction, a semiconductor channel extending along a second direction and a word line extending along a third direction located on the array area; the ladder structure in the periphery region includes a plurality of steps each is in contact with either the bit line or the word line; a plurality of conductive columns in contact with the top surfaces of the steps and extending along the direction that is the same direction as the other one of the bit line or the word line; and a support frame located between any two adjacent conductive columns and connected to each step of the latter structure.
The present disclosure discloses a semiconductor structure and a method for fabricating the semiconductor structure. The semiconductor structure includes a plurality of word lines and a plurality of bit lines; ladder structure, including multiple steps, each step includes a first part which extends along the first direction, and a second part which extends along the second direction; a plurality of electrical contact structures, the electrical contact structures is disposed on the top surfaces of a portion of the first part and the second part of the steps, and the electrical contact structures are electrically connected to the word lines or bit lines.
Embodiments provide a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes a substrate, a capacitor structure, a transistor structure, bit lines, and word lines. The capacitor structure is arranged on the substrate, the transistor structure is arranged on a side of the capacitor structure, one of a source and a drain of the transistor structure is electrically connected to the capacitor structure, a gate of the transistor structure is electrically connected to the word lines, and other one of the source and the drain of the transistor structure is electrically connected to the bit lines. A word line isolation structure is arranged between adjacent two of the word lines, and a bit line isolation structure is arranged between adjacent two of the bit lines. A width of the word line isolation structure is not equal to a width of the bit line isolation structure.
A semiconductor structure and a fabricating method are disclosed. The method includes: providing a substrate; forming a bit line contact structure and a bit line on the substrate; the bit line contact structure is located between the bit line and the substrate; performing ion doping treatment on the sidewalls of the lower part of the bit line contact structure to forming a doped region; performing nitridation treatment on the doped region to transform the doped region into a nitride structure.
The disclosed semiconductor structure includes a conductive layer, a channel in the conductive layer. The inner wall of the channel is covered with a first dielectric layer. The thickness of the first dielectric layer is greater at the orifice of the channel than the thickness on the side away from the orifice; the first dielectric layer on the side close the orifice is covered with a second dielectric layer, and the second dielectric layer blocks the orifice; an air gap is formed in the first dielectric layer and the second dielectric layer, and the size of the air gap on the side away from the orifice is larger than the size of the air gap on the side close to the orifice. The present application can effectively reduce the parasitic capacitance of the conductive connection structure, alleviate its RC delay problem, and optimize the storage performance of the memory.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 12/00 - Dynamic random access memory [DRAM] devices
18.
Bump with stepped passivation structure with varying step heights
A semiconductor structure and a method of fabricating the semiconductor structure are disclosed. The semiconductor structure includes: a carrying layer, a barrier layer, a solder layer and an adhesive layer. The barrier layer is located on the surface of the carrying layer, and there are openings in the barrier layer. The barrier layer includes multiple sub-barrier layers in a stack. The multiple sub-barrier layers respectively form a plurality of steps in the opening, and the heights of the plurality of steps decrease sequentially in a direction from outside of the opening to inside of the opening. A solder layer and an adhesive layer are located in the opening, and the adhesive layer covers the solder layer.
A delay measuring circuit includes a control oscillation module with its input terminal connected to its output terminal, which sequentially generates a number of time delay signals with a cycle time T after receiving first enable control signal; a target oscillating module receives a second enabling signal delayed by a first preset threshold than the first enabling signal; after the first preset time T1 is disconnected from the ground terminal/power supply terminal, each stage of the target unit in the target oscillating module connects at the second preset time T2. The level of the target unit turns over at first preset time T1, and target unit maintains logic level for second preset time T2; T1+T2=T/2, and N is an odd integer. So leakage current is reduced and mutual influence of the action current between the adjacent two-level target units are avoided, thus improving ring oscillator performance and reliability.
H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
20.
Three-dimensional Stack Package Structure And Method Making The Same
Disclosed three-dimensional stacked package structure includes: a packaging substrate, having a substrate body, connecting leads, a through-hole penetrating the substrate body, a first pad and a second pad on opposite surfaces of the substrate body. The stacked structure on the first surface of the substrate body includes a second storage block, and a first storage block above the second storage block; the connecting leads include a first lead and a second lead with equal lengths, the first lead is above the package substrate, and one end is electrically connected to the first pad, and the other end is electrically connected to the first storage block. The second lead passes through the through-hole, and one end is electrically connected to the second storage block, the other end is electrically connected to the second pad. The present disclosure reduces the crosstalk between signal lines, thereby reducing signal delay between different storage blocks.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
21.
Anti-fuse circuit and anti-fuse unit programming state verification method
An embodiment of the present disclosure provides an anti-fuse circuit, including: an anti-fuse unit; a programming circuit connected to the anti-fuse unit, and the programming circuit performs programming of the anti-fuse unit according to the programming control signal and the programming signal; the read unit reads the anti-fuse unit to obtain a data signal; the verification control unit controls the electrical connection between the reading unit and the anti-fuse unit according to the verification enable signal and the programming signal of the anti-fuse unit, when verifying the programming state of the anti-fuse unit. When the anti-fuse circuit verifies the programming state of the anti-fuse unit, it controls the electrical connection between the read unit and the anti-fuse unit according to the verification enable signal and the programming signal of the anti-fuse unit, to realize real-time verification of programming status.
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
The present disclosure provides an electronic device and a driving method. The electronic device comprises: a sensitivity amplifier and a voltage adjustment circuit. The sensitivity amplifier includes: a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, and a control circuit. The control circuit is connected to the third node, the fourth node, and a preset voltage terminal. A first control signal terminal responds to the signal of the first control signal terminal to connect the preset voltage terminal and the third node and the fourth node. The preset voltage terminal inputs a preset voltage signal. The electronic device write a preset voltage signal of a suitable size to the sensitivity amplifier through the voltage adjustment circuit, so that the sensitivity amplifier has an appropriate voltage difference between the bit line and the complementary bit line during offset elimination.
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
A semiconductor structure includes: a core device region and an anti-fuse device region, disposed on a same substrate; a first dielectric layer, disposed on the substrate of the core device region and the anti-fuse device region, wherein the first dielectric layer has a first dielectric constant; a second dielectric layer, disposed on the first dielectric layer of the core device region; and a conductive layer, disposed on the second dielectric layer of the core device region and the first dielectric layer of the anti-fuse device region; wherein the second dielectric layer has a dielectric constant larger than the first dielectric constant.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
24.
Data transmission circuit, data transmission method and memory device
A data transmission circuit, method and memory device are provided. A comparison circuit is configured to compare global data with bus data to output a comparison result on whether the number of different bits between the global data and the bus data exceeds a preset threshold; a correction circuit is configured to check and/or correct the global data to generate corrected data; a first data conversion circuit is configured to invert the corrected data and transmit the inverted corrected data to the data bus when exceeding the preset threshold, and transmit the corrected data to the data bus when not exceeding the preset threshold, and the first data conversion circuit is further configured to output a mark signal; and a recovery circuit is configured to transmit data or inverted data on the data bus to a serial-parallel conversion circuit according to a value of the mark signal.
The disclosed semiconductor structure includes a window region, a transistor region, and a step region arranged in a first direction. The transistor region includes a word line region and a window region. The method making the semiconductor structure includes: forming active layers at intervals, forming dummy word line structures in the word line region and the step region covering the active layers at the same layer; forming a first isolation layer which a main body part and an interval part connected together, wherein the main body part is located in the window region, and the interval is located in the word line region and the step region between adjacent dummy word line structures; removing the active layers from the step region, removing the dummy word line structures; and forming a dielectric layer in the step region and the word line region. The embodiments improve the semiconductor structure's performance.
BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY (China)
Inventor
Shao, Guangsu
Xiao, Deyuan
Qiu, Yunsong
Abstract
Embodiments provide a semiconductor structure and a fabrication method thereof, which relate to the field of semiconductor technology. The method for fabricating a semiconductor structure includes: providing a substrate; forming a plurality of active pillars arranged in an array in the substrate; and forming a gate arranged around each of the active pillars, where a projection of the gate on the active pillar covers a channel region of the active pillar. Along a direction perpendicular to the substrate, the gate includes a first conductive layer and a second conductive layer sequentially arranged in a stack, and a work function of the first conductive layer is different from a work function of the second conductive layer.
H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
27.
Method for forming semiconductor structure and a semiconductor
The embodiments of the present application provide a semiconductor structure manufacturing method for forming a semiconductor structure. The method includes: forming a plurality of discrete transistor structures (102) on a substrate (101); forming a dielectric layer (111) covering the transistor structure (102); forming a plurality of metal lines (103) on the top surface of the dielectric layer (111); forming an opening (105) in the gap between two of the plurality of metal lines (103); the insulation layer (106) fills the opening (105), the dielectric constant of the insulating layer (106) is smaller than the dielectric constant of the dielectric layer, and therefore the insulating layer (106) reduces the parasitic capacitance between the metal lines (103) as well as the parasitic capacitance between the metal lines (103) and the transistor structure (102); this method discloses how to form plurality of metal lines in the chip array area, meanwhile keeping the parasitic capacitance between the formed metal lines and other conductive structures small.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
28.
An Apparatus and Method of Generating Chip Select Signals
A method and apparatus for generating a chip select signal include: sampling an external control signal to obtain a first and a second sampling signals; inputting the first sampling signal into a first vector file to generate a power supply control signal; inputting the second sampling signal into a second vector file to generate a chip select control signal; generating a chip select signal based on the power supply control signal and the chip select control signal, which include a high potential, a low potential and a high resistance state, the high potential voltages of the power supply control signal and the chip select control signal are different, and the low potential voltages of the power supply control signal and the chip select control signal are different. The disclosure realizes four different potentials for the chip select signals by applying two vector files.
The disclosed data transmission circuit and a memory include a sense amplifier circuit, a first sub-discharge path, a second sub-discharge path, and a discharge adjustment unit. The sense amplifier circuit generate amplified signals based on two terminals. The first sub-discharge path, in the read state, discharges at the first terminal to the discharge terminal based on the first data line signal; the second sub-discharge path, in reading state, discharges at the second terminal to the discharge terminal based on the discharge adjustment signa. The discharge adjustment unit is electrically connected to the second sub-discharge path and the control signal, but is not connected to the first sub-discharge path, and is used for generating the discharge adjustment signal based on the control signal, to adjust the discharge capacity of the second sub-discharge path. The present disclosure improves the anti-interference ability and data transmission efficiency of the data transmission circuit.
A read/write switching circuit and a memory are provided. The read/write switching circuit includes: a first data line (Ldat) connected to a bit line (BL) through a column select module, a first complementary data line (Ldat#) connected to a complementary bit line through the column select module, a second data line (Gdat) and a second complementary data line (Gdat#), and further includes: a read/write switching module (101) configured to transmit data between the first data line and the second data line and transmit data between the first complementary data line (Ldat#) and the second complementary data line (Gdat#)during read and write operations in response to read and write control signals; and an amplification module (102) connected between the first data line (Ldat) and the first complementary data line (Ldat#) and configured to amplify data of the first data line (Ldat) and data of the first complementary data line (Ldat#).
A semiconductor die, a semiconductor device and a method for forming a semiconductor device are provided. The semiconductor die includes: a substrate including a top surface and a bottom surface; and a plurality of pairs of signal via groups independent of each other, a plurality of signal via groups being arranged in the substrate and spaced apart from each other, two signal via groups in each pair of signal via groups are distributed symmetrically with respect to an axis located on the top surface of the substrate, one of the two signal via groups being distributed in a first region arranged on one side of the axis, and another one of the two signal via groups being distributed in a second region arranged on another side of the axis, the axis being parallel to a first direction or a second direction.
H01L 23/528 - Layout of the interconnection structure
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
32.
Semiconductor structure and method of making the same
The disclosed method provides a solution to the gate-induced drain leakage (GIDL) current in a semiconductor structure. The method includes forming a first trench with a first initial doped region at its bottom, oxidizing the first trench, forming a first oxide layer on the sidewalls of the first trench, and forming a second oxide layer at the bottom of the first trench. The first oxide layer's thickness is greater than the second oxide layer's thickness. The doping element of the first initial doped region prolongs the reduction rate, so that the oxidation rate of the first initial doped region is lower than the oxidation rate of the substrate, thereby forming the first oxide layer. The GIDL of the semiconductor structure can be reduced, the turn-on sensitivity of the semiconductor structure can be improved, and the yield of the semiconductor structure can be increased.
A CMP method includes: provide a substrate with a dielectric layer and a conductive layer, using a mixture of a first polishing liquid and a second polishing liquid to do first CMP polish the substrate placed on the polishing disc to remove the conductive layer covering the upper surface of the intermediate dielectric layer; after the substrate is rinsed with a cleaning solution, the second polishing solution is applied to do second CMP polish on the substrate to remove a part of the dielectric layer, so that the upper surface of the dielectric layer is lower than the upper surface of the conductive layer filled in the groove, so as to ensure that the conductive layer in the groove can protrude from the surface of the dielectric layer. This technique improves product yield for single disc CMP process.
The present application provides a semiconductor structure and a manufacturing method thereof. The method of manufacturing the semiconductor structure includes: providing a base, the base including a substrate and a first dielectric layer on the substrate; forming a through silicon via in the base, the through silicon via penetrating through the first dielectric layer, extending into the substrate, and having a depth less than a thickness of the base; forming an electrically conductive structure in the through silicon via; forming a filling hole in the first dielectric layer and the substrate, the filling hole surrounding the electrically conductive structure, exposing a sidewall of the electrically conductive structure and a part of the substrate, and having a stepwise sidewall; and forming a thermally conductive structure in the filling hole.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/26 - Bombardment with wave or particle radiation
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
35.
Semiconductor memory having discrete active regions and method of making the same
The present application provides a method for fabricating a semiconductor memory structure. The method includes: providing a substrate; forming a stack layer on the substrate, and arranging spacer rows in the stack layer, forming a plurality of active lines, and forming a plurality of transfer pillars in the stack layer; forming a spacer structure outside the transfer pillars, and forming an etching hole; etching the second composite mask layer and the initial semiconductor along the etching hole layer of the active lines to form a plurality of discrete active region masks; and etching the substrate along the active region masks to form a plurality of discrete active regions. The disclosed technique can effectively reduce the preparation difficulty of the active area, improve the LCDU of the active area, and improve the performance of the semiconductor structure.
A semiconductor structure and a method making it are disclosed. The method includes: providing a substrate, and sequentially forming a bitline contact structure and a bitline on the substrate; the bitline includes a connection layer connected to the bitline contact structure. The bitline contact structure and the sidewalls of the connection layer are etched back. A first silicide layer covering the sidewalls of the bitline contact structure, and a second silicide layer covering the sidewalls of the connection layer are formed. This structure can reduce the contact resistance between the bitline contact structure and the bitline, as well as the parasitic capacitance between the bitline contact structure and the adjacent conductive structures, thereby improving the electrical performance and reliability of the semiconductor structure and improving the semiconductor yield.
Embodiments of the present disclosure provide a semiconductor device, comprising a semiconductor layer, extending along the first direction; the semiconductor layer includes a capacitor area facing the capacitor structure, and the capacitor structure includes: a lower electrode layer, the capacitor dielectric layer and the upper electrode layer, sequentially surrounding the sidewalls of the capacitor area extending along the first direction, a part of the lower electrode layer surrounds the sidewalls of the capacitor region, and also surrounds the bottom of the upper electrode layer, the sidewalls extending along the first direction, and the capacitor dielectric layer is located between the upper electrode layer and the lower electrode layer. The disclosed device improves the capacitance of the capacitor structure while improving the integration density of the semiconductor structure.
A semiconductor structure and a preparation method making it are disclosed. The semiconductor structure includes: a substrate, a bit line contact structure, a first epitaxial layer, a bit line and a second epitaxial layer. The structure includes bit line contact holes. The bit line contact structure is disposed in one of the bit line contact holes. The first epitaxial layer is epitaxially grown on the sidewalls of the bit line contact structure. The bit line includes a connection layer connected to the bit line contact structure. The second epitaxial layer is epitaxially grown on the sidewalls of the connection layer. The present disclosure can reduce the contact resistance and parasitic capacitance between the bit line contact structures and the bit lines, thereby improving the electrical performance of the semiconductor structure, thereby raising the reliability and yield of the semiconductor structure.
The present disclosure relates to a semiconductor device and a method of forming the same. The semiconductor device includes: a substrate; a transistor on the substrate, which includes an active cylinder, the active cylinder includes a channel region, a source region and a drain distributed on opposite sides of the channel region, a first doped region located between the source region and the channel region, and a second doped region located between the drain region and the channel region, the first doped impurity region, the source region, the second doped impurity region and the drain region, all these regions include doped ions of the first type, and the doped concentration of the first impurity region is lower than that of the source region impurity concentration, the doped concentration of the second doped region is lower than the doped concentration of the drain region. The present disclosure reduces the band-to-band tunneling effect inside the transistor, thereby reducing the GIDL effect.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A memory structure of an integrated circuit includes a plurality of memory arrays arranged in parallel along the first direction and extending along the second direction, a sensitivity amplifier array extending along the second direction is arranged between every two memory arrays, and the sensitivity amplifier array includes an odd-numbered sensitivity amplifier array and an even-numbered sensitivity amplifier array, the odd-numbered sensitivity amplifier array is connected to an odd-numbered global signal line, and the even-numbered sensitivity amplifier array is connected to the even-numbered global signal line; a first sensitivity amplifier array is arranged between the memory arrays at the edge, and the first sensitivity amplifier array is connected to both the odd-numbered global signal line and the even-numbered global signal line. The present disclosure can improve reliability, yield and test success rate of the memory products.
A method for manufacturing the semiconductor structure includes following operations. A base is provided. A plurality of stack structures spaced apart from each other along a first direction are formed on a surface of the base and a plurality of first isolation layers arranged between the plurality of stack structures are formed, the plurality of stack structures include a plurality of first interlayer dielectric layers, a plurality of initial active layers and a plurality of second interlayer dielectric layers. Portion of each initial active layer is etched to form a first trench in each initial active layer. A plurality of oxide semiconductor layers are formed in a plurality of first trenches. Portions of the plurality of oxide semiconductor layers and remaining portions of the plurality of initial active layers are etched to form a plurality of active structures arranged in an array along the first direction and a second direction.
Provided are a data transmission circuit, a data transmission method, and a storage device. The data transmission circuit includes a controllable delay module and a mode register data processing unit. The controllable delay module is configured to generate a delayed read command in response to a mode register read command. The mode register data processing unit is configured to read setting parameters from a mode register in response to the mode register read command, and to output the setting parameters in response to the delayed read command. Here, a time difference between a start moment of outputting of the setting parameters and a moment when the controllable delay module receives the mode register read command is a first preset threshold.
Embodiments of the present disclosure relate to an electrostatic protection structure and an electrostatic protection circuit. The electrostatic protection structure includes: a SCR structure and a trigger structure; the SCR structure includes: a well region of a second conductivity type and a first well of a first conductivity type region, a first-doped region of the first conductivity type, and a first-doped region of the second conductivity type; the trigger structure includes: a first-doped region of the second conductivity type, a second well region of the first conductivity type, a second-doped region of two conductivity types, a third-doped region of the second conductivity type, a fourth-doped region of the second conductivity type, and a first gate electrode. The electrostatic protection structure weakens the positive feedback of the parasitic transistor in the SCR device, improves the anti-latch capability of the device, realizes stronger protection capability, and enhances the reliability of the circuit.
H02H 9/02 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
44.
Latch performance detection method, device and electronic device
The present disclosure provide latch performance detecting method and a device. The method includes: extracting circuit structure information of a latch, having a transmission gate and a latch unit, an output terminal of the transmission gate is coupled to the input terminal of the latch unit, and the input terminal is coupled to the output terminal of the drive unit corresponding to the latch; the resistance value of the equivalent resistor of the latch is determined based on the circuit structure information, The first terminal of the equivalent resistor is the output terminal of the driving unit, and the second terminal is the input terminal of the latching unit; based on the resistance value of the equivalent resistor, the latching performance is determined. The embodiments of the present disclosure can accurately detect whether the latch is in a metastable state, which helps to improve the performance of the circuit.
A method of manufacturing a semiconductor structure is disclosed. The semiconductor structure includes a transistor area, which includes a first source-drain area and a word line region. The method includes forming an active layer on a substrate, and the active layer of the transistor region includes a plurality of active structures. A dummy word line structure covering the active structure of the same layer is formed in the first source drain region and the word line region. The first isolation layers arranged alternately with the dummy word line structures in the third direction are formed. Then the dummy word line structure is removed. An initial dielectric layer is formed on the surface of the active structure of the first source-drain region and the word line region. An initial word line is formed on the surface of the initial dielectric layer. The initial word line and the initial dielectric layer located in the first source and drain region are removed.
A method for fabricating a semiconductor structure and the device are disclosed. The method includes: providing a first sacrificial layer and semiconductor columns on a substrate; forming an isolation structure, disposed between adjacent stacked structures along the first direction; etching the isolation structure to form a through-hole, the through-hole exposes a part of the surface of the substrate, and also exposes each side of each stacked structure; along the second direction, the width of the bottom of the through-hole is greater than the width of the top of the through-hole, and the second direction is perpendicular to the first direction; the first sacrificial layer exposed by the through-hole is laterally etched, and a part of the first sacrificial layer is removed. A sacrificial layer exposes the top surface and the bottom surface of each semiconductor column. The present disclosure improves the morphology of the semiconductor structure.
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
47.
Semiconductor structure including an electrode cover layer over a capacitor of a dynamic random access memory (DRAM) formed in a substrate, and a contact structure electrically connected to the electrode cover layer, and method of making the same
A semiconductor structure includes: an electrode cover layer; a first conductive structure on the electrode cover layer; a contact structure, including a first and a first contact layer. The first contact layer is in contact with the first conductive structure, the bottom of the second contact layer is in contact with the top of the first contact layer, the width of the first contact layer is greater than the width of the bottom of the second contact layer, the lower surface of the contact structure is not lower than the lower surface of the electrode cover layer, and the resistivity of the first conductive structure is not greater than that of the contact structure and is not greater than that of the electrode cover layer.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H10B 12/00 - Dynamic random access memory [DRAM] devices
48.
Method for manufacturing semiconductor structure with diffusion barrier layers
A method for manufacturing a semiconductor structure includes: a base provided with a contact hole is provided; an initial contact structure including a first diffusion barrier layer, a conductive layer and a second diffusion barrier layer stacked onto one another is formed on the base, the first diffusion barrier layer conformably covering the contact hole and covering part of a top surface of the base, the conductive layer covering first diffusion barrier layer and being filled in unoccupied space in the contact hole, the second diffusion barrier layer covering a side of the conductive layer away from first diffusion barrier layer, the initial contact structure outside the contact hole being provided with a groove exposing side walls of conductive layer and second diffusion barrier layer; a third diffusion barrier layer is formed on a side wall of initial contact structure exposed by the groove to obtain a target contact structure.
The present application relates to the technical field of semiconductor manufacturing equipment, and provides a dust collection device. The dust collection device includes: an air inlet channel, a dust settling channel extending along a preset path, an airflow rotation channel surrounding the settling channel, an air outlet channel and a collection chamber, where one end of the airflow rotation channel is communicated with the dust settling channel, and the other end of the airflow rotation channel is communicated with the air outlet channel; an upstream end of the dust settling channel is communicated with the air inlet channel, and a downstream end of the dust settling channel is communicated with the collection chamber; and the height of the dust settling channel gradually decreases in an extension direction of the preset path. Dust in the airflow rotation channel can easily settle under the action of a centrifugal force when moving along the airflow rotation channel, and the other end of the airflow rotation channel is communicated with the air outlet channel to discharge air.
B01D 45/16 - Separating dispersed particles from gases or vapours by gravity, inertia, or centrifugal forces by centrifugal forces generated by the winding course of the gas stream
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
50.
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME
The method of forming the semiconductor structure comprises operations of: forming a substrate, and forming active regions located above the substrate and arranged at intervals in a first direction parallel to a top face of the substrate; and performing a modifying treatment to a part of the substrate below the active regions from at least one side face of the substrate, to form bit lines each of which extends in the first direction and is electrically connected with a plurality of the active regions arranged at intervals in the first direction
The disclosed anti-fuse circuit includes: an anti-fuse unit; a programming circuit, configured to program the anti-fuse unit according to a programming signal; a verification unit, including a first input terminal, a second input terminal and a first output terminal, the programming signal of the anti-fuse unit is the input signal of the first input terminal, and the data signal stored in the anti-fuse unit is the input signal of the second input terminal. The verification unit verifies the programming state of the anti-fuse unit according to the input signals of the first input terminal and the second input terminal, and the first output terminal outputs a verification signal. The anti-fuse circuit does not need to read out the data signal of the anti-fuse unit to a test machine followed by verifying the programming state of the anti-fuse unit. This anti-fuse circuit saves time and enables high verification accuracy.
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
52.
Semiconductor memory structure with L-shaped channel and method for manufacturing the same
The semiconductor structure comprises: semiconductor channels, first gate structures, second gate structures and bit lines. Each semiconductor channel extends in a third direction and has an L-shaped cross-section in a plane perpendicular to the third direction, each of the semiconductor channels comprises a first L-shaped sidewall and a second L-shaped sidewall which are opposite to each other and extend in the third direction, the first L-shaped sidewall comprises a first face extending in a first direction and a second face extending in a second direction. Each first gate structure is in contact with the first face. Each second gate structures is in contact with the second face, each first gate structure is in contact with the respective second gate structure. The bit lines extend in the second direction and are located on a side of each of the semiconductor channels in the third direction.
A memory is provided. The memory includes: a storage array that includes multiple bit lines, each of the multiple bit lines is connected to multiple storage cells in the storage array; multiple column select signal units that are connected to sensitive amplifiers, the sensitive amplifiers and the multiple bit lines are disposed in one-to-one correspondence; local data buses that are divided into local data buses O and local data buses E, adjacent bit lines are electrically connected to a respective local data bus O and a respective local data bus E, respectively, through a respective sensitive amplifier and a respective column select signal unit; and a first error checking and correcting unit and a second error checking and correcting unit that are configured to check and correct errors of data.
Provided in the embodiments of the present disclosure are a delay control circuit and method, and a semiconductor memory. The delay control circuit includes a clock circuit and a delay circuit. The clock circuit is configured to receive a temperature adjustment signal, and generate a first clock signal according to the temperature adjustment signal; and a clock cycle of the first clock signal is a preset value. The delay circuit is configured to receive the first clock signal and an initial command signal, and perform delay processing on the initial command signal according to the first clock signal, so as to obtain a target command signal; and a time interval between the target command signal and the initial command signal meets a preset timing condition.
G11C 11/40 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
A control circuit is provided, including a random module and an output module. A first input terminal of the random module receives a refresh count signal, a second input terminal receives random data, and a control terminal is connected to an output terminal of the output module. The random module processes the refresh count signal and the random data based on a row hammer refresh (RHR) signal output by the output module to obtain and output a random signal. A first input terminal of the output module receives the refresh count signal, a second input terminal is connected to an output terminal of the random module. The output module generates and outputs the RHR signal according to the random signal and the refresh count signal.
A counting control circuit includes a logic control circuit and a counting statistic circuit, an output terminal of the logic control circuit is connected to a clock terminal of the counting statistic circuit. The logic control circuit is configured to receive a first clock signal and a first identification signal, and generate a counting clock signal according to the first clock signal under a control of the first identification signal. The counting statistic circuit is configured to receive the counting clock signal, count according to the counting clock signal, and generate the first identification signal which indicates a generation of a command signal for performing a first operation, here, the first identification signal is in a valid state when a counting value meets a preset condition.
A delay control circuit includes a delay circuit. The delay circuit is configured to receive an initial command signal, and to perform a non-clock-triggered delay processing on the initial command signal to obtain a target command signal. The initial command signal is generated based on an ECS operation mode, a time interval between the target command signal and the initial command signal meets a preset timing condition, the initial command signal is used for performing a first operation and the target command signal is used for performing a second operation.
A semiconductor structure and a manufacturing method are provided. The semiconductor structure includes: a substrate having a bit line extending along a first direction; a semiconductor channel located on the bit line; a semiconductor doping layer located on the side of the bit line, wherein the top surface of the semiconductor doping layer is connected to the semiconductor channel contact; a word line extending in the second direction, encircling part of the semiconductor channel, and the bottom surface of the word line is higher than the top surface of the bit line; a word line dielectric layer located between the word line and the semiconductor channel; an isolation layer located between the word line and the bit line and between the word line and the semiconductor doping layer. The device and method improve the prior weak electrical conductivity between the bit line structure and the active structure.
Provided are a semiconductor structure and a method for forming the same. The method for forming a semiconductor structure includes the following operations. A stack is formed on a substrate. The stack includes interlayer insulating layers and sacrifice layers alternately stacked in a first direction. The stack includes a plurality of storage regions arranged at intervals in a second direction. Part of the sacrifice layers of storage regions is removed to form first trenches between adjacent interlayer insulating layers. Transistor structures are formed in the first trenches. The transistor structures include gate layers covering inner walls of the first trenches and active structures located in the gate layers. A word line extending in the second direction is formed. The word line envelops gate layers of the plurality of storage regions arranged at intervals in the second direction.
The application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate and multiple Word Lines (WLs), the multiple WLs extend along a first direction and are arranged on the substrate at intervals along a second direction, a WL isolation structure is arranged between every two adjacent WLs and includes at least a first isolation layer and a second isolation layer stacked along the second direction and made of different materials, and the first direction and the second direction intersect with each other.
The present disclosure relates to the technical field of semiconductors and provides a semiconductor structure, a method of forming same, and a memory. The method of forming a semiconductor structure of the present disclosure includes: providing a carrier board; forming a chipset on one side of the carrier board, where the chipset includes multiple chips stacked in a direction perpendicular to the carrier board; where among multiple chips, an orthographic projection of a chip closer to the carrier board on the carrier board is within an orthographic projection of a chip farthest from the carrier board on the carrier board; forming an insulating dielectric layer covering the chipset; and performing a grinding process to expose a predetermined surface of the chip farthest from the carrier board outside the insulating dielectric layer.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A memory includes a substrate, a control circuit layer located in the substrate, and at least two memory structure layers. The control circuit layer includes at least part of control circuits of the memory. The at least two memory structure layers are sequentially stacked on the control circuit layer. Each memory structure layer includes multiple memory blocks arranged in an array. The memory block includes multiple parallel Word Lines (WLs) extending in a first direction. The first direction is parallel to a surface of the substrate. An opening is provided between adjacent memory blocks located in the same memory structure layer. The openings located in different memory structure layers go through each other. WLs in the at least one memory structure layer are connected to the control circuit layer through the openings that go through each other.
A semiconductor structure includes: a high-speed circuit module including a clock signal with a frequency greater than a first threshold; a first conductive metal layer including power conductive wires extending along a first direction and arranged at intervals, and the power conductive wires being electrically connected with the high-speed circuit module; and a redistribution layer located above the first conductive metal layer and including power pads and electrical wires connected with the power pads, in which the power pads are located at one side of the high-speed circuit module, a projection of the power pads does not overlap with that of the high-speed circuit module, the electrical wires include a first electrical wire region where the electrical wires are repeatedly bent, the first electrical wire region at least partially covers the high-speed circuit module, and the electrical wires are used for electrically connecting the power conductive wires and power pads.
H01L 23/528 - Layout of the interconnection structure
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 12/00 - Dynamic random access memory [DRAM] devices
64.
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME
A method for manufacturing a semiconductor structure includes: forming first base which includes first substrate and active areas arranged in an array along first direction and second direction in first substrate, word lines being disposed in first base, extending along second direction and covering at least opposite sides of each active area; forming charge storage structures electrically connected with first ends of active areas on first base; forming second base which includes second substrate and bit lines disposed in second substrate, bit lines extending along first direction; connecting first base and second base by using a first surface of first base away from charge storage structures and a second surface of second base having structures of bit lines as connection surfaces, bit lines being electrically connected with second ends of active areas, and each first end being disposed opposite to a corresponding second end.
The present disclosure provides a semiconductor package structure, relating to the technical field of semiconductors. The semiconductor package structure includes: a substrate; and at least one chip stack structure provided on the substrate, where the at least one chip stack structures include a plurality of first chips vertically stacked, each of the first chips includes a first conductive plug set, a connection layer is provided between two adjacent first chips, a wire structure is provided in the connection layer, the wire structure is electrically connected to the first conductive plug sets in two first chips adjacent to the wire structure, projections of two first conductive plug sets electrically connected to a same wire structure on the substrate are staggered from each other, and the first conductive plug sets in the plurality of first chips are connected in series through the wire structures to form an inductor structure.
The present application discloses a semiconductor structure and a method for fabrication. This technique improves the stability of the bit line structure. The semiconductor structure is formed in a bit line trench in a substrate, it includes: a bit line conductive layer formed in the bit line trench, and the top surface of the bit line conductive layer is higher the top surface of the substrate; a barrier layer formed at least partially between the bit line conductive layer and the inner wall of the bit line trench; and an isolation layer formed on top of the bit line conductive layer.
A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The manufacturing method includes the following operations. A substrate is provided, and a first groove and a second groove are formed in the substrate, each of the first groove and the second groove having a depth in a first direction. The first groove includes multiple first sub-grooves arranged in the first direction, the second groove includes multiple second sub-grooves arranged in the first direction, and sidewalls of the first sub-grooves and sidewalls of the second sub-grooves are convex outwards. Word lines protruding away from the first groove each are formed at an interface of adjacent first sub-grooves. First source-drain layers formed on the sidewalls of the first sub-grooves, and second source-drain layers protruding away from the second groove each are formed at an interface of adjacent second sub-grooves.
A semiconductor structure includes a plurality of dies. The plurality of dies are stacked sequentially along a first direction. The first direction is a direction perpendicular to a plane of the dies. Each of the dies includes a base and n first conductive structures penetrating the base along the first direction, where n is greater than or equal to 2. In at least one group of the corresponding first conductive structures in the dies, projections of the group of the first conductive structures in two adjacent layers of the dies along the first direction are not overlapped with each other.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
69.
DATA SAMPLING CIRCUIT, DELAY DETECTION CIRCUIT AND MEMORY
A data sampling circuit includes a first signal path and a second signal path. The first signal path is arranged to receive a first signal, process and transmit the first signal. The first signal path has a first delay, and the first delay includes a first physical delay and a compensation delay. The second signal path is arranged to receive a second signal, receive processed first signal from the first signal path, and sample the second signal according to the processed first signal.
The present disclosure provides a semiconductor structure including: a channel on a semiconductor substrate for a first transistor; first bit lines are in contact with the first doped region arranged along the first direction; first word lines surround the channel region; the gate conductive layer and the second doped region, the channel layer arranged around the outer side of the gate conductive layer; the first semiconductor doped layer and the second semiconductor doped layer arranged on the outer side of the channel layer, so the channel layer and the gate conductive layer constitute the second transistor. The second bit line is in contact with either the first semiconductor doped layer or the second semiconductor doped layer; the second word line is in contact with the other one of the first semiconductor or the second semiconductor doped layer. The structure forms a new 2T0C DRAM structure.
A method for manufacturing a semiconductor structure includes: providing a substrate including a transistor structure; forming a laminated structure on the substrate, the laminated structure including a dielectric layer and an insulating layer which are sequentially stacked in a thickness direction of the substrate, and the insulating layer being arranged on a side, away from the substrate, of the dielectric layer; forming a through hole penetrating through the laminated structure in the laminated structure to expose a source/drain of the transistor structure; and etching at least part of a side wall of the through hole located in the dielectric layer to form a conductive hole in the insulating layer and the dielectric layer. An aperture size of a medial part of the conductive hole is greater than an aperture size of each of both ends of the conductive hole.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
72.
Memory and method of operation with dummy and loaded route
A memory includes: a storage cell array; a write driver; and a first column decoder, the first column selection line includes a dummy route and a loaded route, the dummy route is coupled to the first column decoder and the loaded route and transmits a first column selection signal to the loaded route; the loaded route is coupled to a first storage cell area and transmits the first column selection signal to the first storage cell area; the first column selection signal selects a storage cell column, on which a write operation is performed, from the first storage cell area. A transmission direction of a data signal to be written transmitted by the write driver is identical to a transmission direction of the first column selection signal transmitted via the loaded route.
A semiconductor structure includes: multiple active areas arranged in an array along intersecting first and second directions and spaced apart by an isolation structure; a bit line select structure comprising a first gate, a second gate, a third gate and a fourth gate located on four mutually adjacent active areas, and at least one connecting line located on the isolation structure; and multiple contact structures, each of the multiple contact structures being located on one side, close to the connecting line, of both sides of a respective gate and connected with a respective one of the multiple active areas, and an orthographic projection of the contact structure on a plane where the active area is located being at a position, close to the connecting line, in the active area.
A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure includes a substrate, a chip stack disposed on the substrate through a plurality of first conductive structures. Each of the plurality of the first conductive structures includes a first conductive bump, and the first conductive bump includes at least one concave surface. Concave surfaces of adjacent first conductive bumps are disposed facing each other.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
75.
SEMICONDUCTOR STRUCTURE AND FORMING METHOD AND OPERATING METHOD THEREFOR
A semiconductor structure includes: a substrate; a memory array, including a plurality of storage cells arranged in a first direction and a second direction, where each storage cell includes an active pillar including a first channel region and a second channel region that are arranged at intervals in a third direction; a word line structure, including a first word line extending in the first direction and a second word line extending in the second direction, where the first word line covers the first channel regions of the active pillars of the plurality of storage cells that are arranged at intervals in the first direction, and the second word line covers the second channel regions of the active pillars of the plurality of storage cells that are arranged at intervals in the second direction; and a common bit line, electrically connected to all the storage cells in the memory array.
The present disclosure provides a single-loop memory device, a double-loop memory device, and a ZQ calibration method. The single-loop memory device includes: a master chip and a plurality of slave chips each provided with a first transmission terminal and a second transmission terminal, where the second transmission terminal of the master chip is connected to the first transmission terminal of the slave chip of a first stage, and the second transmission terminal of the slave chip of each stage is connected to the first transmission terminal of the slave chip of a next stage; and the master chip is provided with a first signal receiver, and the slave chip is provided with a second signal receiver.
A semiconductor structure includes a base, a chip stack located on the base, and first conductive structures. The chip stack includes chips stacked in sequence in a direction perpendicular to a plane of the base, a chip includes first and second sub-portions, a first surface of the first sub-portion is flush with that of the second sub-portion, a second surface of the first sub-portion protrudes from that of the second sub-portion, and the first and second surfaces are oppositely arranged. A first conductive structure includes a first conductive bump and a first through-silicon via, the first conductive bump is located between first sub-portions of two adjacent chips, the first through-silicon via penetrates through the first sub-portion in the direction perpendicular to the plane of the base and is connected to the first conductive bump, and the materials of the first conductive bump and the first through-silicon via are same.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A memory includes: a memory cell array; a first column decoder, coupled to the memory cell array and configured to perform a write operation on the memory cell array; a second column decoder, coupled to the memory cell array and configured to perform a read operation on the memory cell array; and a read amplifier, the read amplifier and the second column decoder being located on two opposite sides of the memory cell array, the read amplifier being coupled to the memory cell array and configured to receive read data information output by the memory cell array based on the read operation. The read amplifier, the first column decoder, the memory cell array and the second column decoder are arranged in a first direction, and the first column decoder and the second column decoder are located on two opposite sides of the memory cell array.
A transistor includes a source structure, a trench, a drain structure, and a gate structure. The trench sequentially has first and second end faces which are arranged opposite in a first direction. The source structure extends from the first end face in a second direction. The source structure sequentially has third and fourth end faces which are arranged opposite in the first direction. The fourth end face is connected to the first end face. The drain structure extends from the second end face in a direction opposite to the second direction. The drain structure sequentially has fifth and sixth end faces which are arranged opposite in the first direction. The fifth end face is connected to the second end face. The second direction intersects the first direction. The gate structure surrounds the trench and is connected to the fourth and the fifth end face.
A semiconductor structure, a method for preparing the semiconductor structure and a memory are provided. The method includes: providing a wafer in which multiple conductive pillars are formed; inverting the wafer and performing etching on a back plane of the wafer to expose each conductive pillar from the back plane of the wafer, and lengths of the multiple conductive pillars exposed to the back plane are different; depositing an insulation layer on the back plane of the wafer and the conductive pillars, and depositing a filling layer on the insulation layer, the filling layer completely covering back ends of the multiple conductive pillars; and performing polishing on the filling layer and back ends of a part of the conductive pillars, until a back end of each conductive pillar is exposed and the back ends of the multiple conductive pillars are flush with a back plane of the filling layer.
A data receiving circuit includes a decision feedback equalization circuit, configured to perform decision feedback equalization on a receive circuit based on a feedback signal to adjust a first output signal and a second output signal, where the feedback signal is obtained based on previously received data, the decision feedback equalization circuit responds to a first control signal group and a second control signal group to change an adjustment capability, the first control signal group corresponds to one data port corresponding to a data signal, and the second control signal group corresponds to all data ports. The capability of the decision feedback equalization circuit can be controlled to adjust the first output signal and the second output signal, where the adjustment capability has a wide adjustable range, to reduce impact of intersymbol interference of received data on the data receiving circuit.
Embodiments provide a method for fabricating a semiconductor structure and a semiconductor structure. The method includes: providing a substrate; forming, on a surface of the substrate, stacked structures arranged at intervals in a first direction and a first isolation layer located between adjacent stacked structures, the stacked structure including a first interlayer dielectric layer, an initial active layer, and a second interlayer dielectric layer; etching a portion of the initial active layer to form a first trench; forming a metal conductive layer in the first trench, the metal conductive layer being in contact connection with the remained initial active layer; and etching a portion of the metal conductive layer to form lower electrode structures arranged in an array in the first direction and a second direction, where the first direction is perpendicular to the surface of the substrate, and the second direction is parallel to the surface of the substrate.
A write leveling circuit applied to a memory includes a write signal generation unit and a sampling unit. The write signal generation unit is configured to receive a first clock signal and a first indication signal, and delay a first write signal according to the first clock signal, the first indication signal and a specified bit in the first indication signal, and output a second write signal. The sampling unit is connected to the write signal generation unit, and configured to receive a first data strobe signal and the second write signal, and output a second sampling signal according to received first Data Strobe Signal (DQS) and the second write signal.
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
84.
SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREFOR
A semiconductor structure and a fabrication method are provided. The semiconductor structure includes: a substrate, where a plurality of capacitor contact structures arranged at intervals are formed on the substrate; an isolation structure, where the isolation structure is disposed on the substrate and between adjacent capacitor contact structures, and a top surface of the isolation structure is not higher than a top surface of each capacitor contact structure; and an isolation groove, where the isolation groove extends from the top surface of the isolation structure to an interior of the isolation structure, and a spacing is provided between the isolation groove and the capacitor contact structure.
A semiconductor structure includes a substrate and a word line structure. The substrate includes an array region and a peripheral region. The word line structure includes a first conductive layer disposed on the substrate, and the first conductive layer penetrates the array region and extends to the peripheral region in a first direction. In a normal direction of the substrate, a height of the first conductive layer on a surface of the peripheral region is higher than a height of the first conductive layer on a surface of the array region.
The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a word line, and at least two dielectric layers. The word line is arranged in the substrate; the at least two dielectric layers are located between the word line and the substrate and have different dielectric constants.
A semiconductor structure includes: a logic device including a first power line and a second power line located on a same wiring layer, extending along a first direction and arranged in parallel along a second direction, the first direction and the second direction intersecting with each other and being parallel to a plane where the wiring layer is located; and a switch driving device, the switch driving device and the logic device being arranged in parallel along the first direction, the switch driving device including a first input line and a first output line located on the same wiring layer as the first power line, extending along the first direction and arranged in parallel along the second direction, the first output line being connected with the first power line or the second power line.
H03K 19/0948 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET using CMOS
88.
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME
A semiconductor structure includes a substrate and a word line (WL) structure. The WL structure includes: a work function stacking structure located in the substrate, where the work function stacking structure includes multiple sequentially and alternately stacked first work function layers and second work function layers, and a work function of the first work function layer is greater than a work function of the second work function layer; a WL conductive layer located in the substrate, and located on an upper surface of the work function stacking structure; and a gate oxide layer located between the work function stacking structure and the substrate as well as between the WL conductive layer and the substrate.
A clock system and a memory are disclosed. The clock system includes a system on chip (SoC) configured to generate a first oscillation signal, a second oscillation signal, a third oscillation signal and a fourth oscillation signal of a same frequency and amplitude. Further, the clock system includes a memory chip configured to output a data signal based on signal edges of the first oscillation signal, the second oscillation signal, the third oscillation signal and the fourth oscillation signal, and output a command/address signal based on the signal edges of the first oscillation signal and the third oscillation signal. The signal edges are rising edges or falling edges.
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
90.
Semiconductor structure, method for manufacturing same, and semiconductor memory
A semiconductor structure includes: a substrate; and a plurality of device structures, a plurality of bit line structures and a plurality of word line structures formed on the substrate. The device structure extends in a first direction, and the word line structure extends in a second direction, and the bit line structure extends in a third direction. The device structure includes a capacitor area and an active area. The bit line structure is electrically connected to the active areas arranged in the third direction. Herein, at least some of the bit line structures are formed with air gaps around them.
The method for manufacturing the semiconductor structure includes: providing a substrate, and forming contact holes in the substrate; depositing a metal at a bottom of each contact hole, and performing a reverse sputtering treatment to form a metal layer; in the reverse sputtering treatment, metal atoms or metal ions are sputtered onto at least a part of a side wall of each contact hole; performing a annealing treatment, to cause the substrate reacts with the metal layer to form a metal silicide layer.
The disclosed driver and memory include: a phase driver that receives a first voltage signal, configured to output a second phase signal according to the first phase signal and the first voltage signal; a complementary phase driver includes: a first inverter for generating a complementary inverted phase signal based on a first complementary phase signal, the first phase signal and the first complementary phase signal are mutually inverted; a second inverter for receiving an output signal of the first inverter and a second voltage signal, the voltage value of the second voltage signal is smaller than that of the first voltage signal, and the second inverter is configured to be based on the first complementary inverted phase signal, and the second voltage signal outputs a second complementary phase signal. The driver of the embodiment provides the second phase signal and the second complementary phase signal.
A semiconductor structure includes a substrate and a stack structure located on the substrate. The stack structure includes a plurality of memory units arranged at intervals in a first direction. Each memory unit includes a transistor structure. The transistor structure includes an active structure and a gate layer. At least part of the active structure is distributed around a periphery of part of the gate layer, and the projection of the active structure on a top surface of the substrate is in the shape of a U which opens toward a second direction. Both the first direction and the second direction are parallel to the top surface of the substrate, and the first direction intersects with the second direction. A method for forming the semiconductor structure is also provided.
A semiconductor structure and a memory are provided. The semiconductor structure includes multiple active regions, a column selector and multiple bit lines. The column selector includes a first gate, a second gate, a third gate, a fourth gate and a connection line. The first gate and the second gate intersect at a first node, the third gate and the fourth gate intersect at the second node, and the connection line connects the first node and the second node. Each of the multiple bit lines includes a first portion, a second portion and a connection portion. Each of the multiple bit lines is connected to a respective one of the multiple active regions, the active regions connected to different bit lines among the multiple bit lines are different.
The present disclosure provides a memory and a memory system thereof, relating to the technical field of semiconductors. The memory includes: memory sections and a plurality of bit lines (BLs) corresponding to a same memory section; sense amplifiers electrically connected to the plurality of BLs in one-to-one correspondence, where two of the sense amplifiers corresponding to adjacent two of the BLs are located on two sides of the memory section; and a first error checking and correction (ECC) module and a second ECC module, where one of two adjacent sense amplifiers located on a same side of the memory section is electrically connected to the first ECC module, and the other one of the two adjacent sense amplifiers located on the same side of the memory section is electrically connected to the second ECC module.
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method of a semiconductor structure includes: providing a substrate, and forming a stacked structure on the substrate; forming a hard mask layer on the stacked structure, where the hard mask layer includes a first etched window, and the first etched window exposes part of a top surface of the stacked structure; forming a photoresist layer, where the photoresist layer covers the first etched window; and trimming the photoresist layer for a plurality of times, after each trimming of the photoresist layer, etching the stacked structure according to a trimmed photoresist layer, and forming a plurality of steps in the stacked structure along a direction away from the substrate.
A semiconductor structure, a method for forming a semiconductor structure, and a memory are provided. The method for forming the semiconductor structure in the disclosure includes: providing a base, the base including a substrate and an insulating dielectric layer, the substrate including a plurality of first trenches spaced apart from each other in a first direction, and the insulating dielectric layer being filled in each of the plurality of first trenches; patterning and etching the base to form a plurality of second trenches spaced apart from each other in a second direction, the second direction intersecting with the first direction; forming a word line structure in each of the plurality of second trenches; forming an air gap between each two adjacent word line structures of a plurality of word line structures; and sealing the air gap.
A failure analysis method includes: obtaining failure data of IO channels in a target chip particle, the target chip particle including a plurality of physical modules, a number of the plurality of physical modules is M, and each physical module including a plurality of IO channels, wherein M is a positive integer greater than or equal to 2; splitting the failure data to form M groups of module failure data corresponding to the physical modules; determining a partial failure type of each physical module according to each module failure data; and determining a storage failure type of the target chip particle according to the partial failure type of each physical module.
Embodiments relate to the field of semiconductor, and disclose a semiconductor device layout structure, a method for forming the same, and a test system. The semiconductor device layout structure includes: an active layout layer including active pattern regions arranged along a first direction; device layout sublayers, where each of the device layout sublayer includes a gate pattern region; and a plurality of contact plug sets, where each of the contact plug sets includes a source contact plug and a drain contact plug. Along the first direction, in adjacent two gate pattern regions of the device layout sublayers, a pitch between the latter gate pattern region and the corresponding source contact plug and/or the drain contact plug and a pitch between the former gate pattern region and the corresponding source contact plug and/or the drain contact plug form an arithmetic progression.
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
100.
SEMICONDUCTOR STRUCTURE, FORMING METHOD OF SAME AND MEMORY
A semiconductor structure includes a base, a chipset and a heat conduction adjusting layer. The chipset is disposed at one side of the base and includes multiple chip units arranged at intervals along a direction perpendicular to the base. Each of the chip units includes a substrate and a circuit module disposed on a surface of the substrate. The substrate includes a circuit interconnection region and a non-circuit interconnection region distributed adjacently. The circuit module is disposed on a surface of the circuit interconnection region, and adjacent chip units are electrically connected by the circuit module. The heat conduction adjusting layer is in contact with at least one of the substrates for reducing the difference of heat conduction rates between surfaces of the substrates.
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