Toshiba Corporation

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        Patent 12,171
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[Owner] Toshiba Corporation 12,246
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New (last 4 weeks) 63
2025 April (MTD) 30
2025 March 173
2025 February 64
2025 January 63
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IPC Class
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate 540
H01L 29/66 - Types of semiconductor device 462
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions 414
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched 321
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form 309
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09 - Scientific and electric apparatus and instruments 64
42 - Scientific, technological and industrial services, research and design 27
07 - Machines and machine tools 24
11 - Environmental control apparatus 23
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1.

COMBINED CYCLE POWER GENERATION FACILITY

      
Application Number 19005225
Status Pending
Filing Date 2024-12-30
First Publication Date 2025-04-24
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ENERGY SYSTEMS & SOLUTIONS CORPORATION (Japan)
Inventor
  • Okuyama, Tomomi
  • Shimada, Hideaki
  • Itoh, Masao
  • Morisawa, Yuichi
  • Kasuya, Hiroki
  • Hirayama, Ryu
  • Tada, Kojiro

Abstract

A combined cycle power generation facility of an embodiment includes a first heat recovery steam generator including a high-pressure steam generation part using an exhaust gas of a gas turbine and a reheat part; a high-pressure turbine to which steam is introduced from the high-pressure steam generation part; a combustor which combusts hydrogen and oxygen; a reheat steam pipe connecting the high-pressure turbine and the combustor with the reheat part interposed therebetween; an oxygen-hydrogen combustion turbine to which steam is introduced from the combustor; a second heat recovery steam generator including a steam generation part using an exhaust gas of the oxygen-hydrogen combustion turbine; a low-pressure turbine to which steam is introduced from the steam generation part; and a condenser which steam is introduced from the low-pressure turbine.

IPC Classes  ?

  • F01K 23/10 - Plants characterised by more than one engine delivering power external to the plant, the engines being driven by different fluids the engine cycles being thermally coupled combustion heat from one cycle heating the fluid in another cycle with exhaust fluid of one cycle heating the fluid in another cycle
  • F01K 7/16 - Steam engine plants characterised by the use of specific types of enginePlants or engines characterised by their use of special steam systems, cycles or processesControl means specially adapted for such systems, cycles or processesUse of withdrawn or exhaust steam for feed-water heating the engines being only of turbine type
  • F22B 1/18 - Methods of steam generation characterised by form of heating method by exploitation of the heat content of hot heat carriers the heat carrier being a hot gas, e.g. waste gas such as exhaust gas of internal-combustion engines

2.

OPTICAL INSPECTION APPARATUS, OPTICAL INSPECTION METHOD, AND NON-TRANSITORY STORAGE MEDIUM STORING OPTICAL INSPECTION PROGRAM

      
Application Number 18773997
Status Pending
Filing Date 2024-07-16
First Publication Date 2025-04-24
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Okano, Hideaki
  • Ohno, Hiroshi
  • Kamikawa, Takahiro
  • Kano, Hiroya
  • Takanashi, Kenta

Abstract

According to an embodiment, an optical inspection apparatus includes a controller. The controller is configured to: project first modulation pattern lights having an intensity modulation pattern, in which an extending direction of an end portion of an object and a modulation direction are substantially parallel, onto the object; acquire a first image group by imaging the object onto which the first modulation pattern lights are projected; and generate, by a peculiar scattering extraction process, a first peculiar light scattering image that is able to include an image of a peculiar area that is located at the end portion of the object or in an area inside the end portion, is extracted based on the first image group, and causes peculiar light scattering due to the first modulation pattern lights.

IPC Classes  ?

  • G01N 21/88 - Investigating the presence of flaws, defects or contamination
  • G01N 21/47 - Scattering, i.e. diffuse reflection

3.

STEAM TURBINE POWER GENERATION FACILITY USING OXYGEN-HYDROGEN COMBUSTION

      
Application Number 19005274
Status Pending
Filing Date 2024-12-30
First Publication Date 2025-04-24
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ENERGY SYSTEMS & SOLUTIONS CORPORATION (Japan)
Inventor
  • Tada, Kojiro
  • Inoue, Shota
  • Hirayama, Ryu

Abstract

A steam turbine power generation facility in an embodiment includes: a steam generator that generates steam by heat of reaction generated by combustion of oxygen and hydrogen; a high-pressure steam turbine into which steam is introduced from the steam generator; a combustor into which steam discharged from the high-pressure steam turbine is introduced and that combusts oxygen and hydrogen to reheat the introduced steam; a low-pressure steam turbine into which steam discharged from the combustor is introduced and into which steam discharged from the high-pressure turbine is introduced as a cooling medium; and a condenser that condenses steam discharged from the low-pressure steam turbine.

IPC Classes  ?

  • F01K 25/00 - Plants or engines characterised by use of special working fluids, not otherwise provided forPlants operating in closed cycles and not otherwise provided for
  • F01K 7/22 - Steam engine plants characterised by the use of specific types of enginePlants or engines characterised by their use of special steam systems, cycles or processesControl means specially adapted for such systems, cycles or processesUse of withdrawn or exhaust steam for feed-water heating the engines being only of turbine type the turbines having inter-stage steam heating
  • F01K 7/38 - Steam engine plants characterised by the use of specific types of enginePlants or engines characterised by their use of special steam systems, cycles or processesControl means specially adapted for such systems, cycles or processesUse of withdrawn or exhaust steam for feed-water heating the engines being of extraction or non-condensing typeUse of steam for feed-water heating the engines being of turbine type

4.

Magnetic disk device

      
Application Number 18600867
Grant Number 12283294
Status In Force
Filing Date 2024-03-11
First Publication Date 2025-04-22
Grant Date 2025-04-22
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Watanabe, Toru

Abstract

According to one embodiment, a magnetic disk device includes a magnetic disk and a magnetic head. The magnetic disk includes a data area on/from which data can be recorded/reproduced. The magnetic head records data on the data area and reproduces data from the data area. An outer edge of the data area includes first outer edge, second outer edge positioned on the further inner circumferential side of the magnetic disk relatively to the first outer edge, and third outer edges each connecting between the first outer edge and the second outer edge. The outer edge of the data area incudes concave parts made inwardly concave toward the inner circumferential side of the magnetic disk at not less than part thereof.

IPC Classes  ?

  • G11B 5/54 - Disposition or mounting of heads relative to record carriers with provision for moving the head into, or out of, its operative position or across tracks
  • G11B 5/187 - Structure or manufacture of the surface of the head in physical contact with, or immediately adjacent to, the recording mediumPole piecesGap features
  • G11B 5/55 - Track change, selection, or acquisition by displacement of the head
  • G11B 33/14 - Reducing influence of physical parameters, e.g. temperature change, moisture, dust

5.

METHOD OF ANALYZING ISOPROPYLPHENYL PHOSPHATE

      
Application Number 18789830
Status Pending
Filing Date 2024-07-31
First Publication Date 2025-04-17
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Kondo, Asato
  • Oki, Mitsuhiro
  • Kuboki, Takashi

Abstract

A method of analyzing isopropylphenyl phosphate according to an embodiment includes desorbing a sample by hot extraction, analyzing the desorbed sample to obtain a mass chromatogram of one or more compounds in the sample by gas chromatography mass spectrometry and determining whether the mass chromatogram includes one or more peaks of one or more product ions and/or one or more molecular ions each having a predetermined mass-to-charge ratio (m/z).

IPC Classes  ?

6.

MIXED REALITY DEVICE, PROCESSING METHOD, AND STORAGE MEDIUM

      
Application Number 18827099
Status Pending
Filing Date 2024-09-06
First Publication Date 2025-04-17
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Yoshii, Takanori
  • Aoki, Yusuke
  • Hayashi, Kyotaro
  • Nakamura, Hiroaki
  • Hirahara, Yoshiyuki
  • Fukuda, Masamitsu
  • Kozakai, Takafumi
  • Namioka, Yasuo

Abstract

According to one embodiment, a mixed reality device is configured to display a virtual space to overlap a real space. The mixed reality device is configured to set an origin of the virtual space by using a prescribed object imaged in the real space. The mixed reality device is configured to acquire a display position of a virtual object in a three-dimensional coordinate system based on the origin. The mixed reality device is configured to determine whether or not the display position is present inside a visible region set in front of the mixed reality device. The mixed reality device is configured to display a guide indicating a direction of the display position when the display position is not present inside the visible region.

IPC Classes  ?

  • G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
  • G02B 27/01 - Head-up displays
  • G06T 19/00 - Manipulating 3D models or images for computer graphics

7.

MIXED REALITY DEVICE, ACQUISITION SYSTEM, PROCESSING METHOD, AND STORAGE MEDIUM

      
Application Number 18830017
Status Pending
Filing Date 2024-09-10
First Publication Date 2025-04-17
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Yamashita, Ren
  • Aoki, Yusuke
  • Yoshii, Takanori
  • Hayashi, Kyotaro
  • Nakamura, Hiroaki
  • Hirahara, Yoshiyuki
  • Fukuda, Masamitsu
  • Kozakai, Takafumi
  • Namioka, Yasuo

Abstract

According to one embodiment, a mixed reality device is configured to display a virtual object corresponding to a fastening location where a screw is turned. The virtual object is displayed at a position away from the fastening location. The mixed reality device is configured to change a display position of the virtual object with respect to the fastening location according to a physique of a wearer.

IPC Classes  ?

  • G09G 3/00 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G02B 27/01 - Head-up displays
  • G06T 11/00 - 2D [Two Dimensional] image generation

8.

PROCESSING DEVICE, MIXED REALITY DEVICE, PROCESSING METHOD, AND STORAGE MEDIUM

      
Application Number 18830958
Status Pending
Filing Date 2024-09-11
First Publication Date 2025-04-17
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Masui, Yukino
  • Namioka, Yasuo
  • Yoshii, Takanori
  • Hirahara, Yoshiyuki
  • Fukuda, Masamitsu
  • Hayashi, Kyotaro
  • Nakamura, Hiroaki

Abstract

According to one embodiment, a processing device is configured to measure a plurality of coordinates of a hand respectively in a plurality of images, the hand being consecutively visible in the plurality of images, the hand turning a screw by using a first tool. The processing device is configured to calculate a center coordinate of a rotation of the first tool by using the plurality of coordinates.

IPC Classes  ?

  • G06T 7/20 - Analysis of motion
  • G06T 7/70 - Determining position or orientation of objects or cameras
  • G06V 40/20 - Movements or behaviour, e.g. gesture recognition

9.

MIXED REALITY DEVICE, PROCESSING METHOD, AND STORAGE MEDIUM

      
Application Number 18882426
Status Pending
Filing Date 2024-09-11
First Publication Date 2025-04-17
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Hayashi, Kyotaro
  • Hirose, Yusuke
  • Yoshii, Takanori
  • Hirahara, Yoshiyuki
  • Fukuda, Masamitsu
  • Nakamura, Hiroaki
  • Kozakai, Takafumi
  • Namioka, Yasuo

Abstract

According to one embodiment, a mixed reality device is configured to set an origin of a virtual space by using a marker located in a real space. The mixed reality device is configured to display a virtual object at a preset position in a three-dimensional coordinate system, the three-dimensional coordinate system being based on the origin. The mixed reality device is configured to acquire a movement amount of the marker with respect to a reference position of the marker. The reference position of the marker being acquired when the origin is set. The mixed reality device is configured to move the origin according to the movement amount when the movement amount is greater than a first threshold, the first threshold being preset.

IPC Classes  ?

  • G06T 19/00 - Manipulating 3D models or images for computer graphics
  • G06T 7/246 - Analysis of motion using feature-based methods, e.g. the tracking of corners or segments
  • G06T 7/73 - Determining position or orientation of objects or cameras using feature-based methods

10.

PROCESSING DEVICE, PROCESSING SYSTEM, MIXED REALITY DEVICE, PROCESSING METHOD, AND STORAGE MEDIUM

      
Application Number 18910513
Status Pending
Filing Date 2024-10-09
First Publication Date 2025-04-17
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Nishijima, Sumire
  • Yoshii, Takanori
  • Hayashi, Kyotaro
  • Nakamura, Hiroaki
  • Hirahara, Yoshiyuki
  • Kato, Takehiro
  • Namioka, Yasuo

Abstract

According to one embodiment, a processing device is configured to acquire an image including a hand of a worker and a plurality of markers attached to a first tool for turning a screw. The processing device is further configured to calculate a first position of the first tool based on a plurality of positions of the plurality of markers in a case where the hand touches a virtual first object. The processing device is further configured to determine whether a screw is turned at a fastening location corresponding to the first object based on a first distance between the first object and the first position.

IPC Classes  ?

  • G06T 7/73 - Determining position or orientation of objects or cameras using feature-based methods
  • G06T 7/33 - Determination of transform parameters for the alignment of images, i.e. image registration using feature-based methods
  • G06T 19/00 - Manipulating 3D models or images for computer graphics

11.

MIXED REALITY DEVICE, PROCESSING METHOD, PROCESSING DEVICE AND STORAGE MEDIUM

      
Application Number 18910629
Status Pending
Filing Date 2024-10-09
First Publication Date 2025-04-17
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Nakamura, Hiroaki
  • Yoshii, Takanori
  • Hirahara, Yoshiyuki
  • Hayashi, Kyotaro
  • Kato, Takehiro
  • Namioka, Yasuo

Abstract

According to one embodiment, a mixed reality device includes an imaging part and a processing part. The imaging part is configured to acquire an image. The processing part is configured to recognize, from the image, a hand of a worker performing a fastening task. The processing part is further configured to determine whether the fastening task is appropriate based on a first distance between a first position corresponding to a fastening location of a screw and a second position of the hand holding a first tool.

IPC Classes  ?

  • G06V 40/20 - Movements or behaviour, e.g. gesture recognition
  • G06T 7/73 - Determining position or orientation of objects or cameras using feature-based methods
  • G06T 19/00 - Manipulating 3D models or images for computer graphics
  • G06V 10/75 - Organisation of the matching processes, e.g. simultaneous or sequential comparisons of image or video featuresCoarse-fine approaches, e.g. multi-scale approachesImage or video pattern matchingProximity measures in feature spaces using context analysisSelection of dictionaries
  • G06V 20/50 - Context or environment of the image

12.

CROSS-REALITY DEVICE, STORAGE MEDIUM, PROCESSING DEVICE, GENERATION METHOD, AND PROCESSING METHOD

      
Application Number 18910631
Status Pending
Filing Date 2024-10-09
First Publication Date 2025-04-17
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Hayashi, Kyotaro
  • Yoshii, Takanori
  • Nakamura, Hiroaki
  • Hirahara, Yoshiyuki
  • Kato, Takehiro
  • Namioka, Yasuo

Abstract

According to one embodiment, a cross-reality comprises an imaging device, a display device, and a processing device. The imaging device is configured to acquire an image. The display device is configured to display a virtual space. The processing device is configured to detect a hand of a human from the image. the processing device is configured to generate an object in the virtual space in response to a command input by the human, and change a position and a size of the generated object in accordance with a movement of the hand.

IPC Classes  ?

  • G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
  • G06V 40/20 - Movements or behaviour, e.g. gesture recognition
  • G10L 15/22 - Procedures used during a speech recognition process, e.g. man-machine dialog

13.

DISK DEVICE

      
Application Number 18985652
Status Pending
Filing Date 2024-12-18
First Publication Date 2025-04-17
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Setoma, Shunya

Abstract

According to one embodiment, a disk device includes a magnetic disk, a magnetic head, a flexure, a piezoelectric element, a first bonding material, a second bonding material, and a protrusion. The flexure includes a first outer surface, a first pad, and a second pad. The first pad and the second pad are on the first outer surface. The piezoelectric element includes a second outer surface, a first electrode, and a second outer surface. The first electrode and the second electrode are on the second outer surface. The first bonding material, which is conductive, bonds the first pad and the first electrode. The second bonding material, which is conductive, bonds the second pad and the second electrode. The protrusion is provided on the flexure, is located at least partially between the first bonding material and the second bonding material, and protrudes from the first outer surface.

IPC Classes  ?

  • G11B 5/48 - Disposition or mounting of heads relative to record carriers
  • H10N 30/87 - Electrodes or interconnections, e.g. leads or terminals

14.

DISK DEVICE

      
Application Number 18985671
Status Pending
Filing Date 2024-12-18
First Publication Date 2025-04-17
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Setoma, Shunya

Abstract

According to one embodiment, a disk device includes a magnetic disk, a magnetic head, a flexure, a piezoelectric element, a first bonding material, a second bonding material, and a protrusion. The flexure includes a first outer surface, a first pad, and a second pad. The first pad and the second pad are on the first outer surface. The piezoelectric element includes a second outer surface, a first electrode, and a second outer surface. The first electrode and the second electrode are on the second outer surface. The first bonding material, which is conductive, bonds the first pad and the first electrode. The second bonding material, which is conductive, bonds the second pad and the second electrode. The protrusion is provided on the flexure, is located at least partially between the first bonding material and the second bonding material, and protrudes from the first outer surface.

IPC Classes  ?

  • G11B 5/48 - Disposition or mounting of heads relative to record carriers
  • H10N 30/87 - Electrodes or interconnections, e.g. leads or terminals

15.

MATERIAL FOR CERAMIC BALL, DEVICE FOR PROCESSING CERAMIC FORMED BODY, AND METHOD FOR PROCESSING CERAMIC FORMED BODY

      
Application Number 19003080
Status Pending
Filing Date 2024-12-27
First Publication Date 2025-04-17
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA MATERIALS CO., LTD. (Japan)
Inventor
  • Sano, Shoya
  • Yamada, Katsuhiko
  • Sakai, Ryo
  • Yamaguti, Haruhiko
  • Funaki, Kai
  • Akiya, Suguru
  • Kijima, Kouichi

Abstract

In a material for a ceramic ball according to an embodiment, a sphericity is 2% or less, and an arithmetic mean roughness Ra is 0.2 μm or more and 2 μm or less. In the material for the ceramic ball, a total height of profile Rt is preferably 4 μm or more and 20 μm or less. In the material for the ceramic ball, when a surface roughness Ra in a circumferential direction of a belt-like portion mark is defined as Ra1, and a surface roughness Ra of a circumference in a direction perpendicular to the belt-like portion mark is defined as Ra2, Ra1/Ra2 is preferably 0.2 or more and 2 or less.

IPC Classes  ?

16.

MIXED REALITY DEVICE, PROCESSING DEVICE, PROCESSING METHOD, AND STORAGE MEDIUM

      
Application Number 18830496
Status Pending
Filing Date 2024-09-10
First Publication Date 2025-04-17
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Shinagawa, Hiroki
  • Yoshii, Takanori
  • Hayashi, Kyotaro
  • Nakamura, Hiroaki
  • Hirahara, Yoshiyuki
  • Fukuda, Masamitsu
  • Kozakai, Takafumi
  • Namioka, Yasuo

Abstract

According to one embodiment, a mixed reality device overlays, on a real space, and displays a virtual object in a virtual space. The mixed reality device is configured to obtain a position of an object in the real space and a position of the virtual object. The mixed reality device is configured to change an external appearance of the virtual object when the virtual object is positioned on a far side of the object relative to the mixed reality device and overlaps the object.

IPC Classes  ?

  • G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
  • G06T 17/20 - Wire-frame description, e.g. polygonalisation or tessellation

17.

CONTENT GENERATION DEVICE, MIXED REALITY DEVICE, CONTENT GENERATION SYSTEM, CONTENT GENERATION METHOD, AND STORAGE MEDIUM

      
Application Number 18882371
Status Pending
Filing Date 2024-09-11
First Publication Date 2025-04-17
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Shinagawa, Hiroki
  • Nishijima, Sumire
  • Masui, Yukino
  • Yamashita, Ren
  • Yoshii, Takanori
  • Hayashi, Kyotaro
  • Nakamura, Hiroaki
  • Hirahara, Yoshiyuki
  • Fukuda, Masamitsu
  • Kozakai, Takafumi
  • Namioka, Yasuo

Abstract

According to one embodiment, a content generation device is configured to recognize a voice of a worker when performing a task. The content generation device is configured to generate an instruction related to the task based on a recognition result of the voice. The content generation device is configured to associate the instruction with data of the task and record the instruction. Preferably, the content generation device is configured to generate a prompt by using the recognized voice. The content generation device is configured to acquire a summary of the voice by inputting the prompt to a language model, the language model including a neural network, and record the summary as the instruction.

IPC Classes  ?

  • G10L 15/22 - Procedures used during a speech recognition process, e.g. man-machine dialog
  • G06T 19/00 - Manipulating 3D models or images for computer graphics

18.

CONTROL METHOD, MIXED REALITY SYSTEM, MIXED REALITY DEVICE, AND STORAGE MEDIUM

      
Application Number 18909737
Status Pending
Filing Date 2024-10-08
First Publication Date 2025-04-17
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Yamashita, Ren
  • Aoki, Yusuke
  • Yoshii, Takanori
  • Hayashi, Kyotaro
  • Nakamura, Hiroaki
  • Hirahara, Yoshiyuki
  • Fukuda, Masamitsu
  • Kozakai, Takafumi
  • Namioka, Yasuo

Abstract

According to one embodiment, a control method includes causing a first mixed reality device to display a first virtual object at a first fastening location. The control method includes causing a second mixed reality device to display a second virtual object at a second fastening location. The control method includes, when a screw is determined to have been turned at the first fastening location and a screw is determined to have been turned at the second fastening location, causing the first mixed reality device to display a third virtual object at a third fastening location, and causing the second mixed reality device to display a fourth virtual object at a fourth fastening location.

IPC Classes  ?

  • G06T 19/00 - Manipulating 3D models or images for computer graphics
  • G06F 3/14 - Digital output to display device

19.

PROCESSING SYSTEM, MIXED REALITY DEVICE, PROCESSING METHOD, STORAGE MEDIUM

      
Application Number 18909754
Status Pending
Filing Date 2024-10-08
First Publication Date 2025-04-17
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Hayashi, Kyotaro
  • Yoshii, Takanori
  • Nakamura, Hiroaki
  • Hirahara, Yoshiyuki
  • Kato, Takehiro
  • Namioka, Yasuo

Abstract

According to one embodiment, a processing system is used for a task of turning a screw at a fastening location with a tool. The processing system comprises a display device and a processing device. The display device is configured to display a virtual first object around a region where the tool can be positioned during the task. The processing device is configured to estimate a position of the tool. The processing device is configured to issue an alert in a case where the tool is determined to be in contact with the first object based on the estimated position.

IPC Classes  ?

  • G06T 19/00 - Manipulating 3D models or images for computer graphics
  • G06T 7/73 - Determining position or orientation of objects or cameras using feature-based methods

20.

PROCESSING DEVICE, TRAINING DEVICE, MIXED REALITY DEVICE, PROCESSING METHOD, AND STORAGE MEDIUM

      
Application Number 18910430
Status Pending
Filing Date 2024-10-09
First Publication Date 2025-04-17
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Nishijima, Sumire
  • Shinagawa, Hiroki
  • Masui, Yukino
  • Yoshii, Takanori
  • Hayashi, Kyotaro
  • Nakamura, Hiroaki
  • Hirahara, Yoshiyuki
  • Kase, Akiko
  • Fukuda, Masamitsu
  • Kozakai, Takafumi
  • Namioka, Yasuo

Abstract

According to one embodiment, a processing device is configured to estimate a first task location by using a first image, a screw being turned at the first task location. The processing device is configured to extract first time-series data from time-series data acquired by a tool turning the screw, the first time-series data being time-series data when the screw is being turned at the first task location. The processing device is configured to associate the first time-series data with data related to the first task location.

IPC Classes  ?

  • G06T 7/00 - Image analysis
  • G01L 5/24 - Apparatus for, or methods of, measuring force, work, mechanical power, or torque, specially adapted for specific purposes for determining value of torque or twisting moment for tightening a nut or other member which is similarly stressed
  • G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
  • G06T 7/70 - Determining position or orientation of objects or cameras
  • G06V 20/20 - ScenesScene-specific elements in augmented reality scenes
  • G06V 40/10 - Human or animal bodies, e.g. vehicle occupants or pedestriansBody parts, e.g. hands

21.

MIXED REALITY DEVICE, DISPLAY CONTROL METHOD, AND STORAGE MEDIUM

      
Application Number 18910707
Status Pending
Filing Date 2024-10-09
First Publication Date 2025-04-17
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Shinagawa, Hiroki
  • Nishijima, Sumire
  • Masui, Yukino
  • Yoshii, Takanori
  • Hayashi, Kyotaro
  • Nakamura, Hiroaki
  • Hirahara, Yoshiyuki
  • Fukuda, Masamitsu
  • Kato, Takehiro
  • Kozakai, Takafumi
  • Namioka, Yasuo

Abstract

According to one embodiment, a mixed reality device is capable of superimposing a virtual space on a real space. The mixed reality device is configured to set a three-dimensional coordinate system in the virtual space based on a prescribed object imaged in the real space. The mixed reality device is further configured to display a virtual object at a predetermined position in the three-dimensional coordinate system. The mixed reality device is further configured to change a display direction of the virtual object according to a positional relationship between the virtual object and the mixed reality device.

IPC Classes  ?

  • G06T 19/00 - Manipulating 3D models or images for computer graphics

22.

MIXED REALITY DEVICE, PROCESSING METHOD, AND STORAGE MEDIUM

      
Application Number 18912312
Status Pending
Filing Date 2024-10-10
First Publication Date 2025-04-17
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Yamashita, Ren
  • Aoki, Yusuke
  • Yoshii, Takanori
  • Hayashi, Kyotaro
  • Nakamura, Hiroaki
  • Hirahara, Yoshiyuki
  • Fukuda, Masamitsu
  • Kozakai, Takafumi
  • Namioka, Yasuo

Abstract

According to one embodiment, a mixed reality device is configured to display a virtual space to overlap a real space. The mixed reality device measures a first coordinate of the mixed reality device and calculates a first region by using the first coordinate as a reference. The mixed reality device detects an object present in the real space in a surrounding area of the mixed reality device and calculates a second region by using a second coordinate of the object as a reference. The mixed reality device outputs an alert when the first region and the second region overlap.

IPC Classes  ?

  • G06T 19/00 - Manipulating 3D models or images for computer graphics

23.

DISK DEVICE

      
Application Number 18981954
Status Pending
Filing Date 2024-12-16
First Publication Date 2025-04-10
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Uehara, Manabu

Abstract

According to one embodiment, a disk device includes two magnetic disks opposing each other at intervals of 1.2 to 1.5 mm, and at least two suspension assemblies movable respectively between the two magnetic disks. Each of the suspension assemblies includes a base plate, a load beam extending from the base plate, a tab extending from a distal end of the load beam, a wiring member on the load beam and the base plate, including a gimbal portion, and a magnetic head on the gimbal portion, abutting on a dimple of the load beam via the gimbal portion. The ratio of a distance from a bendable location of the load beam to a center of the dimple with respect to a distance from the center of the dimple to a tip of the tab is 2.8 to 3.8.

IPC Classes  ?

  • G11B 5/48 - Disposition or mounting of heads relative to record carriers
  • G11B 25/04 - Apparatus characterised by the shape of record carrier employed but not specific to the method of recording or reproducing using flat record carriers, e.g. disc, card

24.

SPEECH MODIFICATION ASSISTANCE APPARATUS, SPEECH MODIFICATION ASSISTANCE METHOD, SPEECH MODIFICATION ASSISTANCE COMPUTER PROGRAM PRODUCT, AND SPEECH MODIFICATION ASSISTANCE SYSTEM

      
Application Number 18983871
Status Pending
Filing Date 2024-12-17
First Publication Date 2025-04-10
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA DIGITAL SOLUTIONS CORPORATION (Japan)
Inventor Kurata, Yoshinori

Abstract

A speech modification assistance apparatus (10) includes one or more hardware processors configured to function as a first reception unit (22A), a display control unit (21), and a second reception unit (22B). The first reception unit (22A) receives selection of target recorded speech data, which is basic recorded speech data (70) to be processed, from among one or more pieces of basic recorded speech data (70) that are recorded. The display control unit (21) converts the target recorded speech data into a basic character string and displays the basic character string. The second reception unit (22B) receives designation of a change target character string to be changed in the displayed basic character string. The generation control unit (24) generates modified speech data corresponding to the target recorded speech data and the change target character string.

IPC Classes  ?

  • G10L 21/013 - Adapting to target pitch
  • G10L 13/033 - Voice editing, e.g. manipulating the voice of the synthesiser
  • G10L 13/08 - Text analysis or generation of parameters for speech synthesis out of text, e.g. grapheme to phoneme translation, prosody generation or stress or intonation determination

25.

TRANSMISSION DEVICE, COMMUNICATION SYSTEM, TRANSMISSION METHOD, AND COMPUTER PROGRAM PRODUCT

      
Application Number 18985366
Status Pending
Filing Date 2024-12-18
First Publication Date 2025-04-10
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Gondo, Shunichi
  • Kurosaka, Takumi

Abstract

A transmission device according to an embodiment includes one or more processors. The processors divide a plurality of pieces of transmission data to be transmitted into first data and second data. The processors transmit the first data to a server device configured to distribute the transmission data to a reception device. The processors store the second data in storage. The processors receive, from the reception device or the server device, a request for transmission of the second data. The processors transmit the second data to the server device in accordance with the request for transmission.

IPC Classes  ?

  • H04N 19/423 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
  • H04N 19/159 - Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction

26.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD

      
Application Number 18796397
Status Pending
Filing Date 2024-08-07
First Publication Date 2025-04-10
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor
  • Iwakaji, Yoko
  • Kawamura, Keiko
  • Motai, Takako

Abstract

A semiconductor device according to an embodiment includes a cell region and a termination region adjacent to the cell region. A first insulating film is provided on a first main surface of a semiconductor portion. A first semiconductor region of a first conductivity type provided in the semiconductor portion, a gate electrode, and a gate insulating film covering the gate electrode are provided in the cell region. A second semiconductor region of a second conductivity type provided between the first semiconductor region and the first main surface from the cell region to the termination region is in contact with at least a part of a bottom surface of the gate insulating film. A first member is provided between the second semiconductor region and the first insulating film.

IPC Classes  ?

  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
  • H01L 29/66 - Types of semiconductor device

27.

SEMICONDUCTOR DEVICE

      
Application Number 18812334
Status Pending
Filing Date 2024-08-22
First Publication Date 2025-04-10
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Takada, Yoshiharu

Abstract

A semiconductor device includes a semiconductor element that includes a first electrode and a second electrode facing the first electrode in a first direction, a first conductor, and a first fixing member. The first conductor includes a first portion facing the first electrode in the first direction, and a second portion at least partially spaced apart from and facing the first portion in the first direction. The first fixing member is provided between the first electrode and the first portion, and between the first portion and the second portion in the first direction.

IPC Classes  ?

  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/495 - Lead-frames

28.

Magnetic disk device

      
Application Number 18596334
Grant Number 12272389
Status In Force
Filing Date 2024-03-05
First Publication Date 2025-04-08
Grant Date 2025-04-08
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Kawabe, Takayuki

Abstract

According to one embodiment, a magnetic disk device includes a disk, a read head, and a control unit. The control unit includes a read processing unit that executes first read processing of moving the read head to n1 radial positions within a period in which the disk makes m1 rotations and reading the data of the track, a comparison unit that derives a first signal of highest quality, and a determination unit that determines a radial position at which the first signal of the highest quality is derived as a first appropriate read position. Where 1≤m1

IPC Classes  ?

  • G11B 5/58 - Disposition or mounting of heads relative to record carriers with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following
  • G11B 5/48 - Disposition or mounting of heads relative to record carriers
  • G11B 5/55 - Track change, selection, or acquisition by displacement of the head
  • G11B 5/56 - Disposition or mounting of heads relative to record carriers with provision for moving the head for the purpose of adjusting the position of the head relative to the record carrier, e.g. manual adjustment for azimuth correction or track centering

29.

CERAMIC SUBSTRATE, CERAMIC CIRCUIT BOARD, SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING CERAMIC SUBSTRATE, AND METHOD FOR MANUFACTURING CERAMIC SPLIT SUBSTRATE

      
Application Number 18957959
Status Pending
Filing Date 2024-11-25
First Publication Date 2025-04-03
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA MATERIALS CO., LTD. (Japan)
Inventor Matsumoto, Yukihisa

Abstract

In a ceramic substrate according to an embodiment, there are two or more peaks within a range of 98 eV or higher and 106 eV or lower in a spectrum obtained by measuring a laser-irradiated zone on a laser-processed surface by X-ray Photoelectron Spectroscopy (XPS). A ceramic circuit board and a semiconductor device including the ceramic substrate are provided. Methods for manufacturing the ceramic substrate and a ceramic split substrate are also provided.

IPC Classes  ?

  • H05K 3/00 - Apparatus or processes for manufacturing printed circuits
  • B23K 1/00 - Soldering, e.g. brazing, or unsoldering
  • B23K 26/364 - Laser etching for making a groove or trench, e.g. for scribing a break initiation groove
  • B23K 26/402 - Removing material taking account of the properties of the material involved involving non-metallic material, e.g. isolators
  • B23K 101/42 - Printed circuits
  • B23K 103/00 - Materials to be soldered, welded or cut
  • G01N 23/2273 - Measuring photoelectron spectra, e.g. electron spectroscopy for chemical analysis [ESCA] or X-ray photoelectron spectroscopy [XPS]
  • H05K 1/03 - Use of materials for the substrate

30.

NITRIDE STRUCTURE AND SEMICONDUCTOR DEVICE

      
Application Number 18665786
Status Pending
Filing Date 2024-05-16
First Publication Date 2025-04-03
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor
  • Kaneko, Ryoma
  • Yoshida, Hisashi
  • Hikosaka, Toshiki

Abstract

According to one embodiment, a nitride structure includes a base, a nitride member, and a semiconductor member including Ga and N. The nitride member is provided between the base and the semiconductor member in a first direction. The nitride member includes a first nitride region, a second nitride region, and a third nitride region. The first nitride region is provided between the base and the third nitride region. The second nitride region is provided between the first nitride region and the third nitride region. The first nitride region includes AlN. The second nitride region includes Alx2Ga1-x2N (0

IPC Classes  ?

  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 29/15 - Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds

31.

SEMICONDUCTOR DEVICE WITH INTEGRATED RESISTOR AT ELEMENT REGION BOUNDARY

      
Application Number 18977231
Status Pending
Filing Date 2024-12-11
First Publication Date 2025-03-27
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Komatsu, Kanako

Abstract

According to one embodiment, a semiconductor device includes a substrate having a first surface and an insulator that surrounds a first region of the first surface. A gate electrode is on the first region and has a first resistivity. A first conductor is also on the first region. The first conductor comprises a same material as the gate electrode, but has a second resistivity that is different from the first resistivity. The resistivity may be different, for example, by either use of different dopants/impurities or different concentrations of dopants/impurities. Resistivity may also be different due to inclusion of a metal silicide on the conductors or not.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/45 - Ohmic electrodes
  • H01L 29/49 - Metal-insulator semiconductor electrodes

32.

CERAMIC SUBSTRATE, CERAMIC CIRCUIT SUBSTRATE, AND SEMICONDUCTOR DEVICE

      
Application Number 18977706
Status Pending
Filing Date 2024-12-11
First Publication Date 2025-03-27
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA MATERIALS CO., LTD. (Japan)
Inventor
  • Yamagata, Yoshihito
  • Aoki, Katsuyuki

Abstract

A ceramic substrate according to an embodiment includes a ratio A/B of an arc discharge voltage A to a dielectric breakdown voltage B of not less than 0.3 when the arc discharge voltage A (kV) is measured when an arc discharge is detected when applying an AC voltage of 50 Hz or 60 Hz between a front surface and a back surface of the ceramic substrate at a voltage increase rate of 200 V/s, and when the dielectric breakdown voltage B (kV) between the front surface and the back surface is measured according to IEC 672-2.

IPC Classes  ?

33.

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

      
Application Number 18433964
Status Pending
Filing Date 2024-02-06
First Publication Date 2025-03-27
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor
  • Hyodo, Ko
  • Yoshikawa, Daiki

Abstract

A manufacturing method of a semiconductor device according to an embodiment includes: forming a semiconductor portion including a transistor region and a diode region; forming a first lifetime control region in a lower portion of the semiconductor portion in the diode region, with ion irradiated from an upper side of the semiconductor portion; and forming a second lifetime control region in an upper portion of the semiconductor portion, with ion irradiated through a mask from the upper side of the semiconductor portion, the second lifetime control region being formed simultaneously with the first lifetime control region so as not to overlap with the first lifetime control region.

IPC Classes  ?

  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect

34.

MAGNETIC DISK DEVICE

      
Application Number 18435302
Status Pending
Filing Date 2024-02-07
First Publication Date 2025-03-27
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Yaguchi, Tomoki

Abstract

A magnetic disk device according to one embodiment includes a base, five or more magnetic disks in the base, a head actuator, and a spindle motor. The base has a bottom wall having a second thickness and a side wall. The spindle motor includes a sleeve with a first hole, fixed to the bottom wall, a shaft inserted in the first hole rotatably, and a hub rotatable integrally with the shaft. The hub includes a first part, a second part extending from a lowermost surface of the first part in a first direction being from the magnetic disks toward the bottom wall, and a third part having a first thickness and extending from a lowermost surface of the second part in a second direction orthogonal to the first direction. A value obtained by dividing the second thickness by the first thickness is greater than or equal to 1.89.

IPC Classes  ?

  • G11B 33/04 - CabinetsCasesStandsDisposition of apparatus therein or thereon modified to store record carriers
  • G11B 5/54 - Disposition or mounting of heads relative to record carriers with provision for moving the head into, or out of, its operative position or across tracks
  • G11B 5/82 - Disk carriers
  • G11B 19/20 - DrivingStartingStoppingControl thereof

35.

SYSTEM AND METHOD FOR TRAINING A MACHINE LEARNING MODEL IN A DISTRIBUTED SYSTEM

      
Application Number 18471749
Status Pending
Filing Date 2023-09-21
First Publication Date 2025-03-27
Owner Kabushiki Kaisha Toshiba (Japan)
Inventor
  • Herzog, Alexander
  • Bullo, Marcello
  • Carnelli, Pietro Edoardo
  • Khan, Aftab

Abstract

A computer-implemented method for training a machine learning model in a distributed system, The distributed system comprises a plurality of nodes that exchange updates to communally train the machine learning model. Each node of the plurality of nodes maintains a local version of the machine learning model. The local version of the machine learning model of each of the plurality of nodes has been initialised with the same one or more respective parameter values. The method comprises a node: receiving an update to a local model from at least one other node in the distributed system, the local model comprising the local version of the machine learning model and the update comprising a dense array of one or more first parameter deltas, the one or more first parameter deltas being ordered in the dense array in an order determined by a reference model, each first parameter delta representing a difference between a parameter of the local model and a corresponding parameter of an updated version of the machine learning model that is maintained by the at least other node; updating the local model based on the received update and the reference model to determine an updated local model; determining one or more second parameter deltas, each second parameter delta representing a difference between a parameter of the updated local model and a corresponding parameter of a previous version of the local model; and sending an update to the at least one other node in the distributed system, wherein the update comprises a dense array of the one or more second parameter deltas, the one or more second parameter deltas being ordered in the dense array in an order determined by the reference model.

IPC Classes  ?

  • G06N 3/098 - Distributed learning, e.g. federated learning

36.

DISK DEVICE AND METHOD OF INSPECTING DISK DEVICE

      
Application Number 18589382
Status Pending
Filing Date 2024-02-27
First Publication Date 2025-03-27
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Mizutani, Akiyo

Abstract

A disk device according to one embodiment includes a housing, a magnetic disk, a circuit board, a first oscillator, and a first adsorption film. The housing is provided with an internal space. The magnetic disk is disposed in the internal space. The circuit board is attached to the housing outside the internal space. The first oscillator is disposed away from an electric circuit in the internal space. The electric circuit is electrically connected to the circuit board. The first adsorption film is formed on the first oscillator, exposed to the internal space, and configured to adsorb a first substance.

IPC Classes  ?

  • G01N 29/02 - Analysing fluids
  • G01N 29/24 - Probes
  • G01N 33/00 - Investigating or analysing materials by specific methods not covered by groups
  • G11B 33/06 - CabinetsCasesStandsDisposition of apparatus therein or thereon combined with other apparatus having a different main function

37.

DISK APPARATUS

      
Application Number 18591696
Status Pending
Filing Date 2024-02-29
First Publication Date 2025-03-27
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Nojima, Yusuke

Abstract

A disk apparatus includes a carriage, a magnetic disk, a base plate, a load beam, a flexure, and a magnetic head. The carriage rotates around a first rotation axis. The base plate includes a first surface facing the magnetic disk and is attached to the carriage. The load beam is attached to the base plate. The flexure includes a plurality of wirings and is attached to the base plate and the load beam. The magnetic head is attached to the flexure and electrically connected to at least one of the plurality of wirings. The flexure includes a thin portion that is thinner than other portions of the flexure. The thin portion includes a first portion which covers the first surface and at which the plurality of wirings extends in non-parallel directions with respect to each other.

IPC Classes  ?

  • G11B 5/48 - Disposition or mounting of heads relative to record carriers
  • G11B 5/53 - Disposition or mounting of heads on rotating support
  • G11B 5/82 - Disk carriers

38.

SEMICONDUCTOR DEVICE

      
Application Number 18596066
Status Pending
Filing Date 2024-03-05
First Publication Date 2025-03-27
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor
  • Shigesawa, Eriko
  • Ogura, Akio

Abstract

According to one embodiment, a semiconductor device includes a first terminal which is coupled to a first node and to which a control signal is externally input, a first circuit coupled to the first node, configured to switch based on a logic level of the first node between a first state where a first voltage is not output to a second node and a second state where the first voltage is output to the second node, and configured to control a slew rate of an output voltage at a time of switching from the first state to the second state, and a second circuit including a switch circuit which includes one end coupled to the first node and another end applied with a second voltage, and configured to control the switch circuit based on a voltage at the second node.

IPC Classes  ?

  • H03K 19/017 - Modifications for accelerating switching in field-effect transistor circuits
  • H03K 17/16 - Modifications for eliminating interference voltages or currents
  • H03K 17/30 - Modifications for providing a predetermined threshold before switching
  • H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits

39.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 18601059
Status Pending
Filing Date 2024-03-11
First Publication Date 2025-03-27
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Tsukamoto, Teppei

Abstract

A semiconductor device according to an embodiment includes a transistor, and a plurality of metal layers that is respectively arranged in a plurality of layers stacked above the transistor, in which the plurality of metal layers includes a first metal layer that is arranged in a lowermost layer of the plurality of layers, a second metal layer that is arranged in an uppermost layer of the plurality of layers and that is thicker than the first metal layer, and a third metal layer that is arranged in the uppermost layer and that is thicker than the second metal layer.

IPC Classes  ?

  • H01L 23/00 - Details of semiconductor or other solid state devices
  • C25D 5/02 - Electroplating of selected surface areas
  • C25D 7/12 - Semiconductors
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure

40.

ETCHING METHOD

      
Application Number 18602237
Status Pending
Filing Date 2024-03-12
First Publication Date 2025-03-27
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Kawakami, Hiroki
  • Higuchi, Kazuhito
  • Obata, Susumu
  • Tajima, Takayuki

Abstract

According to one embodiment, an etching method is provided. The etching method includes: forming a layer containing a first metal catalyst at a surface containing a semiconductor; first etching using the first metal catalyst; forming a layer containing a second metal catalyst having a larger diffusion coefficient than that of the first metal catalyst at the layer containing the first metal catalyst; and second etching using the second metal catalyst.

IPC Classes  ?

  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching

41.

SEMICONDUCTOR DEVICE

      
Application Number 18602569
Status Pending
Filing Date 2024-03-12
First Publication Date 2025-03-27
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Sato, Kazuyuki

Abstract

A semiconductor device includes a first electrode, a semiconductor part located on the first electrode, an insulating member located in the semiconductor part, a first insulating film located on a portion of the semiconductor part, a second insulating film located on another portion of the semiconductor part, a second electrode located in the insulating member, a first wiring part connected to the second electrode, and a third electrode located on the semiconductor part, on the insulating member, and on the first insulating film. The second insulating film is thicker than the first insulating film. The first wiring part is located on the insulating member and on the second insulating film but not on the first insulating film.

IPC Classes  ?

  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

42.

CONTROL DEVICE, HOLDING SYSTEM, CARGO HANDLING DEVICE, PROCESSING METHOD, AND STORAGE MEDIUM

      
Application Number 18604362
Status Pending
Filing Date 2024-03-13
First Publication Date 2025-03-27
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA INFRASTRUCTURE SYSTEMS & SOLUTIONS CORPORATION (Japan)
Inventor
  • Ushiyama, Takafumi
  • Sugahara, Atsushi

Abstract

According to one embodiment, a control device controls a holding device capable of holding an object. The control device calculates a first position at which a first object is held by the holding device. The control device determines whether the holding device is capable of coming into contact with another object when the holding device is present at the first position. In a case where the holding device is capable of coming into contact with the other object, the control device calculates a second position at which the holding device comes into contact with the first object and does not come into contact with the other object.

IPC Classes  ?

  • B65G 47/91 - Devices for picking-up and depositing articles or materials incorporating pneumatic, e.g. suction, grippers

43.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

      
Application Number 18635862
Status Pending
Filing Date 2024-04-15
First Publication Date 2025-03-27
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Shoji, Shunsuke

Abstract

A semiconductor device according to an embodiment includes: a semiconductor part including a first main surface and a second main surface on an opposite side of the first main surface; a surface structure part provided on the first main surface, the surface structure part including a first electrode; a second electrode provided on the second main surface; a first protective resin film configured to cover an upper surface of the surface structure part; and a second protective resin film connected to the first protective resin film and configured to cover a side surface of the surface structure part.

IPC Classes  ?

  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 21/782 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
  • H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

44.

ISOLATOR

      
Application Number 18637328
Status Pending
Filing Date 2024-04-16
First Publication Date 2025-03-27
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Koike, Daisuke

Abstract

An isolator according to one embodiment, includes a substrate and a plurality of leads. The substrate includes a lower surface, a plurality of coils, and a plurality of conductive parts. The lower surface has a quadrilateral shape. The plurality of coils includes a first coil, and a second coil. The plurality of conductive parts includes a first conductive part, a second conductive part, a third conductive part, and a fourth conductive part. The first conductive part includes a first terminal. The second conductive part includes a second terminal. The third conductive part includes a third terminal. The fourth conductive part includes a fourth terminal. The plurality of leads includes a first lead, a second lead, a third lead, and a fourth lead. The plurality of leads includes a metal.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

45.

OSCILLATION CIRCUIT

      
Application Number 18667927
Status Pending
Filing Date 2024-05-17
First Publication Date 2025-03-27
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor
  • Miyao, Kazuki
  • Kambashi, Tomoharu
  • Yoshino, Hiroshi

Abstract

According to one embodiment, an oscillation circuit includes: a ring oscillator; a first transistor having a gate terminal coupled to an output port of the ring oscillator and a drain terminal coupled to a first node; a second transistor having a drain terminal and a gate terminal that are both coupled to the first node; a third transistor having a gate terminal coupled to the first node and a drain terminal coupled to a second node; a fourth transistor having a gate terminal coupled to the first node and a drain terminal coupled to a third node; a fifth transistor having a drain terminal coupled to the second node and a source terminal coupled to the third node; and a voltage buffer having an input port coupled to the second node.

IPC Classes  ?

  • H03K 3/03 - Astable circuits
  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors

46.

PROCESSING DEVICE, PROCESSING SYSTEM, HANDLING SYSTEM, PROCESSING METHOD, AND STORAGE MEDIUM

      
Application Number 18830686
Status Pending
Filing Date 2024-09-11
First Publication Date 2025-03-27
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Sawa, Kazuhide
  • Tokura, Seiji
  • Hiraguri, Kazuma
  • Chatani, Harutoshi
  • Ogawa, Akihito

Abstract

According to one embodiment, a processing device is configured to obtain first events indicating that a holding part of a handling robot has passed through respective predetermined passing-through positions. The processing device is configured to obtain a plurality of images of the handling robot. The processing device is configured to identify, when obtaining a second event indicating an abnormality in the handling robot, a first period that is between two of the plurality of first events and includes occurrence timing of the second event, or a second period that is from one of the plurality of first events immediately before the occurrence timing to the occurrence timing. The processing device is configured to extract at least one of the plurality of images obtained in the first period or the second period from the plurality of images.

IPC Classes  ?

  • G06T 7/00 - Image analysis
  • B25J 9/16 - Programme controls
  • G06T 7/70 - Determining position or orientation of objects or cameras
  • G06V 20/52 - Surveillance or monitoring of activities, e.g. for recognising suspicious objects

47.

HEAT TREATMENT FURNACE APPARATUS

      
Application Number 18973520
Status Pending
Filing Date 2024-12-09
First Publication Date 2025-03-27
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA MATERIALS CO., LTD. (Japan)
Inventor
  • Hoshino, Masanori
  • Kato, Hiromasa
  • Sato, Hideki

Abstract

A heat treatment furnace apparatus according to an embodiment heats, when a metal plate is brazed to a ceramic substrate, at least one storage container made of stainless steel, in which a plurality of ceramic metal substrates are stored, to subject the plurality of ceramic metal substrates to a heat treatment at 600 degrees Celsius or more and less than 950 degrees Celsius. The heat treatment furnace apparatus includes: a heater provided outside a furnace body; A heat treatment furnace apparatus according to an embodiment heats, when a metal plate is brazed to a ceramic substrate, at least one storage container made of stainless steel, in which a plurality of ceramic metal substrates are stored, to subject the plurality of ceramic metal substrates to a heat treatment at 600 degrees Celsius or more and less than 950 degrees Celsius. The heat treatment furnace apparatus includes: a heater provided outside a furnace body; a rail section that transports the storage container placed inside the furnace body; and a transport device that transports the storage container placed on the rail section in a predetermined transport direction along the rail section while moving the storage container in a direction perpendicular to the rail section.

IPC Classes  ?

48.

SEMICONDUCTOR DEVICE

      
Application Number 18423373
Status Pending
Filing Date 2024-01-26
First Publication Date 2025-03-27
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Ando, Tomohiro

Abstract

According to one embodiment, a semiconductor device includes: a first circuit configured to drive a load couplable to a first terminal by supplying a load current to the load; and a third circuit including a second circuit configured to copy the load current based on a first voltage of the first terminal and output a first current obtained by copying the load current, the third circuit being configured to monitor a second current based on the first current. The third circuit further includes a fourth circuit configured to adjust the second current in a case where the load current is not supplied to the load.

IPC Classes  ?

  • G05F 3/26 - Current mirrors
  • G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
  • H03F 3/45 - Differential amplifiers

49.

DISK DEVICE

      
Application Number 18428988
Status Pending
Filing Date 2024-01-31
First Publication Date 2025-03-27
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor
  • Zaima, Shino
  • Mizutani, Akiyo

Abstract

According to one embodiment, a disk device includes a magnetic disk, a housing, a first filter unit, and a second filter unit. The housing is provided with an internal space and is provided with a first through hole. The first filter unit includes a first case with a first accommodation space which is in communication with the first through hole, a first adsorbent in the first accommodation space, and a first filter. The first accommodation space is in communication with the internal space through the first filter. The second filter unit includes a second case with a second accommodation space which is separated from the first accommodation space, a second adsorbent in the second accommodation space, and a second filter. The second accommodation space is in communication with the internal space through the second filter.

IPC Classes  ?

  • G11B 33/14 - Reducing influence of physical parameters, e.g. temperature change, moisture, dust

50.

SEMICONDUCTOR DEVICE

      
Application Number 18437854
Status Pending
Filing Date 2024-02-09
First Publication Date 2025-03-27
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor
  • Yasutake, Takuya
  • Kachi, Tsuyoshi

Abstract

A semiconductor device includes first to fourth electrodes, first to third semiconductor regions, first and second insulating parts, and a connection part. The third electrode includes first to third electrode regions. The third electrode region connects the first electrode region and the second electrode region. The first insulating part includes first to third insulating regions. The first insulating region includes first and second insulating portions. The second insulating region includes third and fourth insulating portions. The third insulating region connects the first insulating region and the second insulating region. The third insulating region includes fifth and sixth insulating portions. The connection part includes first and second connection parts. The first connection part is positioned between the third insulating region and the second insulating part. The second connection part is positioned between the third insulating region and the first connection part.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/40 - Electrodes
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device

51.

SEMICONDUCTOR DEVICE

      
Application Number 18437906
Status Pending
Filing Date 2024-02-09
First Publication Date 2025-03-27
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor
  • Yasutake, Takuya
  • Katou, Hiroaki
  • Nishiwaki, Tatsuya
  • Kobayashi, Kenya
  • Kachi, Tsuyoshi

Abstract

A semiconductor device includes first to fourth electrodes, first to third semiconductor regions, and first and second insulating parts. The third electrode includes first to third electrode regions. The third electrode region connects the first electrode region and the second electrode region. The first insulating part includes first to third insulating regions. The first insulating region includes first and second insulating portions. The second insulating region includes third and fourth insulating portions. The third insulating region connects the first insulating region and the second insulating region. The third insulating region includes fifth and sixth insulating portions. A lower end of the sixth insulating portion is positioned lower than a lower end of the second insulating portion and a lower end of the fourth insulating portion.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/40 - Electrodes
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device

52.

SEMICONDUCTOR DEVICE

      
Application Number 18438024
Status Pending
Filing Date 2024-02-09
First Publication Date 2025-03-27
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor
  • Yasutake, Takuya
  • Kobayashi, Kenya
  • Katou, Hiroaki
  • Kachi, Tsuyoshi

Abstract

A semiconductor device includes first to fourth electrodes, first to fourth semiconductor regions, and first and second insulating parts. The third electrode includes first to third electrode regions. The first insulating part includes first to third insulating regions. The first insulating region includes first and second insulating portions. The second insulating region includes third and fourth insulating portions. The third insulating region includes fifth and sixth insulating portion. The fourth electrode is arranged with the first semiconductor region and the third electrode. The second insulating part is located between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode. The fourth semiconductor region is located under the sixth insulating portion.

IPC Classes  ?

  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/41 - Electrodes characterised by their shape, relative sizes or dispositions

53.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

      
Application Number 18442336
Status Pending
Filing Date 2024-02-15
First Publication Date 2025-03-27
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Komatsu, Kanako

Abstract

A semiconductor device includes a semiconductor substrate, an insulating film located on the semiconductor substrate, a silicon film located on the insulating film, a silicide layer located on the silicon film, and a first contact and a second contact connected to portions of the silicide layer. A first recess is formed in an upper surface of the insulating film. The silicon film includes an impurity. A second recess is formed in an upper surface of the silicon film in a region directly above the first recess. The silicide layer contacts the silicon film. A region directly above the second recess is interposed between the portions.

IPC Classes  ?

  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 21/762 - Dielectric regions

54.

INTELLIGENT TASK ALLOCATION FOR DISTRIBUTED MOBILE MULTI-ROBOT SYSTEMS

      
Application Number 18471820
Status Pending
Filing Date 2023-09-21
First Publication Date 2025-03-27
Owner Kabushiki Kaisha Toshiba (Japan)
Inventor
  • Shan, Xiaotao
  • Jurt, Marius David
  • Jin, Yichao

Abstract

Provided is a decentralised multi-robot task allocation method comprising: performing, by a first robot of a plurality of robots, the steps of: obtaining information regarding a new task comprising at least one single robot task, SRT, and at least one multi-robot task, MRT; determining which SRTs each remaining robot of the plurality of robots is likely to select; determining a preferred MRT for the first robot to perform, and potential coalition partners for performing the preferred MRT with the first robot; consulting with the remaining robots of the plurality of robots to determine a coalition of robots including the first robot to perform an MRT of the at least one MRT; and performing at least one of the at least one SRT or the at least one MRT based on the determination of which SRTs each robot from the subset of robots is likely to select, the determination of which MRTs each robot from the subset of robots is likely to select, and the consultation.

IPC Classes  ?

55.

SEMICONDUCTOR DEVICE

      
Application Number 18592123
Status Pending
Filing Date 2024-02-29
First Publication Date 2025-03-27
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Nakamura, Kazutoshi

Abstract

A semiconductor device of embodiments includes a transistor region and a diode region. The transistor region includes: a first conductive type first semiconductor region, a second conductive type second semiconductor region, a first conductive type third semiconductor region in this order in a semiconductor layer; a second conductive type fourth semiconductor region and a first conductive type fifth semiconductor region on the third semiconductor region and arranged alternately in a first direction; a first conductive type sixth semiconductor region between the third and the fourth semiconductor region a first trench spaced from the sixth semiconductor region; a gate electrode in the first trench; a first electrode having a first portion, a bottom surface of the first portion being in contact with the third semiconductor region and side surfaces of the first portion being in contact with the fourth, the fifth, and the sixth semiconductor regions; and a second electrode.

IPC Classes  ?

  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/861 - Diodes

56.

Magnetic recording and reproducing device and adjustment method of the same

      
Application Number 18594478
Grant Number 12266388
Status In Force
Filing Date 2024-03-04
First Publication Date 2025-03-27
Grant Date 2025-04-01
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor
  • Furuhashi, Takao
  • Kimura, Kaori

Abstract

According to one embodiment, a method of adjusting a magnetic recording and reproducing device is a method of adjusting a magnetic recording and reproducing device incorporating a heat-assisted magnetic recording head and a magnetic disk, and the method includes performing a first write operation at a first position on a recording surface, measuring a first error rate at a second position different in radial position from the first position, performing a second write operation and then measuring a second error rate, obtaining a first difference between the first error rate and the second error rate, measuring a third error rate at the first position, performing a third write operation and then measuring a fourth error rate, calculating a second difference between the third error rate and the fourth error rate, comparing the first difference with the second difference and determining a change in flying height.

IPC Classes  ?

  • G11B 5/60 - Fluid-dynamic spacing of heads from record carriers
  • G11B 5/012 - Recording on, or reproducing or erasing from, magnetic disks
  • G11B 5/02 - Recording, reproducing or erasing methodsRead, write or erase circuits therefor
  • G11B 5/455 - Arrangements for functional testing of headsMeasuring arrangements for heads
  • G11B 5/00 - Recording by magnetisation or demagnetisation of a record carrierReproducing by magnetic meansRecord carriers therefor

57.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

      
Application Number 18599965
Status Pending
Filing Date 2024-03-08
First Publication Date 2025-03-27
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Taniguchi, Tomohiro

Abstract

A semiconductor device according to an embodiment includes a semiconductor substrate; a first electrode provided on the semiconductor substrate, and the first electrode containing aluminum; a second electrode provided on the semiconductor substrate, the second electrode being provided separately from the first electrode, and the second electrode containing aluminum; a third electrode provided on the first electrode, and the third electrode containing aluminum oxide.

IPC Classes  ?

  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
  • C23C 18/54 - Contact plating, i.e. electroless electrochemical plating
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 29/66 - Types of semiconductor device

58.

SEMICONDUCTOR DEVICE

      
Application Number 18601346
Status Pending
Filing Date 2024-03-11
First Publication Date 2025-03-27
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Shibata, Toyokazu

Abstract

A semiconductor device includes a first conductive member, a second conductive member, a semiconductor chip, a connection plate, a first bonding member, a second bonding member, and a resin part. The second conductive member includes a first part and a second part. The second part includes a lead part. The semiconductor chip is located between the first part and the first conductive member. The connection plate is located between the semiconductor chip and the first part. The first bonding member is positioned between the semiconductor chip and the connection plate. The second bonding member is positioned between the first part and the connection plate. The resin part covers the semiconductor chip, the connection plate, and the first part. The resin part does not cover a portion of the lead part and a portion of the first conductive member.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/00 - Details of semiconductor or other solid state devices

59.

SEMICONDUCTOR DEVICE

      
Application Number 18604297
Status Pending
Filing Date 2024-03-13
First Publication Date 2025-03-27
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Minami, Shogo
  • Matsuo, Keiichiro
  • Yamamoto, Tetsuya

Abstract

A semiconductor device 100 according to an embodiment including: a semiconductor element 2 placed on an insulating substrate 1 and having an electrode 21 on a surface 2a; a bonding wire 3 bonded to the electrode 21 and electrically coupling the semiconductor element 2; and a first resin material 4 covering a bonding portion 31 between the electrode 21 and the bonding wire 3, the bonding portion 31 includes a non-bonding region 32 where the electrode 21 and the bonding wire 3 are not bonded.

IPC Classes  ?

  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

60.

SEMICONDUCTOR DEVICE

      
Application Number 18627980
Status Pending
Filing Date 2024-04-05
First Publication Date 2025-03-27
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor
  • Tabakoya, Taira
  • Tsujimura, Toshihiro

Abstract

A semiconductor device includes a first substrate, a second substrate, a first semiconductor element, a second semiconductor element, a connection conductor, a connection conductor, and a sealing part. The first substrate includes a first surface, a second surface, a first insulating substrate, and a first conductive layer. The second substrate includes a third surface, a fourth surface, a second insulating substrate, and a second conductive layer. The first semiconductor element includes a first semiconductor layer, a first electrode, a second electrode, and a first control electrode. The second semiconductor element includes a second semiconductor layer, a third electrode, a fourth electrode, and a second control electrode. The connection conductor electrically connects the first and fourth electrodes. The sealing part covers a portion of the first substrate, a portion of the second substrate, the first semiconductor element, and the second semiconductor element.

IPC Classes  ?

  • H01L 23/04 - ContainersSeals characterised by the shape
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/498 - Leads on insulating substrates

61.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 18649568
Status Pending
Filing Date 2024-04-29
First Publication Date 2025-03-27
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Shimabayashi, Masaharu

Abstract

In a method for manufacturing a semiconductor device according to one embodiment, an opening is formed in an upper surface of a first semiconductor region of a first conductivity type. In the method, a gap is formed at a lower portion of the opening by performing atomic layer deposition to plug the opening by forming a first insulating layer at an upper portion of the opening. In the atomic layer deposition, adsorption of an inhibitor to an inner surface of the lower portion of the opening, or termination of dangling bonds of a semiconductor material present at the inner surface of the lower portion of the opening, and adsorption of a precursor to an inner surface of the upper portion of the opening are repeatedly performed.

IPC Classes  ?

  • H01L 29/66 - Types of semiconductor device
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups

62.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

      
Application Number 18680325
Status Pending
Filing Date 2024-05-31
First Publication Date 2025-03-27
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor
  • Sasaki, Yuichiro
  • Shibata, Takeshi
  • Yoshikawa, Daiki

Abstract

According to one embodiment, a semiconductor device includes a first electrode, a second electrode separated from the first electrode, and a semiconductor part located between the first electrode and the second electrode. The semiconductor part includes a first region, a second region, and a third region located between the first region and the second region in a second direction perpendicular to a first direction that is from the first electrode toward the second electrode. The third region includes a tenth semiconductor region of the first conductivity type located on the first electrode, and a current blocking region located between the sixth semiconductor region and the ninth semiconductor region in the second direction and located on the tenth semiconductor region.

IPC Classes  ?

  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
  • H01L 23/64 - Impedance arrangements
  • H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/66 - Types of semiconductor device

63.

DRONE-HUNTING DRONE, INFORMATION PROCESSING METHOD, AND SYSTEM

      
Application Number 18884396
Status Pending
Filing Date 2024-09-13
First Publication Date 2025-03-27
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA INFRASTRUCTURE SYSTEMS & SOLUTIONS CORPORATION (Japan)
Inventor
  • Yasuda, Takeshi
  • Yoshida, Toshiaki

Abstract

According to an embodiment, a hunting drone includes a hunting mechanism, a net gun, a flying mechanism, and a control unit. The hunting mechanism captures a target. The net gun generates a sound at the time of firing a hunting net. After approaching the target to a predetermined distance, the hunting drone captures the target using the hunting mechanism, while avoiding false recognition of the target by using the sound generated at the time of firing the net gun as a threatening sound to repel a wrong target such as a bird.

IPC Classes  ?

  • G05D 1/683 - Intercepting moving targets
  • A01M 29/16 - Scaring or repelling devices, e.g. bird-scaring apparatus using sound waves
  • F41H 13/00 - Means of attack or defence not otherwise provided for
  • G05D 105/50 - Specific applications of the controlled vehicles for animal husbandry or control, e.g. catching, trapping or scaring of animals
  • G05D 109/20 - Aircraft, e.g. drones
  • G05D 111/30 - Radio signals

64.

MAGNETIC DISK APPARATUS AND METHOD

      
Application Number 18939917
Status Pending
Filing Date 2024-11-07
First Publication Date 2025-03-20
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Maeto, Nobuhiro

Abstract

According to an embodiment, tracks on a magnetic disk each include a long-distance sector having a length in the circumferential direction covering two or more servo sectors. A controller executes an acquisition operation to acquire one or more evaluation amounts on the basis of a track pitch in each of the two or more servo sectors included in a portion adjacent to the long-distance sector. The controller executes a protection operation to protect data of an adjacent track in a case where a total value of the one or more evaluation amounts exceeds a first threshold value.

IPC Classes  ?

  • G11B 20/12 - Formatting, e.g. arrangement of data block or words on the record carriers

65.

SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, INVERTER CIRCUIT, DRIVE DEVICE, VEHICLE, AND ELEVATOR

      
Application Number 18965021
Status Pending
Filing Date 2024-12-02
First Publication Date 2025-03-20
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor Shimizu, Tatsuo

Abstract

A semiconductor device of embodiments includes: a silicon carbide layer having a first face having an off-angle of 0° or more and 8° or less with respect to a {0001} face and a second face opposite to the first face, having a 4H-SiC crystal structure, and including a first silicon carbide region of p-type, a second silicon carbide region of n-type between the first silicon carbide region and the first face, and a third silicon carbide region between the first silicon carbide region and the first face and containing oxygen, the second silicon carbide region disposed between the third silicon carbide region and the first face; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration of 1×1021 cm−3 or more.

IPC Classes  ?

  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
  • H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
  • H01L 29/66 - Types of semiconductor device

66.

BONDED BODY AND CERAMIC CIRCUIT BOARD USING SAME

      
Application Number 18969254
Status Pending
Filing Date 2024-12-04
First Publication Date 2025-03-20
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA MATERIALS CO., LTD. (Japan)
Inventor
  • Fujisawa, Sachiko
  • Suenaga, Seiichi
  • Mori, Yoichiro

Abstract

A bonded body according to an embodiment includes a nitride ceramic member, and a metal member bonded with the nitride ceramic member via a bonding layer. A titanium nitride layer that includes titanium nitride as a major component is formed at a nitride ceramic member and the interface between the bonding layer. The titanium nitride layer includes a location at which an oxygen amount is not less than 1 at %.

IPC Classes  ?

67.

SUSPENSION ASSEMBLY AND DISK DRIVE

      
Application Number 18418869
Status Pending
Filing Date 2024-01-22
First Publication Date 2025-03-20
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Furutani, Kazuhiro

Abstract

According to one embodiment, a suspension assembly includes a support plate, a wiring member provided on the support plate and including a head-mount surface, and a support protrusion which includes a first area having a first height and a second area having a second height smaller than the first height, and a magnetic head including a slider having a placement surface and a medium-facing surface opposed to the placement surface and a head portion provided at the slider, the placement surface being placed on the support protrusion and fixed on the head-mount surface, the medium-facing surface being tilted with respect to the head-mount surface such that a side on the second area is lower than a side on the second area.

IPC Classes  ?

  • G11B 5/48 - Disposition or mounting of heads relative to record carriers
  • G11B 5/60 - Fluid-dynamic spacing of heads from record carriers

68.

SEMICONDUCTOR DEVICE

      
Application Number 18443729
Status Pending
Filing Date 2024-02-16
First Publication Date 2025-03-20
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Tomita, Kouta

Abstract

A semiconductor device includes a first electrode, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a second electrode, a third electrode, and a fourth electrode. The third electrode is arranged along a boundary between adjacent regions of the plurality of regions. The third electrode is not located at a portion of the boundary most distant to the second electrode. The third electrode faces the second semiconductor layer via an insulating body. The fourth electrode is located on the third semiconductor layer. The fourth electrode is connected to the second semiconductor layer, the third semiconductor layer, and the second electrode. A portion of the fourth electrode located at the most distant portion has a Schottky barrier junction with the first semiconductor layer.

IPC Classes  ?

  • H01L 29/40 - Electrodes
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

69.

ACOUSTIC CONTROL APPARATUS, ACOUSTIC CONTROL METHOD, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM

      
Application Number 18583634
Status Pending
Filing Date 2024-02-21
First Publication Date 2025-03-20
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA DIGITAL SOLUTIONS CORPORATION (Japan)
Inventor Goto, Tatsuhiko

Abstract

According to one embodiment, an acoustic control apparatus includes a processor. The processor calculates a frequency characteristic of a filter from 1) a complex volume velocity of a sound radiated from each point sound source based on the number of point sound sources in a simulated rotating sound source and a lobe mode of the simulated rotating sound source, and 2) an acoustic transfer function between a sound receiving point and each point sound source, which is based on a radius of a circle formed by the point sound sources, a horizontal distance between a center of the circle and the sound receiving point, and a vertical distance between the center of the circle and the sound receiving point. The processor calculates the filter from the frequency characteristic of the filter. The processor stores the filter in a storage.

IPC Classes  ?

  • H04S 7/00 - Indicating arrangementsControl arrangements, e.g. balance control

70.

ACOUSTIC SIGNAL PROCESSING APPARATUS AND ACOUSTIC SIGNAL PROCESSING METHOD

      
Application Number 18583988
Status Pending
Filing Date 2024-02-22
First Publication Date 2025-03-20
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA DIGITAL SOLUTIONS CORPORATION (Japan)
Inventor Goto, Tatsuhiko

Abstract

According to an embodiment, an acoustic signal processing apparatus includes processing circuitry. The processing circuitry includes a modulation frequency control unit, frequency shift processing unit, and amplitude control unit. The modulation frequency control unit is configured to control a first modulation frequency based on velocity information indicating a velocity of a sound source. The frequency shift processing unit is configured to perform single-sideband (SSB) modulation on a first acoustic signal in accordance with the first modulation frequency to generate a first modulated acoustic signal. The amplitude control unit is configured to control an amplitude of the first modulated acoustic signal.

IPC Classes  ?

  • H04R 5/04 - Circuit arrangements
  • H04S 7/00 - Indicating arrangementsControl arrangements, e.g. balance control

71.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 18584900
Status Pending
Filing Date 2024-02-22
First Publication Date 2025-03-20
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Sakakura, Seiya

Abstract

According to one embodiment, a method for manufacturing a semiconductor device includes a first process, a second process, and a third process. The first process is performed on a semiconductor member including a first face and a crystal. The first process includes at least one of implanting a first element into a first portion of the semiconductor member from the first face or irradiating the first portion with a particle beam. In the second process, a second element is implanted into a first region of the semiconductor member and is not implanted into a second region of the semiconductor member. The first region and the second region are located between the first face and the first portion. The third process is performed to irradiate the semiconductor member with a first electromagnetic wave from the first face through the first region and the second region, after the second process.

IPC Classes  ?

  • H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
  • H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
  • H01L 29/861 - Diodes

72.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, COMPUTER PROGRAM PRODUCT, AND INFORMATION PROCESSING SYSTEM

      
Application Number 18585470
Status Pending
Filing Date 2024-02-23
First Publication Date 2025-03-20
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA INFRASTRUCTURE SYSTEMS & SOLUTIONS CORPORATION (Japan)
Inventor
  • Aisu, Hideyuki
  • Sakakibara, Shizu
  • Yoshida, Takufumi

Abstract

According to an embodiment, an information processing device includes processors configured to: determine, based on a plurality of pieces of rack data including first identification information of one or more kinds of products housed in each rack, a processing sequence of a plurality of pieces of first order data including second identification information of one or more kinds of products to be picked, and one or more racks from which the products identified by the second identification information are to be picked; and perform hierarchical clustering that repeats processing of merging similar or matching pieces of first order data into a cluster such that a cluster number of a plurality of clusters resulting from the hierarchical clustering becomes equal to or more than a station number of a plurality of work stations where housing containers corresponding to at least some pieces of first order data are placed.

IPC Classes  ?

  • G06Q 10/087 - Inventory or stock management, e.g. order filling, procurement or balancing against orders

73.

DISK DEVICE

      
Application Number 18589341
Status Pending
Filing Date 2024-02-27
First Publication Date 2025-03-20
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor
  • Hoshi, Ryogo
  • Kido, Takuma

Abstract

According to one embodiment, a disk device includes a first adhesive attaching a slider to a suspension. A flexure of the suspension includes an outer surface of a metal plate and an insulator. The insulator surrounds the first adhesive. The insulator includes two first walls, a second wall, and a third wall. The first walls extend closer to each other toward a axis of a carriage. The second wall is spaced apart from the first walls and further away from the axis than the first walls. The third wall is located at a center of the insulator in a circumferential direction and is located between the first walls and the second wall. The third wall is shorter than the second wall. The distance between the second wall and the third wall is shorter than a distance between the first walls and the third wall.

IPC Classes  ?

  • G11B 5/48 - Disposition or mounting of heads relative to record carriers

74.

SEMICONDUCTOR DEVICE

      
Application Number 18589769
Status Pending
Filing Date 2024-02-28
First Publication Date 2025-03-20
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Inokuchi, Tomoaki
  • Gangi, Hiro
  • Kobayashi, Yusuke
  • Baba, Shotaro
  • Nemoto, Hiroki
  • Fukuda, Taichi
  • Sakano, Tatsunori

Abstract

A semiconductor device includes a major element including a first semiconductor region, a first electrode, a second electrode, a first gate electrode, and a first insulating member being positioned between the first gate electrode and the first semiconductor region, and a recording element electrically connected with the first electrode. The recording element records, as analog data, a maximum value of a change amount dV/dt of a voltage of the first electrode over time.

IPC Classes  ?

  • H10B 99/00 - Subject matter not provided for in other groups of this subclass
  • H01L 29/40 - Electrodes
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS

75.

SEMICONDUCTOR DEVICE

      
Application Number 18589964
Status Pending
Filing Date 2024-02-28
First Publication Date 2025-03-20
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor
  • Inokuchi, Tomoaki
  • Shimizu, Tatsuo
  • Kobayashi, Yusuke
  • Baba, Shotaro
  • Gangi, Hiro
  • Nemoto, Hiroki
  • Fukuda, Taichi
  • Nishiwaki, Tatsuya

Abstract

A semiconductor device includes a first conductive part, a second conductive part, a third conductive part, a first insulating part, and a semiconductor part of a first conductivity type. The second conductive part is separated from the first conductive part in a first direction. The third conductive part arranged with a portion of the second conductive part in a second direction crossing the first direction. The first insulating part includes a first insulating region located between the third conductive part and the portion of the second conductive part. The semiconductor part includes a first semiconductor region and a second semiconductor region. The first semiconductor region is located between the first conductive part and the second conductive part. The second semiconductor region is located between the first insulating region and the portion of the second conductive part. The second semiconductor region has a Schottky junction with the second conductive part.

IPC Classes  ?

  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 29/812 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a Schottky gate

76.

DISK DEVICE

      
Application Number 18590756
Status Pending
Filing Date 2024-02-28
First Publication Date 2025-03-20
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Tokizaki, Tomoyuki

Abstract

A disk device according to one embodiment includes a base, a first cover, a second cover, and a damper. The base includes a bottom surface, a side wall protruding in a first direction from the bottom surface, and a support surface located at an end of the side wall in the first direction. The first cover is attached to the base to close the inner space. The second cover is joined to the base while being supported by the support surface, to cover the first cover. The damper includes a constrained layer in-between the first cover and the second cover and a viscoelastic material between the first cover and the constrained layer. The constrained layer includes a smaller-thickness part extending along the support surface and a larger-thickness part connected to the smaller-thickness part.

IPC Classes  ?

  • G11B 5/48 - Disposition or mounting of heads relative to record carriers

77.

SEMICONDUCTOR DEVICE

      
Application Number 18591188
Status Pending
Filing Date 2024-02-29
First Publication Date 2025-03-20
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Inokuchi, Tomoaki
  • Gangi, Hiro
  • Kobayashi, Yusuke
  • Sakano, Tatsunori
  • Shimizu, Tatsuo
  • Baba, Shotaro
  • Fukuda, Taichi

Abstract

The major element includes a first electrode, a second electrode, a first semiconductor layer located between the first electrode and the second electrode, the first semiconductor layer forming a first Schottky junction with the second electrode, and a first gate electrode facing the first Schottky junction. The control element includes a third electrode, a fourth electrode, a second semiconductor layer located between the third electrode and the fourth electrode, the second semiconductor layer forming a second Schottky junction with the fourth electrode, and a second gate electrode facing the second Schottky junction.

IPC Classes  ?

  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 29/40 - Electrodes
  • H01L 29/47 - Schottky barrier electrodes
  • H01L 29/812 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a Schottky gate

78.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM

      
Application Number 18595284
Status Pending
Filing Date 2024-03-04
First Publication Date 2025-03-20
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA INFRASTRUCTURE SYSTEMS & SOLUTIONS CORPORATION (Japan)
Inventor
  • Otsuki, Tomoshi
  • Ogawa, Shinichiro
  • Iyama, Hitoshi
  • Kubo, Hideki

Abstract

An information processing device comprising processing circuitry to acquire information on operations each including an operation duration, a number of vehicles necessary for execution of each operation, and train information including a number of vehicles included in each train, mergeable or splittable among two or more trains; and produce an operation plan by allocating one or more trains to each operation, a total number of vehicles included in the allocated trains to each operation matches the number of vehicles necessary for the operation. Merge work of two or more trains is needed to allocate the two or more trains to one of the operations, and split work of the merged two or more trains is needed to allocate the two or more trains to different ones of the operations. The processing circuitry produces the operation plan based on a merge iteration number or a split iteration number.

IPC Classes  ?

  • G06Q 10/0631 - Resource planning, allocation, distributing or scheduling for enterprises or organisations

79.

ELECTROCHEMICAL REACTION DEVICE AND METHOD OF OPERATING ELECTROCHEMICAL REACTION DEVICE

      
Application Number 18598149
Status Pending
Filing Date 2024-03-07
First Publication Date 2025-03-20
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Mikoshiba, Satoshi
  • Fujiwara, Naoya
  • Kofuji, Yusuke
  • Kudo, Yuki
  • Kitagawa, Ryota

Abstract

An electrochemical reaction device includes: a structure that includes: a cathode; an anode; a diaphragm, a cathode chamber; and an anode chamber; a first to a fourth flow path through which a first to fourth fluid flows respectively; at least one controller selected from a first and a second flow rate controller, a first and a second pressure controller, a temperature controller and a power supply, the controller including the first flow rate controller; a gas/liquid separator in the middle of the fourth flow path; a first flowmeter that measures a flow rate of the third fluid; a second flowmeter that measures a flow rate of the fourth fluid; and a control device that measures the sum of the flow rates of the first, third and fourth fluids and controls the controller according to the sum to control a pressure difference between the chambers.

IPC Classes  ?

  • C25B 9/23 - Cells comprising dimensionally-stable non-movable electrodesAssemblies of constructional parts thereof with diaphragms comprising ion-exchange membranes in or on which electrode material is embedded
  • C25B 1/04 - Hydrogen or oxygen by electrolysis of water
  • C25B 1/23 - Carbon monoxide or syngas
  • C25B 3/26 - Reduction of carbon dioxide
  • C25B 15/021 - Process control or regulation of heating or cooling
  • C25B 15/023 - Measuring, analysing or testing during electrolytic production
  • C25B 15/08 - Supplying or removing reactants or electrolytesRegeneration of electrolytes

80.

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

      
Application Number 18598456
Status Pending
Filing Date 2024-03-07
First Publication Date 2025-03-20
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Japan)
Inventor Arima, Kazusa

Abstract

A manufacturing method a semiconductor device according to an embodiment is a manufacturing method a semiconductor device located on a semiconductor wafer within a region surrounded by a first dicing line extending in a first direction and a second dicing line perpendicular to the first direction, the semiconductor device including a cell region and a termination region, the cell region including a semiconductor device located within a semiconductor substrate, the termination region including a metal wiring line located on the semiconductor substrate and electrically connected to the semiconductor device. In this method, a stopper film is formed around the metal wiring line in the termination region, a protection film covering the metal wiring line and ending at a side surface of the stopper film is formed, and the semiconductor wafer is diced along the first dicing line and the second dicing line.

IPC Classes  ?

  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
  • H01L 21/8234 - MIS technology
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

81.

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM

      
Application Number 18605059
Status Pending
Filing Date 2024-03-14
First Publication Date 2025-03-20
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor Iwamasa, Mikito

Abstract

According to one embodiment, an information processing apparatus comprising a processing circuitry configured to: select, based on a content of an input question, a database corresponding to the question among a plurality of databases respectively storing different kinds of data; generate a prompt to be input to a language model based on the selected database and the question; and generate an answer based on the prompt and the language model.

IPC Classes  ?

  • G06F 40/40 - Processing or translation of natural language

82.

PROCESSING DEVICE, TRAINING DEVICE, PROCESSING SYSTEM, PROCESSING METHOD, AND STORAGE MEDIUM

      
Application Number 18605538
Status Pending
Filing Date 2024-03-14
First Publication Date 2025-03-20
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Zhou, Xinyi
  • Yamamoto, Fumiya
  • Yoshii, Takanori
  • Namioka, Yasuo
  • Tanaka, Takashi
  • Oka, Kazuhiro
  • Kato, Takehiro
  • Nishimura, Keisuke
  • Kotake, Masahiro

Abstract

According to one embodiment, a processing device acquires an image, a coordinate, and dialog data communicated between a first device and a second device. The first device is used by a first person performing a task, and the second device is used by a second person. The processing device extracts at least one of a plurality of the coordinates based on the dialog data. The processing device associates the extracted at least one of the plurality of coordinates with the task.

IPC Classes  ?

  • G06F 40/35 - Discourse or dialogue representation

83.

SEMICONDUCTOR DEVICE

      
Application Number 18625761
Status Pending
Filing Date 2024-04-03
First Publication Date 2025-03-20
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor Kamiya, Shunsuke

Abstract

A semiconductor device according to an embodiment includes: first and second electrodes respectively provided on first and second main surfaces of a semiconductor layer; a first semiconductor region of a first conductivity type; a plurality of insulating regions formed to extend in a second direction orthogonal to a first direction from the second electrode toward the first electrode; a plurality of third electrodes provided in the plurality of insulating regions; a second semiconductor region of a second conductivity type sandwiched between the plurality of insulating regions, formed to extend in the second direction; a third semiconductor region of the first conductivity type located between the second semiconductor region and the first electrode; and a carrier conduction part formed to extend in the second direction in the second semiconductor region and electrically connected to the first electrode via a connection part not penetrating the third semiconductor region.

IPC Classes  ?

  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

84.

INFORMATION PROCESSING APPARATUS, SYSTEM, METHOD AND STORAGE MEDIUM

      
Application Number 18626492
Status Pending
Filing Date 2024-04-04
First Publication Date 2025-03-20
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor Sekiya, Ryota

Abstract

According to one embodiment, an information processing apparatus includes a processor. The processor is configured to acquire a first observation signal from a radar device with a plurality of antennas configured to transmit a radar signal and to receive a radar echo based on a reflected wave of the radar signal, generate a first radar image by executing a signal process based on a predetermined first condition, and generate a second radar image by executing a signal process based on a second condition. The first and second radar images are used as training data for a learning model to detect an object to which the radar signal is transmitted.

IPC Classes  ?

  • G01S 13/04 - Systems determining presence of a target
  • G01S 13/90 - Radar or analogous systems, specially adapted for specific applications for mapping or imaging using synthetic aperture techniques

85.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM

      
Application Number 18664517
Status Pending
Filing Date 2024-05-15
First Publication Date 2025-03-20
Owner
  • KABUSHIKI KAISHA TOSHIBA (Japan)
  • TOSHIBA INFRASTRUCTURE SYSTEMS & SOLUTIONS CORPORATION (Japan)
Inventor
  • Otsuki, Tomoshi
  • Ogawa, Shinichiro
  • Iyama, Hitoshi
  • Kubo, Hideki

Abstract

An information processing device comprises processing circuitry to: acquire pieces of train line information and departure and arrival times at each stop position of a train; split the train line information based on replacement stop positions at which a task for working on the train can switch between staffs, to obtain a plurality of pieces of task fragment information each indicating a task of a staff corresponding to each split train line part; and allocate the pieces of task fragment information to target durations to create work schedules indicating a schedule of tasks for each of the target durations, wherein a series of the tasks continuously allocated in each work schedule corresponds to a basic work schedule, each work schedule includes one or more basic work schedule and the processing circuitry performs allocation of the pieces of task fragment information based on a constraint related to the basic work schedule.

IPC Classes  ?

86.

CONTROL DEVICE, ENERGY MANAGEMENT SYSTEM, AND NON-TRANSITORY COMPUTER READABLE MEDIUM

      
Application Number 18671170
Status Pending
Filing Date 2024-05-22
First Publication Date 2025-03-20
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Lin, Qiang
  • Shijo, Tetsu
  • Kanekiyo, Yasuhiro
  • Ogawa, Kenichiro

Abstract

According to one embodiment, a control device for an electric power system capable of supplying power to load devices in a plurality of demand areas based on first to N-th power devices in first to N-th placement areas and configured to be able to perform at least one of discharge or charge of power, comprising: a controller configured to detect, based on information of power consumption in each of the demand areas, a demand area in which the power consumption fluctuates more significantly than usual, and determine, according to distances between a detected demand area and the first to N-th placement areas, a control parameter related to input and output of power in the first to N-th power devices.

IPC Classes  ?

  • H02J 3/24 - Arrangements for preventing or reducing oscillations of power in networks
  • H02J 3/32 - Arrangements for balancing the load in a network by storage of energy using batteries with converting means
  • H02J 3/38 - Arrangements for parallelly feeding a single network by two or more generators, converters or transformers

87.

TRANSMIT/RECEIVE ANTENNA MODULE, SYSTEM, METHOD, AND STORAGE MEDIUM

      
Application Number 18731848
Status Pending
Filing Date 2024-06-03
First Publication Date 2025-03-20
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor Mori, Hiroki

Abstract

According to one embodiment, a transmit/receive antenna module includes a radar circuit arranged at a substrate, a transmit antenna arranged at a first end portion of the substrate and connected to the radar circuit, a receive antenna arranged at a second end portion of the substrate and connected to the radar circuit. The transmit antenna is capable of transmitting an electromagnetic wave parallel to the substrate. The receive antenna is capable of receiving an electromagnetic wave parallel to the substrate.

IPC Classes  ?

  • H01Q 1/24 - SupportsMounting means by structural association with other equipment or articles with receiving set
  • H01Q 21/24 - Combinations of antenna units polarised in different directions for transmitting or receiving circularly and elliptically polarised waves or waves linearly polarised in any direction
  • H01Q 21/29 - Combinations of different interacting antenna units for giving a desired directional characteristic

88.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND COMPUTER PROGRAM PRODUCT

      
Application Number 18732981
Status Pending
Filing Date 2024-06-04
First Publication Date 2025-03-20
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Matsuoka, Kei
  • Miyachi, Yuki
  • Enamito, Akihiko

Abstract

An information processing device according to an embodiment includes a processor connected to a memory. The processor serves to identify, as resonant frequency of components of a structure, frequency of first-type peaks included in a first-type transfer function waveform representing relationship between amplitude and frequency of output vibration. The output vibration occurs in the components of the structure when the structure is subjected to sweep excitation. The processor serves to calculate a vibration propagation path along which input vibration having the resonant frequency propagates when applied to the structure. The vibration propagation path is calculated based on frequency and half width of second-type peaks included in a second-type transfer function waveform representing relationship between amplitude and frequency of output vibration. The output vibration occurs in at least part of the components of the structure when the input vibration is applied to the structure for a predetermined vibration excitation duration.

IPC Classes  ?

  • G06F 30/20 - Design optimisation, verification or simulation

89.

ELECTRODE, SECONDARY BATTERY, AND BATTERY PACK

      
Application Number 18738194
Status Pending
Filing Date 2024-06-10
First Publication Date 2025-03-20
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Sugizaki, Tomoko
  • Takami, Norio
  • Hoshina, Keigo

Abstract

In general, according to one embodiment, an electrode includes an electrode layer and a film containing F, S, and N. The electrode layer includes at least one of a Li metal or a Li alloy. The film covers at least a part of a surface of the electrode layer. The electrode satisfies the following formula (1): In general, according to one embodiment, an electrode includes an electrode layer and a film containing F, S, and N. The electrode layer includes at least one of a Li metal or a Li alloy. The film covers at least a part of a surface of the electrode layer. The electrode satisfies the following formula (1): 1.5 ≤ I 1 / I 2 ( 1 ) where I1 is an intensity of a first peak that appears in a range of 686 eV or more and 690 eV or less of an F1s spectrum obtained by X-ray photoelectron spectroscopy, and I2 is an intensity of a second peak that appears in a range of 683 eV or more and 685 eV or less of the F1s spectrum.

IPC Classes  ?

  • H01M 4/134 - Electrodes based on metals, Si or alloys
  • H01M 4/02 - Electrodes composed of, or comprising, active material
  • H01M 4/38 - Selection of substances as active materials, active masses, active liquids of elements or alloys
  • H01M 4/62 - Selection of inactive substances as ingredients for active masses, e.g. binders, fillers
  • H01M 10/0525 - Rocking-chair batteries, i.e. batteries with lithium insertion or intercalation in both electrodesLithium-ion batteries
  • H01M 10/0568 - Liquid materials characterised by the solutes
  • H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells

90.

INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, COMPUTER PROGRAM PRODUCT, AND DEVICE

      
Application Number 18753937
Status Pending
Filing Date 2024-06-25
First Publication Date 2025-03-20
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Hamakawa, Yohei
  • Tatsumura, Kosuke

Abstract

An information processing system according to an embodiment includes an information processing device and a solver device. The information processing device generates a plurality of coefficients based on a combinatorial optimization problem, encodes a first coefficient represented by a predetermined first data type into a first identification value represented by a second data type having a smaller data size than the first data type, outputs, to the solver device, coefficient information including the first identification value instead of the first coefficient, acquires ground state information from the solver device, and outputs a solution of the combinatorial optimization problem based on the ground state information. In the solving process, the solver device executes an operation on the first coefficient by using a first restoration value corresponding to the first identification value represented by the restoration information. The first restoration value is expressed by the first data type.

IPC Classes  ?

  • G06F 17/11 - Complex mathematical operations for solving equations

91.

NUCLEIC ACID PROBE, CHEMICAL SENSOR, AND DETECTION METHOD

      
Application Number 18760449
Status Pending
Filing Date 2024-07-01
First Publication Date 2025-03-20
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Sugizaki, Yoshiaki
  • Miki, Hiroko

Abstract

A nucleic acid probe includes first and second nucleic acids. The first nucleic acid includes a binding site. The first nucleic acid includes first to seventh base sequences. The fourth base sequence is complimentary with the third base sequence. The fifth base sequence is complimentary with the second base sequence. The seventh base sequence is complimentary with the sixth base sequence. The binding site is positioned at least between the fourth base sequence and the seventh base sequence. The second nucleic acid includes an eighth base sequence. The eighth base sequence is complimentary with at least a portion of the first base sequence and at least a portion of the second base sequence. A number of bases of the eighth base sequence is more than a number of bases of the second base sequence.

IPC Classes  ?

  • G01N 27/327 - Biochemical electrodes
  • C12N 15/115 - Aptamers, i.e. nucleic acids binding a target molecule specifically and with high affinity without hybridising therewith
  • G01N 33/94 - Chemical analysis of biological material, e.g. blood, urineTesting involving biospecific ligand binding methodsImmunological testing involving narcotics

92.

PROCESSING DEVICE, INSPECTION SYSTEM, PROCESSING METHOD, AND COMPUTER PROGRAM PRODUCT

      
Application Number 18761014
Status Pending
Filing Date 2024-07-01
First Publication Date 2025-03-20
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Sugiyama, Nobukatsu
  • Ooga, Junichiro
  • Oaki, Junji

Abstract

According to one embodiment, a processing device includes a memory and one or more processors coupled to the memory. The one or more processors are configured to: divide shape data of a surface of an inspection object into a plurality of curved surfaces; calculate a plurality of teaching points indicating positions at which the inspection object is inspected by an inspection device mounted on a movable body; calculate a path between curved surfaces transitioning the plurality of curved surfaces and a path in a curved surface transitioning teaching points within the curved surface of each of the plurality of curved surfaces; and calculate, based on the path between the curved surfaces, the path in the curved surface, and movement performance of the movable body, an orbit of the movable body so that an inspection time of the inspection object becomes shorter.

IPC Classes  ?

  • G05B 19/425 - Teaching successive positions by numerical control, i.e. commands being entered to control the positioning servo of the tool head or end effector

93.

LIGHT-RECEIVING DEVICE

      
Application Number 18761384
Status Pending
Filing Date 2024-07-02
First Publication Date 2025-03-20
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Sugizaki, Yoshiaki
  • Nishida, Yasutaka
  • Yoshida, Takashi
  • Yuzawa, Akiko
  • Nagai, Miyu

Abstract

A light-receiving device includes graphene including a light-receiving part; major electrodes electrically connected with the graphene, the major electrodes including a source electrode and a drain electrode, the light-receiving part being positioned between the source electrode and the drain electrode; a gate electrode electrically connected with the light-receiving part of the graphene via capacitive coupling; a circuit part electrically connected with the major electrode and the gate electrode; and an ionic substance contacting the light-receiving part of the graphene. The ionic substance is one of an anion having an acid dissociation constant of not less than 3 or a cation having an acid dissociation constant of not more than 11.

IPC Classes  ?

  • H01L 31/113 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect photo- transistor being of the conductor-insulator- semiconductor type, e.g. metal- insulator-semiconductor field-effect transistor
  • H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
  • H01L 31/028 - Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic System
  • H01L 31/0384 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including other non-monocrystalline materials, e.g. semiconductor particles embedded in an insulating material

94.

WAVEFORM SIGNAL PROCESSING SYSTEM, STRUCTURE EVALUATION SYSTEM, AND WAVEFORM SIGNAL PROCESSING METHOD

      
Application Number 18761806
Status Pending
Filing Date 2024-07-02
First Publication Date 2025-03-20
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Usui, Takashi
  • Ohno, Hiroshi

Abstract

According to one embodiment, a waveform signal processing system according to an embodiment includes a neural network, a learner, and an extractor. The neural network is configured to generate at least first time-series data on noise and second time-series data on a signal other than noise on the basis of input random noise. The learner is configured to update parameters of the neural network on the basis of a loss function including a main limitation term of which a value becomes lower as synthetic time-series data obtained by adding the first time-series data and the second time-series data generated by the neural network and an observed time-series waveform including noise become more similar to each other. The extractor is configured to extract at least one of the first time-series data and the second time-series data generated by the neural network as a target signal on the basis of the parameters updated by the learner.

IPC Classes  ?

95.

INFORMATION PROCESSING DEVICE, QKD NETWORK SYSTEM, INFORMATION PROCESSING METHOD, AND COMPUTER PROGRAM PRODUCT

      
Application Number 18763052
Status Pending
Filing Date 2024-07-03
First Publication Date 2025-03-20
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Tanizawa, Yoshimichi
  • Katsube, Yasuhiro
  • Takahashi, Ririka
  • Yu, Yu

Abstract

According to one embodiment, an information processing device includes a processing circuit as a hardware processor and configured to establish encrypted tunnel communication with a second node by using a second encryption key subjected to encrypted relay transmission to the second node by a first encryption key shared, by quantum key distribution, with a plurality of first nodes adjacent to each other. The second node is one of the plurality of first nodes. The processing circuit is configured to cause a network interface (IF) unit to transfer a third encryption key to the second node by the encrypted tunnel communication.

IPC Classes  ?

  • H04L 9/14 - Arrangements for secret or secure communicationsNetwork security protocols using a plurality of keys or algorithms

96.

ROTATING ELECTRIC MACHINE

      
Application Number 18764230
Status Pending
Filing Date 2024-07-04
First Publication Date 2025-03-20
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Kinouchi, Hiroaki
  • Hagiwara, Masaya
  • Sakurada, Shinya

Abstract

In one embodiment, a rotating electric machine includes a rotor and a stator. The rotor is a rotor which is rotatable around a center axis. The stator surrounds the rotor from one radial side. The stator includes a back yoke, a coil unit, and a plurality of partition units. The back yoke has an annular shape centered on the center axis. The coil unit is disposed on the other radial side of the back yoke. The plurality of partition units partition a winding range in which the coil unit is disposed in a circumferential direction. Each of the partition units includes a magnetic body portion made of a magnetic material. A circumferential dimension of the magnetic body portion is less than a circumferential dimension of the winding range. A radial dimension of the magnetic body portion is ½ or more of a radial dimension of the coil unit.

IPC Classes  ?

  • H02K 3/47 - Air-gap windings, i.e. iron-free windings
  • B64D 27/30 - Aircraft characterised by electric power plants
  • H02K 1/02 - Details of the magnetic circuit characterised by the magnetic material
  • H02K 1/278 - Surface mounted magnetsInset magnets
  • H02K 1/28 - Means for mounting or fastening rotating magnetic parts on to, or to, the rotor structures
  • H02K 21/14 - Synchronous motors having permanent magnetsSynchronous generators having permanent magnets with stationary armatures and rotating magnets with magnets rotating within the armatures

97.

ROTATING ELECTRIC MACHINE

      
Application Number 18764233
Status Pending
Filing Date 2024-07-04
First Publication Date 2025-03-20
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Hagiwara, Masaya
  • Matsuoka, Kei
  • Kinouchi, Hiroaki
  • Sakurada, Shinya

Abstract

A rotating electric machine of an embodiment includes a stator, a rotor, a housing, and a cover member. The stator includes a stator core and a coil. The stator core includes a core back portion. The core back portion has an annular shape centered on a center axis. The coil is attached to the stator core. The coil is located on the radially inside of the core back portion. The coil includes a coil straight portion and a pair of coil end portions. The coil straight portion extends in a straight line shape along the axial direction. The pair of coil end portions respectively protrude in the axial direction from both axial end surfaces of the stator core. The cover member includes a first cover portion. The first cover portion contacts one coil end portion so that the coil end portion is bent toward an inner peripheral surface of the housing and is brought into contact with the inner peripheral surface of the housing.

IPC Classes  ?

  • H02K 1/14 - Stator cores with salient poles
  • H02K 9/22 - Arrangements for cooling or ventilating by solid heat conducting material embedded in, or arranged in contact with, the stator or rotor, e.g. heat bridges

98.

SYSTEM AND STORAGE MEDIUM

      
Application Number 18764678
Status Pending
Filing Date 2024-07-05
First Publication Date 2025-03-20
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Hashimoto, Mikio
  • Shimbo, Atsushi
  • Amemiya, Jiro
  • Tanaka, Hiroshi

Abstract

According to one embodiment, a system includes a central control device connected to a plurality of sub-devices each having an embedded computer. The central control device is configured to detect an anomality caused by a cyberattack, transmit a stop instruction to each of the sub-devices to stop an operation of the system, transmit a restart instruction to each of the sub-devices to restart each of the sub-devices by secure boot, transmit a diagnostic instruction to at least one sub-device to diagnose whether or not physical elements configuring the system are degraded and determine whether or not to resume the operation of the system based on a result of the restart executed in each of the sub-devices and a result of the diagnosis executed in the at least one sub-device.

IPC Classes  ?

  • G06F 21/55 - Detecting local intrusion or implementing counter-measures
  • G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities

99.

CONTROL DEVICE, CONTROL METHOD, AND CONTROL SYSTEM

      
Application Number 18771628
Status Pending
Filing Date 2024-07-12
First Publication Date 2025-03-20
Owner
  • Kabushiki Kaisha Toshiba (Japan)
  • Toshiba Electronic Devices & Storage Corporation (Japan)
Inventor
  • Suzuki, Koji
  • Yamada, Yutaka

Abstract

According to the present embodiment, a control device controlling a control target is provided which includes a first controller, a second controller, a detector, and a corrector. The first controller is configured to, by using a first measured value measured for the control target and a first command value that is a target value of the first measured value as inputs, generate a second command value. The second controller is configured to, by using a second measured value measured for the control target and the second command value as inputs, generate a target value supplied to the control target as a third command value. The detector is configured to detect a change in the second measured value and to change a control mode. The corrector is configured to generate a second correction value and correct the second controller in accordance with the control mode.

IPC Classes  ?

  • H02P 21/22 - Current control, e.g. using a current control loop
  • H02P 7/03 - Arrangements for regulating or controlling the speed or torque of electric DC motors for controlling the direction of rotation of DC motors
  • H02P 21/00 - Arrangements or methods for the control of electric machines by vector control, e.g. by control of field orientation
  • H02P 21/14 - Estimation or adaptation of machine parameters, e.g. flux, current or voltage

100.

ELECTRODE, SECONDARY BATTERY, BATTERY PACK, VEHICLE, AND STATIONARY POWER SUPPLY

      
Application Number 18777156
Status Pending
Filing Date 2024-07-18
First Publication Date 2025-03-20
Owner KABUSHIKI KAISHA TOSHIBA (Japan)
Inventor
  • Yamashita, Yasunobu
  • Hoshina, Keigo

Abstract

An electrode includes a current collector and an active material-containing portion. The current collector has a first porosity, and the electrode including the current collector and the active material-containing portion has a second porosity. The first porosity is 70% or more and 90% or less and the second porosity is 60% or more and 80% or less.

IPC Classes  ?

  • H01M 4/80 - Porous plates, e.g. sintered carriers
  • B60L 50/64 - Constructional details of batteries specially adapted for electric vehicles
  • H01M 4/02 - Electrodes composed of, or comprising, active material
  • H01M 4/66 - Selection of materials
  • H01M 10/36 - Accumulators not provided for in groups
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