The present application relates to a capacitive pressure sensor and a manufacturing method therefor. The capacitive pressure sensor comprises: a substrate; a variable capacitor located on the substrate; and a reference capacitor located on the substrate on one side of the variable capacitor. The variable capacitor and the reference capacitor both comprise a bottom electrode, a top electrode, and a capacitor dielectric located between the bottom electrode and the top electrode. The capacitor dielectric of the variable capacitor comprises an air cavity, and the capacitor dielectric of the reference capacitor comprises a dielectric layer provided with an air groove. The capacitive pressure sensor of the present application comprises the variable capacitor and the reference capacitor at the same time, thereby adding the calibration function, and improving the test precision of the capacitive pressure sensor; the air groove is formed in the dielectric layer of the reference capacitor, so that the capacitance of the reference capacitor can be adjusted by changing the size of the air groove, thereby improving the controllability of the reference capacitor; and since the controllability of the reference capacitor is high, by accurately controlling the reference capacitor according to requirements, the test precision of the capacitive pressure sensor can be improved.
G01L 9/12 - Measuring steady or quasi-steady pressure of a fluid or a fluent solid material by electric or magnetic pressure-sensitive elementsTransmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means by making use of variations in capacitance
B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
2.
DOUBLE-LAYER COMPONENT HAVING ISOLATION STRUCTURE, AND SEMICONDUCTOR DEVICE
A double-layer component having an isolation structure, and a semiconductor device. The double-layer component comprises an upper structure, a lower structure, and an isolation structure located between the upper structure and the lower structure. The isolation structure comprises: a main dielectric layer, located between the lower structure and the upper structure; and a first buffer structure, located on the main dielectric layer and comprising a first buffer layer and a second buffer layer, wherein the material of the second buffer layer comprises silicon nitride and/or silicon oxynitride, and the dielectric constant of the first buffer layer is greater than that of the second buffer layer. By providing the double-layer first buffer structure between the main dielectric layer and the upper structure, wherein the first buffer layer has a higher dielectric constant, the surface electric field intensity can be effectively reduced, thereby improving the withstand voltage of the double-layer component.
The present invention relates to a bidirectional ESD protection device and a manufacturing method therefor. The device comprises a P-substrate; an N-bury layer, which is located on part of the P-substrate; a first P-well region, which is located on the N-bury layer; a P-bury layer, which is located on part of the P-substrate; a second P-well region, which is located on the P-bury layer; a first insulating structure, which is located between the first P-well region and the second P-well region, and between the N-bury layer and the P-bury layer. The present invention optimizes the current discharge path of the bidirectional ESD protection device from the transversal direction into the longitudinal direction, such that the device area can be saved, thereby improving the current discharge capability per unit area of the device.
The present invention relates to an SOI ESD protection device and a manufacturing method therefor. The device comprises: a bottom semiconductor layer having P-type doping; a buried dielectric layer, located on the bottom semiconductor layer; a conductive structure, located on the bottom semiconductor layer, the bottom of the conductive structure being electrically connected to the bottom semiconductor layer; a P-type region, located on the buried dielectric layer and electrically connected to the conductive structure; an N-type region, located on the P-type region; a first P-type doped region, part of the N-type region being located below the first P-type doped region; and an insulating structure, which is located on the conductive structure, and the side surfaces of the first P-type doped region and the N-type region. The present invention uses the bottom semiconductor layer of an SOI as a grounding port of an ESD device, and optimizes the direction of a current discharge path of the SOI ESD protection device from a transverse direction into a longitudinal direction, thus improving the current discharge capacity of unit area of the SOI ESD protection device. Therefore, the area occupied by the SOI ESD protection device on a chip is small.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
5.
ESD PROTECTION DEVICE AND MANUFACTURING METHOD THEREFOR
The present invention relates to an ESD protection device and a manufacturing method therefor. The device comprises: a P-type substrate; a first P-type well region; a first insulating structure, which extends into the P-type substrate and is located on a side surface of the first P-type well region; an N-type region, comprising a lower layer located at the bottom of the first P-type well region and an upper layer located on the lower layer, at least part of the P-type substrate being located below the lower layer; a conductive structure, at least part of the first insulating structure being located between the conductive structure and the first P-type well region and between the conductive structure and the lower layer; a first N-type doped region, located at the bottom of the conductive structure; a second insulating structure, the conductive structure being located between the first insulating structure and the second insulating structure; and a second P-type well region, located on the side of the second insulating structure opposite to the conductive structure, part of the P-type substrate being located below the second P-type well region. The present invention can reduce a trigger voltage of SCRs.
H01L 23/60 - Protection against electrostatic charges or discharges, e.g. Faraday shields
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
6.
ESD PROTECTION DEVICE AND MANUFACTURING METHOD THEREFOR
The present invention relates to an ESD protection device and a manufacturing method therefor. The ESD protection device comprises: a P-type substrate; an N-type region, located above at least part of the P-type substrate; a P-type well region, located on the N-type region; an insulation structure, located on the side of the N-type region and the side of the P-type well region, wherein the bottom depth of the insulation structure is deeper than that of the N-type region; and a conductive structure, wherein at least part of the insulation structure is located between the conductive structure and a transistor body structure, the transistor body structure comprises the P-type well region, the N-type region, and the portion of the P-type substrate below the N-type region, and the bottom of the conductive structure is connected to the P-type substrate. The top of the conductive structure is used for grounding, and the top of the P-type well region is used for connection to an ESD port. In the present invention, the occupied chip area is small.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
7.
SILICON-ON-INSULATOR TRANSVERSE DEVICE AND MANUFACTURING METHOD THEREFOR
The present application relates to a silicon-on-insulator transverse device and a manufacturing method therefor. The device comprises: a substrate; a buried dielectric layer provided on the substrate; a drift region provided on the buried dielectric layer, a vertical conductive structure extending downwards from the drift region to the buried dielectric layer; a low-K dielectric provided in the buried dielectric layer and surrounding the bottom of the vertical conductive structure; and a dielectric layer provided on a side surface of the vertical conductive structure and located between the vertical conductive structure and the drift region and above the low-K dielectric.
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 86/80 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors
The present application relates to a level shift circuit and a level shift device. The level shift circuit comprises a signal output module and a control module; the signal output module comprises a triode; a high-voltage end of the triode is used for receiving a power supply voltage; a low-voltage end of the triode is used for outputting a shift signal; a base of the triode is used for receiving a first control signal; the control module comprises a junction field-effect transistor and an insulated-gate field-effect transistor; a drain of the junction field-effect transistor is connected to the base of the triode and used for outputting the first control signal; the gate of the junction field-effect transistor is grounded; a source of the junction field-effect transistor is connected to a drain of the insulated-gate field-effect transistor; a gate of the insulated-gate field-effect transistor is used for receiving a second control signal; and a source of the insulated-gate field-effect transistor is grounded. According to the level shift circuit of the present application, the power consumption of the level shift circuit during working can be reduced.
UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA (China)
CSMC TECHNOLOGIES FAB2 CO., LTD. (China)
Inventor
Liu, Teng
Chong, Shixiong
He, Nailong
Zhang, Sen
Zhang, Wentong
Zhang, Bo
Zou, Min
Abstract
The present application relates to a laterally diffused metal-oxide-semiconductor device and a preparation method therefor. The laterally diffused metal-oxide-semiconductor device comprises: a substrate structure 11; a first doped region 111, which is arranged in the substrate structure 11; a first well region 115 and a drain region 113, which are arranged in the first doped region 111 at intervals; a source region 112, which is arranged in the first well region 115; a variable-K dielectric layer 12, which is embedded in the first doped region 111 and is located between the first well region 115 and the drain region 113, wherein in a direction from a front surface of the substrate structure 11 to a back surface of the substrate structure 11, a dielectric constant of the variable-K dielectric layer 12 gradually increases; and a super-junction structure 13, which is arranged in the first doped region 111 on the side of the variable-K dielectric layer 12 that is close to the back surface of the substrate structure 11.
The present application relates to a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises a substrate (1), a buried dielectric layer (2), a lateral power device (3), a longitudinal power device (4), and an isolation structure (5). The buried dielectric layer (2) is provided in the substrate, and comprises a first portion having a gradient thickness, and an opening (21) is formed in the buried dielectric layer (2). The lateral power device is provided above the first portion (22) of the buried dielectric layer, and comprises a source region (31) and a drain region (32) spaced apart in a direction parallel to the substrate (1). The longitudinal power device (4) comprises a well region (41), a drift region (42), a source region (43), and a drain region (44); the well region (41) is located in the substrate (1) above the opening (21) of the buried dielectric layer (2); the source region (43) is located in the well region (41), the drift region (42) passes through the opening (21) of the buried dielectric layer (2) and the well region (41), and comprises a region of the substrate (1) located below the buried dielectric layer (2); and the drain region (44) is located at the bottom of the drift region (42). The isolation structure (5) is located in the substrate (1) between the lateral power device (3) and the longitudinal power device (4), and has the bottom connected to the buried dielectric layer (2). The present application can expand the application of SOI high voltage integrated circuits.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
11.
MEMORY CELL, MEMORY, CHIP AND MEMORY CELL MANUFACTURING METHOD
The present application relates to a memory cell, a memory, a chip and a memory cell manufacturing method. The memory cell (200) comprises: a tunneling oxide layer (210), which is formed by a first oxide layer (120) and is arranged on a second silicon layer (130); a floating gate layer (220), which is formed by a first silicon layer (110) and is arranged on the tunneling oxide layer (210); an intermediate oxide layer (230), which is arranged on the floating gate layer (220); a control gate layer (240), which is arranged on the intermediate oxide layer (230); a control electrode (250), which is arranged on the control gate layer (240); and a source electrode (260) and a drain electrode (270), which are arranged on the second silicon layer (130) and are respectively arranged on two sides of the control electrode (250). In the present application, a channel operation area of a memory cell is in a second silicon layer, the second silicon layer of a DSOI wafer is not required to be fully depleted and the thickness of the second silicon layer can be far greater than that of a first silicon layer, so that a large current required by a write operation based on a hot carrier effect can be provided, so as to complete electron writing and erasing.
The present application relates to a trench substrate lead-out structure, a manufacturing method therefor and a semiconductor device. The method comprises: forming a main trench in a substrate; forming a heavily doped region in the substrate on a side surface of the main trench, the conductivity type of the heavily doped region being the same as that of the substrate; forming a metal-semiconductor structure, the metal-semiconductor structure extending from the top of the heavily doped region to the side surface of the main trench close to the heavily doped region and continuing to extend to the bottom of the main trench, and a metal-semiconductor structure being formed at partial positions at the bottom of the main trench, or no metal-semiconductor structure being formed at the bottom of the main trench; and filling the main trench with a first insulating material. The method has larger collection area for substrate carriers, thus more effectively collecting current formed by substrate carriers, and preventing occurrence of latch up.
The semiconductor device comprises a high-voltage device region, a low-voltage device region, and an isolation region. It further comprises a drift region, a second conductivity type well region, an isolation well region, an isolation structure, a power device source region, and a power device drain region. The drift region is disposed in the high-voltage device region. The second conductivity type well region is disposed in the isolation region and extends to the low-voltage device region. The isolation well region is disposed in the drift region and separates the drift region into a high-voltage drift region and a power device drift region. The isolation structure is disposed in the isolation well region. The power device source region is disposed in the isolation region and located in the second conductivity type well region, and the power device drain region is disposed in the power device drift region.
The present application relates to a semiconductor device, an isolation structure, and a manufacturing method for an isolation structure. The isolation structure comprises: a buried region (222) located in a substrate (210); a second conductive type region (230) located on the buried region (222); a second conductive type buffer layer (233) located in the second conductive type region (230), the doping concentration of the second conductive type buffer layer (233) being greater than that of the second conductive type region (230); first well regions (224) located on the second conductive type buffer layer (233), the doping concentration of the first well region (224) being less than that of the second conductive type buffer layer (233); and second well regions (220) located on the buried region (222), the second well regions (220) surrounding the second conductive type buffer layer (233) and the first well regions (224) in the transverse direction. In the present application, the second conductive type buffer layer has enough upward anti-diffusion capability for the second conductive type region above, and can also provide better RESURF capability for a drift region of a device body, so as to obtain higher isolation withstand voltage.
A laterally-diffused metal-oxide-semiconductor device (1), comprising: a substrate (11); a body region (1131) and a drift region (1132) arranged in the substrate (11) in a first direction, a drain region (1133) being provided in the drift region (1132), and a source region (1134) being provided in the body region (1131); a first dielectric layer (121) arranged on the substrate (11) and covering at least part of the body region (1131) and part of the drift region (1132); a first field plate (13) arranged on the side of the first dielectric layer (121) that is away from the substrate (11), the orthographic projection of the first field plate (13) on the substrate (11) being located between the body region (1131) and the drain region (1133), and covering part of the drift region (1132); and a first high-K dielectric layer (141) arranged on the side of the first dielectric layer (121) that is away from the substrate (11) and connected to the end of the first field plate (13) that is close to the drain region (1133), the orthographic projection of the first high-K dielectric layer (141) on the substrate (11) covering part of the drift region (1132).
A laterally diffused metal oxide semiconductor device, and a preparation method therefor. The laterally diffused metal oxide semiconductor device comprises at least one cellular structure (10), the cellular structure (10) comprising: a substrate (11); an N-type first well region (12), disposed in the substrate (11); a first section (121), a partition region (122) and a second section (123), provided in the first well region (12) in sequence along a first direction; a P-type first doped region (131) and a P-type second doped region (132), the first doped region (131) being located in the first section (121) and the second doped region (132) being located in the second section (123); and a P-type source region (141) and a P-type drain region (142) provided in the substrate (11) and located at two sides of the first doped region (131), respectively, along a second direction. The first direction is a width direction of a conductive channel, and the second direction is a length direction of the conductive channel.
The present application relates to a semiconductor device with an isolation structure, and a manufacturing method for an isolation structure. The semiconductor device comprises: a substrate (110); a first doped region (112), which is located on the substrate (110), wherein the doping concentration of the first doped region (112) is below the doping concentration of the substrate (110); a junction isolation structure, which comprises a first buried region (122), and a second buried region (124) which is in direct contact with the first buried region (122), wherein the first buried region (122) is located on the first doped region (112), the second buried region (124) is located on the first buried region (122), and the doping concentration of the second buried region (124) is below the doping concentration of the first buried region (122); a second doped region (130), which is located on the second buried region (124); and a device body region (140), which is located in the second doped region (130). In the present application, a hole barrier layer is formed on surfaces of the first buried region and second buried region, such that holes can be prevented from passing through the hole barrier layer to transit to the substrate to cause substrate electric leakage, thereby improving the latch-up effect of a device. Moreover, since a first doped region is provided, the width of an effective base region can be increased by using a base widening effect, thereby effectively reducing parasitic leakage flowing into a substrate.
An electrostatic discharge (ESD) protection device and a manufacturing method therefor. The ESD protection device comprises: an N well (122), a P well (124), a first P-type region (132), a second P-type region (134), a third P-type region (136), and a first N-type region (142). The first P-type region (132) is located in the N well (122). The second P-type region (134) is located in the N well (122). The third P-type region (136) is located in the P well (124). The first N-type region (142) is located in the P well (124). The second P-type region (134) is in short circuit connection to the third P-type region (136), the first P-type region (132) and the N well (122) are connected to an anode, and the first N-type region (142) and the P well (124) are connected to a cathode.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
19.
LATERALLY-DIFFUSED METAL-OXIDE SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREFOR
The present application relates to a laterally-diffused metal-oxide semiconductor device and a preparation method therefor. The laterally-diffused metal-oxide semiconductor device comprises: a substrate 10; a first doped region 111, which is arranged in the substrate 10; a second doped region 123, which is arranged in the substrate 10 and is located on the side of the first doped region 111 close to a surface of the substrate 10; a first trench 13, which is arranged in the substrate 10 and is open from the surface of the substrate 10 and extends to the first doped region 111 to expose part of the first doped region 111; a drain region 121, which is arranged in the exposed part of the first doped region 111; a source region 122, which is arranged in the substrate 10; a gate 20, which is arranged on the side of the source region 122 away from the drain region 121; and a well region 124, which is arranged in the substrate 10, wherein the well region 124 extends towards the first doped region 111 from the surface of the substrate 10 and is adjacent to the second doped region 123, and the well region 124 is located between the gate 20 and the drain region 121.
The present invention relates to an SOI semiconductor structure and a manufacturing method therefor. The method comprises: providing a wafer, wherein the wafer comprises a substrate, a buried dielectric region on the substrate, and a top semiconductor layer in the buried dielectric region; patterning the wafer, and exposing the substrate in a longitudinal device region; forming a first insulating isolation portion on a side face of the longitudinal device region; forming a first conductivity type region in the longitudinal device region by means of epitaxy; by means of a CMOS process, forming a CMOS device in a first device region, and forming a first well region and a first source region in the longitudinal device region, wherein the first well region is formed in the first conductivity type region, and the first source region is formed in the first well region; and forming a first drain region at the bottom of the substrate.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
21.
SCHOTTKY BARRIER DIODE, LDMOSFET INTEGRATED WITH SCHOTTKY BARRIER DIODE, AND MANUFACTURING METHOD THEREFOR
The present application relates to a Schottky barrier diode, comprising: a well region having a first conductivity type; a body region (124) provided at the upper portion of the well region and having a second conductivity type, the body region (124) being penetrated by a trench (131), and the bottom of the trench (131) extending into the well region; and a first cobalt silicide layer (142), which is formed on the bottom surface and the inner wall of the trench (131), the first cobalt silicide layer (142) forming a Schottky contact with the well region. The well region serves as a cathode of the Schottky barrier diode, and the first cobalt silicide layer (142) which is in direct contact with the well region serves as an anode of the Schottky barrier diode, the first conductive type and the second conductive type being opposite conductive types. The present application uses the bottom surface and the inner wall of the trench to form a Schottky contact of a U-shaped structure between the first cobalt silicide layer and the well region, so that a relatively large Schottky contact area can be obtained by means of a relatively small planar area. In addition, since the Schottky contact is formed by the cobalt silicide, the overcurrent capacity thereof is high.
The present application relates to a gallium nitride power device and a preparation method therefor. The device comprises a voltage-withstanding region, and the voltage-withstanding region comprises a first conductivity type doped region, a second conductivity type doped region, a plurality of resistor structures, a plurality of conductive structures, a drain doped region and a first drain. The first conductivity type doped region and the second conductivity type doped region are arranged in a substrate, and the resistor structures are arranged on the substrate; two ends of each conductive structure are each connected to one resistor structure, so that the resistor structures are connected in series; and the bottom of one conductive structure is electrically connected to the second conductivity type doped region, and the bottoms of the remaining conductive structures are electrically connected to the first conductivity type doped region. The drain doped region is arranged in the substrate, and the first conductivity type doped region is located between the second conductivity type doped region and the drain doped region, the first drain is arranged on the drain doped region, and the bottom of the first drain is electrically connected to the drain doped region.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
The present invention relates to an isolation structure, comprising: a junction terminal comprising a plurality of junction terminal floating field plates; and a lateral double-diffused metal-oxide-semiconductor (LDMOS) field effect transistor comprising a plurality of LDMOS floating field plates, wherein each LDMOS floating field plate is electrically connected to at least one junction terminal floating field plate, and the length of each junction terminal floating field plate is greater than the length of the LDMOS floating field plate electrically connected to the junction terminal floating field plate.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
24.
CAPACITOR, ISOLATION TRANSFORMER, AND SEMICONDUCTOR DEVICE
The present invention relates to a capacitor, an isolation transformer, and a semiconductor device. The isolation transformer comprises: a first dielectric layer of a lower coil, wherein the first dielectric layer covers the lower coil and has a dielectric constant greater than that of silicon dioxide; a main dielectric layer located on the first dielectric layer; a second dielectric layer located on the main dielectric layer, wherein the second dielectric layer has a dielectric constant greater than that of silicon dioxide; an upper coil located on the second dielectric layer; and a third dielectric layer covering the upper coil, wherein the third dielectric layer has a dielectric constant greater than that of silicon dioxide.
The present application relates to a silicon-on-insulator semiconductor component, comprising: a substrate; a buried dielectric layer, provided on the substrate; a first electrode; a second electrode; and a drift region, provided on the buried dielectric layer. A drop structure is formed on the upper surface of the drift region, the drop structure comprising a first side close to the first electrode, a second side close to the second electrode and a transition region between the first side and the second side, and the upper surface of the second side being higher than the lower surface of the first side, such that the thickness of the drift region on the second side is greater than the thickness of same on the first side; the first electrode and the second electrode are configured such that: when reverse bias is applied to the component, a voltage applied to the second electrode is greater than a voltage applied to the first electrode.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
The present application relates to a laterally diffused metal oxide semiconductor device and a preparation method therefor. The laterally diffused metal oxide semiconductor device comprises: a substrate (10), wherein a back electrode (40) is provided on the substrate (10); a buried dielectric layer (20) provided on the substrate (10); and a top silicon layer (30) provided on the buried dielectric layer (20). A drift region (31), a source lead-out region (32) and a drain lead-out region (33) are provided in the top silicon layer (30); the source lead-out region (32) and the drain lead-out region (33) are respectively located on two sides of the drift region (31) along a first direction; the first direction is perpendicular to the thickness direction of the substrate (10); the orthographic projection of the drain lead-out region (33) on the substrate (10) is located within the orthographic projection range of the buried dielectric layer (20) on the substrate (10); the orthographic projection of the substrate (10) on the top silicon layer (30) covers the drain lead-out region (33); and the source lead-out region (32) is located outside the orthographic projection range of the substrate (10) on the top silicon layer (30). The present application not only overcomes the disadvantage that the drain end of an ultra-thin top silicon device cannot be used, but also can increase the longitudinal voltage of the drain end when the top silicon layer is thin, thereby increasing the withstand voltage of the device.
The present application relates to an integrated circuit having an electrostatic discharge protection structure. The integrated circuit comprises: a first metal connecting line region (172); a first well region (122), which is electrically connected to the first metal connecting line region (172) by means of a conductive structure in a first contact hole (162) above the first well region (122); a first isolation well (132), which has a first conductivity type; a second isolation well (134), which has a second conductivity type, wherein the first isolation well (132) is located between the second isolation well (134) and the first well region (122); a second well region (136), which has the first conductivity type, wherein at least part of the structure of the second isolation well (134) is located between the second well region (136) and the first isolation well (132); a second metal connecting line region (174), which is electrically connected to the second isolation well (134) by means of a conductive structure in a second contact hole (166) below the second metal connecting line region (174); and a third metal connecting line region (173), which is electrically connected to the second well region (136) by means of a conductive structure in a third contact hole (168) below the third metal connecting line region (173). In the present application, an ESD current is discharged by means of a parasitic triode, such that a relatively good ESD protection effect can be achieved.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
The present application relates to a power management module and method, and a multi-time programmable nonvolatile memory. The power management module comprises: a working state detection unit (110) that outputs a starting signal upon detecting that a main circuit is in a working state, and outputs a turn-off signal upon detecting that the main circuit is in a non-working state; an LDO circuit (120) that is turned off upon receiving the turn-off signal, is started upon receiving the starting signal, and outputs a first working voltage; a rapid voltage generation unit (130) that is turned off upon receiving the turn-off signal, is started upon receiving the starting signal, and outputs a second working voltage; a selector (140) that receives the first working voltage and the second working voltage, outputs the first working voltage after the LDO circuit (120) is started, and outputs the second working voltage when the rapid voltage generation unit is started but the LDO circuit (120) is not started; and a starting detection unit (150) that controls, upon detecting that the LDO circuit (120) is started, the rapid voltage generation unit to be turned off. The present application can solve the problems caused by high circuit power consumption and slow LDO starting.
The present application relates to an insulated gate bipolar transistor and a manufacturing method therefor. The method comprises: obtaining a wafer, the wafer comprising a substrate; performing emitter doping on the substrate, forming an emitter doped region of a first conductivity type; forming an interlayer dielectric layer on the substrate; coating a photoresist layer on the interlayer dielectric layer, and performing contact hole lithography on the photoresist layer, forming a contact hole etching window above the emitter doped region; etching downwards through the contact hole etching window to form a first hole; and after forming the first hole, performing thermal annealing on the wafer. The application avoids the influence of wafer warping on the alignment precision of contact hole lithography, thereby improving the alignment precision of contact hole lithography.
In a manufacturing method for an LDMOS integrated device, a provided semiconductor substrate has an NLDMOS area and a PLDMOS area; then a dielectric layer on the NLDMOS area and a dielectric layer on the PLDMOS area are formed on the semiconductor substrate, and a stress material layer is formed on the dielectric layer on the NLDMOS area and/or on the dielectric layer on the PLDMOS area, the thickness of the dielectric layer on the NLDMOS region being greater than the thickness of the dielectric layer on the PLDMOS region; then heat treatment is performed to adjust the stress of the stress material layer, so as to improve the electron mobility of a device; then the stress material layer is removed.
The present application relates to a semiconductor device having an isolation structure, and a manufacturing method for the isolation structure. The semiconductor device comprises: a substrate (110), having a second conductivity type; a junction isolation structure, comprising a first buried region (122) and a second buried region (124) in direct contact with the first buried region, wherein the first buried region (122) is located on the substrate (110) and has a first conductivity type, the second buried region (124) is located on the first buried region (122) and has the first conductivity type, and the doping concentration of the second buried region (124) is less than the doping concentration of the first buried region (122); a second conductivity type region (130), located on the second buried region (124); and a device body region, located in the second conductivity type region (130), wherein the junction isolation structure is used for performing insulation isolation on the substrate and the second conductivity type region. According to the present application, a hole blocking layer is formed on an interface between the first buried region and the second buried region, so that holes can be prevented from passing through the hole blocking layer to transit to the substrate to form substrate leakage, and a latch-up effect of a device is mitigated.
The present disclosure relates to a single-photon avalanche diode integrated with a quenching resistor and a manufacturing method thereof. The method includes: obtaining a wafer; patterning and etching a front surface of the base to form a quenching resistor trench and an isolation trench, wherein a width of the isolation trench is greater than a width of the quenching resistor trench; forming an insulation layer on an inner surface of the quenching resistor trench; depositing polycrystalline silicon on the front surface of the base, where the polycrystalline silicon is filled into the quenching resistor trench and seals the quenching resistor trench while the polycrystalline silicon is filled into the isolation trench and does not seal the isolation trench; performing oxidation treatment on the polycrystalline silicon in the isolation trench; filling a light-shielding conductive material into the isolation trench.
H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
The present application relates to a semiconductor device, comprising a high-voltage device region (20), a low-voltage device region (30), a first device region (10), and a first isolation structure (22) located between the high-voltage device region (20) and the low-voltage device region (30), and further comprising a first isolation region (12). The first isolation region (12) is connected to the first isolation structure (22), and the first isolation region (12) and the first isolation structure (22) together surround the first device region (10). The first isolation region (12) comprises: an isolation well (124) having a second conductivity type and connected to the first isolation structure (22); and a second isolation structure (122) extending downwards from the top of the isolation well (124) to pass through the bottom of the isolation well, so that the depth of the second isolation structure (122) is greater than the depth of the isolation well (124). The second isolation structure comprises an insulating medium.
The present application relates to a digital filter module, an ADC unit, an ADC array, and a conditioner chip. The conditioner chip comprises a thermopile array (11), an amplifier array (12), an ADC array (13), an RAM storage unit array (14), an analog module (15), and an I/O functional module (16). The ADC array (13) comprises a plurality of modulators (1312), a plurality of digital filter modules (1311), and a plurality of look-up tables (1313). Each digital filter module (1311) comprises: a multiplier, which is used for performing multiple multiplication on signals output by the modulators and coefficients of the look-up tables to obtain a plurality of multiplication results; an accumulator, which is connected to the multiplier and is used for processing the plurality of multiplication results so as to obtain a processing result; and a down-sampling unit, which is connected to the accumulator and is used for performing down-sampling on the processing result output by the accumulator, so as to obtain an output signal.
A semiconductor device having a split gate structure and a method for manufacturing the same. The method includes: obtaining a base formed with a trench; forming a trench wall oxide isolation dielectric on the inner surface of the trench, and forming a split gate by filling the trench with a split gate material; forming a first oxide isolation dielectric on the split gate; forming a silicon nitride isolation dielectric on the first oxide isolation dielectric; filling a second oxide isolation dielectric above the split gate in the trench in the position where the silicon nitride isolation dielectric is not formed; and forming a control gate on the second oxidation isolation dielectric. The isolation structure between the split gate and the control gate is a multi-dielectric structure which has a higher gate-source voltage resistance compared to the those using a single layer of oxide dielectric.
The present disclosure involves a semiconductor device and a manufacturing method thereof. A second well region is inserted between first well regions of a semiconductor device to improve the breakdown voltage of the device, and at the same time, the dimension of the upper surface of the second well region in the width direction of the device's conductive channel is set to be smaller than the dimension of the lower surface of the second well region in the width direction of the device's conductive channel to increase the dimension of the upper surface of the adjacent first well region in the width direction of the device's conductive channel. That is, the path width of the current flowing through the upper surface of the drift region is increased when the device is on, and thus the device's on-resistance is reduced.
A forming method for a floating contact hole, and a semiconductor device. The method comprises: obtaining a substrate, and forming a tunnel oxide layer and a plurality of gates on the substrate; forming a metal silicide barrier layer; forming a self-aligned metal silicide; forming an interlayer dielectric layer; performing photoetching on the interlayer dielectric layer to obtain a photoresist pattern, the photoresist pattern comprising a small adhesive strip in the middle of the floating contact hole; and etching the floating contact hole by using the photoresist pattern as an etching mask layer.
The present application relates to a gallium nitride semiconductor device and a preparation method therefor. The gallium nitride semiconductor device (1) comprises: a substrate (10); a first gallium nitride layer (21), which is arranged on the substrate; a first dielectric layer (22), which is arranged on the first gallium nitride layer (21); and a first gate electrode (23), which is arranged on the first dielectric layer (22). According to the gallium nitride semiconductor device and the preparation method therefor provided in the present application, a first dielectric layer (22) is provided between a first gate electrode (23) and a first gallium nitride layer (21). In this way, a high-concentration two-dimensional electron gas, which is generated by means of the first dielectric layer and the first gallium nitride layer due to a polarization effect, can consume a hole in a region where the first gate electrode is located, so as to improve a threshold voltage of the device; and compared with a gallium nitride semiconductor device which is not provided with a first dielectric layer, insofar as it is ensured that a device is in an enhancement mode, the present application can make the thickness of the first gallium nitride layer below the first gate electrode greater, so as to reduce the on-resistance of the device, thereby improving an output current of the device.
The present disclosure provides a GGNMOS transistor structure, an ESD protection device, and an ESD protection circuit. The GGNMOS transistor structure can increase a capability of the ESD protection device to discharge an ESD current per unit size under the action of a P-N-P-N parasitic thyristor formed by an N-potential well, a P-type heavily doped region, and an N-type heavily doped region; the GGNMOS transistor structure can limit a transient peak current of ESD under the action of an equivalent resistor formed by an N-potential well, so that respective GGNMOS transistors of the ESD protection device can conduct uniformly, improving the reliability of the ESD protection circuit.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action
40.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
The present application relates to a semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a substrate (210); a first-conductivity-type buried layer (222) located in the substrate (210); a device main body portion located above the first-conductivity-type buried layer (222); and a body lead-out structure, which comprises a low-resistance structure (264), which is located above the first-conductivity-type buried layer (222) and on an outer side of the device main body portion, wherein the low-resistance structure (264) is a vertical downwards-extending structure, and the low-resistance structure (264) is made of at least one of a metallic material and an alloy material.
A manufacturing method for a semiconductor device includes: forming an etching termination layer, a first dielectric layer, an auxiliary dielectric layer and a second dielectric layer which are successively stacked from bottom to top; by taking a photoresist layer as an etching barrier layer, patterning the second dielectric layer to obtain a first opening pattern, the bottom of the first opening being provided with a second opening pattern exposing part of the auxiliary dielectric layer; forming a first trench passing through the second dielectric layer and the auxiliary dielectric layer and extending to the first dielectric layer, and forming a second trench passing through the first dielectric layer from the bottom of the first trench and extending to the etching termination layer; and forming a conductive layer in the first and second trenches.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
42.
SEMICONDUCTOR DEVICE WITH ISOLATION STRUCTURE, AND MANUFACTURING METHOD THEREFOR
The present application relates to a semiconductor device with an isolation structure, and a manufacturing method therefor. The semiconductor device comprises: a substrate (210), which has a second conduction type; a first conductive buried layer (222), which has a first conduction type and is located in the substrate (210), wherein the first conduction type and the second conduction type are opposite conduction types; a first electrode doped region (242), which has the first conduction type and is located above the first conductive buried layer (222); a second electrode doped region (244), which has the first conduction type and is located above the first conductive buried layer (222) and on two sides of the first electrode doped region (242); and an isolation structure, which is provided with an isolation groove and comprises an insulating layer (228) that is located on a side wall of the isolation groove, wherein the isolation groove extends downwards from the second electrode doped region (244) to the first conductive buried layer (222), and a conductive structure (226) electrically connected to the first conductive buried layer (222) is also provided in the isolation groove.
A double-layer component having an isolation structure, and a semiconductor device. The double-layer component comprises an upper-layer component structure, a lower-layer component structure, and an isolation structure located between the upper-layer component structure and the lower-layer component structure. The isolation structure comprises: a main dielectric layer, located between the lower-layer component structure and the upper-layer component structure; and a first hafnium oxide layer, located on the main dielectric layer, wherein the upper-layer component structure is located on the first hafnium oxide layer. Hafnium oxide has a high wide band gap and a high dielectric constant, and thus can effectively reduce the electric field intensity on a dielectric surface and further improve the withstand voltage of a device.
A laterally diffused metal oxide semiconductor device and a preparation method thereof are disclosed. The semiconductor device includes: a substrate; a body region having a first conductivity type and formed in the substrate; a drift region, having a second conductivity type, formed in the substrate and adjacent to the body region; a field plate structure, formed on the drift region, a lower surface of an end of the field plate structure close to the body region being flush with the upper surface of the substrate, and the end of the field plate structure close to the body region also having an upwardly extending inclined surface; and a drain region, having a second conductivity type, formed in an upper layer of the drift region, and in contact with the end of the field plate structure away from the body region.
A reverse conducting lateral insulated-gate bipolar transistor includes a drift region formed on a substrate, a gate located on the drift region, an emitter region located on the drift region and close to one side of the gate, and a collector region located on the drift region and away from one side of the gate. Two or more N-well regions arranged at intervals are provided on the side of the drift region where the collector region is located. A P-well region is provided between the two or more N-well regions arranged at intervals; a P+ contact region is provided on the N-well region; an N+ contact region is provided on the P-well region; both the P+ contact region and the N+ contact region are conductively connected to a collector lead-out end.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
The present disclosure provides a DMOS device with a junction field plate and its manufacturing method. A drain region is located on a surface of a semiconductor substrate. A source region is located in the semiconductor substrate at a bottom of a first trench. A gate electrode is located at the bottom of the first trench. The junction field plate improves an effect on reducing surface resistance. At the same time, a depth of trenches in the DMOS device may be reduced, and thereby a depth-to-width ratio of the device is reduced, improving the feasibility of increasing a voltage resistance level. Both the source region and the drain region in the DMOS device are led out on a same surface. A second doped polycrystalline silicon layer includes a first doped sublayer and a second doped sublayer with different conduction types.
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
47.
TRENCH ISOLATION STRUCTURE, MANUFACTURING METHOD THEREFOR, AND SEMICONDUCTOR STRUCTURE
The present application relates to a trench isolation structure, a manufacturing method therefor, and a semiconductor structure. The bottom of the trench isolation structure is located in a substrate (110), and the trench isolation structure comprises insulation materials (210) provided in a trench, and a conductive structure (222) extending from the top to the bottom of the trench, wherein the bottom of the conductive structure (222) is electrically connected to the substrate (110), and the conductive structure (222) is used for grounding or connecting a potential lower than a cathode during operation. The present application is provided with the conductive structure extending from the top to the bottom of the trench, the bottom of the conductive structure is electrically connected to the substrate, and the top thereof is led out and grounded, such that hole currents can be collected by means of the conductive structure so as to prevent the currents from flowing to the substrate, thereby further enhancing the electrical isolation effect of the trench isolation structure.
The present application relates to a method for manufacturing an insulated gate bipolar transistor, comprising: providing a substrate; annealing the back surface of the substrate; removing surface oxide on the back surface of the substrate; and performing hydrogen plasma treatment on the back surface of the substrate to reduce oxide in a near-surface layer on the back surface of the substrate. In this way, hydrogen ions in a plasma state can reduce silicon oxide (formed during annealing) in a shallow surface layer of the substrate. On one hand, the situation that leakage of devices is increased due to the fact that further penetration of silicon oxide affects a field stop injection concentration is avoided, and then the performance of the devices is improved. On the other hand, an ohmic contact between metal on the back surface and the substrate is prevented from being affected by silicon oxide, so that a turn-on voltage of devices is reduced, and the convergence of device parameters is improved. Additionally, the hydrogen ions in the plasma state cannot damage the back surface of the substrate, the physical bombardment onto the back surface of the substrate is avoided, and the damage to the substrate is prevented, so that a doping dose of a collector is prevented from being affected by the damage to the substrate, and the convergence of device parameters is further improved.
A crystal oscillator starting control circuit (120) and method, a crystal oscillator apparatus, and an SOC chip. The circuit (120) comprises: a logic circuit (122); and a linear voltage regulator (124) for determining, according to a first signal output by the logic circuit (122), a voltage of a power supply signal output to a crystal oscillator (110), the power supply signal being used as a power supply of the crystal oscillator (110). The logic circuit (122) is further used for detecting a clock signal output by the crystal oscillator (110), and if the logic circuit (122) detects a clock signal output by the crystal oscillator (110) within a preset duration after the first signal is output, the logic circuit (122) changes the output first signal, so as to reduce the voltage of the power supply signal output by the linear voltage regulator (124) until a clock signal is not detected within the preset duration, and at this time, the logic circuit (122) changes the first signal once again so as to increase the voltage of the power supply signal, and supply same as a stable power supply signal to the crystal oscillator (110). The LDO output voltage can be flexibly lowered according to the oscillation starting condition of the crystal oscillator, thus reducing the power consumption of the crystal oscillator as much as possible.
The present invention relates to a capacitor structure and a semiconductor device. The capacitor structure comprises: a lower plate, a main dielectric layer that covers the lower plate, a silicon oxynitride layer located on the main dielectric layer, and an upper plate located on the silicon oxynitride layer. In the present invention, the silicon oxynitride layer is provided between the main dielectric layer and the upper plate, which can reduce the influence of a high-voltage region on a low-voltage region while ensuring the withstand voltage of the device, thereby prolonging the overall service life of the device.
The present disclosure provides an electrostatic discharge protection device. The electrostatic discharge protection device comprises a substrate and a gate structure located on the substrate, wherein a first well region and a second well region connected to each other are formed in the substrate, the first well region has a first conductivity type, and the second well region has a second conductivity type; the gate structure spans from above part of the first well region to above part of the second well region, a first doped region and a second doped region located on one side of the gate structure are formed at the top of the first well region, the first doped region has a first conductivity type, and the second doped region has a second conductivity type; a third doped region and a fourth doped region located on the other side of the gate structure are formed at the top of the second well region, the third doped region has a first conductivity type, and the fourth doped region has a second conductivity type. In this way, a first parasitic triode and a second parasitic triode for discharging static electricity can be formed in the electrostatic discharge protection device, which facilitates improvement of the electrostatic discharge capability of a circuit.
The present application relates to a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: an isolation tray (118) having a first conductivity type; an injection assistance structure comprising a plurality of grooves filled by a filler; a first well region (112) which has the first conductivity type, continues extending downward from the bottom of the injection assistance structure, and is located below the isolation tray (118); and a second well region (114), which has the first conductivity type, and is located below the isolation tray (118) and above the first well region (112); the injection assistance structure passes through the second well region (114) in a vertical direction, and the second well region (114) is in direct contact with the first well region (112) and the isolation tray (118). In the present application, providing the injection assistance structure allows for forming a deeper first well region, and thus a deeper transverse voltage-resistant structure (isolation tray, second well region, and first well region), capable of withstanding a higher voltage.
The present invention relates to an isolation transformer and a semiconductor device. The isolation transformer comprises: a lower coil; a main dielectric layer covering the lower coil; a silicon oxynitride layer located on the main dielectric layer; and an upper coil located on the silicon oxynitride layer. According to the present invention, a silicon oxynitride layer is arranged between the main dielectric layer and the upper coil; thus, voltage resistance of the device is ensured, and the impact of a high-voltage area on a low-voltage area can be reduced, thereby prolonging the overall service life of the device.
The present application relates to a thermopile infrared sensor and a manufacturing method therefor. The thermopile infrared sensor comprises an MEMS unit, and the MEMS unit comprises: a plurality of thermocouples, each thermocouple comprising a hot junction end and a cold junction end and the thermocouples being connected in series to form a thermopile; and an infrared absorption layer covering each thermocouple, the infrared absorption layer being a composite layer comprising a silicon oxide and a silicon nitride. A plurality of release holes passing through the infrared absorption layer are provided near each thermocouple. The density of the release holes near the hot junction end of each thermocouple is higher than that of the release holes near the cold junction end of each thermocouple. The release holes near the hot junction ends of the thermocouples are provided with first cavities recessed into side walls of the release holes. In the present application, the composite layer of the silicon oxide and the silicon nitride is used as the infrared absorption layer and is easy to manufacture, infrared energy is gathered via the first cavities to improve the infrared absorption rate, and therefore the infrared absorption rate is high.
G01J 5/12 - Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors using thermoelectric elements, e.g. thermocouples
55.
ELECTROSTATIC PROTECTION STRUCTURE AND PREPARATION METHOD THEREFOR
The present application relates to an electrostatic protection structure and a preparation method therefor. The electrostatic protection structure comprises a substrate, a buried layer, a first deep well, a second deep well and a third deep well. A well region of the opposite conductivity type and a heavily doped region of the same conductivity type are provided in the first deep well, and well regions and heavily doped regions of the same conductivity type are respectively provided in the second deep well and the third deep well. The first deep well, a first well region and a second well region are floating; a first heavily doped region leads out electrostatic voltage; and a sixth heavily doped region is grounded.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
56.
ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT
The present application relates to an electrostatic discharge protection device and an electrostatic discharge protection circuit. An electrostatic discharge protection device 1 comprises: a substrate 10; an isolation ring 102, arranged in the substrate 10, wherein an isolation ring lead-out area 103 is arranged in the isolation ring 102, and an isolation ring heavily doped area 110 is arranged in the isolation ring lead-out area 103; a transistor area, provided in the substrate 10 inside the isolation ring 102 and spaced apart from the isolation ring 102; and first well areas 104, arranged in the substrate 10 between the isolation ring 102 and the transistor area and spaced apart from the isolation ring 102 and the transistor area, wherein first heavily doped areas 105 are arranged in the first well areas 104.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
57.
SILICON CONTROLLED RECTIFIER AND ESD PROTECTION DEVICE
The present application relates to a silicon controlled rectifier (SCR) and an ESD protection device. The ESD protection device comprises the SCR. The SCR comprises: an N-type region (110); a P-type region (120), the P-type region (120) being in direct contact with the N-type region (110); a first N-type doped region (112), provided in the N-type region (110); a second N-type doped region (114), provided in the N-type region (110); a first P-type doped region (116), provided in the N-type region (110); a third N-type doped region (122), provided in the P-type region (120); and a second P-type doped region (124), provided in the P-type region (120). The ESD protection device further comprises a voltage division unit, and the voltage division unit has one end connected to the second N-type doped region (114) and the other end connected to the third N-type doped region (122). The first N-type doped region (112) and the first P-type doped region (116) are connected to an anode, and the other end of a first voltage division unit and the second P-type doped region (124) are connected to a cathode. According to the present application, a trigger voltage is low, and the latch-up resistance is high. Moreover, the advantage of strong ESD protection capability of an SCR in a unit area can be fully utilized.
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
58.
DIODE AND MANUFACTURING METHOD THEREFOR, AND SEMICONDUCTOR DEVICE
A diode and a manufacturing method therefor, and a semiconductor device. The diode includes: a substrate; an insulating buried layer provided on the substrate; a semiconductor layer provided on the insulating buried layer; anode; and a cathode, comprising: a trench-type contact, a trench being filled with a contact material, the trench extending from a first surface of the semiconductor layer to a second surface of the semiconductor layer, the first surface being a surface distant from the insulating buried layer, and the second surface being a surface facing the insulating buried layer; a cathode doped region surrounding the trench-type contact around and at the bottom of the trench-type contact, and also disposed on the first surface around the trench-type contact; and a negative electrode located on the cathode doped region and electrically connected to the cathode doped region.
A laterally diffused metal oxide semiconductor device and a preparation method therefor. The laterally diffused metal oxide semiconductor device (1) comprises: a substrate (10), which is provided with a trench (16); a drift region (30), which is located in the substrate (10), wherein the trench (16) is arranged around the drift region (30); a dielectric layer (20), which is located on the substrate (10) and is arranged around the drift region (30), wherein the dielectric layer (20) covers at least part of a first side wall (16a) and part of a bottom wall (16b) connected to the first side wall (16a); and a gate (40), which is arranged around the drift region (30). The gate (40) covers part of the surface of the dielectric layer (20) and extends towards a bottom wall (16b) of the trench (16) to cover part of the bottom wall (16b) of the trench (16).
This application provides a semiconductor device. The semiconductor device includes: a substrate (101) having a first conductivity type; an STI structure (108) disposed in the substrate (101) in the form of a first ring-like structure and surrounding a portion of the substrate (101), wherein a portion of the substrate surrounded by the STI structure serves as an active area (105); a drain doped region (103) disposed an a top of a central portion of the active area (105) and having a second conductivity type; source doped regions (102) having the second conductivity type, wherein the source doped regions are disposed at the top of the active area (105) on opposite sides of the drain doped region (103) and are spaced apart from the drain doped region (103); a field oxide layer (104) that is disposed over the top surface of the substrate (101) within the active area (105) in the form of a second ring-like structure and surrounds the drain doped region (103); gate polysilicon (106) that is disposed over the top surface of the substrate (101) and is in the form of a third ring-like structure surrounding the field oxide layer (104); and a drift region (107) having the second conductivity type wherein the drift region is disposed in the substrate (101) and surrounds the drain doped region (103).
The present disclosure relates to a field-stop insulated gate bipolar transistor and a manufacturing method therefor. The field-stop insulated gate bipolar transistor comprises a drift region, a front surface structure and a back surface structure. The back surface structure comprises: an electrode layer; a collector region located on the electrode layer and having a second conductivity type; and a field stop layer located on the collector region and having a first conductivity type, the drift region being located on the field stop layer. Notches are formed in the collector region and the field stop layer to form a notch region, the notch region has the first conductivity type, the doping concentration of the notch region is less than that of the field stop layer, and the drift region has the first conductivity type. According to the present disclosure, the withstand voltage of the device can be further increased.
A shorted anode lateral insulated gate bipolar transistor model, which is suitable for a shorted anode lateral insulated gate bipolar transistor (SA-LIGBT) having an NPN triode at an anode, comprising: an NMOS transistor (M1), an NPN triode (QN1), a PNP triode (QP1) and a second controlled current source (G2). A source electrode of the NMOS transistor (M1) is connected to an emitter of the SA-LIGBT, and a gate electrode of the NMOS transistor (M1) is connected to a gate electrode of the SA-LIGBT; an emitter of the NPN triode (QN1) is connected to a drain electrode of the NMOS transistor (M1), and a collector electrode of the NPN triode (QN1) is connected to a collector electrode of the SA-LIGBT; an emitter of the PNP triode (QP1) is connected to the collector electrode of the SA-LIGBT and a base electrode of the NPN triode (QN1), a collector electrode of the PNP triode (QP1) is connected to the emitter of the SA-LIGBT, and a base electrode of the PNP triode (QP1) is connected to the emitter of the NPN triode (QN1); one end of the controlled current source (G2) is connected to the emitter of the NPN triode (QN1), the other end of the controlled current source (G2) is connected to the source electrode of the NMOS transistor (M1), and a current generated by the second controlled current source (G2) is controlled by a current of the NMOS transistor (M1).
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
63.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
A semiconductor device and a manufacturing method therefor are disclosed. The method includes: providing a substrate of a first conductivity type; forming doped regions of a second conductivity type in the substrate, the doped regions including adjacent first and second drift regions, wherein the second conductivity type is opposite to the first conductivity type; forming a polysilicon film on the substrate, the polysilicon film covering the doped regions; forming patterned photoresist on the polysilicon film, which covers the first and second drift regions, and in which the polysilicon film above a reserved region for a body region between the first and second drift regions is exposed; and forming the body region of the first conductivity type in the reserved region by performing a high-energy ion implantation process, the body region having a top surface that is flush with top surfaces of the doped regions, the body region having a bottom surface that is not higher than bottom surfaces of the doped regions. The problem of morphological changes possibly experienced by the photoresist due to a high temperature in an etching process, which may lead to an impaired effect of the high-energy ion implantation process, can be circumvented.
The present application relates to a lateral insulated gate bipolar transistor and a preparation method therefor. The lateral insulated gate bipolar transistor comprises a drift region (120), a first well region (171), a first electrode lead-out region (130), a second electrode lead-out region (140), and conductivity modulation structures (160). The drift region (120) has a first conductivity type, and the first well region (171) is provided on the upper surface layer of the drift region (120) and has a second conductivity type. The conductivity modulation structures (160) are provided in the drift region (120) between the first electrode lead-out region (130) and the second electrode lead-out region (140); and each conductivity modulation structure (160) comprises a first doped region (161) that is provided on the upper surface layer of the drift region (120) and has the first conductivity type, and a second doped region (162) that is provided in the first doped region (161) and has the second conductivity type. The doping concentration of the first doped region (161) is greater than the doping concentration of the drift region (120).
The present disclosure provides an MTP memory power supply system and power supply method. A power source voltage generated by a power source is firstly processed by a voltage generator to form a first voltage, and a lifting voltage is then added to the first voltage to form a second voltage, such that when a reading operation is performed on an MTP memory, the processed second voltage can be used, and the voltage during the reading operation is thus relatively high or relatively stable. Therefore, when a reading operation is performed on an MTP memory, same can be read stably, or the reading speed is increased.
The present application relates to a semiconductor device and a preparation method therefor. The semiconductor device comprises a semiconductor substrate (111), an insulating buried layer (112), a drift region (120), and a plurality of dielectric isolation structures (130). The insulating buried layer (112) is located on the semiconductor substrate (111). The drift region (120) is located on the insulating buried layer (112). A drain region (150) is provided on part of the upper surface of the drift region (120). The plurality of dielectric isolation structures (130) are located in the drift region (120) and on the insulating buried layer (112), and are spaced apart from each other in a direction towards the drain region (150). At least one dielectric isolation structure (130) protrudes from the insulating buried layer (112) and is bent towards the drain region (150).
A trench-type double-diffused metal oxide semiconductor device and a manufacturing method therefor. The method comprises: using an active region photomask to form a hard mask layer (230) on a substrate (210); using the hard mask layer (230) as an etching barrier layer to form via etching a first trench (211), one side of the first trench (211) being a source region (254); within the first trench (211), forming a bottom gate (242) and an insulating isolation structure (224) on the bottom gate (242); by means of photolithography, forming an opening (291) above the source region (254), the width of the opening (291) being greater than the width of the source region (254); etching the insulating isolation structure (224) exposed in the first trench (211), forming a third trench (217), with the remaining insulating isolation structure (224) at least being located between the third trench (217) and the bottom gate (242); filling the third trench (217) with a first gate material acting as a top gate; removing the hard mask layer (230); and doping to form a source region (254) and a drain region (252).
UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA (China)
CSMC TECHNOLOGIES FAB2 CO., LTD. (China)
Inventor
Liu, Teng
He, Nailong
Wen, Tianlong
Zhang, Wentong
Zhang, Anna
Song, Hua
Zhang, Zhili
Abstract
A shorted-anode lateral insulated gate bipolar transistor and a manufacturing method therefor. The transistor comprises: a drift region (103) having a first conductivity type; a collector region (109) provided in the drift region (103) and having a second conductivity type; an anode region (110) having the first conductivity type; and an isolation structure (106), comprising a first structure provided between the collector region (109) and the anode region (110), and a second structure (1062) forming an included angle with the first structure (1061) and extending from the first structure (1061) to below the anode region. The first conductivity type is one of an N type and a P type, and the second conductivity type is the other one of the N type and the P type.
The present invention relates to a semiconductor device and a manufacturing method therefor. The semiconductor device comprises a high-voltage device region, a low-voltage device region and an isolation region located between the high-voltage device region and the low-voltage device region, and further comprises a drift region, a second conductivity type well region, an isolation well region, an isolation structure, a power device source region and a power device drain region. The drift region is arranged in the high-voltage device region. The second conductivity type well region is arranged in the isolation region and extends to the low-voltage device region. The isolation well region is arranged in the drift region, and divides the drift region into a high-voltage drift region and a power device drift region. The isolation structure is arranged in the isolation well region. The power device source region is arranged in the isolation region and located in the second conductivity type well region, and the power device drain region is arranged in the power device drift region. The semiconductor device can reduce leakage current flowing from the high-voltage device region, through the drift region, to a power device without affecting the withstand voltage thereof.
A manufacturing method for a super-β bipolar junction transistor includes providing a substrate, and forming a first conductive type isolation buried layer and a first conductive type doped layer based on the substrate. The isolation buried layer is located at a bottom of the doped layer. The method also includes forming a second conductive type base region in the doped layer and forming a second conductive type doped island on a peripheral side of the base region. A doping concentration of the doped island is greater than that of the base region. Additionally, the method includes forming a first conductive type collector region in the doped layer, and the collector region is spaced from the base region. Further, the method includes forming a first conductive type emitter region in the base region.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
71.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
The present disclosure relates to a semiconductor device and a manufacturing method therefor. The semiconductor device includes: a base, where a first surface of the base is provided with a first trench and a second trench; a gate, provided in the first trench; a gate insulation isolation structure, provided in the first trench, wherein the gate insulation isolation structure covers the gate at a bottom, sides and a top of the gate; a source doped region, provided in the base, on both sides of the first trench and on both sides of the second trench; a trench conductive structure, provided in the second trench; a source electrode, provided on the trench conductive structure and the source doped region, and electrically connected to the trench conductive structure and the source doped region; and a drain electrode, provided on a second surface of the base. The semiconductor device in the present disclosure, in addition to be conducted through a channel, can also be conducted through the trench conductive structure; thus, conductivity thereof is stronger. Since the channel conducts faster, a turn-on voltage (forward voltage drop) thereof is lower.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
The present application relates to a shorted-anode lateral insulated gate bipolar transistor and a manufacturing method therefor. The transistor comprises a drift region, a collector region arranged in the drift region, an anode region, a first conductivity-type doped region located in the drift region between the collector region and the anode region, and a depletion structure arranged in the first conductivity-type doped region, wherein the doping concentration in the first conductivity-type doped region is greater than the doping concentration in the drift region; and the depletion structure comprises a vertical conductive structure, and a dielectric layer that surrounds the vertical conductive structure so as to isolate the vertical conductive structure from the first conductivity-type doped region.
The present application relates to a semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a first metal layer, which is arranged on a substrate; a dielectric layer, which is arranged on the side of the first metal layer that faces away from the substrate; a buffer layer, which is arranged on the side of the dielectric layer that is away from the first metal layer; a second metal layer, which is arranged on the side of the buffer layer that is away from the dielectric layer; and a metal ring, which is arranged on the side of the buffer layer that is away from the dielectric layer, and surrounds an outer side of the second metal layer. The potential of the second metal layer is higher than the potential of the first metal layer.
The present application relates to a semiconductor device and a preparation method therefor. The semiconductor device comprises: a first metal layer disposed on a substrate; a dielectric layer disposed on a side of the first metal layer distant from the substrate; a second metal layer disposed on a side of the dielectric layer distant from the first metal layer, the potential of the second metal layer being higher than the potential of the first metal layer; and a metal ring disposed on a side of the dielectric layer distant from the first metal layer, the metal ring being arranged around an outer side of the second metal layer. A portion of the metal ring is located in the dielectric layer.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/62 - Protection against overcurrent or overload, e.g. fuses, shunts
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
75.
SILICON-ON-INSULATOR TRANSVERSE DEVICE AND MANUFACTURING METHOD THEREFOR
The present application relates to a silicon-on-insulator transverse device and a manufacturing method therefor. The device comprises: a substrate; a buried dielectric layer provided on the substrate; a drift region provided on the buried dielectric layer; a vertical conductive structure extending downwards from the drift region to the buried dielectric layer; a low-K dielectric provided in the buried dielectric layer and surrounding the bottom of the vertical conductive structure; and a dielectric layer provided on a side surface of the vertical conductive structure and located between the vertical conductive structure and the drift region and above the low-K dielectric.
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
76.
DIFFERENTIAL CAPACITIVE MEMS MICROPHONE AND MANUFACTURING METHOD THEREFOR
The present application relates to a differential capacitive MEMS microphone and a manufacturing method therefor. The microphone comprises: a substrate (110) comprising a second backplane (112); a first support layer (124) provided on the substrate (110); a diaphragm (122) provided on the first support layer (124); a second support layer (126) provided on the diaphragm (122); and a first backplane (132) provided on the second support layer (126), the diaphragm (122) being located between the first backplane (132) and the second backplane (112), wherein a first capacitor formed by the diaphragm (122) and the first backplane (132) is used for outputting a first capacitance value signal, a second capacitor formed by the diaphragm (122) and the second backplane (112) is used for outputting a second capacitance value signal, and the first capacitance value signal and the second capacitance value signal form a differential signal. According to the present application, a part of the structure of the substrate is used as the second backplane, and therefore, the second backplane does not lead to an increase in thickness of the microphone. Moreover, the capacitance signals output by the capacitors formed by the diaphragm together with the first backplane and with the second backplane form a differential signal, so that the signal-to-noise ratio of the microphone can be improved.
A manufacturing method for a P-type laterally diffused metal oxide semiconductor device, comprising: forming a N-type buried layer (220) in a substrate (210), forming a P-type region (230) located on the N-type buried layer (220), and forming a mask layer (240) located on the P-type region (230); patterning the mask layer (240) to form at least two injection windows (241, 243, 245); performing N-type ion implantation by means of the at least two injection windows (241, 243, 245), so as to form a high-voltage N-well doped region (231) and a low-voltage N-well doped region (233); forming an oxide layer (244); removing at least part of the mask layer (240); performing P-type ion implantation on the P-type region (230) to form a P-type doped region (234); by means of thermal annealing, diffusing the P-type doped region (234) to form a drift region (236) and two P-type well regions (238), diffusing the high-voltage N-well doped region (231) to form a high-voltage N-type well region (235), and diffusing the low-voltage N-well doped region (233) to form a low-voltage N-type well region (237); and forming a source doped region (252), a drain doped region (254), and a gate (260).
A stacked spiral inductor, comprising: a substrate, and multiple stacked insulating layers and inductive metal layers formed on the substrate by means of a semiconductor process. Each inductive metal layer comprises a conductive coil in a shape of a spiral and a through hole area used for connecting two adjacent inductive metal layers. The conductive coils of the inductive metal layers have a common coil center. In two adjacent inductive metal layers, the conductive coil of the lower inductive metal layer is retracted toward the coil center with respect to the conductive coil of the upper inductive metal layer.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
79.
ISOLATION TRANSFORMER AND MANUFACTURING METHOD THEREFOR, AND SEMICONDUCTOR DEVICE
The present invention relates to an isolation transformer and a manufacturing method therefor, and a semiconductor device. The isolation transformer comprises: a first metal layer, which comprises a first metal pattern and a second metal pattern; a second metal layer, which comprises a third metal pattern and a fourth metal pattern; and a dielectric layer, which is arranged between the first metal layer and the second metal layer, wherein a dielectric layer between the first metal pattern and the third metal pattern is provided with a first through hole, and a conductive material is provided in the first through hole; a dielectric layer between the second metal pattern and the fourth metal pattern is provided with a second through hole, and a conductive material is provided in the second through hole; and the first metal pattern and the third metal pattern serve as a primary coil of the isolation transformer, and the second metal pattern and the fourth metal pattern serve as a secondary coil of the isolation transformer. In the present invention, a primary coil and a secondary coil can not only be coupled to each other on the same plane, but can also be longitudinally coupled to each other, thereby improving the current signal transmission intensity and greatly increasing a coupling coefficient of the coils.
The present application relates to a method for preparing an LDMOS device, and the LDMOS device. The method for preparing the LDMOS device comprises the steps of: forming a drift region of a first conductivity type; forming a buried layer of a second conductivity type in the drift region of the first conductivity type; and forming a channel region of the first conductivity type in the drift region of the first conductivity type, the channel region of the first conductivity type being located above the buried layer of the second conductivity type and adjoining the buried layer of the second conductivity type, and the area of the channel region of the first conductivity type being greater than the area of the buried layer of the second conductivity type. The channel region of the first conductivity type and the buried layer of the second conductivity type are formed in the drift region of the first conductivity type, and the area of the channel region of the first conductivity type is greater than the area of the buried layer of the second conductivity type, so that the effect of the device further reducing on-resistance while improving breakdown voltage is achieved.
A semiconductor memory comprising: a comparison readout circuit comprising a first port configured to receive an electric signal of a read memory unit and a second port configured to receive a reference electric signal, the comparison readout circuit being configured to compare the electric signal of the read memory unit with the reference electric signal to obtain storage information of the memory unit; and a first/second column decoder connected to a first/second memory array and the comparison readout circuit and configured to select a bitline corresponding to the read memory unit when a memory array selection signal enables the first/second memory array, and output the electric signal of the memory unit to the first port by means of the bitline, and further configured to connect a first bitline of the first/second memory array to the second port when the memory array selection signal does not enable the first/second memory array.
The present invention relates to a trench DMOS device and a manufacturing method therefor. The trench DMOS device comprises an extended gate layer provided on the inner surface of a gate insulation layer; and the extended gate layer comprises a first extended gate area of a second conductive type and a second extended gate area and a third extended gate area of a first conductive type. The contradictory relationship between the pressure resistance and the specific on-resistance of the trench DMOS device is improved, such that the trench DMOS device not only has a high pressure resistance, but also has a low specific on-resistance. Moreover, the trench DMOS device is of a longitudinal pressure-resistant structure, such that the area of the device is reduced, so as to reduce the on-resistance of the device. Furthermore, both a source area and a drain area can be lead out from the front surface, and CMOS is compatible.
The present invention relates to a semiconductor device and a preparation method therefor. A second well region is inserted between first well regions of a semiconductor device to improve the breakdown voltage of the device, and the size of the upper surface of the second well region in the width direction of a conductive channel of the device is set to be less than that of the lower surface of the second well region in the width direction of the conductive channel of the device, so that the size of the upper surface of the adjacent first well region in the width direction of the conductive channel of the device is increased, that is, the width of the path of current flowing through the upper surface of a drift region when the device is turned on is increased, thus the on-resistance of the device is reduced. Finally, the on-resistance of the device is effectively reduced while the breakdown voltage of the device is improved.
The present invention provides a DMOS device having a junction field plate and a manufacturing method therefor. A drain area is located at a surface of a semiconductor substrate, a source area is located in the semiconductor substrate at the bottom of a first trench, and a gate is located at the bottom of the first trench, such that the longitudinal withstand voltage is achieved, the size of the entire device can be decreased, the on-resistance is decreased, and the relationship between the withstand voltage and the on-resistance is greatly optimized. The effect of decreasing the surface resistance is improved by means of the junction field plate, and meanwhile, the depth of the trench in the DMOS device can be decreased, such that the depth-to-width ratio of the device is decreased, and the feasibility of increasing a withstand voltage gear is further improved. The source area and the drain area in the DMOS device are both drawn from a same surface, such that the manufacturing process of a CMOS device can be compatible. A second doped polysilicon layer comprises a first sub-doped layer and a second sub-doped layer that have different conductivity types, such that a P-type doped layer can also be directly connected to a gate potential in the case of an N-type gate, and the effect of the junction field plate is improved.
A semiconductor device (100), comprising: a substrate (110); a first-conductivity-type buried layer (120), which is arranged in the substrate (110); a drift region (142), which is arranged on the buried layer (120); a drain region (130), which is arranged in the drift region (142); a body region (132), which is arranged on the buried layer (120); a source region (130), which is arranged in the body region (132); and a first to a fourth doped region (162, 164, 166, 168), which are arranged on the buried layer (120) and are sequentially arranged in the direction of the drift region (142) away from the body region (132), wherein the doping concentration of the third doped region (166) is less than the doping concentration of the first doped region (162), and the doping concentration of the second doped region (164) is greater than the doping concentration of the fourth doped region (168).
A single-photon avalanche diode having a quenching resistor integrated therein, and a manufacturing method therefor, the method comprising: obtaining a wafer; patterning and etching a front surface of a substrate (210) to form a quenching resistor trench (211) and an isolation trench (213), the width of the isolation trench (213) being greater than the width of the quenching resistor trench (211); forming an insulating layer (254) at an inner surface of the quenching resistor trench (211); depositing polycrystalline silicon (260) onto the front surface of the substrate (210), the polycrystalline silicon (260) filling the quenching resistor trench (211) and sealing same, and filling the isolation trench (213) but not sealing same; oxidizing the polycrystalline silicon (260) in the isolation trench (213); and filling the isolation trench (213) with a light-shielding conductive material (270). The manufacturing method is compatible with CMOS processing. Because the quenching resistor trench (211) and the isolation trench (213) can share the same photo-etching plate, the manufacture of the quenching resistor does not require the separate use of a photo-etching plate, thus reducing production costs.
H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
The present invention relates to an MEMS structure and a manufacturing method therefor. The manufacturing method for an MEMS structure comprises: acquiring a substrate; forming, on the substrate, a sacrificial layer having a plurality of hollowed tunnels; forming a structural layer on the sacrificial layer; patterning the structural layer to form a required structure, which involves respectively forming, right above the hollowed tunnels, corrosion holes corresponding to the hollowed tunnels; and corroding the sacrificial layer by means of the corrosion holes, so as to form a cavity. In the present invention, the plurality of hollowed tunnels are arranged in the sacrificial layer, such that a corrosive agent can enter the tunnels during the corrosion of the sacrificial layer, so as to increase the corrosion rate. Moreover, since the corrosive agent can be diffused in the whole lengthwise direction of a tunnel after entering the tunnel from any position, a sacrificial layer in a predetermined corrosion area can be completely corroded simply by means of providing a small number of corrosion holes, thereby preventing the strength of the structural layer from being affected by the intensive provision of corrosion holes.
The present invention provides a silicon controlled rectifier and a preparation method therefor. A first low-resistance region and a second low-resistance region are additionally provided in a first well region and a second well region of the silicon controlled rectifier, respectively. Since the resistance values of the first low-resistance region and the second low-resistance region are low, the overall resistance of the first well region and the overall resistance of the second well region are both reduced, so that the turn-on voltage of the device is reduced, thereby improving the current bleeding capability of the silicon controlled rectifier. In addition, the first low-resistance region is provided below a first doped region, and the second low-resistance region is provided below a fourth doped region. Therefore, the first low-resistance region does not affect the turn-on of a transistor formed by a second doped region, the first well region, and the second well region; and the second low-resistance region does not affect the turn-on of a transistor formed by the first well region, the second well region, and a third doped region. Therefore, the silicon controlled rectifier and the preparation method therefor provided by the present invention can realize the reduction of the turn-on voltage of the silicon controlled rectifier without affecting the response speed of the silicon controlled rectifier.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
In the manufacturing method for an LDMOS integrated device provided by the present invention, a provided semiconductor substrate has an NLDMOS region and a PLDMOS region; then a dielectric layer on the NLDMOS region and a dielectric layer on the PLDMOS region are formed on the semiconductor substrate, and a stress material layer is formed on the dielectric layer on the NLDMOS region and/or on the dielectric layer on the PLDMOS region, the thickness of the dielectric layer on the NLDMOS region being greater than the thickness of the dielectric layer on the PLDMOS region; then heat treatment is performed to adjust the stress of the stress material layer, so as to improve the electron mobility of a device; then the stress material layer is removed. Thus, the electron mobility of an NLDMOS device and/or a PLDMOS device can be improved, and a high-performance NLDMOS and a high-performance PLDMOS can be prepared simultaneously in a same process flow; moreover, the thickness of the dielectric layer on the NLDMOS region is greater than the thickness of the dielectric layer on the PLDMOS region, that is, the thickness of the dielectric layer under the Big contact in the NLDMOS region can meet RESURF requirements, and the thickness of the dielectric layer under the Big contact in the PLDMOS region can meet RESURF requirements, thereby improving the RESURF capability of the Big contact of the LDMOS integrated device as a whole.
Provided in the present invention is an electrostatic discharge protection structure. In the electrostatic discharge protection structure, a substrate has a first conductivity type; a source region and a drain region each have a second conductivity type opposite to the first conductivity type, and are arranged, spaced apart from each other, in the substrate; a gate structure is arranged on the substrate between the source region and the drain region; a first doped region arranged in a floating manner has the first conductivity type, is arranged in the substrate at the side of the drain region that is away from the gate structure, and is arranged spaced apart from the drain region, and the doping concentration of the first doped region is greater than the doping concentration of the substrate; and the source region and the gate structure are jointly electrically connected to a first potential end, and the drain region is electrically connected to a second potential end. The first doped region is added, such that an avalanche breakdown voltage of a current collector junction of a parasitic NPN transistor of the electrostatic discharge protection structure can be reduced, thereby facilitating the reduction of a trigger voltage of the electrostatic discharge protection structure.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
91.
MANUFACTURING METHOD FOR SELF-ALIGNMENT HOLE, AND SEMICONDUCTOR DEVICE
A manufacturing method for a self-alignment hole, and a semiconductor device. The semiconductor device comprises: a trench sidewall gate structure, comprising a gate (440) formed at the bottom of the sidewall of a trench, and an insulating material (452) covering the gate (440) in the trench; a source region (422), disposed below the trench; and a drain region (432), disposed on both sides of the top of the trench. The semiconductor device is further provided with a source contact hole (462) downwardly running through the insulating material (452) to the source region (422); the source contact hole (462) is filled with a conductive material so as to be electrically connected to the source region (422); the source contact hole (462) passes between the gates (430) on both sides of the trench; an etching barrier layer (454) is formed on the sidewall of the source contact hole (462).
The present invention relates to an LDMOS device and a method of forming the device, in which a barrier layer includes n etch stop layers. Insulating layers are formed between adjacent etch stop layers. Since an interlayer dielectric layer and the insulating layers are both oxides that differ from the material of the etch stop layers, etching processes can be stopped at the n etch stop layers when they are proceeding in the oxides, thus forming n field plate holes terminating at the respective n etch stop layers. A lower end of the first field plate hole proximal to a gate structure is closest to a drift region, and a lower end of the n-th field plate hole proximal to a drain region is farthest from the drift region. With this arrangement, more uniform electric field strength can be obtained around front and rear ends of the drift region, resulting in an effectively improved electric field distribution throughout the drift region and thus in an increased breakdown voltage.
The present invention provides a semiconductor device and a manufacturing method therefor, applicable to the field of semiconductors. The present invention provides a method for forming a double SOI (DSOI) device structure on a DSOI substrate on the basis of the prior art and without adding an additional process. Specifically, the step of forming back gate openings in the prior art is adjusted before the step of forming a gate structure, and then the formed back gate openings are filled with a gate material layer deposited in the gate structure forming process at the same time, so that after the subsequent etching step and conductive plug filling step, conductive plugs formed by means of the back gate openings comprise not only a conductive material, but also a gate material. Thus, after an interlayer dielectric layer is deposited, and when the conductive plugs are formed in a CT etching process, a process risk caused by extreme step difference caused by the DSOI substrate being relatively thick in the DSOI structure is avoided.
An MEMS microphone and a manufacturing method therefor. The MEMS microphone comprises: a substrate (110); a backplate (130) arranged on the substrate (110); a plurality of support columns (144) arranged on the substrate (110); and a diaphragm (150) arranged on the support columns (144), wherein each of the support columns (144) is used for supporting the diaphragm (150); the diaphragm (150) is provided with an air hole (151), and penetrates the diaphragm (150); an airflow channel is formed in a space located between the diaphragm (150) and the backplate (130) and provided with no support column (144); the substrate (110) directly below the backplate (130) is not provided with a cavity; and the backplate (130) and the diaphragm (150) form a capacitor.
An LDMOS device. In the LDMOS device, a drift region (101), a body region (102), a source region (104) located at the top of the body region (102), and a drain region (106) located at the top of the drift region (101) are provided in a semiconductor substrate (100). The drift region (101) and the source region (104) and the drain region (106) have a first doping type, and the body region (102) has a second doping type. A gate structure (103) is located on the body region (102), and the gate structure (103) has one side extending onto the source region (104), and has the other side extending onto the drift region (101). An isolation structure (105) is embedded in the drift region (101) between the gate structure (103) and the drain region (106) and extends below the gate structure (103). A first enrichment region (109) having the first doping type is located in the drift region (101) and is distributed along the side walls and the bottom wall of the isolation structure (105), and a doping concentration of the first enrichment region (109) is greater than a doping concentration of the drift region (101). The first enrichment region is provided on a path through which a current of the LDMOS device flows, thereby facilitating reducing the on-resistance of the LDMOS device under the condition that a breakdown voltage of the device is not affected. Also provided is a manufacturing method for the LDMOS device.
A semiconductor-on-insulator structure and a manufacturing method therefor. The manufacturing method comprises: obtaining a wafer, which comprises a substrate (10) and an insulating layer (12) on the substrate (10); patterning the insulating layer (12) to form trench arrays (13), which are in communication with each other, expose the substrate (10), and divide the insulating layer (12) into a plurality of block-shaped structures; and forming an epitaxial layer (16) on the substrate (10) and the insulating layer (12), wherein the epitaxial layer (16) covers the substrate (10).
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
A semiconductor memory, comprising a negative voltage providing unit, which is used for providing a first negative voltage to a word line during a read operation, and comprises: a clamping unit that comprises an input end, a control end and an output end, wherein the input end is coupled to a common ground end of the memory, and the control end is used for receiving a first signal; an energy storage capacitor, a first end of which is coupled to the output end, and a second end that is used for receiving a second signal; and a negative voltage providing end which is coupled to the first end, wherein the clamping unit is used for: pulling the voltage at the output end to the voltage at the input end when the first signal is “0”; and clamping the output end at a clamping voltage when the first signal is “1”.
A laterally diffused metal-oxide-semiconductor (LDMOS) device and a method for fabricating the LDMOS device are disclosed. The device includes: a substrate (101) having a second conductivity type; a drift region (102) that has a first conductivity type and is disposed on the substrate (101), wherein the first conductivity type is opposite to the second conductivity type; a plurality of layers of doped structures disposed in the drift region (102), each layer of the doped structure comprising at least one doped bar (105) extending in a lengthwise direction of a conductive channel; and a plurality of doped polysilicon pillars (106) disposed in the drift region (102) so as to extend downward through the doped bar (105) of at least one of the layer of doped structures, wherein ions doped in the doped polysilicon pillars (106) and ions doped in the doped bar have opposite conductivity types.
A laterally diffused metal oxide semiconductor device and a fabrication method therefor, the laterally diffused metal oxide semiconductor device comprising: a substrate (110); a drift region (120), which is disposed in the substrate (110); a drain region (122), which is disposed in the substrate (110) and which makes contact with the drift region (120); a body region (130), which is disposed in the substrate (110); an insulating layer (140), which is at least partially disposed in the body region (130); a source region (124), which is located on the insulating layer (140); and a gate structure (160), which is disposed on the substrate (110) between the drain region (122) and the source region (124).
A transient voltage suppression device includes: a substrate; a first conductive type well region including a first well and a second well; a second conductive type well region including a third well and a fourth well, the third well being disposed between the first well and the second well so as to isolate the first well and the second well, and the second well being disposed between the third well and the fourth well; a zener diode active region; a first doped region, provided in the first well; a second doped region, provided in the first well; a third doped region, provided in the second well; a fourth doped region, provided in the second well; a fifth doped region, provided in the zener diode active region; and a sixth doped region, provided in the zener diode active region.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
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