Wireless transport of multiple service versions of a transport framework. First and second information may be processed for transmission, respectively, according to first and second service versions of a transport framework. The first and second information may be encoded using a first type of error correction coding; after processing, the processed first information may include error correction coding according to the first type of error correction coding, while the processed second information may remain uncoded according to the first type of error correction coding. Control information may be generated indicating that the second information remains uncoded according to the first type of error correction coding, which may signal to receivers that the second information is processed according to the second service version of the transport framework. Packets including the processed first information, the processed second information, and the control information may be generated and transmitted in a wireless manner.
H03M 13/05 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H04H 20/95 - Arrangements characterised by special technical features of the broadcast information, e.g. signal form or information format characterised by a specific format, e.g. an encoded audio stream
H04H 60/07 - Arrangements for generating broadcast informationArrangements for generating broadcast-related information with a direct linkage to broadcast information or to broadcast space-timeArrangements for simultaneous generation of broadcast information and broadcast-related information characterised by processes or methods for the generation
H04L 65/611 - Network streaming of media packets for supporting one-way streaming services, e.g. Internet radio for multicast or broadcast
H04N 21/2381 - Adapting the multiplex stream to a specific network, e.g. an IP [Internet Protocol] network
H04N 21/2383 - Channel coding of digital bit-stream, e.g. modulation
H04N 21/414 - Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance
H04N 21/438 - Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
Various embodiments are disclosed of a compilation with optimization for multi-processor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Application source code may be initially compiled into an intermediate representation. Following the initial compilation, resources may be mapped and communication synthesis performed. Simulation and debug may be performed prior to loading an executable image onto the multi-processor system. At each step, checks may be performed for possible optimizations, and one or more steps repeated using results of the checks.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
3.
DNA Alignment using a Hierarchical Inverted Index Table
System and method for constructing a hierarchical index table usable for matching a search sequence to reference data. The index table may be constructed to contain entries associated with an exhaustive list of all subsequences of a given length, wherein each entry contains the number and locations of matches of each subsequence in the reference data. The hierarchical index table may be constructed in an iterative manner, wherein entries for each lengthened subsequence are selectively and iteratively constructed based on the number of matches being greater than each of a set of respective thresholds. The hierarchical index table may be used to search for matches between a search sequence and reference data, and to perform misfit identification and characterization upon each respective candidate match.
Methods and devices for dynamically designated first and second subsets of a plurality of frequency channels as upstream and downstream channels, respectively, for performing wired communications using virtual segmentation between a network controller and an endpoint device. performing virtual segmentation to service an endpoint device. Communications are performed between the network controller and the endpoint device through a wired communication medium using the upstream and downstream channels. The first subset and second subsets of the plurality of channels are designated as upstream channels and downstream channels, respectively, based at least in part on one or both of upstream and downstream channel demand and channel availability.
Methods and device for constructing a specification data structure for a module of a multiprocessor array (MPA) chip. The specification data structure includes parameters for combining a plurality of register transfer language (RTL) templates for submodules of the modules into an RTL description of the module, parameters for combining a plurality of test bench templates for respective submodules into a test bench for the module, parameters for combining a plurality of physical design script templates for respective submodules into a physical design script for the module, and/or parameters for constructing an API for the module based on a set of functional criteria for module operation. The RTL description, the test bench, the physical design script, and/or the API are constructed and stored in memory for use in designing and fabricating the module.
A flexible diplexer may include a programmably reconfigurable filter pair capable of rendering a variety of band-split arrangements in a digital signal processor (DSP) backed design in hybrid fiber coaxial cable plant/system deployments. The flexible diplexers may thereby meet a larger range of band-split requirements, including the full range of band-split requirements. Configurability may be achieved by digitizing the signal at either input interface of a diplexer in a diplexer/amplifier complex after bandpass filtering, and two-to-four wire conversion at the respective forward (e.g. downstream) and reverse (e.g. upstream) input interfaces. A new band-split may be obtained by updating the digital filters using specified coefficient sets determined off-line and retrieved from memory. The flexible diplexer/amplifier complex may enable the implementation of additional functionality including equalization and tilt regeneration, self-interference cancellation, virtual segmentation, and/or creation of auxiliary service points to provide access to/from a small cell base station and/or Wi-Fi access point.
H04B 3/20 - Reducing echo effects or singingOpening or closing transmitting pathConditioning for transmission in one direction or the other
H04B 3/21 - Reducing echo effects or singingOpening or closing transmitting pathConditioning for transmission in one direction or the other using a set of bandfilters
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
45 - Legal and security services; personal services for individuals.
Goods & Services
Digital signal processors; data processors; micro
processors; signal processors; integrated circuits;
downloadable computer-aided manufacturing (CAM) software for
integrated circuits; downloadable computer-aided design
(CAD) software for designing and programming integrated
circuits. Engineering services, namely, non-recurring engineering in
the field of computer software, integrated circuits, and
processors; design for others in the fields of computer
software and engineering for integrated circuits and
processors; custom design and engineering of computer
software, integrated circuits, and processors; engineering
design services; research, development, engineering, and
testing services in the field of computer software,
integrated circuits, and processors; consulting in the field
of engineering; electrical engineering. Licensing of industrial property rights; licensing of
intellectual property rights; computer software licensing;
licensing of software for design of integrated circuits.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
45 - Legal and security services; personal services for individuals.
Goods & Services
(1) Digital signal processors; central processing units; micro processors; signal processors; integrated circuits; downloadable computer-aided manufacturing (CAM) software for integrated circuits; downloadable computer-aided design (CAD) software for designing and programming integrated circuits. (1) Engineering services, namely, non-recurring computer hardware and computer software engineering in the field of computer software, integrated circuits, and computer processors; design for others in the fields of computer software and computer hardware and computer software engineering for integrated circuits and computer processors; custom design and engineering of computer software, integrated circuits, and computer processors; engineering design services in the field of computer hardware and computer software; research, development, engineering, and testing services in the field of computer software, integrated circuits, and computer processors; consulting in the field of computer hardware and computer software engineering; electrical engineering.
(2) Licensing of industrial property rights; licensing of intellectual property rights; computer software licensing; licensing of software for design of integrated circuits.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
45 - Legal and security services; personal services for individuals.
Goods & Services
Digital signal processors; data processors; micro processors; signal processors; integrated circuits; downloadable computer-aided manufacturing (CAM) software for integrated circuits; downloadable computer-aided design (CAD) software for designing and programming integrated circuits Engineering services, namely, non-recurring engineering in the field of computer software, integrated circuits, and processors; design for others in the fields of computer software and engineering for integrated circuits and processors; custom design and engineering of computer software, integrated circuits, and processors; engineering design services; research, development, engineering, and testing services in the field of computer software, integrated circuits, and processors; consulting in the field of engineering; electrical engineering Licensing of industrial property rights; licensing of intellectual property rights; computer software licensing; licensing of software for design of integrated circuits
09 - Scientific and electric apparatus and instruments
Goods & Services
Digital signal processors; data processors; micro processors; signal processors; integrated circuits; downloadable computer-aided manufacturing (CAM) software for integrated circuits; downloadable computer-aided design (CAD) software for designing and programming integrated circuits
11.
A COMPREHENSIVE SYSTEM DESIGN TO ADDRESS THE NEEDS FOR VIRTUAL SEGMENTATION OF THE COAXIAL CABLE PLANT
Methods and devices for dynamically designated first and second subsets of a plurality of frequency channels as upstream and downstream channels, respectively, for performing wired communications using virtual segmentation between a network controller and an endpoint device, performing virtual segmentation to service an endpoint device. Communications are performed between the network controller and the endpoint device through a wired communication medium using the upstream and downstream channels. The first subset and second subsets of the plurality of channels are designated as upstream channels and downstream channels, respectively, based at least in part on one or both of upstream and downstream channel demand and channel availability.
Methods and devices for a home power networking system including a first wireless access point (AP) configured to perform wired communications over a first circuit connected to the first wireless AP. The first wireless AP further performs wireless communications with a second wireless AP, wherein the second wireless access point is connected to a second circuit and is not connected to the first circuit. The first wireless AP provides wireless transport through the second wireless AP to bridge communications between the first circuit and the second circuit.
Techniques are disclosed relating to spectrum sharing between different radio access technologies. In some embodiments, a broadcast base station is configured to wirelessly broadcast audio and video data to a plurality of broadcast receiver devices using a particular frequency band. In these embodiments, the broadcast base station is configured to discontinue broadcasting in the particular frequency band during a scheduled time interval, to enable one or more cellular base stations to perform cellular packet-switched wireless data communications using the particular frequency band.
Methods and systems for rendering an output image from a plurality of input images. The plurality of input images is received, and each input image is taken from a different first location. A view specification for rendering the output image is received, and the view specification includes at least a second location. The second location is different from each of the first locations. An output image is rendered based at least in part on the plurality of input images and the view specification, and the output image includes an image of a region as seen from the second location. The output image is displayed on a display.
Methods and devices are described for a parallel multi-processor encoder system for encoding video data, wherein the video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system may divide the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks may be transmitted to the decoder for each processor prior to transmission of the next respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.
H04N 19/107 - Selection of coding mode or of prediction mode between spatial and temporal predictive coding, e.g. picture refresh
H04N 19/436 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
H04N 19/147 - Data rate or code amount at the encoder output according to rate distortion criteria
A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.
Various embodiments are disclosed of a compilation with optimization for multi-processor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Application source code may be initially compiled into an intermediate representation. Following the initial compilation, resources may be mapped and communication synthesis performed. Simulation and debug may be performed prior to loading an executable image onto the multi-processor system. At each step, checks may be performed for possible optimizations, and one or more steps repeated using results of the checks.
Methods and devices are described for polar encoding and decoding control information that has been modulated based on one or more identifiers of the transmitter and/or receiver. Some embodiments describe scrambling sequence design for multi-mode block discrimination on control information blind detection and decoding. Separate scrambling masks may be applied to disparate bit fields within a coded DCI message, wherein each of the scrambling masks is derived from a user equipment (UE)-specific identifier, a UE group identifier, or a base station identifier. Frozen bits of the polar code may be used to encode and transmit hybrid automatic repeat request (HARQ) acknowledgment messaging for early retransmission of unsuccessful downlink messages. A tiered process of UE identification may be employed to improve a balance between early termination of the decoding process and success of the UE identification process.
Methods and devices are described for determining reliabilities of bit positions in a bit sequence for information bit allocation using polar codes. The reliabilities are calculated using a weighted summation over a binary expansion of each bit position, wherein the summation is weighted by an exponential factor that is selected based at least in part on the coding rate of the polar code. Information bits and frozen bits are allocated to the bit positions based on the determined reliabilities, and data is polar encoded as the information bits. The polar encoded data is then transmitted to a remote device.
Methods and devices are described for encoding and decoding control information that has been modulated based on one or more identifiers of the transmitter and/or receiver. Some embodiments describe scrambling sequence design for multi-mode block discrimination on downlink control information (DCI) blind detection. Separate scrambling masks may be applied to disparate bit fields within a coded DCI message, wherein each of the scrambling masks is derived from a unique identifier associated with either the transmitter or the intended receiver. The scrambling masks may be used by the receiver to perform early termination of the decoding process, to mitigate intercell interference, and to verify that the receiver is the intended receiver.
Methods and devices are described for encoding and decoding control information that has been modulated based on one or more identifiers of the transmitter and/or receiver. Some embodiments describe scrambling sequence design for multi-mode block discrimination on downlink control information (DCI) blind detection. Separate scrambling masks may be applied to disparate bit fields within a coded DCI message, wherein each of the scrambling masks is derived from a unique identifier associated with either the transmitter or the intended receiver. The scrambling masks may be used by the receiver to perform early termination of the decoding process, to mitigate intercell interference, and to verify that the receiver is the intended receiver.
Various embodiments are described of a system for improved processor instructions for a software-configurable processing element. In particular, various embodiments are described which accelerate functions useful for FEC encoding and decoding. In particular, the processing element may be configured to implement one or more instances of the relevant functions in response to receiving one of the processor instructions. The processing element may later be reconfigured to implement a different function in response to receiving a different one of the processor instructions. Each of the disclosed processor instructions may be implemented repeatedly by the processing element to repeatedly perform one or more instances of the relevant functions with a throughput approaching one or more solutions per clock cycle.
Various embodiments are described of a system and method for improved SCL decoder operation. In particular, various embodiments are described which improve the efficiency of the buffer management based on updated path metric statistics. In some embodiments, the SCL decoder may perform selective replacement to limit the extent of LLR updates per row only to the statistics that have changed since the previous update cycle. In some embodiments, the SCL decoder may perform deferred updates, which may involves in-place calculation of both ûφ= 0 and ûφ= 1 bit estimate (LLR) updates based on the row from which the updated row will be derived.
System and method for constructing a hierarchical index table usable for matching a search sequence to reference data. The index table may be constructed to contain entries associated with an exhaustive list of all subsequences of a given length, wherein each entry contains the number and locations of matches of each subsequence in the reference data. The hierarchical index table may be constructed in an iterative manner, wherein entries for each lengthened subsequence are selectively and iteratively constructed based on the number of matches being greater than each of a set of respective thresholds. The hierarchical index table may be used to search for matches between a search sequence and reference data, and to perform misfit identification and characterization upon each respective candidate match.
G06F 19/24 - for machine learning, data mining or biostatistics, e.g. pattern finding, knowledge discovery, rule extraction, correlation, clustering or classification
G06F 19/18 - for functional genomics or proteomics, e.g. genotype-phenotype associations, linkage disequilibrium, population genetics, binding site identification, mutagenesis, genotyping or genome annotation, protein-protein interactions or protein-nucleic acid interactions
25.
SHARED SPECTRUM ACCESS FOR BROADCAST AND BI-DIRECTIONAL, PACKET-SWITCHED COMMUNICATIONS
Techniques are disclosed relating to spectrum sharing between different radio access technologies. In some embodiments, a broadcast base station is configured to wirelessly broadcast audio and video data to a plurality of broadcast receiver devices using a particular frequency band. In these embodiments, the broadcast base station is configured to discontinue broadcasting in the particular frequency band during a scheduled time interval, to enable one or more cellular base stations to perform bi-directional packet-switched wireless data communications using the particular frequency band.
Techniques relating to generating and receiving radio frames with multiple partitions are disclosed. A mobile device may include a wireless radio, one or more antennas, and one or more processors. In some embodiments, the mobile device is configured to receive a frame of wireless data that includes a plurality of partitions and partition data. In some embodiments, the plurality of partitions each include multiple orthogonal frequency-division multiplexing (OFDM) symbols, and different ones of the partitions have different frequency transform sizes (e.g., different FFT sizes). In some embodiments, the partition data indicates the frequency transform sizes for the ones of the partitions. In some embodiments, the mobile device is configured to select, based on the partition data, one or more of the plurality of partitions and decode the selected one or more partitions to determine data represented by the OFDM symbols in the selected one or more partitions.
In a next generation broadcast architecture, a broadcast gateway may send segments of a data file to a broadcast transmission system and to a server. The broadcast transmission system wirelessly transmits the segments to a user equipment (UE) device. When the UE device fails to decode a segment, it sends a request for re-transmission of the segment to the server via an IP network. The server re-transmits the requested segment to the UE device via the IP network. Furthermore, the gateway may receive one or more IP data flows (e.g., video streams) having variable bit rate. The gateway may apply dynamically-variable coding to the IP data flows so that the resulting coded IP data flows have an aggregate bit rate that matches a constant physical transport rate of the broadcast transmission system.
H04L 29/06 - Communication control; Communication processing characterised by a protocol
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04L 1/16 - Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
A method for operating a wireless network in a plurality of radio operating environments is disclosed. A first parameter value set is selected from a library of two or more parameter value sets. Each of the parameter value sets includes a value for each of one or more communication-related parameters. The first parameter value set is appropriate for a first target radio operating environment. The action of selecting the first parameter value set is performed for a first set of one or more infrastructure radios that are to be operated in the first target radio operating environment. The first parameter value set is applied to the first set of one or more infrastructure radios so that the first set of one or more infrastructure radios will start using the first parameter value set to wirelessly communicate with user devices.
A broadcast/broadband convergence system that delivers content from content sources to user equipment devices. The system provides: significantly enhanced mobile capability to the broadcast industry; an additional revenue source for the broadcast industry by dynamically selling available spectral resources for use by wireless broadband networks and/or broadcast content off-loaded from wireless broadband networks; additional spectrum for the broadband industry through the dynamic purchase of available spectrum; and an enriched user experience. A spectrum server may facilitate the dynamic allocation of radio spectrum made available by the broadcast networks. The broadcast networks may broadcast with enhanced waveform parameters to support mobile devices as well as fixed devices.
Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. A first address generator unit may be configured to perform an arithmetic operation dependent upon a first field of the plurality of fields. A second address generator unit may be configured to generate at least one address of a plurality of addresses, wherein each address is dependent upon a respective field of the plurality of fields. A parallel assembly language may be used to control the plurality of address generator units and the plurality of pipelined datapaths.
A multiprocessor system and method for swapping applications executing on the multiprocessor system are disclosed. The plurality of applications may include a first application and a plurality of other applications. The first application may be dynamically swapped with a second application. The swapping may be performed without stopping the plurality of other applications. The plurality of other applications may continue to execute during the swapping to perform a real-time operation and process real-time data. After the swapping, the plurality of other applications may continue to execute with the second application, and at least a subset of the plurality of other applications may communicate with the second application to perform the real time operation and process the real time data.
Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.
Embodiments of a synchronous digital system are disclosed that may include generation of clock and synchronization signals. Any of a plurality of available clock signals may be selected for use as a primary clock, without causing clock-induced errors in the synchronous digital system. The clock signals may be selected automatically or programmatically. Clock generation circuitry may generate a clock signal that is initially used as the primary clock. The clock generation circuitry may be dynamically reconfigured without interrupting operation of the synchronous digital system, by first selecting another of the available clock signals for use as the primary clock.
Embodiments are disclosed of a multi-chip apparatus capable of performing multi-rate synchronous communication between component chips. Each chip may receive a common clock reference signal, and may generate an internal clock signal dependent on the clock reference signal. A clock distribution tree and phase-locked loop may be used to minimize internal clock skew at I/O circuitry at the chip perimeter. Each chip may also generate an internal synchronizing signal that is phase-aligned to the received clock reference signal. Each chip may use its respective synchronizing signal to synchronize multiple clock dividers that provide software-selectable reduced-frequency clock signals to the I/O cells of the chip. In this way, the reduced-frequency clock signals of the multiple chips are edge-aligned to the low-skew internal clock signals, and phase-aligned to the common clock reference signal, allowing the I/O cells of the multiple chips to perform synchronous communication at multiple rates with low clock skew.
Embodiments of a synchronous digital system are disclosed that may include generation of clock and synchronization signals. Any of a plurality of available clock signals may be selected for use as a primary clock, without causing clock-induced errors in the synchronous digital system. A clock signal generated on-chip with the synchronous digital system may be automatically selected in response to detecting a condition indicating that use of a local clock may be necessary. Such conditions may include detection of tampering with the synchronous digital system. If an indication of tampering is detected, security measures may be performed.
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
G06F 11/16 - Error detection or correction of the data by redundancy in hardware
G06F 21/75 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation, e.g. to counteract reverse engineering
36.
PROCESSING SYSTEM WITH SYNCHRONIZATION INSTRUCTION
Embodiments of a multi-processor array are disclosed that may include a plurality of processors, and controllers. Each processor may include a plurality of processor ports and a sync adapter. Each sync adapter may include a plurality of adapter ports. Each controller may include a plurality of controller ports, and a configuration port. The plurality of processors and the plurality of controllers may be coupled together in an interspersed arrangement, and the controllers may be distinct from the processors. Each processor may be configured to send a synchronization signal through its adapter ports to one or more controllers, and to pause execution of program instructions while waiting for a response from the one or more controllers.
Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.
Embodiments of a multi-processor array are disclosed that may include a plurality of processors, local memories, configurable communication elements, and direct memory access (DMA) engines, and a DMA controller. Each processor may be coupled to one of the local memories, and the plurality of processors, local memories, and configurable communication elements may be coupled together in an interspersed arrangement. The DMA controller may be configured to control the operation of the plurality of DMA engines.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
39.
MULTIPROCESSOR PROGRAMMING TOOLKIT FOR DESIGN REUSE
Techniques for specifying and implementing a software application targeted for execution on a multiprocessor array (MPA). The MPA may include a plurality of processing elements, supporting memory, and a high bandwidth interconnection network (IN), communicatively coupling the plurality of processing elements and supporting memory. In one embodiment, software code may include first program instructions executable to perform a function. In this embodiment, the software code may also include one or more language constructs that are configurable to specify one or more communication ports and one or more parameter inputs. In this embodiment, the one or more communication ports are configurable to specify communication with other software code. In this embodiment, the one or more parameter inputs are configurable to specify a set of hardware resources usable to execute the software code. In this embodiment, the hardware resources include multiple processors and may include multiple supporting memories.
System and method for testing a DUT that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.
A split architecture for encoding a video stream. A source encoder may encode a video content stream to obtain an encoded bitstream and a side information stream. The side information stream includes information characterizing rate and/or distortion estimation functions per block of the video content stream. Also, a different set of estimation functions may be included per coding mode. The encoded bitstream and side information stream may be received by a video transcoder, which transcodes the encoded bitstream to a client-requested picture resolution, according to a client-requested video format and bit rate. The side information stream allows the transcoder to efficient and compactly perform rate control for its output bitstream, which is transmitted to the client device. This split architecture may be especially useful to operators of content delivery networks.
H04N 21/2343 - Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements
H04N 21/235 - Processing of additional data, e.g. scrambling of additional data or processing content descriptors
H04N 21/258 - Client or end-user data management, e.g. managing client capabilities, user preferences or demographics or processing of multiple end-users preferences to derive collaborative data
H04N 21/2662 - Controlling the complexity of the video stream, e.g. by scaling the resolution or bitrate of the video stream based on the client capabilities
42.
THREE DIMENSIONAL HOLOGRAPHIC DISPLAY COMPUTER SYSTEM
System and method for video holographic display. Information is received regarding a 2D hogel array with multiple hogel apertures, specifying number, size, and/or spacing of the hogel apertures. Information regarding a 3D scene is received, including a scaling factor mapping the 3D scene to a 3D display volume. Due to gradual variation of radiation patterns from hogel to hogel, a full set of color radiation intensity patterns for the entire hogel array may be generated by interpolating the color radiation intensity patterns from a sparse subset of the hogels without having to compute all of the patterns. The full set of color radiation intensity patterns may then be used to holographically display the 3D scene.
A frequency divider based on a series of divide-by-2/3 cells and divide-by-1/2/3 cells using extended division range is disclosed. The frequency divider uses modified divide-by-1/2/3 cells and additional circuit elements to correctly divide an input frequency by a divisor on successive output cycles while the divisor transitions across an octave boundary. The frequency divider creates a divide-by-1 mode for unused divide-by-1/2/3 cells in the series of cells. The divide-by-1 mode passes the input clock in the unused latches of each unused divide-by-1/2/3 cell as opposed to having each unused divide-by-1/2/3 cell implement divide-by-3 mode.
H03L 7/193 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
H03K 23/64 - Pulse counters comprising counting chainsFrequency dividers comprising counting chains with a base or radix other than a power of two
44.
DISABLING COMMUNICATION IN A MULTIPROCESSOR SYSTEM
Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.
A receiver system and method for recovering information from a symbol data sequence Y. The symbol data sequence Y corresponds to a symbol data sequence X that is transmitted onto the channel by a transmitter. The symbol data sequence X is generated by the transmitter based on associated information bits. At the receiver, a set of two or more processors operate in parallel on two or more overlapping subsequences of the symbol data sequence Y, where each of the two or more overlapping subsequences of the symbol data sequence Y corresponds to a respective portion of a trellis. The trellis describes redundancy in the symbol data sequence Y. The action of operating in parallel generates soft estimates for the associated information bits. The soft estimates are useable to form a receive message corresponding to the associated information bits.
First control information, generated according to a first protocol version, for configuring an audiovisual device to present a multimedia stream, may be generated. A first data structure specifying that the first control information is of the first protocol version may be generated. A plurality of packets, including a multimedia stream, the first control information, and the first data structure, may be generated and transmitted. Second control information, generated according to a second protocol version, for configuring an audiovisual device to present a multimedia stream, may be generated. The first data structure may be modified to include information about the second control information. A second plurality of packets, including the modified first data structure, the first control information, a multimedia stream specified by the first control information, the second control information, and a multimedia stream specified by the second control information, may be generated.
A system and method for wirelessly transmitting audiovisual information. First audiovisual information may be encoded using a first error correction coding method. A plurality of packets may be generated, including the first audiovisual information, second audiovisual information, and control information. The second audiovisual information may not be encoded using the first error correction coding method, and the control information may indicate this. The plurality of packets may be wirelessly transmitted. The control information may be usable by a receiver to determine that the second audiovisual information is not encoded using the first error correction coding method, and may thereby determine that the second audiovisual information is a different service version than the first audiovisual information.
H04H 60/07 - Arrangements for generating broadcast informationArrangements for generating broadcast-related information with a direct linkage to broadcast information or to broadcast space-timeArrangements for simultaneous generation of broadcast information and broadcast-related information characterised by processes or methods for the generation
A system and method for wirelessly transmitting audiovisual information. A first plurality of packets including audiovisual information may be generated. A second plurality of packets including error correction coding information for the audiovisual information may be generated. Control information for associating the error correction coding information with the audiovisual information may be generated, and a third plurality of packets including the control information may also be generated. The plurality of packets, including the first, second, and third pluralities of packets, may be transmitted to a mobile device in a wireless manner. The control information may inform the mobile device of the association of the first error correction coding information with the audiovisual information.
A system and method for wirelessly transmitting audiovisual information. Training information may be stored in a memory. A plurality of packets may be generated, including the training information. The plurality of packets may also include audiovisual information. The plurality of packets may include first information identifying a first training pattern of a plurality of possible training patterns. The first training pattern may specify one or more locations of the training information in the plurality of packets. The first information may be usable by a receiver to determine the first training pattern of the plurality of possible training patterns. The plurality of packets may be transmitted in a wireless manner.
A digital television broadcast system with transmission and/or reception of digital television signals for improved mobile reception. The communication layers in the transmit and receive portions of the transmission system can be dynamically modified, e.g., based on usage patterns or current channel characteristics. The transmission system also provides for cross layer control, whereby parameters in various of the communication layers are analyzed to determine appropriate updates to the system configuration.
System and method for developing an ASIC. A software program may be stored which includes program instructions which implement a function. The software program may be executed on a processing system at a desired system speed and may be validated based on the execution. A first hardware description of at least a portion of the processing system may be stored and may specify implementation of at least a portion of the processing system. A second hardware description may be generated that corresponds to a first portion of the first hardware description. The second hardware description may specify a dedicated hardware implementation of a first portion of the software program executing on the processing system. Generation of the second hardware description may be performed one or more times to fully specify the ASIC. An ASIC may be created which implements the function of the software program.
A computer-implemented method for creating a program for a multi-processor system comprising a plurality of interspersed processors and memories. A user may specify or create source code using a programming language. The source code specifies a plurality of tasks and communication of data among the plurality of tasks. However, the source code may not (and preferably is not required to 1) explicitly specify which physical processor will execute each task and 2) explicitly specify which communication mechanism to use among the plurality of tasks. The method then creates machine language instructions based on the source code, wherein the machine language instructions are designed to execute on the plurality of processors. Creation of the machine language instructions comprises assigning tasks for execution on respective processors and selecting communication mechanisms between the processors based on location of the respective processors and required data communication to satisfy system requirements.
G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
