Abstract

At least one aspect of the technical solutions can be directed to a system. The system can include a first access point (AP) that can be configured to transmit, to a second AP that can be capable of participating in coordinated beamforming (CBF) and a first candidate set of stations of the first AP, a first message to initiate transmission opportunity (TXOP). The second AP can be configured to transmit a second message to the first AP and a second candidate set of stations of second AP identified to participate in the TXOP. The second AP can be configured to transmit a third message having a CFB response to the first AP. The first AP can be configured to transmit a fourth message to second AP having a CBF trigger that can include information on a preamble of a CBF transmission to be communicated during the TXOP.

IPC Classes  ?

• H04W 74/0816 - Non-scheduled access, e.g. ALOHA using carrier sensing, e.g. carrier sense multiple access [CSMA] with collision avoidance
• H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
• H04W 28/02 - Traffic management, e.g. flow control or congestion control
• H04W 74/08 - Non-scheduled access, e.g. ALOHA

Abstract

The technical solutions are directed to coordinated beamforming per-TXOP frame sequence negotiation. A first access point (AP) can transmit, to a second AP and a first candidate set of stations, a first message to initiate transmission opportunity (TXOP) and a CBF request. The second AP can transmit a second message to a second candidate set of stations of the second AP identified to participate in the TXOP with a CBF response responsive to the CBF request. The first AP, responsive to receiving the CBF response, can transmit to the second AP a third message having a CBF trigger comprising information to synchronize a CBF transmission to be communicated during the TXOP.

IPC Classes  ?

• H04W 74/0816 - Non-scheduled access, e.g. ALOHA using carrier sensing, e.g. carrier sense multiple access [CSMA] with collision avoidance
• H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
• H04W 72/12 - Wireless traffic scheduling
• H04W 74/08 - Non-scheduled access, e.g. ALOHA

Abstract

A system includes a voltage booster circuit to receive an input voltage and provide an output voltage. A first device that is coupled to the voltage booster circuit to receive a digitized input voltage and a digitized output voltage and to determine, based on the digitized input voltage and the digitized output voltage, a first threshold level for the voltage booster circuit to operate in a pulse frequency modulation (PFM) mode. A second device that is coupled to the voltage booster circuit to receive the input voltage and the output voltage and to determine a second threshold level for the voltage booster circuit to operate in the PFM mode. A selector device that is coupled to the first device and the second device to select one of the first threshold level or the second threshold level for the voltage booster circuit.

IPC Classes  ?

• H02M 1/00 - Details of apparatus for conversion
• H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
• H03K 7/06 - Frequency or rate modulation, i.e. PFM or PRM
• H05B 45/335 - Pulse-frequency modulation [PFM]
• H05B 45/34 - Voltage stabilisationMaintaining constant voltage
• H05B 45/345 - Current stabilisationMaintaining constant current

Abstract

A system may include a transmitter and one or more processors. The one or more processors may be configured to identify a number of additional symbols to be added to existing symbols corresponding to payload data to be encoded. The one or more processors may be configured to calculate, based on a length of the payload data and the number of additional symbols, a number of available bits for error correction. The one or more processors may be configured to encode, via an low-density parity-check (LDPC) encoder, the payload data using an LDPC code to generate a codeword having a number of parity bits corresponding to the available bits. The one or more processors may be configured to transmit, via the transmitter, the encoded data.

IPC Classes  ?

• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

Technical solutions provide setup sequences for multi access point (AP) coordinated beamforming (CBF) at a transmission opportunity (TXOP) stage. A first AP can transmit, to a second AP capable of participating in CBF and a first station of the first AP, a notification indicative of a CBF TXOP. The first AP can receive, from at least the first station, responsive to the notification, a first response identifying a first capability of the first station. The first AP can receive, from the second AP associated with a second one or more stations, responsive to the notification, a second response identifying a second capability of at least one of the second AP or a second station of the second one or more stations. The first AP can communicate data to the first station during the CBF TXOP according to at least one of the first capability or the second capability.

IPC Classes  ?

• H04W 74/0808 - Non-scheduled access, e.g. ALOHA using carrier sensing, e.g. carrier sense multiple access [CSMA]

Abstract

Technical solutions include systems and methods for multi-access-point (AP) coordination of coordinated beamforming (CBF) for nulling of mutual interferences. A first AP can be configured to identify a second AP that is capable of participating in coordinated beamforming (CBF), select one or more candidate stations of the first AP and identify capabilities of at least one of the first AP or the one or more candidate stations. The first AP can be configured to determine one or more stations of the one or more candidate stations to participate in CBF based at least on the capabilities and perform a sequence with the second AP to exchange, between the first AP and the second AP, a set of stations of the first AP and the second AP to participate in CBF. The first AP can identify to the second AP the determined one or more stations as participating in CBF.

IPC Classes  ?

• H04B 7/024 - Co-operative use of antennas at several sites, e.g. in co-ordinated multipoint or co-operative multiple-input multiple-output [MIMO] systems
• H04W 48/08 - Access restriction or access information delivery, e.g. discovery data delivery

Abstract

Technical solutions providing setup sequences for multi-access point (AP) coordinated beamforming (CBF). A system can include a first access point (AP) configured to transmit, to a second AP that is capable of participating in coordinated beamforming (CBF), a first notification frame comprising a first set of stations of the first AP to participate in a CBF transmission. The first AP can be configured to receive, from the second AP, responsive to the first notification frame, a first response frame comprising a second set of stations of the second AP to participate in the CBF transmission. The first AP can be configured to transmit data in the CBF transmission to at least one station of the first set of stations or the second set of stations, responsive to the first response frame.

IPC Classes  ?

• H04B 7/026 - Co-operative diversity, e.g. using fixed or mobile stations as relays
• H04W 24/02 - Arrangements for optimising operational condition

Abstract

Novel tools and techniques are provided for implementing a novel integrated programmable gain amplifier (“PGA”) and protection circuit. In various embodiments, a circuit is provided that comprises: a PGA, an analog-to-digital converter (“ADC”), and a protection circuit all disposed on the same semiconductor chip. The PGA is configured to receive as input a wireless signal received from an antenna and to output, at its output, an amplified wireless signal based on the wireless signal being amplified by a programmable gain amount. The protection circuit is configured to, in response to detecting a spike in gain at the output of the PGA that exceeds a threshold amplitude, control a decrease in the programmable gain amount to cause a resultant signal at the output of the PGA to be below the threshold amplitude. A normally-open switch may also be added at differential outputs of the PGA to further clamp PGA output.

IPC Classes  ?

• H04B 1/04 - Circuits
• H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission

Abstract

Novel tools and techniques are provided for implementing migration of one or more drives, and more particularly to methods, systems, and apparatuses for implementing migration of one or more drives by setting one or more indications on a memory of the one or more drives. A controller for a redundant array of independent disks can be configured to set a first indication indicating a first drive is safe to migrate or not safe to migrate and store the first indication in a first memory on the first drive. The first drive can be a mirror of a second drive. The controller can further be configured to set a second indication indicating the second drive was offline or not offline and store the second indication in the first memory on the first drive.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A circuit for driving digital-to-analog converter (DAC) comprising a serializer configured to combine multiple signals to one input signal to drive a forward inverter coupled to a first node with a first impedance in serial configuration and a first capacitance in shunt configuration. The circuit includes a chain of inverters coupled in series to transfer the input signal from the first node to the fifth node based on a signal transfer function. The circuit further includes a feedback inverter between the third node and the first node to form a feedback loop with two inverters in the chain, adding peaking in the signal transfer function at the first node. A second feedback inverter can be added between the fifth node and the third node to add peaking in the signal transfer function at the third node. The feedback inverter is designed as a current-starved inverter in order to alleviate hot-carrier injection (HCI) aging of the transistors and add programmability in the peaking. The circuit includes a DAC switch coupled to the fifth node.

IPC Classes  ?

• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Abstract

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 1/2, a second parity check matrix corresponding to a first exponent matrix comprising 1152 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Abstract

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 5/6, a second parity check matrix corresponding to a first exponent matrix comprising 384 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes

Abstract

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 3/4, a second parity check matrix corresponding to a first exponent matrix comprising 576 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Abstract

A digital signal processing (DSP)-based serializer-deserializer (SERDES) includes a first filter configured to mitigate inter-symbol interference (ISI) attributed to dispersion associated with a long-reach transmission medium. The SERDES includes a second filter configured to shape the ISI. The SERDES includes also includes a third filter coupled in parallel with the second filter and configured to reduce ISI attributed to reflections associated to both near-zero delays and long delays.

IPC Classes  ?

• H03H 21/00 - Adaptive networks
• H03H 17/00 - Networks using digital techniques
• H03H 17/02 - Frequency-selective networks

Abstract

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 2/3, a second parity check matrix corresponding to a first exponent matrix comprising 768 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes

Abstract

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, by a low-density parity-check (LDPC) encoder, a target code rate for which to encode data. The one or more processors may receive, by the LDPC encoder, a first set of information bits. The one or more processors may receive, by the LDPC encoder from an output of a shaping encoder, a second set of information bits. The one or more processors may adjust a code rate of an LDPC code to a second code rate higher than the target code rate to cause the LDPC encoder to encode the data at the target code rate. The one or more processors may encode the data using the LDPC code. The transmitter may transmit the encoded data.

IPC Classes  ?

• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

A device configured to support different numbers of outputs. The device includes an input port configured to receive an input signal. The device also includes a first transmission line characterized by a first characteristic impedance and coupled to a first output port. A switch is configured to either connect or disconnect the first transmission line to the input port. The device also includes a second transmission line characterized by a second characteristic impedance and coupled between the input port and a second output port. A controller is configured to activate the first switch to set a two-output mode or to deactivate the first switch to set a one-output mode. The second characteristic impedance is configured to be the same as the first characteristic impedance at the two-output mode or configured to be reduced to 1/√{square root over (2)} of the first characteristic impedance at the one-output mode.

IPC Classes  ?

• H01P 5/16 - Conjugate devices, i.e. devices having at least one port decoupled from one other port

Abstract

Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package or a chip package including a one or more channel vias. In various embodiments, an apparatus includes a first layer comprising a channel and a first via extending through the first layer to a first surface of a first ridge of the first channel. The apparatus can further include a second layer coupled to the first layer. The second layer can be a first outer layer of the first substrate. The apparatus can also include a first line coupled to the first via and extending along the first ridge of the first channel and embedded in the second layer.

IPC Classes  ?

• H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids

Abstract

Described embodiments provide systems and methods for profiling low latency applications using telemetry. A data processing system can include one or more processors and memory. The data processing system can receive telemetry data for a plurality of flows of packets. The data processing system can determine, using the telemetry data, a variance of bandwidth, a variance of packet lengths, and a variance of inter-arrival times between packets for each of the flows of packets. The data processing system can determine a type of application for a flow of the flows of packets based at least on a signature of the variance of bandwidth, the variance of packet lengths, and the variance of inter-arrival times for the flow. The data processing system can take, in response to determining the type of application, one or more actions to provide a quality of service for the flow according to the type of application.

IPC Classes  ?

• H04L 43/062 - Generation of reports related to network traffic
• H04L 43/067 - Generation of reports using time frame reporting
• H04L 47/22 - Traffic shaping

Abstract

An integrated circuit package includes a first integrated circuit die, a second integrated circuit die, and a third integrated circuit die. The integrated circuit package also includes a support structure. The first die, the second die, and the third die are attached to the support structure. The first integrated circuit die includes a first interface on a first side of the first integrated circuit die and the second integrated circuit die includes a second interface on a second side of the second integrated circuit die. The first side neighbors the second side. The first integrated circuit die is configured to communicate with second integrated circuit die via the first interface and the second interface. The first integrated circuit die includes a third interface on a third side of the first integrated circuit die and the second integrated circuit die includes a fourth interface on a fourth side of the second integrated circuit die. The third die includes a fifth interface on a fifth side and a sixth interface on sixth side. The sixth side is parallel to the third side and the fifth side, The first integrated circuit die is configured to communicate with the third integrated circuit die via the fifth interface and the third interface. The second integrated circuit die is configured to communicate with the third integrated circuit die via the sixth interface and the fourth interface.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/498 - Leads on insulating substrates
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

A system can include circuitry. The circuitry can receive an entry index of a table, perform a cycle walk of a first pipeline stage to change the entry index from a first value to a second value, determine that the second value of the entry index is an illegal value, provide the second value of the entry index to a second pipeline stage, and perform a cycle walk of the second pipeline stage to change the entry index to a legal value.

IPC Classes  ?

• G06F 12/14 - Protection against unauthorised use of memory
• G06F 12/02 - Addressing or allocationRelocation

Abstract

An apparatus for aligning a fiber array unit (FAU) connector with a photonic integrated circuit (PIC) includes an aligner having a front section and a bottom section respectively joined with two side sections spaced apart by a first distance. The front section and the bottom section are partially removed to expand a semi-confined open space between the two side sections for receiving a shelf extended out beyond a lens at a side edge of a PIC chip. The shelf has an alignment feature associated with the lens. The front section is configured as a support bar positioned on a surface of the PIC chip. The semi-confined open space between the two side sections allows a body of the FAU connector to be loaded down from top to sit on the shelf in the semi-confined open space and be aligned with the lens through the alignment feature.

IPC Classes  ?

• G02B 6/30 - Optical coupling means for use between fibre and thin-film device

Abstract

The technical solutions are directed to MAC address protection for frame integrity verification. A sender device can compute, using a temporal key (TK) programmed in hardware, a first key for a body of a frame and a second key for a header of the frame, different from the first key. The sender can encrypt the body of the frame at a machine access control (MAC) layer using the first key and the header of the frame at the MAC layer using the second key. The sender can compute a first MIC of the encrypted frame using the first key and a second MIC of a content of the header at the MAC layer using the second key. The sender can transmit the frame with the first MIC and the second MIC to a receiver configured to determine integrity of the header of the frame based on the second MIC.

IPC Classes  ?

• H04L 9/08 - Key distribution
• H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems

Abstract

Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package or a chip package including an optical package or co-packaged optics package comprising a lid. In an embodiment, an optical package can include a first substrate, a first circuit coupled to the first substrate and configured to transmit or receive an electrical signal, a second circuit coupled to the first substrate and configured to transmit or receive an optical signal, and a lid configured to couple to the first substrate and configured to cover at least a portion of the first circuit or the second circuit.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

An apparatus for supporting two fiber array unit (FAU) connectors in alignment with respective lenses of a photonics integrated circuit (PIC) includes a frame with a pair of arm sections joined with two side sections of a bottom section. The pair of arm sections is configured to parallelly insert in a package structure associated with a PIC chip to make the frame in a floating state. The bottom section provides a first support surface to support two aligners disposed respectively along the two side sections from top. Each aligner provides a semi-confined open space to receive a shelf extended out from a side edge of a PIC chip. The shelf is characterized by an alignment feature associated with a lens of the PIC chip. The semi-confined open space allows a body of a FAU connector to be loaded from top onto the shelf and be aligned with the lens based on the alignment feature.

IPC Classes  ?

• G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

Solutions for providing more customizable performance for a virtual disk in a RAID environment. Some solutions provide for a flexible write cache policy that manages a proportion of input-output operations written in write-back mode against input-output operations written in write-though mode. In some cases, aspects of the flexible write cache policy can be specified by a user.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A device is provided that includes computer-readable storage media storing one or more sequences of instructions and processing circuitry configured to execute the one or more sequences of instructions. Upon executing the instructions, the processing circuitry may receive a plurality of network packets containing content encapsulated in a plurality of layers; process the received plurality of network packets to extract the content for presentation; generate a predicted presentation quality indicator for the extracted content using a plurality of machine learning models in a hierarchical order with data generated during processing of the received plurality of network packets used as inputs to the plurality of machine learning models; and provide the predicted presentation quality indicator for the extracted content to a server via a network, wherein the data generated during processing of the received plurality of network packets is correlated across the plurality of layers to generate the predicted presentation quality indicator.

IPC Classes  ?

• H04N 21/24 - Monitoring of processes or resources, e.g. monitoring of server load, available bandwidth or upstream requests
• H04L 65/80 - Responding to QoS
• H04N 21/442 - Monitoring of processes or resources, e.g. detecting the failure of a recording device, monitoring the downstream bandwidth, the number of times a movie has been viewed or the storage space available from the internal hard disk
• H04N 21/466 - Learning process for intelligent management, e.g. learning user preferences for recommending movies

Abstract

A circuitry can transmit a first probe request to discover a first access point of a first channel. The circuitry can also transmit one or more additional probe requests to discover one or more other access points of one or more other channels. The circuitry can also, responsive to transmission of the one or more additional probe requests, check for the response to the first probe request on the first channel. The circuitry can also receive the response to the first probe request. The response can identify the first access point.

IPC Classes  ?

• H04W 40/24 - Connectivity information management, e.g. connectivity discovery or connectivity update
• H04W 24/08 - Testing using real traffic
• H04W 88/08 - Access point devices

Abstract

Wide-band output isolation is provided. A device includes a first output for a first radio frequency (RF) signal. A device includes a second output for a second RF signal. The device includes a first transistor having a first source/drain. The device includes a second transistor having a first source/drain, wherein the first source/drain of the first transistor is coupled to the first source/drain of the second transistor and wherein the first and second transistors are disposed between the first output and the second output.

IPC Classes  ?

• H01P 5/16 - Conjugate devices, i.e. devices having at least one port decoupled from one other port
• H04B 1/40 - Circuits

Abstract

Novel systems and methods for canvas sanitization are provided. In various embodiments, a system and method include: receiving a request to open a web page from a client device; replacing, via an agent, a first function with a second function, the agent being loaded to a browser; loading the web page from a web server to the browser; in response to an attempt to perform the first function on the web page, performing, via the browser, the second function corresponding to the first function to generate a drawing for a predetermined period of time; converting, via the agent, the drawing to an image; and transmitting the image to the client device. Other aspects, embodiments, and features are also claimed and described.

IPC Classes  ?

• G06F 9/4401 - Bootstrapping

Abstract

A system may include a first analog-to-digital converter (ADC) of a first type electrically coupled by a plurality of switches to a plurality of ADCs of a second type. The plurality of switches may be configured to select, based on a rate of an analog-to-digital conversion, a quantity of ADCs of the second type, from among the plurality of ADCs of the second type, to supply the analog-to-digital conversion at the rate. The plurality of switches may be configured to selectively bypass the first ADC according to a resolution of the analog-to-digital conversion. The plurality of switches may be configured to bypass the first ADC responsive to the resolution of the conversion being below a threshold.

IPC Classes  ?

• H03M 1/12 - Analogue/digital converters
• H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter

Abstract

Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package or a chip package including a backside power distribution network. In various embodiments, an apparatus includes a first substrate comprising a device configured to receive a voltage and a first side located on a front side of the first substrate and a second side located on a back side of the first substrate, a second substrate, the second substrate configured to support the first substrate, and a power distribution network located at an interface between the second side of the first substrate and the second substrate.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

A device to receive a first signal from a driver. The device comprising a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit to provide a second signal having a first level. The second circuit to detect the first level of the first signal and to provide a third signal to control a third circuit of the device. The third circuit to provide a fourth signal, the fourth signal having a first level in response to a difference being smaller than a predetermined value, and the fourth signal having a second level in response to the difference being larger than the predetermined value. The fourth circuit to provide a fifth signal, the fifth signal having a first level based at least on the second signal, and the fifth signal having a second level based at least on the second signal and the fourth signal.

IPC Classes  ?

• H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
• H03F 3/189 - High-frequency amplifiers, e.g. radio frequency amplifiers

Abstract

A system may include one or more receivers, circuitry, and a controller. Each of the one or more receivers may include a plurality of analog-to-digital converters (ADCs). Each ADC may measure a time relating to an analog-to-digital conversion by the ADC, compare the time with a threshold, and generate, based on a result of the comparing, a first signal. The circuitry may be coupled to the one or more receivers. The circuitry may receive the first signal from each ADC, determine, based at least on the first signal, characteristics of performance of each receiver, and output a plurality of second signals. Each of the plurality of second signals may indicate the characteristics of performance of a corresponding receiver. The controller may be coupled to the circuitry and adjust a voltage provided to the one or more receivers, based at least on the plurality of second signals received from the circuitry.

IPC Classes  ?

• H03M 1/44 - Sequential comparisons in series-connected stages with change in value of analogue signal

Abstract

Novel tools and techniques are provided for implementing a semiconductor or optical engine package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package including a dummy die coupled to a top surface of a fan-out wafer comprising an electronic die and coupled to a side of a photonic die. In various embodiments, an apparatus includes a first layer comprising an electronic die. A photonic die can be stacked on and coupled to the electronic die and a dummy die can be coupled to a first side of the photonic die and coupled to the first layer.

IPC Classes  ?

• H01S 5/0233 - Mounting configuration of laser chips

Abstract

Solutions for managing RAID logical devices. Some solutions provide enhanced online capacity expansion for virtual disks on RAID drives, for example by taking advantage of the hardware capabilities to expand a virtual disk stripe by stripe. Some solutions provide increase hardware automation, which can reduce firmware load and/or provide more efficient input-output operations (IO) for the online capacity expansion operation.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

Solutions for managing RAID virtual disks. Some solutions enable increased use of hardware circuitry to schedule and perform IO on a virtual drive, providing for more efficient IO. In some cases, this can be accomplished by notifying the hardware of precise regions of a virtual disk affected by the maintenance operation and any given time. The hardware then, can continue to perform host IO on portions of the logical disk not undergoing maintenance.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

An amplifier includes a first transmission line from a first terminal to a second terminal. The first transmission line is characterized by a first characteristic impedance matched to a resistance of a source from which a first signal is coupled to the second terminal. The amplifier includes a first resistor with a first resistance and a second resistor with a second resistance coupled between the second terminal and a third terminal. The first resistance and the second resistance are adjustable to match an input impedance at the second terminal to the first characteristic impedance and to tune a gain of a second signal at the third terminal over the first signal at the second terminal. The amplifier includes a second transmission line from the third terminal to a third resistor with a third resistance, the second transmission line being characterized by a second characteristic impedance matched to the third resistance.

IPC Classes  ?

• H03F 3/60 - Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
• H03G 3/20 - Automatic control

Abstract

The subject technology is directed to light detection and ranging (LIDAR) systems and methods. In an embodiment, the subject technology provides a device comprising an optical module configured to receive a first optical signal and a first circuit configured to generate a first electrical signal based on the first optical signal. The device also comprises a first comparator configured to generate a second electrical signal by comparing the first electrical signal to a first threshold value. The device further comprises a first filter configured to generate a first pulse based on the second electrical signal. The first pulse comprises a first point associated with a first timestamp. The timestamp data may be briefly retained in the analog domain, followed by subsequent digital conversion, allowing for significant power savings and reduced system bandwidth. There are other embodiments as well.

IPC Classes  ?

• G01S 7/487 - Extracting wanted echo signals
• G01S 7/4865 - Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
• H03M 1/36 - Analogue value compared with reference values simultaneously only, i.e. parallel type

Abstract

The subject technology is related to acoustic resonators. More specifically, an embodiment of the subject technology provides an acoustic resonator device that includes a piezoelectric layer disposed between a first electrode and a second electrode. The total thickness of the first electrode, the second electrode, and the third electrode allows the device to operate according to a second (or higher order) thickness extension mode. There are other embodiments as well.

IPC Classes  ?

• H03H 9/13 - Driving means, e.g. electrodes, coils for networks consisting of piezoelectric or electrostrictive materials
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 9/17 - Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator

Abstract

A device may include an oscillator and a driver. The oscillator may be coupled to circuitry providing calibration of the oscillator. The oscillator may receive from the circuitry a first signal that causes the oscillator to generate a second signal having a first frequency to be used for calibration of an analog-to-digital converter (ADC). The driver may be coupled to the oscillator and the ADC. The driver may receive the second signal from the oscillator. The driver may receive a third signal indicating an amplitude to apply to the second signal. The driver may provide, to the ADC based at least on the second signal and the third signal, an output signal having the first frequency and the amplitude.

IPC Classes  ?

• H03M 1/50 - Analogue/digital converters with intermediate conversion to time interval
• H03M 1/10 - Calibration or testing

Abstract

Wide-band matching in out-of-band blocker rejection filters is provided. A device includes a first inductor. The device includes a second inductor magnetically coupled with the first inductor and with an amplifier. The device includes a notch filter electrically coupled between the first inductor and the second inductor. The amplifier can be configured to amplify a plurality of radio frequency signals. A bandwidth of the radio frequency signals can exceed 1.5 gigahertz (GHz).

IPC Classes  ?

• H03F 3/19 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only

Abstract

Wide-band output isolation is provided. A device includes a first output for a first radio frequency (RF) signal. A device includes a second output for a second RF signal. The device includes a first transistor having a first source/drain. The device includes a second transistor having a first source/drain, wherein the first source/drain of the first transistor is coupled to the first source/drain of the second transistor and wherein the first and second transistors are disposed between the first output and the second output.

IPC Classes  ?

• H03F 3/19 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
• H01P 5/16 - Conjugate devices, i.e. devices having at least one port decoupled from one other port

Abstract

A device comprising a first circuit, a second circuit, and a third circuit. The first circuit to receive, from an amplifier, a first signal having a first amount of power. The first circuit to also determine, based on the first amount of power, a range of power associated with transmission of the first signal by a transmitter. The second circuit to receive a second signal to define one or more characteristics of the second circuit. Receipt of the second signal, by the second circuit, can cause the second circuit to adjust the first signal from the first amount of power to a second amount of power. The third circuit to receive, from the second circuit, the first signal having the second amount of power, and the third circuit to provide a third signal having a voltage level to indicate a third amount of power transmitted by the transmitter.

IPC Classes  ?

• H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets
• H04B 17/318 - Received signal strength

Abstract

A video decoder with in-loop memory bandwidth compression is provided. A video decoder includes a decoding logic configured to decode an encoded bitstream to generate a reference block of video data, and a memory bandwidth compression logic configured to compress the reference block of video data based on a selection between a first compression algorithm, second compression algorithm, or to copy the reference block without compression. Selection is based on at least one of the first block size, second block size, or uncompressed block size. The selected block is written to an off-chip memory, and a compression algorithm indicator associated with the selected block is written to an on-chip memory.

IPC Classes  ?

• H04N 19/423 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
• H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
• H04N 19/124 - Quantisation
• H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock

Abstract

In some implementations, a circuitry may include a series of symmetrical stages with an initial stage in the series coupled to an input signal having a first plurality of phases and an output stage in the series coupling an output signal comprising a second plurality of phases to a calibration engine, where a quantity of the phases in the output signal is increased based at least on a quantity of the symmetrical stages and a quantity of the first plurality of the phases in the input signal. In addition, the circuitry may include implementations, where the calibration engine calibrates a frequency of the circuitry within a range based at least on a target frequency. The circuitry may include implementations, where the calibration engine outputs a current provided to the series, where the output current can be based at least on a calibrated frequency.

IPC Classes  ?

• H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

The disclosure describes systems and methods for downlink channel sounding in multi-access point (multi-AP) networks. The system can be configured to provide one or more sounding options. In joint sounding options, stations can measure the combined downlink channel from all the APs and can provide feedback on the composite channel. In individual sounding options, stations can measure the downlink channel from each AP separately and can provide feedback on the individual channels. In implicit sounding options, each AP can estimate the uplink channel transmitted by the stations. The uplink channel information can then be used to derive the corresponding downlink channel.

IPC Classes  ?

• H04W 24/10 - Scheduling measurement reports
• H04W 48/08 - Access restriction or access information delivery, e.g. discovery data delivery

Abstract

Improved solutions that enable more effective and efficient communications with users, in particular with respect to field diagnostics and services. Some solutions can enable users to better communicate with a provider to obtain more useful diagnostic and service information. Certain solutions can employ multi-model switching machine learning techniques to enhance a user's communication with the provider and/or the provider's response.

IPC Classes  ?

• H04L 43/08 - Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
• G06N 20/20 - Ensemble learning
• H04L 41/083 - Configuration setting characterised by the purposes of a change of settings, e.g. optimising configuration for enhancing reliability for increasing network speed
• H04L 51/02 - User-to-user messaging in packet-switching networks, transmitted according to store-and-forward or real-time protocols, e.g. e-mail using automatic reactions or user delegation, e.g. automatic replies or chatbot-generated messages

Abstract

A filter device for multi-band wireless communication includes a first circuit characterized by a first pass-band from a first frequency to a second frequency; a second circuit characterized by a second pass-band from a frequency no smaller than the first frequency to a third frequency, the third frequency being no higher than the second frequency but higher than the first frequency; a third circuit characterized by a third pass-band from a fourth frequency to a frequency no greater than the second frequency, the fourth frequency being no smaller than the first frequency but smaller than the second frequency; and a switch configured to connect the first circuit either to the second circuit to reconfigure a first filter with the second pass-band or to the third circuit to reconfigure a second filter with the third pass-band.

IPC Classes  ?

• H03H 7/01 - Frequency selective two-port networks
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details

Abstract

The subject technology is directed to acoustic filter systems and methods. In an embodiment, the subject technology provides a first resonator, a second resonator, and a third resonator. The first resonator comprises a first layer coupled to and positioned between a first electrode and a second electrode. The second resonator is coupled to the first resonator at a first node. The third resonator is coupled to the first node and a ground terminal. The third resonator comprises a second layer coupled to and positioned between a third electrode and a fourth electrode. Depending on the implementation, each resonator may be associated with one or more thickness extension (TE) modes and the device can function in high-frequency ranges (e.g., greater than 5 GHz) with low insertion loss. There are other embodiments as well.

IPC Classes  ?

• H03H 9/60 - Electric coupling means therefor
• H03H 9/13 - Driving means, e.g. electrodes, coils for networks consisting of piezoelectric or electrostrictive materials
• H03H 9/205 - Constructional features of resonators consisting of piezoelectric or electrostrictive material having multiple resonators

Abstract

A device may include a digital-to-analog converter (DAC), including a current source, circuitry to mirror the current source, the circuitry including a transistor coupled to the current source, and a plurality of output paths, each output path of the plurality of output paths including a first switch to selectively configure a first transistor to mirror the current source, wherein each output path corresponds to a value of a respective bit of a first digital signal, and a plurality of cells, each cell of the plurality of cells including a second switch to selectively couple a second transistor to a corresponding one of the plurality of output paths, wherein each of the plurality of cells corresponds to a value of a respective bit of a second digital signal.

IPC Classes  ?

• H03M 1/68 - Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits

Abstract

A unit capacitor for a switched-capacitor digital-to-analog converter is provided. An apparatus includes a first plate formed of a conductive material, wherein the first plate comprises one or more first fingers, wherein each respective first finger of the one or more first fingers has an elongated structure extending longitudinally in a first direction. The apparatus further includes a second plate formed of the conductive material, wherein the second plate comprises two or more second fingers, wherein each respective second finger of the two or more second fingers has an elongated structure extending in a second direction. Each first finger of the one or more first fingers is disposed between two adjacent second fingers of the two or more second fingers.

IPC Classes  ?

• H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
• H03M 1/00 - Analogue/digital conversionDigital/analogue conversion

Abstract

An MMU with prefetch functionality is provided. The MMU includes a first TLB, burst buffer, second TLB and control logic. The first TLB is configured to fetch a first set of one or more first page table entries based, at least in part, on a virtual address, and before a request to access a client address is received from a client. The burst buffer stores a plurality of second page table entries from a respective page table associated with a first page table address. A second translation lookaside buffer is configured to fetch a first set of one or more second page table entries of the plurality of second page table entries from the burst buffer based, at least in part, on the virtual address, and before the request to access a client address is received from the client.

IPC Classes  ?

• G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
• G06F 12/1009 - Address translation using page tables, e.g. page table structures
• G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus

Abstract

In some implementations, the circuitry may include a circuit configured to receive a baseband signal, the baseband signal having an intermodulated non-linear distorted portion and a harmonic distorted portion. In addition, the circuitry may include a compensator coupled to the circuit, the compensator configured to generate a value to compensate for the intermodulated non-linear distorted portion without compensating for the harmonic distorted portion. The circuitry may include where the compensator is configured to output the value. The circuitry may include where the circuit is configured to adjust the baseband signal using the value. In some embodiments, the baseband signal can be baseband voltage. In some embodiments, the value can be a complex number.

IPC Classes  ?

• H04B 1/04 - Circuits
• H03F 1/32 - Modifications of amplifiers to reduce non-linear distortion

Abstract

A circuit for determining head gimbal assembly (HGA) height is provided. The circuit includes a first switch configured to be controlled by a first clock signal, an amplifier, and a first capacitor coupled to the first switch, wherein the first capacitor is formed by at least part of a head gimbal assembly and a storage media. The circuit further includes a second capacitor coupled to an input of the amplifier, and an output of the amplifier, wherein the second capacitor is configured to store a charge from the first capacitor over one or more cycles of the first clock signal. The amplifier is configured to generate an output voltage based, at least in part, on a change in the capacitance of the first capacitor over the one or more cycles of the first clock signal.

IPC Classes  ?

• G11B 5/48 - Disposition or mounting of heads relative to record carriers

Abstract

Novel tools and techniques are provided for implementing encoding or decoding of adaptive bitrate streams. In various embodiments, one or more first computing systems may divide a live media content stream into one or more segments, each segment might include a starting segment boundary and an ending segment boundary. The one or more first computing systems might encode the one or more segments into one or more primary adaptive bitrate streams. The one or more first computing systems might also divide the one or more segments of the live media content stream into one or more subsegments. Each subsegment might be less than a length of a corresponding segment of the one or more segments. The one or more first computing systems might the encode and/or a second computing system might decode the one or more subsegments into or from one or more secondary adaptive bitrate streams.

IPC Classes  ?

• H04L 65/75 - Media network packet handling
• H04L 65/61 - Network streaming of media packets for supporting one-way streaming services, e.g. Internet radio
• H04L 65/70 - Media network packetisation

Abstract

In some implementations, the system may include one or more processors, coupled to memory, the processor configured to set in the memory a pool of shared send queues (SSQs), each SSQ in the pool of SSQs is configured for use as a send queue (SQ) for one or more queue pairs (QPs). The one or more processors may allocate at least one of SSQs from the pool of SSQs to the QP, the SSQ set for a process having a plurality of connections to a plurality of remote processes. The one or more processors may send by the SSQ, via the plurality of connections, outgoing messages to separate remote processes of the plurality of remote processes. Also, the system may include implementations where the pool is set responsive to a first number of the QPs reaching a threshold. The system may include implementations where the pool of SSQs is pinned in the memory.

IPC Classes  ?

• H04L 67/1097 - Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]

Abstract

The technical solution is directed to ultra-high reliability (UHR) extended long-range (ELR) packet formats for enhanced long-range communications and applications. A sender can identify data to be transmitted wirelessly to a receiver according to UHR-ELR format. The sender can generate a preamble for a PPDU frame of the UHR-ELR format. The preamble can include slots for a legacy portion and for the UHR-ELR portion. The sender can include an ELR symbol in a slot the legacy portion to auto-detect that the PPDU frame is for UHR-ELR. The sender can identify a power boost for transmitting at least a L-STF or a L-LTF and transmit the PPDU frame providing the power boost to the L-STF or the L-LTF.

IPC Classes  ?

• H04L 1/00 - Arrangements for detecting or preventing errors in the information received
• H04L 5/00 - Arrangements affording multiple use of the transmission path

Abstract

A semiconductor device, such as a gate-all-around field-effect transistor (GAAFET), that can provide advantages in terms of higher operating voltages. The semiconductor device includes a substrate with a p-type well, an n-type well, and a depletion region; an insulating layer disposed on the p-type well; a first epitaxial layer disposed on the insulating layer; a second epitaxial layer disposed on the p-type well, the n-type well, and/or the depletion region; and a gate formed around a channel and between the first epitaxial layer and the second epitaxial layer.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/786 - Thin-film transistors

Abstract

A front-end module in compact printed circuit board (PCB) package. The module comprises a PCB comprising a top surface, the top surface comprising a first portion. The module also comprises a power amplifier block disposed on the PCB, the power amplifier block comprising a power amplifier and an output-matching network (OMN) transformer. The power amplifier is coupled to the first portion of the top surface. The OMN transformer is positioned in the PCB vertically under the power amplifier at a first level below the top surface. The module is provided in a compact package with the power amplifier block in the first portion and other functional blocks comprising a filter block, a switch block, a control block, and a low-noise amplifier block, and being disposed on a remaining area of the PCB, outside of the first portion.

IPC Classes  ?

• H04B 1/58 - Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa

Abstract

A data storage controller is provided that includes: a computer-readable storage medium storing one or more sequences of instructions; and one or more processors configured to execute the one or more sequences of instructions to: receive a host write request for a logical drive corresponding to a redundant array of physical drives, wherein the redundant array of physical drives comprises a first physical drive of a first drive type and a second physical drive of a second drive type different from the first drive type, and wherein data stored on the first physical drive is mirrored on the second physical drive; generate and issue a first input-output (IO) request for the first physical drive based on the host write request and a first cache policy associated with the first drive type; and generate and issue a second IO request for the second physical drive based on the host write request and a second cache policy associated with the second drive type, wherein the first cache policy is different from the second cache policy.

IPC Classes  ?

• G06F 12/0866 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache

Abstract

A network device includes at least one port and a processor for use in a network for communicating a packet. The processor is configured to obtain a packet header for a packet and perform telemetry using postcard and/or passport approaches. The processor uses a repurposed field in the packet header to indicate telemetry is to be performed on the packet.

IPC Classes  ?

• H04L 45/74 - Address processing for routing
• H04L 47/43 - Assembling or disassembling of packets, e.g. segmentation and reassembly [SAR]

Abstract

Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package or a chip package including a substrate comprising a first channel, a first die coupled to the first substrate and comprising at least a first portion of a second channel, and a first opening extending from the first channel to the second channel.

IPC Classes  ?

• H01L 23/46 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

Described herein are systems and methods for implementing a look up table by a network node, and performing or supporting time synchronization based on the look up table. In one aspect, a network node may receive a packet. The network node can identify a few number of bits in the packet, and determine one or more actions or functions corresponding to the few number of bits via the look up table. In addition, the network node can execute or perform the determined one or more actions to support time synchronization.

IPC Classes  ?

• H04J 3/06 - Synchronising arrangements

Abstract

Novel tools and techniques are provided for implementing storage of one or more keys received by a chip, and more particularly to methods, systems, and apparatuses for implementing storage of one or more keys in a storage of a first device that is external to the chip. An integrated circuit can include a circuit configured to receive at least one of a key or a request to retrieve the key and at least one of store the key in a storage of a device when the key is received or retrieve the key from the storage of the device when the request to retrieve the key is received. The first device can be external to the integrated circuit. The circuit can further be configured to control access to the key stored in the storage of the device.

IPC Classes  ?

• G06F 21/45 - Structures or tools for the administration of authentication

Abstract

In some aspects, a method may include identifying, by one or more processors, a presence of an error in a plurality of data storage units in a range of data storage units of an error bitmap of a redundant array of independent disks (RAID). The method may include generating, by the one or more processors, a parity RAID request format (PRRQ) frame, the PRRQ frame identifying the range of data storage units, where at least one data storage unit has an error, the range of data storage units identified at least in the plurality of data storage units. The method may include communicating, by the one or more processors, the PRRQ frame to a controller, the controller is configured, responsive to the PRRQ frame, to recover the data in the range of data storage units in the plurality of data storage units.

IPC Classes  ?

• G06F 11/00 - Error detectionError correctionMonitoring
• G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens

Abstract

The subject technology is directed to systems and methods for power delivery in semiconductor devices. According to an embodiment, the subject technology provides a semiconductor device including a substrate comprising a first side and a second side. A first connection is coupled to the first side and a grid is coupled to the second side. The semiconductor device further comprises a first via coupled to the first connection and the grid, the first via is configured to transmit electrical power between the first side and the second side. In some implementations, the first via may be configured to improve the uniformity of power delivery and distribution, allowing for optimal circuit design and thermal effects. There are other embodiments as well.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

The subject technology is directed to systems and methods for enhancing die-to-die connectivity in semiconductor devices. According to an embodiment, the subject technology provides a device that includes a first layer comprising a first block and a second layer comprising a second block. The device further includes a third layer coupled to and positioned between the first and second layers. The first and second layers are aligned at a first region of the first connection, based on a set of design strategies. Embodiments of the subject technology enable automated and efficient routing of signals across dice, accommodating multiple instantiations of circuit blocks with various orientations. This ensures minimal signal path length and high-density interconnects by minimizing the physical footprint of connections and adhering to stringent design rule checks within a 3D integrated circuit layout. There are other embodiments as well.

IPC Classes  ?

• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 111/04 - Constraint-based CAD

Abstract

Novel tools and techniques are provided for implementing cantilevered power planes to provide a return current path for high-speed signals. In various embodiments, a semiconductor package includes a substrate core, a plurality of layers, and an AC coupler(s). The plurality of layers includes power, ground, and signal layers each layer disposed on or above the substrate core, each signal layer being disposed between a power layer and a ground layer, the power layer and the ground layer each providing a return path for high frequency (e.g., 1 kHz or greater) signals carried by each signal layer. Each dielectric layer is disposed between and in contact with a pair of power, ground, or signal layer. The AC coupler(s) is coupled to each of a power layer(s) and a ground layer(s), without any portion of any power layer that is near an edge of the substrate core being anchored to the substrate core.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/66 - High-frequency adaptations
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

Abstract

A system may have a multiplexer and a controller. For a transition from a first pair of bits in first data provided to digital-to-analog converters (DACs) to a second pair of bits in second data, the controller may determine whether the transition is of a first type or of a second type, and in response to determining that the transition is of the first type, control the multiplexer to output the second pair of bits to the DACs. In response to determining that the transition is of the second type and the second pair of bits are to be swapped, the controller may control the multiplexer to output a swapped pair of bits to the DACs. Data output by the multiplexer based on the second data has a predetermined number of bits that have binary values different from those of corresponding bits in the first data.

IPC Classes  ?

• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters

Abstract

Novel tools and techniques are provided for implementing an encoder capable of performing a self-correction process, and more particularly methods, systems, and apparatuses are provided for implementing an encoder capable of performing a process to correct itself during operation of the encoder. In various embodiments, the encoder includes an exciter and a sensor capable of detecting a position of the exciter and generating a signal based on the position of the exciter. The encoder can then perform one or more steps to detect at least one of a first error in an offset of the signal, a second error in a gain of the signal, or a third error in a phase of the signal as the exciter is rotating and correct the signal from the sensor based on the detection of at least one of the first error, the second error, or the third error.

IPC Classes  ?

• H03M 13/19 - Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
• H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes

Abstract

Novel tools and techniques are provided for implementing an encoder capable of performing a self-calibration or self-correction process, and more particularly methods, systems, and apparatuses are provided for implementing an encoder capable of performing a process to calibrate itself or correct a signal of a sensor at different detected temperatures of an environment. In various embodiments, the encoder includes an exciter and a sensor capable of detecting a position of the exciter and generating a signal based on the position of the exciter. The encoder can then perform one or more steps to calibrate itself or self-correct a signal at different temperatures and calculate one or more values to correct a signal generated by the sensor.

IPC Classes  ?

• G01D 18/00 - Testing or calibrating apparatus or arrangements provided for in groups

Abstract

Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package or a chip package including a one or more channel vias. In various embodiments, an apparatus includes a first layer comprising a channel; a first via extending though the first layer to a first surface of the channel; and a line connecting the first via to a pad. In some cases, the first surface is located at a bottom of the channel.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

The solutions can include devices, systems and methods for facilitating wireless communication of narrowband devices within a communication range of wideband access points. An access point (AP) can be configured to communicate with one or more stations using a wideband preamble and to communicate with a first one or more devices via narrowband channels. The AP can establish a service period (SP) with the one or more stations for which the one or more stations and the AP pause communications over the wideband channels. The AP can receive, during the SP, one or more protocol data units from the first one or more devices over the one or more narrowband channels without the wideband preamble. The AP can forward, during the SP, data from the one or more protocol data units to a second one or more devices over the one or more narrowband channels.

IPC Classes  ?

• H04W 74/0816 - Non-scheduled access, e.g. ALOHA using carrier sensing, e.g. carrier sense multiple access [CSMA] with collision avoidance

Abstract

A method may include receiving, by one or more controllers, a segment of data to write to a logical device, the logical device having a plurality of physical disks. The method may include causing, by the one or more controllers, to store a first plurality of contiguous data strips of the segment of data on a first physical disk of the plurality of the physical disks up to a first threshold. In response to reaching the first threshold, a second plurality of contiguous data strips of the segment of data can be stored on a second physical disk of the plurality of the physical disks, the second plurality of contiguous data strips following sequentially after the first plurality of contiguous data strips. The method may include splitting of the segment of data into the first plurality of contiguous data strips and the second plurality of contiguous data strips.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

Solutions that can provide secure access to memory. Some solutions assign tags to pages of memory and ensure secure access to each page of memory by ensuring that a client seeking to access a tagged page of memory is authorized to access pages marked by that tag.

IPC Classes  ?

• G06F 12/14 - Protection against unauthorised use of memory

Abstract

Novel tools and techniques are provided for implementing an encoder capable of performing a self-calibration process, and more particularly methods, systems, and apparatuses are provided for implementing an encoder capable of performing a process to calibrate itself using a moving average algorithm. In various embodiments, the encoder includes an exciter and a sensor capable of detecting a position of the exciter and generating a signal based on the position of the exciter. The encoder can then perform one or more steps to calibrate itself using a moving average algorithm to account for variations in a rotation speed of the encoder.

IPC Classes  ?

• G01D 18/00 - Testing or calibrating apparatus or arrangements provided for in groups

Abstract

Novel communication techniques for Bluetooth LE devices. In some cases, a central device transmits broadcast messages, which can be received by one or more peripheral devices, which then transmit responses in turn. In an aspect, these techniques can condense multiple advertising/scan request/scan response packets into a single transmission window and/or multiple, contiguous receive windows for the central device and single transmit/single receive windows for each peripheral device.

IPC Classes  ?

• H04W 72/30 - Resource management for broadcast services
• H04L 5/00 - Arrangements affording multiple use of the transmission path
• H04W 12/041 - Key generation or derivation

Abstract

A device in communication with a plurality of memory devices storing a plurality of datasets and a host, the device including one or more circuits to receive a plurality of messages pertaining to the plurality of datasets, determine an amount of information corresponding to each dataset of the plurality of datasets, identify actions for each message of the plurality of messages, the actions including at least one of updates to the plurality of datasets or accesses of the plurality of datasets, update a table to reflect receipt of the plurality of messages, and determine a pattern associated with the plurality of messages.

IPC Classes  ?

• G06F 9/54 - Interprogram communication

Abstract

Techniques for performing automatic PHY updates in Bluetooth devices. In some cases, a device might detect the reception of a packet sent with a particular PHY and automatically update the device's physical layer to employ that PHY for receiving and/or transmitting subsequent packets.

IPC Classes  ?

• H04W 76/14 - Direct-mode setup
• H04W 76/15 - Setup of multiple wireless link connections

Abstract

A power amplifier is provided. The power amplifier includes a first circuit comprising a first transistor and a second transistor coupled respectively to a third transistor and a fourth transistor. The power amplifier also includes a second circuit comprising a transformer having a first winding and a second winding. The first winding comprises a first terminal coupled to the third transistor and a second terminal coupled to the fourth transistor to receive a differential voltage signal with a gain from the first circuit. The second winding comprises a first terminal being grounded and a second terminal serving as an output terminal. The power amplifier circuit further includes a third circuit comprising a programmable capacitor from a midpoint of the first winding to a common node that is coupled to ground. The programmable capacitor is tunable to reduce second harmonic seen at the output terminal.

IPC Classes  ?

• H03F 1/42 - Modifications of amplifiers to extend the bandwidth
• H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages

Abstract

In some embodiments, the method for scaling to a super resolution based on machine learning is provided. The method may include receiving a data stream. The device may include circuitry to upscale media by a scale factor to a super resolution. The circuitry can be configured with a number of one or more multipliers and adders for one or more neurons of one or more layers of a neural network. The number of one or more multipliers and adders can be determined based at least on the scale factor. The method may include determining a plurality of output data points corresponding to the one or more data points upscaled by the scale factor to the super resolution. The method may include providing as output the super resolution of the media. The method may further include identifying one or more features of one or more data points from the data stream.

IPC Classes  ?

• G06N 3/08 - Learning methods
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Abstract

The systems and methods described provide a solution for automatic training of echo canceller (EC) in upstream signal receivers on sub-carriers experiencing low activity in the upstream communication. The solution can include one or more processors identifying a plurality of bins (e.g., EC bins). Each bin of the plurality of bins can correspond to a portion of a frequency range of a cable line. The one or more processors can determine that a power level of an echo signal of each of a bin of the plurality of bins and one or more bins adjacent to the bin exceed a respective threshold for the power level. The one or more processors can train an echo canceller of the echo signal for the bin, responsive to the determining.

IPC Classes  ?

• H04B 3/23 - Reducing echo effects or singingOpening or closing transmitting pathConditioning for transmission in one direction or the other using a replica of transmitted signal in the time domain, e.g. echo cancellers
• H03H 21/00 - Adaptive networks

Abstract

A wireless device can include a first radio configured to transmit over a first link and a second link of a first wireless band. The first radio can be configured to detect an OBSS communication on the first link of the first wireless band. The wireless device can perform coordinated link-switch (CLS) operations. The wireless device can be configured to operate as an access point (AP) for one or more stations of a wireless network or a station.

IPC Classes  ?

• H04W 36/08 - Reselecting an access point
• H04W 36/30 - Reselection being triggered by specific parameters by measured or perceived connection quality data
• H04W 74/0816 - Non-scheduled access, e.g. ALOHA using carrier sensing, e.g. carrier sense multiple access [CSMA] with collision avoidance

Abstract

A device including one or more circuits. The one or more circuits can receive a request associated with a first dataset stored by a memory device of a plurality of memory devices. The one or more circuits can generate, based on information associated with the memory device and the request, a first value corresponding to a first portion of a first map. The one or more circuits can determine, based on a first value of the first portion of the first map, that a first row of the plurality of rows includes a bad block.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

Methods, systems, and devices for improving security of media streams are disclosed. The system can receive a decoded media stream from a media decoding pipeline that receives and decodes an encoded media stream. The system can identify, based on the decoded media stream, a set of features to generate, and generate the set of features using the decoded media stream. Such features may include luma histograms, pixel intensity data, motion vectors, edge detection, audio gain, tonal information, pitch information, among other types of features. The system can provide the set of features to a processor executing a machine-learning model, wherein the processor executing the machine-learning model is prevented from accessing the decoded media stream by the device.

IPC Classes  ?

• H04N 21/44 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
• G06N 20/00 - Machine learning
• H04N 19/14 - Coding unit complexity, e.g. amount of activity or edge presence estimation
• H04N 19/517 - Processing of motion vectors by encoding
• H04N 21/439 - Processing of audio elementary streams

Abstract

A method for improving wafer-level optical characteristic uniformity. The method includes forming a first layer of dielectric overlying the first wafer and a second layer of dielectric overlying the second wafer. The method also includes measuring a refractive index distribution of the second layer and measuring a first thickness distribution of the first layer. The method also includes determining a second thickness distribution for the first layer based on the refractive index distribution and the first thickness distribution. The method further includes removing material nonuniformly and selectively from the first layer based on the second thickness distribution, resulting in a third layer in the second thickness distribution characterized by a spectral response with a characteristic wavelength uniformity better than +/−2.5 nm across the first wafer.

IPC Classes  ?

• G02B 6/132 - Integrated optical circuits characterised by the manufacturing method by deposition of thin films

Abstract

Method and structure for shielding electromagnetic interference in photonic integrated circuits (PIC) disposed on electronic integrated circuits (EIC). The invention addresses the electromagnetic interference problem by employing vias through the PIC's bulk silicon substrate. The invention also uses a conductive layer covering the backside of the PIC bulk silicon substrate on which the metal heat spreader can be placed. Now, the vias can make electrical contact from the reference net formed for PIC's light transmission component on one or more metal layers of the PIC to the conductive layer on the backside of the PIC. Such an arrangement allows for robust electrical connection and allows the metal heat spreader to act as robust ground thus terminating the electromagnetic fields.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

A memory system includes a memory stack including a number of memory dies interconnected via copper bonding, a logic die coupled to the memory stack via a copper bonding. The memory system further includes a buffer die extended to provide the copper bonding between the logic die and the memory stack and a silicon carrier layer bonded to the memory stack and the logic die.

IPC Classes  ?

• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

The current invention offers a method for preparing an electronic integrated circuit (EIC) for the assembly of an optical engine. The method involves stacking a CMOS-based EIC wafer onto a short loop/interposer wafer through face-to-back bonding. This stacked configuration serves as a carrier for the thin CMOS wafers. Subsequently, the stacked wafers are thinned down to the desired height and undergo a via last process. In this process, the thick metal layer from the short loop/interposer wafer acts as an etch stop. The stacked EIC wafers can then be diced and attached to a photonic integrated circuit (PIC) wafer, resulting in the formation of an optical engine.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/498 - Leads on insulating substrates

Abstract

A signal integrity optimized package is provided. An apparatus includes a core comprising a top surface, bottom surface, and a first plane coupled to the top surface of the core. The first plane includes a first region circumscribed by a first ditch, wherein the first region includes an electrically conductive material, and wherein the first ditch is configured to electrically isolate the first region.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details

Abstract

Novel tools and techniques for packet filtering in a network. A networking device might feature an access control list (ACL) with filter rules, each having a field to identify, for example, a possible state of a vehicle. Based on this field, rules inapplicable to that state can be disregarded when evaluating packets against the rules in the ACL.

IPC Classes  ?

• H04L 9/40 - Network security protocols

Abstract

The subject technology is directed to semiconductor devices and manufacturing methods. In various embodiments, the subject technology provides a semiconductor device, which comprises a first circuit characterized by a first coefficient of thermal expansion (CTE) and a substrate characterized by a second CTE. A ratio of the first CTE to the second CTE is greater than or equal to 3:5, which ensures harmonious thermal behavior, leading to improved yield and reduced warpage. In some implementations, one or more circuit elements may be embedded in the substrate. There are other embodiments as well.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or

Abstract

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 5/6 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 96 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Abstract

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 3/4 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 144 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Abstract

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 2/3 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 192 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Abstract

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 1/2 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 288 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

IPC Classes  ?

• H03M 13/25 - Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
• H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

A device may include a plurality of processors coupled to one or more network interfaces configured to provide wireless connectivity, and a controller. The controller may be configured to establish a wireless connection via a first processor of the plurality of processors. Responsive to a trigger of the first processor scanning for one or more channels, the controller may be configured to transfer the established wireless connection from the first processor to a second processor of the plurality of processors. The second process is different from the first processor. Responsive to the second processor detecting data to be received from the established wireless connection, the controller may be configured to transfer the established wireless connection from the second processor back to the first processor.

IPC Classes  ?

• H04W 76/15 - Setup of multiple wireless link connections
• H04W 76/20 - Manipulation of established connections

Abstract

A resonator for beat mode suppression is provided. A resonator includes a substrate comprising a top surface, a bottom electrode disposed on the top surface of the substrate, a piezoelectric layer disposed on the bottom electrode, and a top electrode disposed on the piezoelectric layer. The bottom electrode includes a first elongated member configured to extend longitudinally along the top surface on a first side of the substrate.

IPC Classes  ?

• H03H 9/205 - Constructional features of resonators consisting of piezoelectric or electrostrictive material having multiple resonators
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details

Abstract

Operations of a security device are provided herein. The operations may include receiving, via a first network interface, a network packet, and evaluating attributes of the received network packet against a ruleset to identify a first rule match, wherein the attributes comprise an identifier of the first network interface, a source address, and a destination address. The operations may further include comparing the attributes of the received network packet against a table listing one or more network devices associated with the first network interface or a second network interface. The operations may further include switching the attributes of the received network packet by changing the identifier of the first network interface to an identifier of the second network interface and swapping the source address and the destination address, and evaluating the switched attributes of the received network packet against the ruleset to identify a second rule match. The switched attributes of the received network packet may be compared against the table, and one of the first rule match or the second rule match may be selected based on the comparisons of the network packet attributes and the switched network packet attributes against the table. The received network packet may be processed according to the selected one of the first rule match or the second rule match.

IPC Classes  ?

• H04L 9/40 - Network security protocols