Abstract

An apparatus including a current source. The current source divides a current from a voltage supply into current streams in response to converting a voltage from a voltage supply into a plurality of current streams. The current source modulates a current streams with signals to convert the current streams into first and second current streams. The current source combines the first and second current streams into a single current stream and supplies the single current stream to a load in a flow direction.

IPC Classes  ?

• G11B 5/02 - Recording, reproducing or erasing methodsRead, write or erase circuits therefor

Abstract

A method for generating soft information for a digital signal decoder. The method includes receiving a first plurality of signals, each corresponding to a time index, each time index being associated with two states including state 1 and state 0. The method also includes processing the first plurality of signals to calculate path metric values of state 0 and 1 for generating each of a second plurality of most-likely symbols by hard decisions and intermediate information for a most-likely path and a second-likely path at each time index. The method includes computing a difference between the most-likely path and a second-likely path for a given one of the two states at each time index. The method also includes determining a soft information corresponding to either one of the two states at the time index per one of the second plurality of most-likely symbols.

IPC Classes  ?

• H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups
• H03M 13/41 - Sequence estimation, i.e using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors

Abstract

In an example, a processor for machine learning calculations is described. An adapter input circuit is operable to receive an input tensor. The adapter input circuit includes channels. A first channel of the channels is operable to process samples of the input tensor to generate pre-processed samples and to obtain locations of the samples. A location processor, coupled to the first channel, is operable to determine output locations in response to the locations. An arithmetic logic unit (ALU), coupled to the channels, is operable to calculate output samples from the pre-processed samples. An adapter output circuit, coupled to the location processor and the ALU, operable to process the output locations and the output samples to generate an output tensor.

IPC Classes  ?

• G06F 17/16 - Matrix or vector computation
• G06F 7/57 - Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups or for performing logical operations

Abstract

Some embodiments relate to systems and methods for low latency monitoring. A communication system can include an application operating on the first device. The application is configured to append time stamps to a first packet received by the first device. The time stamps indicate a first time the first packet is received by the first device and a second time the first packet is sent by the first device.

IPC Classes  ?

• H04L 43/0852 - Delays
• H04L 43/065 - Generation of reports related to network devices
• H04L 43/106 - Active monitoring, e.g. heartbeat, ping or trace-route using time related information in packets, e.g. by adding timestamps

Abstract

An example method of processing a command at a device sent by a host in a computing system, the host comprising a central processing unit (CPU) and host memory, is described. The method includes: receiving, at the device, the command from the host; parsing, by the device, the command to identify a flag in the command that is set and to obtain a first address that references a source buffer in the host memory; and reading, by the device in response to the flag being set, source data from the source buffer by reading from a coherent cache on the device using the first address, a cache coherency manager in the host managing the coherent cache.

IPC Classes  ?

• G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
• G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]

Abstract

A method for redirecting data packet on link offline in a network is provided. The method includes detecting an offline link between a first port and a destination port. The method also includes moving the first port to a recovery state by turning on a mirroring feature to make copies of all subsequent frames of data packets to the first port. The method further includes activating a redundant port profile associated with the mirroring feature prepopulated with information including at least a second port linked to the destination port. Furthermore, the method includes forwarding, based on the redundant port profile, the copies of all data packets to the second port linked to the destination port.

IPC Classes  ?

• H04L 45/28 - Routing or path finding of packets in data switching networks using route fault recovery
• H04L 45/42 - Centralised routing

Abstract

An example resonator device includes a first electrode, a second electrode, a first piezoelectric film disposed between the first electrode and the second electrode, and a second piezoelectric film disposed between the first piezoelectric film and the first electrode. The first piezoelectric film has a first polarization in a first orientation, the second piezoelectric film has a second polarization in a second orientation, and the second orientation is opposite of the first orientation.

IPC Classes  ?

• H03H 9/17 - Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H10N 30/853 - Ceramic compositions

Abstract

A low latency gearbox retimer architecture is provided. An apparatus includes a first clock generator configured to generate a first clock signal having a first frequency, and a second clock signal having a second frequency. A control logic is configured to generate the control signal, based, at least in part, on the second clock signal, and two or more analog to digital converter (ADC) slices. Each respective ADC slice includes a multiplexer having a first number of inputs and a second number of outputs, wherein the multiplexer is configured to select a set of the second number of inputs to be output, wherein the set of the second number of inputs selected is based, at least in part, on a control signal. The apparatus includes one or more unit-ADCs, wherein the respective outputs of the one or more unit-ADCs are coupled to the multiplexer as an input.

IPC Classes  ?

• G06F 1/08 - Clock generators with changeable or programmable clock frequency
• H03M 1/12 - Analogue/digital converters

Abstract

Solutions for providing increased performance of write operations that are candidates for coalesced writes but don't end up writing an entire row of new data. In accordance with some embodiments, a controller can perform a pre-read operation early, in some cases as soon as the write request received from the host is identified as a candidate for write coalescing.

IPC Classes  ?

• G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
• G06F 12/0871 - Allocation or management of cache space
• G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means

Abstract

Novel tools and techniques are provided for implementing a filter circuit array, and more particularly methods, systems, and apparatuses are provided for implementing a filter circuit array in a semiconductor package or a chip package. In an embodiment, a filter array can include a first filter circuit and a first resistive circuit connected to the first filter circuit. In various cases, when the first filter circuit is operational, the first filter circuit is configured to transmit or receive one or more first signals and the first resistive circuit is unterminated. In other cases, when the first filter circuit is not operational, the first filter circuit is configured to terminate via the first resistive circuit.

IPC Classes  ?

• H03H 9/00 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators
• H01L 23/66 - High-frequency adaptations

Abstract

Offloading of network processing is provided. A method performed by a client device can include establishing a transport layer connection with a server over a network via an access point or a modem in wireless communication with the client device. The method can include establishing a pipe with one of the access point or the modem to transfer data. The method can include communicating, via the pipe to one of the access point or the modem, a copy of one or more buffers of one or more sockets used for the transport layer connection by the client device. The access point or the modem can be configured to use the copy of the one or more of buffers to handle re-transmission of one or more packets to the server via the transport layer connection instead of the client device.

IPC Classes  ?

• H04W 76/12 - Setup of transport tunnels
• H04L 1/08 - Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system
• H04W 12/033 - Protecting confidentiality, e.g. by encryption of the user plane, e.g. user’s traffic
• H04W 80/06 - Transport layer protocols, e.g. TCP [Transport Control Protocol] over wireless

Abstract

The disclosure describes systems and methods for improving latency for wireless speakers. The system can establish a buffer pipe between a wireless chip of a media player and a wireless chip of a wireless speaker using an inter-IC sound protocol. The system can receive samples of audio data through the media player. The system can communicate the audio data to the wireless speaker using the buffer pipe to bypass the transport layer stack of the media player and the wireless speaker. The system can cause a transmitter of the wireless speaker to provide the audio data to a digital audio converter for output to a speaker of the wireless speaker.

IPC Classes  ?

• H04R 5/04 - Circuit arrangements
• H04L 65/60 - Network streaming of media packets
• H04R 3/12 - Circuits for transducers for distributing signals to two or more loudspeakers

Abstract

A device may advertise a first information element indicating a first maximum size for MAC protocol data unit (MPDU) frames for the first device. A device may select, based at least on the first maximum size, a first polynomial for a cyclic redundancy check (CRC) for an MPDU frame received from a second device. A device may compute, using the selected first polynomial, a CRC for the received MPDU frame. A device may detect, based at least on the computed CRC, an error in the MPDU frame.

IPC Classes  ?

• H03M 13/09 - Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package or a chip package including at least two posts having different widths. In an embodiment, a system can include a first substrate having a first layer comprising a first post having a first width and a second layer coupled to the first layer and comprising an external surface of the first substrate and a second post having a second width connected to the first post. The first width can be less than the second width. The system can further include a solder connected to the second post and configured to connect the second post to a first connector on a second substrate.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package or a chip package including two or more high-density layers for die-to-die interconnections. In various embodiments, a semiconductor device includes a substrate comprising two or more first layers and a second layer. A first length of the two or more first layers can be less than a second length of the second layer. The semiconductor device can further include a first die coupled to the second layer of the substrate and a second die coupled to the second layer. At least one of the two or more first layers comprises a connector coupling the first die to the second die.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or

Abstract

A transistor includes a first well region doped with second type dopants, a second well region doped with first type dopants, and a third well region. The transistor also includes a first isolation structure neighboring the first well region, a second isolation structure neighboring the the second well region and the third well region, a drain region doped with the first type dopants disposed in the third well region, a source region doped with the first type dopants disposed in the first well region, and a gate disposed at least partially over the second isolation structure. The transistor can be configured as a depletion mode transistor.

IPC Classes  ?

• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 21/8234 - MIS technology
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

Semiconductor devices with increased breakdown voltage characteristics for use in a variety of suitable applications. An example semiconductor device having increased breakdown voltage characteristics includes a substrate having a p-type well, an n-type well, an n-type layer, and a depletion region and a gate disposed over the p-type well, the depletion region, and the n-type layer. The depletion region and the n-type layer are disposed between the p-type well and the n-type well and the depletion region is disposed between the p-type well and the n-type layer.

IPC Classes  ?

• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A system for providing an interactive bitstream with embedded messaging is provided. The system includes a server configured to receive message data and transmit message data, wherein the message data is transmitted over a cellular network, and a media player coupled to the server, the media player configured to receive a bitstream. The media player includes a decoder configured to decode the bitstream, wherein decoding the bitstream includes extracting message data, and decoding at least one of encoded video data and encoded audio data. The media player further includes messaging logic configured to parse the message data, and transmit the message data to a user device via the server.

IPC Classes  ?

• H04W 4/14 - Short messaging services, e.g. short message service [SMS] or unstructured supplementary service data [USSD]
• H04L 51/10 - Multimedia information

Abstract

A reference buffer with wide output voltage and current range is provided. A reference buffer includes an error amplifier comprising a first input, a second input, and a first output, wherein the amplifier is configured to generate an output signal indicative of an error between an output reference signal and an internal reference signal. The reference buffer further includes a first voltage follower circuit configured to generate the output reference signal based, at least in part, on the output signal of the error amplifier, wherein the first voltage follower comprises a third input and a second output, and wherein the second output is coupled to the second input of the error amplifier.

IPC Classes  ?

• H03M 1/12 - Analogue/digital converters
• H03F 3/45 - Differential amplifiers

Abstract

An apparatus includes a first phase interpolator configured to receive a first clock signal and generate a second clock signal, and an ADC that includes a clock divider configured to generate a third clock signals based on the second clock signal, a token generator configured to generate a first token signal, a first phase detector configured to generate a first and second output based on the first and third clock signals, and a second phase detector configured to generate a third output based on the token signal. Control logic may be provided to perform a foreground calibration to align the first token signal with a second token signal of a second ADC-group, and a background calibration to align the third clock signal with the first clock signal.

IPC Classes  ?

• H03M 1/10 - Calibration or testing
• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters

Abstract

Described embodiments provide systems and methods for mapping high-priority WiFi packets to low latency data pipe. An access point can receive the one or more low latency classification rules from a device monitoring one or more low latency classification rules at a cable modem termination system (CMTS). The access point can be in communication with the CMTS and provide wireless access to one or more devices in a local network. The access point can receive packets corresponding to the one or more low latency classification rules from the CMTS. The access point can communicate, based at least on the one or more low latency classification rules, the packets to a queue used for transmission of low latency traffic to the one or more devices in the local network.

IPC Classes  ?

• H04W 28/02 - Traffic management, e.g. flow control or congestion control
• H04L 12/28 - Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
• H04L 47/24 - Traffic characterised by specific attributes, e.g. priority or QoS
• H04W 84/12 - WLAN [Wireless Local Area Networks]

Abstract

The disclosure describes systems and methods for dynamically enabling and disabling data aggregation control. A device can communicate with an access point or a station. A first wireless chip in the access point can establish a wireless connection with a second wireless chip in the station. The first wireless chip and second wireless chip can negotiate during setup of the wireless connection whether to enable aggregation of data via the wireless connection. The device can detect that a flow of packets traversing the wireless connection corresponds to a low-latency application. Upon detection, the device can communicate information to the first wireless chip and the second wireless chip to cause the first wireless chip and the second wireless chip to dynamically disable the aggregation of data being communicated by the low-latency application over the wireless connection.

IPC Classes  ?

• H04W 28/06 - Optimising, e.g. header compression, information sizing

Abstract

Some embodiments relate to systems and methods for low latency control. A communication system can include an application operating on the first device. The application is configured to: 1. classify a first packet provided to the first device as being for reception by a second low latency device, or 2. classify the first packet as being for use in a low latency operation. The application is configured to provide the first packet to a first queue associated with a low latency path.

IPC Classes  ?

• H04L 47/28 - Flow controlCongestion control in relation to timing considerations
• H04L 47/6275 - Queue scheduling characterised by scheduling criteria for service slots or service orders based on priority
• H04L 47/762 - Admission controlResource allocation using dynamic resource allocation, e.g. in-call renegotiation requested by the user or requested by the network in response to changing network conditions triggered by the network

Abstract

Queue management for latency control is provided. A method includes receiving packets of multiple flows, each of the packets including an arrival time stamp. The method can include classifying, based on a type of application, the flows for transmission as higher priority via a higher priority channel, or lower priority via a lower priority channel. The method can include determining, for packets for the flows classified as higher priority, a queue of one or more second queues to use for transmission and a departure time stamp for each of the packets according to a latency budget for the type of application. The method can include communicating the higher priority packets with the departure time stamp to a corresponding queue of the one or more second queues based on the type of application. A transmission scheduler can prioritize transmission of packets from the second queues based on the departure time stamp.

IPC Classes  ?

• H04L 47/56 - Queue scheduling implementing delay-aware scheduling
• H04L 47/6275 - Queue scheduling characterised by scheduling criteria for service slots or service orders based on priority

Abstract

A method for creating firmware-dedicated queues for storage system multi-queue operation is provided. The method includes providing a controller to manage a plurality of input/output (IO) operations between hosts and virtual disks by issuing the plurality of IO operations to a plurality of queues comprising submission queues and completion queues, wherein one or more submission queues are mapped to each completion queue. The method also includes configuring at least one submission queue as a FW-dedicated queue for submitting internal IO operations initiated by firmware (FW) associated with the controller. The method further includes adding one or more parameters in FW-queue-related fields in a controller device state table for each device of the virtual disks. The one or more parameters include at least a first parameter to enable the FW-dedicated queue for only submitting the internal IO operations in parallel with other queues to the device.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

An example method of configuring connection between hosts and storage devices over an Internet Protocol (IP) network includes: defining, by a server, a first group of the hosts and a first group of the storage devices, the hosts connected to a first IP network and the storage devices connected to a second IP network; defining an IP zone that includes a connection between the first group of hosts and the first group of storage devices over a link between the first IP network and the second IP network; generating, according to an IP zone policy for the IP zone, an IP configuration for the first groups of hosts and storage devices, the first IP network, and the second IP network; and deploying, to implement the IP zone, the IP configuration to the first groups of hosts and storage devices, the first IP network, and the second IP network.

IPC Classes  ?

• H04L 45/76 - Routing in software-defined topologies, e.g. routing between virtual machines
• H04L 41/0894 - Policy-based network configuration management
• H04L 45/24 - Multipath

Abstract

This invention is directed to network methods and systems. According to an embodiment, the present invention provides a method that includes receiving a plurality of streams, each containing audio or video content. The method includes determining and storing separate statuses and states for these streams based on their association with network ports. The method manages the network resources associated with the streams based on their status. There are other embodiments as well.

IPC Classes  ?

• H04L 65/613 - Network streaming of media packets for supporting one-way streaming services, e.g. Internet radio for the control of the source by the destination
• H04L 65/1093 - In-session procedures by adding participantsIn-session procedures by removing participants
• H04L 65/1095 - Inter-network session transfer or sharing
• H04L 65/1101 - Session protocols

Abstract

Technical solutions present structures, systems and methods for providing a cold plate for thermal management of circuit dies using cooling channels and through surface vias (TSVs) formed through multiple bonded substrates. A first substrate can include a circuit coupled with first electrical contacts etched in the first substrate and a second substrate can include second electrical contacts etched in the second substrate. A channel can be etched between the second electrical contacts. A third substrate can include third electrical contacts etched to form combined channel enclosed by the first substrate, the second substrate and the third substrate. The circuit can be electrically coupled with the third plurality of electrical contacts via the first electrical contacts and the second electrical contacts and the combined channel is configured to dissipate heat generated by the circuit.

IPC Classes  ?

• H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/467 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing gases, e.g. air
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/498 - Leads on insulating substrates

Abstract

The systems and methods for conserving energy by managing variable dynamic range of a receiver device are presented. The system can include a receiver configured to receive wireless transmissions at any of a plurality of amplitude ranges. The receiver can include a processor to operate, for a listening mode of the receiver, at a reduced amplitude range of the plurality of amplitude ranges for which to listen for a preamble of a data frame of a wireless transmission. The reduced amplitude range can have a reduced power level below a threshold. The processor can receive, while operating at the reduced amplitude range, the preamble of the data frame. The processor can switch, for a receiving mode, responsive to receiving the preamble, to an increased amplitude range to receive the data frame, the increased amplitude range operating at an increased linearity or power level above the threshold.

IPC Classes  ?

• H04W 52/02 - Power saving arrangements

Abstract

The present application is directed to methods and systems for data storage. According to an embodiment, the present invention provides an apparatus that includes a first storage having a first portion, alongside a communication interface and a processor. This processor is connected to the first storage and the communication interface. The processor is configured to process a first data, which includes second data and third data. The processor is configured for obtaining the second and third data from the first data, storing the second data in the first portion of the first storage, and sending the third data to a secondary storage via the communication interface. Additionally, the processor is configured to remove the third data from the apparatus. The processor is further configured to obtain the first data by using the stored second data and retrieving the third data through the communication interface. There are other embodiments as well.

IPC Classes  ?

• H04W 12/033 - Protecting confidentiality, e.g. by encryption of the user plane, e.g. user’s traffic
• H04L 67/1097 - Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
• H04W 12/062 - Pre-authentication

Abstract

In some aspects, the disclosure is directed to methods and systems for interference mitigation and cancellation in full duplex amplifiers for cable modem or broadband communication systems. In many implementations, an interference canceller in the downstream path may be provided to equalize composite power on the FDX upstream subbands within a predetermined range of amplitude (e.g. X dB) from the desired downstream signal on the same subband, without affecting the downstream subbands.

IPC Classes  ?

• H04L 12/28 - Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
• H04L 1/08 - Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system
• H04L 5/14 - Two-way operation using the same type of signal, i.e. duplex

Abstract

A method for seamless WiFi roaming of a multi-radio station when transitioning from an initial access point to a target access point, wherein the method comprises activating a second communication link between the multi-radio station and the target access point while a first communication link between the multi-radio station and the initial access point is still active, and after said activating, deactivating the first communication link between the multi-radio station and the initial access point.

IPC Classes  ?

• H04W 36/32 - Reselection being triggered by specific parameters by location or mobility data, e.g. speed data
• H04W 8/12 - Mobility data transfer between location registers or mobility servers
• H04W 12/06 - Authentication
• H04W 52/00 - Power management
• H04W 52/02 - Power saving arrangements
• H04W 84/12 - WLAN [Wireless Local Area Networks]

Abstract

A clock calibrator comprises an input port configured to receive a two-level symbol from a quarter-rate transmitter, the two-level symbol having a period of P unit intervals with a first rising edge launched by one quarter-rate clocks. The clock calibrator includes a clock generator configured to generate four calibration clocks based on the quarter-rate clocks, each calibration clock having the period of P UIs and sequentially having a calibration rising edge delayed by M UIs. The clock calibrator includes a delay-tuner configured to retime the calibration rising edge and a phase detector configured to determine a coarse parameter and a k-th fine parameter based on alignment between the retimed calibration rising edge and the first rising edge with (k−1)M UIs delay. Here P is an integer multiple of 4, M is one less than an integer multiple of 4, and k is selected from 1, 2, 3, and 4.

IPC Classes  ?

• G06F 1/12 - Synchronisation of different clock signals
• G06F 1/08 - Clock generators with changeable or programmable clock frequency
• H03K 17/567 - Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT

Abstract

An apparatus includes a first coupler formed on a substrate coupled with multiple waveguides spaced apart respectively to channel multiple input lights with different wavelengths. The apparatus further includes a wavelength dispersive device formed on the substrate and configured to diffract the multiple input lights to generate an image of diffracted lights coincident at a spot on a focal line associated with the wavelength dispersive device. The apparatus also includes a second coupler positioned in a proximity outside of the substrate and configured to out-couple a light signal with multiplexed wavelengths directly from the image at the spot of the focal line to an external optical device. The multiplexed wavelengths include all different wavelengths of the multiple input lights. The apparatus may include waveguide tapers to re-image the light focused by the wavelength dispersive device to improve coupling efficiency and tolerance. The apparatus may be operated as a wavelength multiplexer or demultiplexer.

IPC Classes  ?

• G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

A vertically oriented circuit die with lateral side metal can include a substrate and a die disposed on the substrate in a vertical orientation. The die can include a via disposed on a lateral side of the die, a metal line disposed on a bottom side of the die, and an electrical connection positioned in the via for coupling the metal line and the substrate.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/66 - High-frequency adaptations
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

The subject technology is directed to wireless communication systems and methods. In an embodiment, the subject technology provides an apparatus that includes a receiver configured to receive a first signal and an analyzer configured to generate a spectrum representation of the first signal. The analyzer is further configured to perform accumulation by averaging magnitudes of frequency components over multiple timestamps, enhancing the signal-to-noise ratio and providing a stable representation of the first signal's power density. Embodiments of the subject technology improve the analysis and management of wireless signals, leading to robust and efficient wireless communication by mitigating interference and optimizing frequency usage. There are other embodiments as well.

IPC Classes  ?

• H04W 24/08 - Testing using real traffic

Abstract

In some aspects, the disclosure is directed to methods and systems for reducing memory utilization and increasing efficiency during affine merge mode for versatile video coding by utilizing motion vectors stored in a motion data line buffer for a prediction unit of a second coding tree unit neighboring a first coding tree unit to derive control point motion vectors for the first coding tree unit.

IPC Classes  ?

• H04N 19/426 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements using memory downsizing methods
• H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
• H04N 19/139 - Analysis of motion vectors, e.g. their magnitude, direction, variance or reliability
• H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
• H04N 19/513 - Processing of motion vectors

Abstract

A system may include a processor, and a non-transitory computer readable medium having encoded thereon a set of instructions executable by the processor to establish a first multilink connection associated with a first basic service set and a second multilink connection associated with a second basic service set, set the second basic service set as a priority basic service set, switch an enabled link of the first basic service set on which communications are carried, and in response to determining that the enabled link of the first basic service set has been switched, switch an enabled link of the second basic service set based, wherein switching the enabled link of the second basic service set includes enabling the first link while the second link is concurrently enabled for a first duration, and disabling the second link after the first duration.

IPC Classes  ?

• H04W 76/15 - Setup of multiple wireless link connections

Abstract

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may identify a target data rate for transmitting data over a channel with a frequency bandwidth. Based at least on the target data rate, the one or more processors may select a forward error correction (FEC) code, a code rate, a modulation scheme, and a number of resource units (RUs) within the frequency bandwidth, to transmit the data within a range of the target data rate. The one or more processors may encode, by an FEC encoder, the data using the FEC code and the code rate to generate encoded data. The one or more processors may modulate the encoded data using the modulation scheme to generate modulated data. The transmitter may transmit the modulated data using the number of RUs.

IPC Classes  ?

• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

A wireless communication device (alternatively, device, WDEV, etc.) includes at least one processing circuitry configured to support communications with other WDEV(s) and to generate and process signals for such communications. In one example, the circuitry is configured to generate a null data packet (NDP), transmit at least a portion of the NDP to another wireless communication device via fewer than all of a plurality of sub-channels of a communication channel, and receive feedback from the another wireless communication device that is based on the another wireless communication processing the at least the portion of the NDP that is received via the fewer than all of the plurality of sub-channels of the communication channel. In one example, the generated NDP includes at least one signal field (SIG) field therein that includes information to specify a preamble puncturing option or the information is transmitted in a previous packet.

IPC Classes  ?

• H04L 5/00 - Arrangements affording multiple use of the transmission path
• H04B 7/0417 - Feedback systems
• H04B 7/0452 - Multi-user MIMO systems
• H04W 84/12 - WLAN [Wireless Local Area Networks]

Abstract

Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly, for implementing a semiconductor package or a chip package including a core or a multilayer core having one or more variable width vias or one or more offset vias. In various embodiments, an apparatus includes a substrate. The substrate includes a core. The core may include one or more vias extending through the core. At least one via of the one or more vias includes a cross-section that varies along a length of the at least one via as the via extends through the core. The cross-section of the via may vary based on at least one of varying a width of the at least one via or offsetting a first portion of the at least one via from a second portion of the at least one via.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H05K 1/02 - Printed circuits Details
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• H05K 3/42 - Plated through-holes

Abstract

Novel tools and techniques are provided for implementing detection and estimation of direct and reflected navigation satellite (e.g., global navigation satellite system (“GNSS”), etc.) signal parameters in a multipath environment. In various embodiments, logic of semiconductor package that is disposed on a user device concurrently receives a plurality of signals from a satellite(s), each signal travelling along a different path between each satellite(s) and the user device within a multipath environment. The logic identifies two or more signal peaks that fall within a tracking aperture based on analysis of the received signals, and determines peak parameter estimates for each signal peak based on measurements of signal parameters from at least one signal peak. The logic provides the determined peak parameter estimates for each signal peak to a position engine (“PE”) of the user device to calculate a navigation solution (e.g., position, velocity, and/or time, etc.) for the user device.

IPC Classes  ?

• G01S 19/22 - Multipath-related issues
• G01S 19/30 - Acquisition or tracking of signals transmitted by the system code related
• G01S 19/37 - Hardware or software details of the signal processing chain
• H04B 1/7075 - Synchronisation aspects with code phase acquisition
• H04B 1/7083 - Cell search, e.g. using a three-step approach
• H04B 1/7087 - Carrier synchronisation aspects
• H04B 1/711 - Interference-related aspects the interference being multi-path interference

Abstract

A system for wireless communications over one or more channels, may include one or more processors and memory coupled with the one or more processors. The one or more processors may identify, based at least on a target data rate and a frequency bandwidth of a channel among the one or more channels, (1) a number of resource units (RUs) within the frequency bandwidth and (2) a number of tones per RU to achieve the target data rate. The one or more processors may transmit, via a transmitter, data using one or more RUs.

IPC Classes  ?

• H04L 5/00 - Arrangements affording multiple use of the transmission path
• H04L 27/26 - Systems using multi-frequency codes
• H04W 24/08 - Testing using real traffic

Abstract

An apparatus may include a transmitter. The apparatus may identify a target code rate and a low density parity check (LDPC) code that has a base code rate for a base size of information bits, select, based at least on the target data rate and the base code rate, a first size that is less than the base size of information bits, generate a second set of information bits to include a first set of information bits corresponding to the first size and one or more bits to increase a size of the second set of information to correspond to the base size of information bits, encode, using the base code rate, the second set of information bits to generate parity data, and generate a codeword by concatenating the first set of information bits and the parity data to achieve the target code rate. The transmitter may transmit the codeword.

IPC Classes  ?

• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

An apparatus may include a transmitter and one or more processors configured to identify a code rate of a low-density parity-check (LDPC) code, receive, by an LDPC encoder, a set of information bits and encode, using the code rate, the set of information bits to generate a set of encoded bits and a set of parity bits, generate, from the set of encoded bits, a matrix of bit arrays, discard one or more parity bits from the set of parity bits to generate a parity bit array with a size equal to a number of column of the matrix, generate a bit array by concatenating (1) one or more bit arrays selected from the matrix of bit arrays and (2) one or more bits selected from the parity bit array corresponding to the one or more bit arrays, and modulate, by a modulator, the bit array to generate modulated data.

IPC Classes  ?

• H04L 1/00 - Arrangements for detecting or preventing errors in the information received
• H04L 27/36 - Modulator circuitsTransmitter circuits

Abstract

Technical solutions include systems and methods for transmission opportunity (TXOP) sharing for latency sensitive traffic of non-TXOP holder devices within a TXOP. A first device granted a TXOP can identify a first portion of a TXOP for a transmission of the first device. The first device can determine that a remaining portion of the TXOP subsequent to the first portion is available for data transmissions of other devices. The first device can transmit, to the other devices, an indication of availability of the remaining portion of the TXOP. The first device can allocate, responsive to one or more responses to the indication, the remaining portion of the TXOP to a second device of the one or more other devices to transmit data of the second device during the remaining portion of the TXOP period.

IPC Classes  ?

• H04W 74/02 - Hybrid access
• H04W 28/02 - Traffic management, e.g. flow control or congestion control
• H04W 74/00 - Wireless channel access

Abstract

Solutions for providing host-initiated read ahead caching on a virtual disk. In some implementations, the virtual disk might be part of a RAID environment. Some solutions expose to a host operating system the read ahead functionality of the virtual disk and allow the host to request prefetching of data from the virtual disk.

IPC Classes  ?

• G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
• G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus

Abstract

A system for controlling power distribution within a vehicular communication network, including a power source equipment comprising a first port in communication with a network node module of a device, and a Power over Ethernet (POE) management module. The POE management module is configured to enable POE to the device via the first port, monitor a current draw of the device, determine whether the current draw of the device exceeds a threshold, and disable POE to the device, responsive to determining that the current draw exceeds the threshold.

IPC Classes  ?

• G07C 5/08 - Registering or indicating performance data other than driving, working, idle, or waiting time, with or without registering driving, working, idle, or waiting time
• B60L 50/00 - Electric propulsion with power supplied within the vehicle
• B60R 16/023 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided forArrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for transmission of signals between vehicle parts or subsystems
• B60R 16/03 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided forArrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for supply of electrical power to vehicle subsystems
• B60R 19/03 - Bumpers, i.e. impact receiving or absorbing members for protecting vehicles or fending off blows from other vehicles or objects characterised by material, e.g. composite
• G06F 1/26 - Power supply means, e.g. regulation thereof
• G06F 7/76 - Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
• G08G 1/16 - Anti-collision systems
• H04B 1/3822 - Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving specially adapted for use in vehicles
• H04L 12/10 - Current supply arrangements
• H04L 12/46 - Interconnection of networks
• H04L 12/54 - Store-and-forward switching systems
• H04L 45/74 - Address processing for routing
• H04L 47/2425 - Traffic characterised by specific attributes, e.g. priority or QoS for supporting services specification, e.g. SLA
• H04L 47/6275 - Queue scheduling characterised by scheduling criteria for service slots or service orders based on priority
• H04L 47/70 - Admission controlResource allocation
• H04L 47/76 - Admission controlResource allocation using dynamic resource allocation, e.g. in-call renegotiation requested by the user or requested by the network in response to changing network conditions
• H04L 49/25 - Routing or path finding in a switch fabric
• H04L 67/12 - Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
• H04L 69/22 - Parsing or analysis of headers
• H04N 7/18 - Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
• H04N 19/102 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
• H04W 4/40 - Services specially adapted for particular environments, situations or purposes for vehicles, e.g. vehicle-to-pedestrians [V2P]
• H04W 4/44 - Services specially adapted for particular environments, situations or purposes for vehicles, e.g. vehicle-to-pedestrians [V2P] for communication between vehicles and infrastructures, e.g. vehicle-to-cloud [V2C] or vehicle-to-home [V2H]
• H04W 4/46 - Services specially adapted for particular environments, situations or purposes for vehicles, e.g. vehicle-to-pedestrians [V2P] for vehicle-to-vehicle communication [V2V]
• H04W 24/08 - Testing using real traffic
• H04W 28/08 - Load balancing or load distribution
• H04W 72/541 - Allocation or scheduling criteria for wireless resources based on quality criteria using the level of interference
• H04W 72/56 - Allocation or scheduling criteria for wireless resources based on priority criteria
• H04W 88/02 - Terminal devices

Abstract

A system includes an amplifier to receive a signal, an analog-to-digital converter (ADC), a first switch coupled to a capacitor to receive an output from the amplifier, the capacitor to provide the output to the ADC, a second switch coupled between the capacitor and the ADC to turn on/off the ADC, a third switch coupled between the amplifier and the first switch to connect/disconnect the output to/from the first switch, a fourth switch coupled between the amplifier and the first switch to bypass the amplifier, and circuitry. The circuitry turns on the first switch and the second switch to initiate charging the capacitor, turns on the fourth switch and turns off the third switch to complete the charging, and turns off the second switch and the first switch to control the ADC to convert the output to a digital signal.

IPC Classes  ?

• H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter

Abstract

The subject technology is directed to systems and methods for integrating inductors within printed circuit boards. In an embodiment, the subject technology provides an apparatus that includes a substrate comprising a first layer and a first inductor coupled to the first layer. The first inductor includes a second layer comprising a first metal material and a third layer comprising a second metal material. The third layer is coupled to the second layer through a first interconnect. The first inductor may be embedded within the substrate to enable efficient space utilization, leading to overall miniaturization and improved performance due to shorter signal paths and reduced parasitic effects. There are other embodiments as well.

IPC Classes  ?

• H01F 27/28 - CoilsWindingsConductive connections
• H01F 27/29 - TerminalsTapping arrangements
• H05K 1/02 - Printed circuits Details
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

A technical solution for band steering of WLAN traffic using multi-link operation is provided. The solution can include a multi-link device (MLD) to establish a multi-link (ML) comprising links across different frequency bands. The MLD can grant a device to share access to a link of the ML with a WLAN device. The device can communicate using a different type of wireless protocol than a protocol of the WLAN device sharing a frequency band with the device. The MLD can block a WLAN communication of the WLAN device on the link of the ML to be used by device for communicating and direct WLAN transmissions to a non-shared link of the ML while the device performs activity (e.g., other than WLAN communication) on the link. The MLD can allow the WLAN device to resume WLAN transmission on the link responsive to the device completing activity on the link.

IPC Classes  ?

• H04W 76/15 - Setup of multiple wireless link connections
• H04W 76/19 - Connection re-establishment
• H04W 84/12 - WLAN [Wireless Local Area Networks]

Abstract

Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package or a chip package including a choke. In an embodiment, a semiconductor device can include a choke comprising a first layer comprising a first inductor and a second inductor. A first path of the first inductor can alternates with a second path of the second inductor. The choke can further include a second layer comprising a first capacitor comprising a first plate and a second capacitor comprising a second plate. The first capacitor plate can be coupled in parallel with at least one of the first inductor or the second inductor and the second capacitor can be coupled in parallel with at least one of the first inductor or the second inductor.

IPC Classes  ?

• H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices

Abstract

Systems and methods use a protocol for multilink operations. The systems and methods can use a circuit configured to provide frames across a connection comprised of one or more links to a second device. The circuit is configured to use a beacon reception pattern where first intervals on a first link are alternately disposed with second intervals on a second link or to select a beacon reception pattern for a first link, a second link, and a third link in response a low battery condition, a delivery traffic indication map setting, or a roam decision.

IPC Classes  ?

• H04W 28/02 - Traffic management, e.g. flow control or congestion control
• H04W 76/15 - Setup of multiple wireless link connections
• H04W 84/12 - WLAN [Wireless Local Area Networks]

Abstract

Novel tools and techniques are provided for implementing distribution of IO requests to a storage array. In various cases, a controller for a redundant array of independent disks can be configured determine a first drive configured to receive a first input/output (IO) request; detect a first number IO requests pending for the first drive; determine the first number of IO requests pending for the first drive exceeds a first predetermined threshold; and based on a determination the first number of IO requests pending for the first drive exceeds the first predetermined threshold, skip sending the first IO request to the first drive.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

Systems and methods use a protocol for multilink operations. The systems and methods can use a circuit configured to provide frames across a connection comprised of one or more links. The circuit 1. is configured to use during an idle condition a lower power consuming link of the links for link management operations, 2. is configured to use during the lower power consuming link of the links for beacon synchronization operations, or 3. is configured to select the links in response to traffic parameters and a power consumption characteristic of the links.

IPC Classes  ?

• H04W 52/02 - Power saving arrangements
• H04W 84/12 - WLAN [Wireless Local Area Networks]

Abstract

Technical solutions improve GNSS receiver performance by combining pilot and data components of the GNSS signal to enhance the accuracy of a DLL, PLL or FLL of the receiver. A receiver receives a GNSS signal, removes a carrier component and provides in-phase and quadrature data and pilot signals. Data circuits can process the in-phase and quadrature data signals for data early and date late offsets and pilot circuits can process the in-phase and quadrature pilot signals for pilot early and pilot late offsets. The data early and data late signals can be combined to provide a data error difference and pilot early and pilot late signals can be combined to provide a pilot error difference. A summing circuit can combine pilot and data error differences to provide a delay lock loop (DLL) error signal.

IPC Classes  ?

• G01S 19/30 - Acquisition or tracking of signals transmitted by the system code related
• G01S 19/29 - Acquisition or tracking of signals transmitted by the system carrier related
• G01S 19/37 - Hardware or software details of the signal processing chain

Abstract

Described herein are related to a device for communication. In one aspect, the device includes a first circuit configured to generate a first signal and a second signal at a first frequency, according to a third signal at a second frequency higher than the first frequency. The first signal and the second signal may have opposite phases with each other. In one aspect, the device includes a second circuit configured to provide a difference between the first signal and the second signal as a fourth signal. In one aspect, the device includes a third circuit configured to provide the first signal to the second circuit, and resonate at a third frequency between the first frequency and the second frequency. In one aspect, the device includes a fourth circuit configured to provide the second signal to the second circuit, and resonate at the third frequency.

IPC Classes  ?

• H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
• H04B 1/04 - Circuits

Abstract

The technical solutions are directed to coordinated beamforming per-TXOP frame sequence negotiation. A first access point (AP) can transmit, to a second AP and a first candidate set of stations, a first message to initiate transmission opportunity (TXOP) and a CBF request. The second AP can transmit a second message to a second candidate set of stations of the second AP identified to participate in the TXOP with a CBF response responsive to the CBF request. The first AP, responsive to receiving the CBF response, can transmit to the second AP a third message having a CBF trigger comprising information to synchronize a CBF transmission to be communicated during the TXOP.

IPC Classes  ?

• H04W 74/0816 - Non-scheduled access, e.g. ALOHA using carrier sensing, e.g. carrier sense multiple access [CSMA] with collision avoidance
• H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
• H04W 72/12 - Wireless traffic scheduling
• H04W 74/08 - Non-scheduled access, e.g. ALOHA

Abstract

At least one aspect of the technical solutions can be directed to a system. The system can include a first access point (AP) that can be configured to transmit, to a second AP that can be capable of participating in coordinated beamforming (CBF) and a first candidate set of stations of the first AP, a first message to initiate transmission opportunity (TXOP). The second AP can be configured to transmit a second message to the first AP and a second candidate set of stations of second AP identified to participate in the TXOP. The second AP can be configured to transmit a third message having a CFB response to the first AP. The first AP can be configured to transmit a fourth message to second AP having a CBF trigger that can include information on a preamble of a CBF transmission to be communicated during the TXOP.

IPC Classes  ?

• H04W 74/0816 - Non-scheduled access, e.g. ALOHA using carrier sensing, e.g. carrier sense multiple access [CSMA] with collision avoidance
• H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
• H04W 28/02 - Traffic management, e.g. flow control or congestion control
• H04W 74/08 - Non-scheduled access, e.g. ALOHA

Abstract

A system includes a voltage booster circuit to receive an input voltage and provide an output voltage. A first device that is coupled to the voltage booster circuit to receive a digitized input voltage and a digitized output voltage and to determine, based on the digitized input voltage and the digitized output voltage, a first threshold level for the voltage booster circuit to operate in a pulse frequency modulation (PFM) mode. A second device that is coupled to the voltage booster circuit to receive the input voltage and the output voltage and to determine a second threshold level for the voltage booster circuit to operate in the PFM mode. A selector device that is coupled to the first device and the second device to select one of the first threshold level or the second threshold level for the voltage booster circuit.

IPC Classes  ?

• H02M 1/00 - Details of apparatus for conversion
• H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
• H03K 7/06 - Frequency or rate modulation, i.e. PFM or PRM
• H05B 45/335 - Pulse-frequency modulation [PFM]
• H05B 45/34 - Voltage stabilisationMaintaining constant voltage
• H05B 45/345 - Current stabilisationMaintaining constant current

Abstract

A system may include a transmitter and one or more processors. The one or more processors may be configured to identify a number of additional symbols to be added to existing symbols corresponding to payload data to be encoded. The one or more processors may be configured to calculate, based on a length of the payload data and the number of additional symbols, a number of available bits for error correction. The one or more processors may be configured to encode, via an low-density parity-check (LDPC) encoder, the payload data using an LDPC code to generate a codeword having a number of parity bits corresponding to the available bits. The one or more processors may be configured to transmit, via the transmitter, the encoded data.

IPC Classes  ?

• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

Technical solutions include systems and methods for multi-access-point (AP) coordination of coordinated beamforming (CBF) for nulling of mutual interferences. A first AP can be configured to identify a second AP that is capable of participating in coordinated beamforming (CBF), select one or more candidate stations of the first AP and identify capabilities of at least one of the first AP or the one or more candidate stations. The first AP can be configured to determine one or more stations of the one or more candidate stations to participate in CBF based at least on the capabilities and perform a sequence with the second AP to exchange, between the first AP and the second AP, a set of stations of the first AP and the second AP to participate in CBF. The first AP can identify to the second AP the determined one or more stations as participating in CBF.

IPC Classes  ?

• H04B 7/024 - Co-operative use of antennas at several sites, e.g. in co-ordinated multipoint or co-operative multiple-input multiple-output [MIMO] systems
• H04W 48/08 - Access restriction or access information delivery, e.g. discovery data delivery

Abstract

Technical solutions providing setup sequences for multi-access point (AP) coordinated beamforming (CBF). A system can include a first access point (AP) configured to transmit, to a second AP that is capable of participating in coordinated beamforming (CBF), a first notification frame comprising a first set of stations of the first AP to participate in a CBF transmission. The first AP can be configured to receive, from the second AP, responsive to the first notification frame, a first response frame comprising a second set of stations of the second AP to participate in the CBF transmission. The first AP can be configured to transmit data in the CBF transmission to at least one station of the first set of stations or the second set of stations, responsive to the first response frame.

IPC Classes  ?

• H04B 7/026 - Co-operative diversity, e.g. using fixed or mobile stations as relays
• H04W 24/02 - Arrangements for optimising operational condition

Abstract

Technical solutions provide setup sequences for multi access point (AP) coordinated beamforming (CBF) at a transmission opportunity (TXOP) stage. A first AP can transmit, to a second AP capable of participating in CBF and a first station of the first AP, a notification indicative of a CBF TXOP. The first AP can receive, from at least the first station, responsive to the notification, a first response identifying a first capability of the first station. The first AP can receive, from the second AP associated with a second one or more stations, responsive to the notification, a second response identifying a second capability of at least one of the second AP or a second station of the second one or more stations. The first AP can communicate data to the first station during the CBF TXOP according to at least one of the first capability or the second capability.

IPC Classes  ?

• H04W 74/0808 - Non-scheduled access, e.g. ALOHA using carrier sensing, e.g. carrier sense multiple access [CSMA]

Abstract

Novel tools and techniques are provided for implementing a novel integrated programmable gain amplifier (“PGA”) and protection circuit. In various embodiments, a circuit is provided that comprises: a PGA, an analog-to-digital converter (“ADC”), and a protection circuit all disposed on the same semiconductor chip. The PGA is configured to receive as input a wireless signal received from an antenna and to output, at its output, an amplified wireless signal based on the wireless signal being amplified by a programmable gain amount. The protection circuit is configured to, in response to detecting a spike in gain at the output of the PGA that exceeds a threshold amplitude, control a decrease in the programmable gain amount to cause a resultant signal at the output of the PGA to be below the threshold amplitude. A normally-open switch may also be added at differential outputs of the PGA to further clamp PGA output.

IPC Classes  ?

• H04B 1/04 - Circuits
• H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission

Abstract

Novel tools and techniques are provided for implementing migration of one or more drives, and more particularly to methods, systems, and apparatuses for implementing migration of one or more drives by setting one or more indications on a memory of the one or more drives. A controller for a redundant array of independent disks can be configured to set a first indication indicating a first drive is safe to migrate or not safe to migrate and store the first indication in a first memory on the first drive. The first drive can be a mirror of a second drive. The controller can further be configured to set a second indication indicating the second drive was offline or not offline and store the second indication in the first memory on the first drive.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A circuit for driving digital-to-analog converter (DAC) comprising a serializer configured to combine multiple signals to one input signal to drive a forward inverter coupled to a first node with a first impedance in serial configuration and a first capacitance in shunt configuration. The circuit includes a chain of inverters coupled in series to transfer the input signal from the first node to the fifth node based on a signal transfer function. The circuit further includes a feedback inverter between the third node and the first node to form a feedback loop with two inverters in the chain, adding peaking in the signal transfer function at the first node. A second feedback inverter can be added between the fifth node and the third node to add peaking in the signal transfer function at the third node. The feedback inverter is designed as a current-starved inverter in order to alleviate hot-carrier injection (HCI) aging of the transistors and add programmability in the peaking. The circuit includes a DAC switch coupled to the fifth node.

IPC Classes  ?

• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Abstract

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 1/2, a second parity check matrix corresponding to a first exponent matrix comprising 1152 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Abstract

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 5/6, a second parity check matrix corresponding to a first exponent matrix comprising 384 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes

Abstract

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 3/4, a second parity check matrix corresponding to a first exponent matrix comprising 576 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Abstract

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 2/3, a second parity check matrix corresponding to a first exponent matrix comprising 768 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.

IPC Classes  ?

• H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
• H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes

Abstract

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, by a low-density parity-check (LDPC) encoder, a target code rate for which to encode data. The one or more processors may receive, by the LDPC encoder, a first set of information bits. The one or more processors may receive, by the LDPC encoder from an output of a shaping encoder, a second set of information bits. The one or more processors may adjust a code rate of an LDPC code to a second code rate higher than the target code rate to cause the LDPC encoder to encode the data at the target code rate. The one or more processors may encode the data using the LDPC code. The transmitter may transmit the encoded data.

IPC Classes  ?

• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

A device configured to support different numbers of outputs. The device includes an input port configured to receive an input signal. The device also includes a first transmission line characterized by a first characteristic impedance and coupled to a first output port. A switch is configured to either connect or disconnect the first transmission line to the input port. The device also includes a second transmission line characterized by a second characteristic impedance and coupled between the input port and a second output port. A controller is configured to activate the first switch to set a two-output mode or to deactivate the first switch to set a one-output mode. The second characteristic impedance is configured to be the same as the first characteristic impedance at the two-output mode or configured to be reduced to 1/√{square root over (2)} of the first characteristic impedance at the one-output mode.

IPC Classes  ?

• H01P 5/16 - Conjugate devices, i.e. devices having at least one port decoupled from one other port

Abstract

Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package or a chip package including a one or more channel vias. In various embodiments, an apparatus includes a first layer comprising a channel and a first via extending through the first layer to a first surface of a first ridge of the first channel. The apparatus can further include a second layer coupled to the first layer. The second layer can be a first outer layer of the first substrate. The apparatus can also include a first line coupled to the first via and extending along the first ridge of the first channel and embedded in the second layer.

IPC Classes  ?

• H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids

Abstract

Described embodiments provide systems and methods for profiling low latency applications using telemetry. A data processing system can include one or more processors and memory. The data processing system can receive telemetry data for a plurality of flows of packets. The data processing system can determine, using the telemetry data, a variance of bandwidth, a variance of packet lengths, and a variance of inter-arrival times between packets for each of the flows of packets. The data processing system can determine a type of application for a flow of the flows of packets based at least on a signature of the variance of bandwidth, the variance of packet lengths, and the variance of inter-arrival times for the flow. The data processing system can take, in response to determining the type of application, one or more actions to provide a quality of service for the flow according to the type of application.

IPC Classes  ?

• H04L 43/062 - Generation of reports related to network traffic
• H04L 43/067 - Generation of reports using time frame reporting
• H04L 47/22 - Traffic shaping

Abstract

An integrated circuit package includes a first integrated circuit die, a second integrated circuit die, and a third integrated circuit die. The integrated circuit package also includes a support structure. The first die, the second die, and the third die are attached to the support structure. The first integrated circuit die includes a first interface on a first side of the first integrated circuit die and the second integrated circuit die includes a second interface on a second side of the second integrated circuit die. The first side neighbors the second side. The first integrated circuit die is configured to communicate with second integrated circuit die via the first interface and the second interface. The first integrated circuit die includes a third interface on a third side of the first integrated circuit die and the second integrated circuit die includes a fourth interface on a fourth side of the second integrated circuit die. The third die includes a fifth interface on a fifth side and a sixth interface on sixth side. The sixth side is parallel to the third side and the fifth side, The first integrated circuit die is configured to communicate with the third integrated circuit die via the fifth interface and the third interface. The second integrated circuit die is configured to communicate with the third integrated circuit die via the sixth interface and the fourth interface.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/498 - Leads on insulating substrates
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

A system can include circuitry. The circuitry can receive an entry index of a table, perform a cycle walk of a first pipeline stage to change the entry index from a first value to a second value, determine that the second value of the entry index is an illegal value, provide the second value of the entry index to a second pipeline stage, and perform a cycle walk of the second pipeline stage to change the entry index to a legal value.

IPC Classes  ?

• G06F 12/14 - Protection against unauthorised use of memory
• G06F 12/02 - Addressing or allocationRelocation

Abstract

An apparatus for aligning a fiber array unit (FAU) connector with a photonic integrated circuit (PIC) includes an aligner having a front section and a bottom section respectively joined with two side sections spaced apart by a first distance. The front section and the bottom section are partially removed to expand a semi-confined open space between the two side sections for receiving a shelf extended out beyond a lens at a side edge of a PIC chip. The shelf has an alignment feature associated with the lens. The front section is configured as a support bar positioned on a surface of the PIC chip. The semi-confined open space between the two side sections allows a body of the FAU connector to be loaded down from top to sit on the shelf in the semi-confined open space and be aligned with the lens through the alignment feature.

IPC Classes  ?

• G02B 6/30 - Optical coupling means for use between fibre and thin-film device

Abstract

The technical solutions are directed to MAC address protection for frame integrity verification. A sender device can compute, using a temporal key (TK) programmed in hardware, a first key for a body of a frame and a second key for a header of the frame, different from the first key. The sender can encrypt the body of the frame at a machine access control (MAC) layer using the first key and the header of the frame at the MAC layer using the second key. The sender can compute a first MIC of the encrypted frame using the first key and a second MIC of a content of the header at the MAC layer using the second key. The sender can transmit the frame with the first MIC and the second MIC to a receiver configured to determine integrity of the header of the frame based on the second MIC.

IPC Classes  ?

• H04L 9/08 - Key distribution
• H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems

Abstract

Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package or a chip package including an optical package or co-packaged optics package comprising a lid. In an embodiment, an optical package can include a first substrate, a first circuit coupled to the first substrate and configured to transmit or receive an electrical signal, a second circuit coupled to the first substrate and configured to transmit or receive an optical signal, and a lid configured to couple to the first substrate and configured to cover at least a portion of the first circuit or the second circuit.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

An apparatus for supporting two fiber array unit (FAU) connectors in alignment with respective lenses of a photonics integrated circuit (PIC) includes a frame with a pair of arm sections joined with two side sections of a bottom section. The pair of arm sections is configured to parallelly insert in a package structure associated with a PIC chip to make the frame in a floating state. The bottom section provides a first support surface to support two aligners disposed respectively along the two side sections from top. Each aligner provides a semi-confined open space to receive a shelf extended out from a side edge of a PIC chip. The shelf is characterized by an alignment feature associated with a lens of the PIC chip. The semi-confined open space allows a body of a FAU connector to be loaded from top onto the shelf and be aligned with the lens based on the alignment feature.

IPC Classes  ?

• G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

Solutions for providing more customizable performance for a virtual disk in a RAID environment. Some solutions provide for a flexible write cache policy that manages a proportion of input-output operations written in write-back mode against input-output operations written in write-though mode. In some cases, aspects of the flexible write cache policy can be specified by a user.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A device is provided that includes computer-readable storage media storing one or more sequences of instructions and processing circuitry configured to execute the one or more sequences of instructions. Upon executing the instructions, the processing circuitry may receive a plurality of network packets containing content encapsulated in a plurality of layers; process the received plurality of network packets to extract the content for presentation; generate a predicted presentation quality indicator for the extracted content using a plurality of machine learning models in a hierarchical order with data generated during processing of the received plurality of network packets used as inputs to the plurality of machine learning models; and provide the predicted presentation quality indicator for the extracted content to a server via a network, wherein the data generated during processing of the received plurality of network packets is correlated across the plurality of layers to generate the predicted presentation quality indicator.

IPC Classes  ?

• H04N 21/24 - Monitoring of processes or resources, e.g. monitoring of server load, available bandwidth or upstream requests
• H04L 65/80 - Responding to QoS
• H04N 21/442 - Monitoring of processes or resources, e.g. detecting the failure of a recording device, monitoring the downstream bandwidth, the number of times a movie has been viewed or the storage space available from the internal hard disk
• H04N 21/466 - Learning process for intelligent management, e.g. learning user preferences for recommending movies

Abstract

A circuitry can transmit a first probe request to discover a first access point of a first channel. The circuitry can also transmit one or more additional probe requests to discover one or more other access points of one or more other channels. The circuitry can also, responsive to transmission of the one or more additional probe requests, check for the response to the first probe request on the first channel. The circuitry can also receive the response to the first probe request. The response can identify the first access point.

IPC Classes  ?

• H04W 40/24 - Connectivity information management, e.g. connectivity discovery or connectivity update
• H04W 24/08 - Testing using real traffic
• H04W 88/08 - Access point devices

Abstract

Wide-band output isolation is provided. A device includes a first output for a first radio frequency (RF) signal. A device includes a second output for a second RF signal. The device includes a first transistor having a first source/drain. The device includes a second transistor having a first source/drain, wherein the first source/drain of the first transistor is coupled to the first source/drain of the second transistor and wherein the first and second transistors are disposed between the first output and the second output.

IPC Classes  ?

• H01P 5/16 - Conjugate devices, i.e. devices having at least one port decoupled from one other port
• H04B 1/40 - Circuits

Abstract

Novel systems and methods for canvas sanitization are provided. In various embodiments, a system and method include: receiving a request to open a web page from a client device; replacing, via an agent, a first function with a second function, the agent being loaded to a browser; loading the web page from a web server to the browser; in response to an attempt to perform the first function on the web page, performing, via the browser, the second function corresponding to the first function to generate a drawing for a predetermined period of time; converting, via the agent, the drawing to an image; and transmitting the image to the client device. Other aspects, embodiments, and features are also claimed and described.

IPC Classes  ?

• G06F 9/4401 - Bootstrapping

Abstract

A system may include a first analog-to-digital converter (ADC) of a first type electrically coupled by a plurality of switches to a plurality of ADCs of a second type. The plurality of switches may be configured to select, based on a rate of an analog-to-digital conversion, a quantity of ADCs of the second type, from among the plurality of ADCs of the second type, to supply the analog-to-digital conversion at the rate. The plurality of switches may be configured to selectively bypass the first ADC according to a resolution of the analog-to-digital conversion. The plurality of switches may be configured to bypass the first ADC responsive to the resolution of the conversion being below a threshold.

IPC Classes  ?

• H03M 1/12 - Analogue/digital converters
• H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter

Abstract

Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package or a chip package including a backside power distribution network. In various embodiments, an apparatus includes a first substrate comprising a device configured to receive a voltage and a first side located on a front side of the first substrate and a second side located on a back side of the first substrate, a second substrate, the second substrate configured to support the first substrate, and a power distribution network located at an interface between the second side of the first substrate and the second substrate.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

A device to receive a first signal from a driver. The device comprising a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit to provide a second signal having a first level. The second circuit to detect the first level of the first signal and to provide a third signal to control a third circuit of the device. The third circuit to provide a fourth signal, the fourth signal having a first level in response to a difference being smaller than a predetermined value, and the fourth signal having a second level in response to the difference being larger than the predetermined value. The fourth circuit to provide a fifth signal, the fifth signal having a first level based at least on the second signal, and the fifth signal having a second level based at least on the second signal and the fourth signal.

IPC Classes  ?

• H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
• H03F 3/189 - High-frequency amplifiers, e.g. radio frequency amplifiers

Abstract

A system may include one or more receivers, circuitry, and a controller. Each of the one or more receivers may include a plurality of analog-to-digital converters (ADCs). Each ADC may measure a time relating to an analog-to-digital conversion by the ADC, compare the time with a threshold, and generate, based on a result of the comparing, a first signal. The circuitry may be coupled to the one or more receivers. The circuitry may receive the first signal from each ADC, determine, based at least on the first signal, characteristics of performance of each receiver, and output a plurality of second signals. Each of the plurality of second signals may indicate the characteristics of performance of a corresponding receiver. The controller may be coupled to the circuitry and adjust a voltage provided to the one or more receivers, based at least on the plurality of second signals received from the circuitry.

IPC Classes  ?

• H03M 1/44 - Sequential comparisons in series-connected stages with change in value of analogue signal

Abstract

Novel tools and techniques are provided for implementing a semiconductor or optical engine package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package including a dummy die coupled to a top surface of a fan-out wafer comprising an electronic die and coupled to a side of a photonic die. In various embodiments, an apparatus includes a first layer comprising an electronic die. A photonic die can be stacked on and coupled to the electronic die and a dummy die can be coupled to a first side of the photonic die and coupled to the first layer.

IPC Classes  ?

• H01S 5/0233 - Mounting configuration of laser chips

Abstract

Solutions for managing RAID logical devices. Some solutions provide enhanced online capacity expansion for virtual disks on RAID drives, for example by taking advantage of the hardware capabilities to expand a virtual disk stripe by stripe. Some solutions provide increase hardware automation, which can reduce firmware load and/or provide more efficient input-output operations (IO) for the online capacity expansion operation.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

Solutions for managing RAID virtual disks. Some solutions enable increased use of hardware circuitry to schedule and perform IO on a virtual drive, providing for more efficient IO. In some cases, this can be accomplished by notifying the hardware of precise regions of a virtual disk affected by the maintenance operation and any given time. The hardware then, can continue to perform host IO on portions of the logical disk not undergoing maintenance.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

An amplifier includes a first transmission line from a first terminal to a second terminal. The first transmission line is characterized by a first characteristic impedance matched to a resistance of a source from which a first signal is coupled to the second terminal. The amplifier includes a first resistor with a first resistance and a second resistor with a second resistance coupled between the second terminal and a third terminal. The first resistance and the second resistance are adjustable to match an input impedance at the second terminal to the first characteristic impedance and to tune a gain of a second signal at the third terminal over the first signal at the second terminal. The amplifier includes a second transmission line from the third terminal to a third resistor with a third resistance, the second transmission line being characterized by a second characteristic impedance matched to the third resistance.

IPC Classes  ?

• H03F 3/60 - Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
• H03G 3/20 - Automatic control

Abstract

The subject technology is directed to light detection and ranging (LIDAR) systems and methods. In an embodiment, the subject technology provides a device comprising an optical module configured to receive a first optical signal and a first circuit configured to generate a first electrical signal based on the first optical signal. The device also comprises a first comparator configured to generate a second electrical signal by comparing the first electrical signal to a first threshold value. The device further comprises a first filter configured to generate a first pulse based on the second electrical signal. The first pulse comprises a first point associated with a first timestamp. The timestamp data may be briefly retained in the analog domain, followed by subsequent digital conversion, allowing for significant power savings and reduced system bandwidth. There are other embodiments as well.

IPC Classes  ?

• G01S 7/487 - Extracting wanted echo signals
• G01S 7/4865 - Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
• H03M 1/36 - Analogue value compared with reference values simultaneously only, i.e. parallel type

Abstract

The subject technology is related to acoustic resonators. More specifically, an embodiment of the subject technology provides an acoustic resonator device that includes a piezoelectric layer disposed between a first electrode and a second electrode. The total thickness of the first electrode, the second electrode, and the third electrode allows the device to operate according to a second (or higher order) thickness extension mode. There are other embodiments as well.

IPC Classes  ?

• H03H 9/13 - Driving means, e.g. electrodes, coils for networks consisting of piezoelectric or electrostrictive materials
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 9/17 - Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator

Abstract

A device may include an oscillator and a driver. The oscillator may be coupled to circuitry providing calibration of the oscillator. The oscillator may receive from the circuitry a first signal that causes the oscillator to generate a second signal having a first frequency to be used for calibration of an analog-to-digital converter (ADC). The driver may be coupled to the oscillator and the ADC. The driver may receive the second signal from the oscillator. The driver may receive a third signal indicating an amplitude to apply to the second signal. The driver may provide, to the ADC based at least on the second signal and the third signal, an output signal having the first frequency and the amplitude.

IPC Classes  ?

• H03M 1/50 - Analogue/digital converters with intermediate conversion to time interval
• H03M 1/10 - Calibration or testing

Abstract

Wide-band matching in out-of-band blocker rejection filters is provided. A device includes a first inductor. The device includes a second inductor magnetically coupled with the first inductor and with an amplifier. The device includes a notch filter electrically coupled between the first inductor and the second inductor. The amplifier can be configured to amplify a plurality of radio frequency signals. A bandwidth of the radio frequency signals can exceed 1.5 gigahertz (GHz).

IPC Classes  ?

• H03F 3/19 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only

Abstract

Wide-band output isolation is provided. A device includes a first output for a first radio frequency (RF) signal. A device includes a second output for a second RF signal. The device includes a first transistor having a first source/drain. The device includes a second transistor having a first source/drain, wherein the first source/drain of the first transistor is coupled to the first source/drain of the second transistor and wherein the first and second transistors are disposed between the first output and the second output.

IPC Classes  ?

• H03F 3/19 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
• H01P 5/16 - Conjugate devices, i.e. devices having at least one port decoupled from one other port

Abstract

A device comprising a first circuit, a second circuit, and a third circuit. The first circuit to receive, from an amplifier, a first signal having a first amount of power. The first circuit to also determine, based on the first amount of power, a range of power associated with transmission of the first signal by a transmitter. The second circuit to receive a second signal to define one or more characteristics of the second circuit. Receipt of the second signal, by the second circuit, can cause the second circuit to adjust the first signal from the first amount of power to a second amount of power. The third circuit to receive, from the second circuit, the first signal having the second amount of power, and the third circuit to provide a third signal having a voltage level to indicate a third amount of power transmitted by the transmitter.

IPC Classes  ?

• H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets
• H04B 17/318 - Received signal strength