Abstract

Embodiments discussed herein generally include methods of fabricating MEMS devices within a structure. The MEMS device may be formed in a cavity above the structure, and additional metallization may occur above the MEMS device. The cavity may be formed by depositing an encapsulating layer over the sacrificial layers that enclose the MEMS device. The encapsulating layer may then be etched to expose portions of the sacrificial layers. The sacrificial layers are exposed because they extend through the sidewalls of the encapsulating layer. Therefore, no release holes are etched through the top of the encapsulating layer. An etchant then removes the sacrificial layers to free the MEMS device and form the cavity and an opening through the sidewall of the encapsulating layer. Another encapsulating layer may then be deposited to seal the cavity and the opening.

IPC Classes  ?

• B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate

Abstract

Embodiments disclosed herein generally include methods of sealing a cavity in a device structure. The cavity may be opened by etching away sacrificial material that may define the cavity volume. Material from below the cavity may be sputter etched and redeposited over and in passageways leading to the cavity to thereby seal the cavity. Material may be sputter etched from above the cavity and redeposited in the passageways leading to the cavity as well. The sputter etching may occur in a substantially inert atmosphere. As the sputter etching is a physical process, little or no sputter etched material will redeposit within the cavity itself. The inert gases may sweep out any residual gases that may be present in the cavity after the cavity has been opened. Thus, after the sputter etching, the cavity may be substantially filled with inert gases that do not negatively impact the cavity.

IPC Classes  ?

• B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate

Abstract

A non-volatile memory bitcell which comprises a first bistable cantilever module and a second bistable cantilever modules. The bistable cantilever modules have a shared output terminal and each has an input terminal and two actuating terminals. The first and second cantilever modules are arranged such that their states are complementary. The memory bitcell further includes buffering means arranged to prevent the flow of current from the shared output terminal and further arranged to indicate the states of the first and second cantilever modules.

IPC Classes  ?

• G11C 23/00 - Digital stores characterised by movement of mechanical parts to effect storage, e.g. using ballsStorage elements therefor

Abstract

A memory cell (1) comprising a cantilever (2) moveable between a first position in which this is in contact with a contact pad (3) and a second position and which is out of contact with the contact pad, - an electromagnetic driving means (4, 5) for controllably driving the cantilever between its two positions; and a transistor (12) having its drain connected to the cantilever.

IPC Classes  ?

• G11C 23/00 - Digital stores characterised by movement of mechanical parts to effect storage, e.g. using ballsStorage elements therefor
• G11C 13/02 - Digital stores characterised by the use of storage elements not covered by groups , , or using elements whose operation depends upon chemical change

Abstract

A method, in a complementary metal oxide semiconductor fabrication process, of creating a layered housing containing a micro-electromechanical system device, the method comprising the steps of providing a cavity in at least one layer of the housing, the cavity being accessible through via holes in a layer of insulating material deposited thereon, and the layer of insulating material being covered by a thin film layer of conductive material. The method further comprises the step of hydrophobically treating at least a portion of the inner surface of the cavity. Finally the method comprises the steps of submerging the wafer in an electroplating solution and electroplating a conductive layer onto the thin film layer of conductive material such that the cavity remains free of electroplating solution.

IPC Classes  ?

• B81C 99/00 - Subject matter not provided for in other groups of this subclass
• H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections

Abstract

A method of manufacturing a cantilever-based micro-electromechanical device comprising the steps of providing a first conductive material layer on a substrate to from a plurality of electrodes. Then, depositing a sacrificial material layer on the electrodes and substrate, thereby defining a non-exposed surface and an exposed surface of the sacrificial material. The method comprises the steps of patterning and etching the sacrificial material layer such that at least a portion of at least one electrode is exposed and sputter etching the sacrificial material layer such that the exposed surface of the sacrificial material layer comprises edges which are incongruous with the edges of the non-exposed surface. The method then involves forming a cantilever structure. Finally, the method comprises the step of removing at least a portion of the sacrificial material layer such that at least a portion of the cantilever structure is suspended.

IPC Classes  ?

• B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
• H01H 1/00 - Contacts

Abstract

A method of manufacturing a non-volatile memory bitcell comprises the steps of depositing a first layer of conductive material on a substrate and patterning and etching the first layer of conductive material to form three non-linearly disposed electrodes. The method also comprises the steps of depositing a first layer of sacrificial material on the electrodes and the substrate and providing an elongate cantilever structure on the first layer of sacrificial material such that the cantilever structure and at least a portion of each electrode overlap each other. The method also includes the steps of depositing a second layer of sacrificial material on the cantilever structure and the first layer of sacrificial material and providing a capping layer on the second layer of sacrificial material and providing holes in the capping layer such that at least a portion of the second layer of sacrificial material is exposed. Finally, the method provides the step of removing the first and second layers of sacrificial material through the holes provided in the capping layer, thereby defining a cavity in which the cantilever structure is suspended.

IPC Classes  ?

• G11C 23/00 - Digital stores characterised by movement of mechanical parts to effect storage, e.g. using ballsStorage elements therefor
• B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes

Abstract

A non-volatile memory device and method of manufacturing a non-volatile micro-electromechanical memory cell. The method comprises the first step of depositing a first layer of sacrificial material on a substrate by use of Atomic Layer Deposition The second step of the method is providing a cantilever (101) over at least a portion of the first layer of sacrificial material. The third step is depositing, by use of Atomic Layer Deposition, a second layer of sacrificial material over the first layer of sacrificial material and over a portion of the cantilever such that a portion of the cantilever is surrounded by sacrificial material. The fourth step is providing a further layer material (107) which covers at least a portion of the second layer of sacrificial material. Finally, the last step is etching away the sacrificial material surrounding the cantilever, thereby defining a cavity (102) in which the cantilever is suspended.

IPC Classes  ?

• B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
• G11C 23/00 - Digital stores characterised by movement of mechanical parts to effect storage, e.g. using ballsStorage elements therefor
• G11C 11/50 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using actuation of electric contacts to store the information
• H01H 1/00 - Contacts

Abstract

The present invention provides a method of integrating a structure, e.g. a fuse, for use in a semiconductor device, the method comprises several steps, the first step is providing a first layer of sacrificial material (1) on a substrate. The second step is providing the structure (5) on the first layer of sacrificial material, the structure having two terminal portions. The third step is providing a second layer of sacrificial material (3) over the first layer of sacrificial material and over a length of the structure between the terminal portions such that the length of the structure is surrounded by sacrificial material, said length defining a usable portion of the structure. The fourth step is providing a layer of dielectric material such that the first and second layers of sacrificial material and the structure are encased by the layer of dielectric material and the substrate. The fifth step is forming a passage through the dielectric material to provide access to the sacrificial material. The final step is injecting a fluid through the passage to remove the sacrificial material surrounding the usable portion of the structure, thereby defining a cavity in which the usable portion is suspended.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections

Abstract

A one time-programmable memory bitcell (9) comprises a transistor (13) and a fuse (12). The transistor is arranged to receive a first signal and, upon receipt of the first signal, to enable communication of a second signal to the fuse. Preferably, the input terminal of the transistor is connected to the source of the first signal, the output terminal of the transistor is connected to one terminal of the fuse the other terminal of the fuse is connected to the source of the second signal. The present invention also provides a fuse memory array and associated control circuit.

IPC Classes  ?

• G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
• G11C 17/18 - Auxiliary circuits, e.g. for writing into memory

Abstract

A memory bitcell comprises first (102) and second (103) transistors and a cantilever module (104) having two states. The first transistor (102) is arranged to communicate a first signal to the input of the cantilever module (104) upon receipt of a second signal. The second transistor (103) is arranged to bypass the cantilever module (104) upon receipt of a third signal (RST) . The memory bitcell is operable such that the state of the cantilever (104) can be changed in order to represent one bit of binary information and can be detected by monitoring the first signal.

IPC Classes  ?

• G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
• G11C 17/18 - Auxiliary circuits, e.g. for writing into memory