Shinko Electric Industries Co., Ltd.

Japan

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IPC Class
G01B 11/00 - Measuring arrangements characterised by the use of optical techniques 1
G03F 9/00 - Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically 1
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or 1
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment 1
H01L 23/12 - Mountings, e.g. non-detachable insulating substrates 1
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Found results for  patents

1.

METHOD FOR RESIST PATTERN FORMATION, PROCESS FOR PRODUCING CIRCUIT BOARD, AND CIRCUIT BOARD

      
Application Number JP2006309851
Publication Number 2007/132533
Status In Force
Filing Date 2006-05-17
Publication Date 2007-11-22
Owner
  • MITSUBISHI PAPER MILLS LIMITED (Japan)
  • SHINKO ELECTRIC INDUSTRIES CO., LTD. (Japan)
Inventor
  • Kaneda, Yasuo
  • Irisawa, Munetoshi
  • Toyoda, Yuji
  • Komuro, Toyokazu
  • Fukase, Katsuya
  • Sakai, Toyoaki

Abstract

This invention provides a method for resist pattern formation, for use in the preparation of a circuit board having landless or narrow-land-width throughholes that realize increased density in a circuit board, a process for producing a circuit board, and a circuit board. The method for resist pattern formation comprises the step of forming a resin layer and a mask layer on a first plane of a board having throughholes and the step of feeding a resin layer removing liquid from a second plane, which is opposite to the first plane of the board, to remove the resin layer on the throughholes and the peripheries of the throughholes in the first plane. There are also provided a process for producing a circuit board using the method for resist pattern formation, and a circuit board.

IPC Classes  ?

  • H05K 3/42 - Plated through-holes
  • H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material

2.

SUBSTRATE WITH BUILT-IN CHIP AND METHOD FOR MANUFACTURING SUBSTRATE WITH BUILT-IN CHIP

      
Application Number JP2006324764
Publication Number 2007/069606
Status In Force
Filing Date 2006-12-12
Publication Date 2007-06-21
Owner SHINKO ELECTRIC INDUSTRIES CO., LTD. (Japan)
Inventor
  • Yamano, Takaharu
  • Iizuka, Hajime
  • Sakaguchi, Hideaki
  • Kobayashi, Toshio
  • Arai, Tadashi
  • Kobayashi, Tsuyoshi
  • Koyama, Tetsuya
  • Iida, Kiyoaki
  • Mashima, Tomoaki
  • Tanaka, Koichi
  • Kunimoto, Yuji
  • Yanagisawa, Takashi

Abstract

A method for manufacturing a substrate having a built-in chip is provided with a first step of mounting a semiconductor chip on a first substrate whereupon a first wiring is formed, and a second step of bonding a second substrate whereupon a second wiring is formed with the first substrate. In the second step, the semiconductor chip is sealed between the first substrate and the second substrate, the first wiring is electrically connected with the second wiring, and a multilayer wiring connected with the semiconductor chip is formed.

IPC Classes  ?

  • H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
  • H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
  • H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
  • H01L 25/11 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in subclass
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
  • H05K 1/14 - Structural association of two or more printed circuits
  • H05K 3/46 - Manufacturing multi-layer circuits

3.

EXPOSING METHOD AND DEVICE

      
Application Number JP2006312319
Publication Number 2006/137396
Status In Force
Filing Date 2006-06-20
Publication Date 2006-12-28
Owner
  • SANEI GIKEN CO., LTD. (Japan)
  • SHINKO ELECTRIC INDUSTRIES CO., LTD. (Japan)
Inventor
  • Hashimoto, Hironobu
  • Takagi, Toshihiro
  • Miyake, Ken

Abstract

An exposing method and an exposing device for transferring a pattern written on a photomask to a substrate. The photomask is arranged at a position covering a substrate. The photomask and the substrate touch each other uniformly to create a state of being deformed concavely or convexly to each other. Under that state, a photosensitive layer on the substrate is irradiated with light through the photomask, thus transferring a pattern having substantially changed dimensions onto the substrate.

IPC Classes  ?

  • G03F 9/00 - Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
  • H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
  • G01B 11/00 - Measuring arrangements characterised by the use of optical techniques