An interconnect substrate includes a core layer, a first interconnect layer formed on a first surface of the core layer, a second interconnect layer formed on a second surface of the core layer, a cavity extending through the core layer, an electronic component in the cavity, a first insulating layer covering the electronic component and covering side surfaces, without covering an upper surface, of the first interconnect layer, and a second insulating layer covering the upper surface of the first interconnect layer and an upper surface of the first insulating layer, wherein the first insulating layer has a recess over the cavity recessed relative to the upper surface of the first insulating layer, a deepest part of the recess is located between a plane including the first surface and a plane including the upper surface of the first interconnect layer, and the second insulating layer fills the recess.
A wiring board includes an interconnect layer including a metal pattern, and an insulating layer, disposed on the interconnect layer, and including a first resin pattern. The insulating layer includes a filler. The metal pattern includes a central region, and an outer region located on an outer periphery of the central region. The first resin pattern includes a first region covering the central region, and a second region covering a portion of the outer region and exposing other portions of the outer region. The metal pattern and the first resin pattern constitute an alignment mark.
A wiring substrate includes a core substrate, a first wiring structure located on an upper surface of the core substrate, and a second wiring structure located on an upper surface of the first wiring structure. The first wiring structure includes a structure in which one or more first wiring layers and one or more first insulating layers are stacked. The second wiring structure includes a structure in which multiple second wiring layers and multiple second insulating layers are stacked. The second wiring structure has a higher wiring density than the first wiring structure. The second insulating layer has a thermal expansion coefficient higher than that of the core substrate and lower than that of the first insulating layer.
An electrostatic chuck includes a ceramic plate, an adsorption electrode, a ground electrode, and a wiring. The adsorption electrode is built-in below one surface of the ceramic plate. The ground electrode is disposed between another surface of the ceramic plate and the adsorption electrode in the ceramic plate and connectable to a ground potential. The wiring is connected to the ground electrode in the ceramic plate and extending through the adsorption electrode to the one surface of the ceramic plate. The wiring includes a connection pad disposed at a same height position as the adsorption electrode, a first via connecting the connection pad and the ground electrode or another connection pad disposed closer to the ground electrode than the connection pad, and a second via connecting the connection pad and the one surface of the ceramic plate.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
5.
LEAD FRAME STRIP, METHOD OF MAKING THE SAME, AND SEMICONDUCTOR DEVICE
A lead frame strip includes a frame portion and a plurality of leads projecting from an inner edge of the frame portion to an inside of the frame portion, wherein each of the leads has a lower surface, an upper surface opposite the lower surface, and a step surface recessed relative to the upper surface toward the lower surface, and wherein the step surface is convex upward in a vertical cross-section that is taken through the step surface perpendicularly to a direction in which the leads project.
A wiring substrate includes a core layer including a first through hole, a magnetic resin filling the first through hole, a first wiring layer arranged on an upper surface of the magnetic resin, and a first wedge portion extending from the first wiring layer and wedged into the core layer. The first wiring layer includes a structure in which a first metal film, a first metal layer, a second metal film, and a second metal layer are sequentially stacked on the upper surface of the magnetic resin. The first wedge portion is formed continuously and integrally with the first metal film. The first wedge portion extends from the first metal film toward the core layer.
An optical waveguide component includes a first support member having a first surface. The first surface includes multiple recesses. The optical waveguide component further includes an optical waveguide supported by the first support member. The optical waveguide includes a first core. The first core has a first end face exposed on the first surface.
A polymer optical waveguide includes a plurality of cores arranged on an imaginary plane, a cladding disposed around the plurality of the cores, and a groove formed in the cladding and positioned between two cores adjacent each other among the plurality of cores, wherein the groove has a first wall surface extending along the two cores, and the first wall surface is inclined with respect to a normal direction of the imaginary plane.
A semiconductor device includes an insulating base material that includes an adhesive layer on one of surfaces of the insulating base material; an electronic component that is fixed to the one of the surfaces; a metal plate that is arranged to sandwich the electronic component with the one of the surfaces; a sealing resin that is filled between the insulating base material and the metal plate; a wiring layer that is formed on another of the surfaces, and connected to the electronic component by way of a via; and a metal layer that is made of a same metal material as that used for the wiring layer and the via, and covers a surface of the metal plate located on a side opposite to a surface that is covered by the sealing resin.
H01L 23/367 - Cooling facilitated by shape of device
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
10.
INTERCONNECT SUBSTRATE AND METHOD OF MAKING THE SAME
An interconnect substrate includes a core layer that is translucent, a first photoelectric conversion member disposed on a first surface of the core layer, a first interconnect layer electrically connected to the first photoelectric conversion member, a second photoelectric conversion member disposed on a second surface of the core layer that is opposite the first surface, and a second interconnect layer electrically connected to the second photoelectric conversion member, wherein the first photoelectric conversion member and the second photoelectric conversion member are arranged at such positions as to exchange optical signals with each other through the core layer.
H10F 55/00 - Radiation-sensitive semiconductor devices covered by groups , or being structurally associated with electric light sources and electrically or optically coupled thereto
A semiconductor device includes a lower substrate, a semiconductor element mounted on an upper surface of the lower substrate, and an upper substrate arranged on an upper surface of the semiconductor element. The semiconductor element includes an electrode arranged on the upper surface of the semiconductor element. The semiconductor device includes via wirings and a wiring layer. The via wirings extend through the upper substrate in a thickness-wise direction and are connected to the electrode. The wiring layer is arranged on an upper surface of the upper substrate and is electrically connected to the electrode by the via wirings. The via wirings include two or more types of via wirings that differ from one another in planar size. The via wirings are arranged so that the planar size decreases from a peripheral portion of the semiconductor element toward a central portion of the semiconductor element in plan view.
A polymer optical waveguide includes a core having an end surface, and a cladding provided around the core and having a first surface, wherein a recess is formed in the first surface. The end surface is exposed inside the recess, and the end surface is located at a position deeper than the first surface.
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
An electrostatic chuck includes a base body having a placement surface on which a target object to be adsorbed is to be placed; and an electrostatic electrode embedded in the base body, wherein a surface of the base body opposite to the placement surface is a flat surface, and the placement surface is convex or concave with respect to the flat surface.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
A substrate fixing device includes a base plate, an electrostatic chuck fixed on the base plate, a first through hole penetrating the base plate in a thickness direction, a recess provided in a lower surface of the electrostatic chuck and communicating with the first through hole, an electrode built in the electrostatic chuck, a power supply terminal inserted into the first through hole and electrically connected to the electrode exposed from the recess, and a tubular insulating member inserted into the first through hole and surrounding an outer periphery of the power supply terminal. The tubular insulating member is formed to surround an entire outer peripheral surface of a portion of the power supply terminal disposed inside the first through hole. The tubular insulating member is formed to extend over an entire length of the first through hole in an axial direction. The tubular insulating member is a single member.
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
An optical waveguide component includes a substrate having a first principal surface, an optical waveguide provided on the first principal surface and including a first core, and a first optical connector fixed to the substrate and including a first collimating lens. A first distance between a first principal point of the first collimating lens and a first end surface of the first core is equal to a first focal distance of the first collimating lens.
An optical waveguide component includes a substrate having a first principal surface, an optical waveguide provided on the first principal surface and including a first core, and a first optical connector fixed to the first principal surface. The first optical connector includes a first mirror provided on a first optical axis of the first core. The first mirror has a second optical axis inclined from the first optical axis, and is configured to reflect light incident from the first core as collimated light.
A manufacturing method of a wiring substrate includes laminating a seed layer on a top surface of a first insulating layer; forming, on a top surface of the seed layer, a pad that includes a pad main body, and a surface treatment layer that covers a top surface and a side surface of the pad main body, and that has a metal layer at least in part; forming a protective film that covers a surface of the pad and the top surface of the seed layer around the pad; forming a second insulating layer that covers a surface of the protective film on the top surface of the first insulating layer; forming a cavity that exposes the surface of the protective film in the second insulating layer by laser processing; removing the protective film; and removing a portion of the seed layer that does not overlap with the pad.
H05K 3/30 - Assembling printed circuits with electric components, e.g. with resistor
H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
18.
SUBSTRATE WITH EMBEDDED ELECTRONIC COMPONENT AND METHOD OF MAKING THE SAME
A substrate with an embedded electronic component includes a first substrate, a second substrate on which an electronic component is mounted, connecting member electrically and a substrate connecting a first pad of the first substrate and a second pad of the second substrate, wherein the first substrate is disposed opposite the second substrate across the electronic component, wherein the substrate connecting member includes a first core in contact with the first pad, a second core in contact with the first core and the second pad, and a conductive member covering the first core and the second core, and in contact with the first pad and the second pad, and wherein the first core and the second core are spherical, and a diameter of the second core is smaller than a diameter of the first core.
An optical waveguide component includes a substrate having a first surface, an optical waveguide disposed on the first surface, a projection formed on the first surface, a glass block including an optical fiber and including a recess into which the projection fits, wherein the optical waveguide and the optical fiber are optically coupled.
A substrate with an embedded electronic component includes a first substrate, a second substrate on which an electronic component is mounted, a substrate connecting member electrically connecting a first pad of the first substrate and a second pad of the second substrate, an encapsulating resin filling a gap between the first substrate and the second substrate to cover the electronic component, wherein the first substrate is disposed opposite the second substrate across the electronic component, wherein a surface area of the second pad in contact with the substrate connecting member is larger than a surface area of the first pad in contact with the substrate connecting member, and wherein the substrate connecting member includes a first section whose width gradually narrows from a surface of the second pad toward a position between the first pad and a center of the substrate connecting member in a height direction in cross-sectional view.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A wiring substrate includes a glass core layer; first and second wiring layers on first and second surfaces, respectively, of the glass core layer; first and second organic insulating layers covering the first and second wiring layers, respectively; first dummy pads provided one in each of corner areas of the first surface and electrically independent of the first wiring layer, second dummy pads provided one in each of corner areas of the second surface and electrically independent of the second wiring layer, and dummy through vias piercing through the glass core layer to connect the first and second dummy pads. In each corner area of the first surface, the distance from the apex of the corner area to the center of the nearest dummy through via is less than or equal to 17 times the maximum width of the dummy through vias at the first surface in a plan view.
A measurement apparatus includes a substrate having a first surface and a second surface opposite the first surface, with a first electrode and a second electrode disposed on the first surface, and a metal plate positioned opposite the second surface of the substrate across a spacer, wherein the metal plate includes a region overlapping the first electrode and the second electrode in plan view.
G01N 27/22 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating capacitance
23.
INTERCONNECT SUBSTRATE AND METHOD OF MAKING INTERCONNECT SUBSTRATE
An interconnect substrate includes a first interconnect layer having a first surface in which a recess is formed, an insulating layer that has a second surface facing the first surface and covers the first interconnect layer, a via hole overlapping the first interconnect layer in plan view and penetrating the insulating layer, and a second interconnect layer formed on the insulating layer and situated in contact with the first interconnect layer through the via hole.
A heat storage device includes a ceramic part, and a latent heat storage part provided inside the ceramic part. The ceramic part includes a first surface, a second surface opposite to the first surface, a third surface connecting the first surface and the second surface, and a first groove provided in the third surface and connected to the first surface and the second surface.
F28D 20/02 - Heat storage plants or apparatus in generalRegenerative heat-exchange apparatus not covered by groups or using latent heat
F28D 20/00 - Heat storage plants or apparatus in generalRegenerative heat-exchange apparatus not covered by groups or
F28F 21/04 - Constructions of heat-exchange apparatus characterised by the selection of particular materials of ceramicConstructions of heat-exchange apparatus characterised by the selection of particular materials of concreteConstructions of heat-exchange apparatus characterised by the selection of particular materials of natural stone
A substrate fixing device includes a ceramic base plate, a ceramic electrostatic chuck having a mounting surface on which an object to be sucked is mounted, and a first brazing part joining the base plate and the electrostatic chuck. The base plate is made of a ceramic material having a thermal expansion coefficient of 0±3 ppm/K at a room temperature. The electrostatic chuck is made of a ceramic material having a thermal expansion coefficient of 0±3 ppm/K at the room temperature.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
A wiring substrate includes a first wiring layer located on an upper surface of a first insulating layer, a second insulating layer located on the first insulating layer and covering the first wiring layer, a via hole extending through the second insulating layer in a thickness-wise direction and exposing the first wiring layer, and a trench recessed from an upper surface of the second insulating layer. The wiring substrate further includes a via wiring filling the via hole, a conductive layer filling the trench, and a second wiring layer electrically connected to the first wiring layer by the via wiring and located on the upper surface of the second insulating layer. The trench does not extend through the second insulating layer in the thickness-wise direction. The trench is arranged peripheral to the via hole and separated from the via hole. The trench overlaps the second wiring layer in plan view.
An optical module includes a wiring substrate and an optical waveguide device mounted on the wiring substrate. The wiring substrate includes a core substrate, a wiring structure formed on an upper surface of the core substrate, and a notch extending through the wiring structure in a thickness direction and exposing a peripheral portion of the core substrate. The optical waveguide device is mounted on an upper surface of the wiring structure at a position proximate to the notch.
An interconnect substrate includes a first insulating layer having a first surface, a pad disposed on the first surface, a second insulating layer disposed on the first surface and covering the pad, the second insulating layer having a second surface facing the first surface and a third surface opposite the second surface, and a first interconnect layer disposed on the third surface, and a third insulating layer disposed on the third surface and covering the first: interconnect layer, wherein a recess penetrates the first insulating layer and the second insulating layer and has an end surface in the third insulating layer, and wherein an opening is formed in the first insulating layer, and the pad is exposed through the opening.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
A substrate fixing device includes a base plate, a first adhesive layer, and an electrostatic chuck mounted on the base plate via the first adhesive layer. The electrostatic chuck includes a first base body made of a ceramic material as a main component, a second adhesive layer, a second base body having a placement surface for mounting a target object to be adsorbed, disposed on the first base body via the second adhesive layer, and made of a ceramic material as a main component, and an electrostatic electrode built in the second base body, and the first base body is disposed on the first adhesive layer.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
A semiconductor device includes a wiring substrate, a semiconductor element, a bonding member bonding connection pads of the wiring substrate and electrode pads of the semiconductor element, and an encapsulation resin provided between the wiring substrate and the semiconductor element. The connection pads each include a first body, first projections projecting from the first body toward a central region of the semiconductor element, and a first recess. The bonding members each include a second body, second projections projecting from the second body toward the central region, and a second recess. A first space surrounded by the upper surface of the substrate body, the wall surface of the first recess, the wall surface of the second recess, and the lower surface of each of the electrode pads is open in a single direction.
A lead frame includes a plurality of terminal portions including a first terminal portion, wherein the first portion has an upper surface and at least one side surface, and includes a plurality of bonding areas that are defined on the upper surface within a mounting region where a semiconductor chip is to be mounted, the bonding areas being designated for bonding with respective electrodes of the semiconductor chip, and a recess that is provided between adjacent bonding areas among the plurality of bonding areas and that opens on the upper surface, the recess reaching the at least one side surface.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
32.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A semiconductor device includes an insulation base material, a wiring layer, a via, and a semiconductor element. The insulation base material includes an insulating layer including an adhesive agent layer formed on one surface of the insulating layer. The wiring layer is formed on the one surface of the adhesive agent layer. The via is separately formed from the wiring layer, and penetrates through the insulating layer and the adhesive agent layer, to be connected with the wiring layer. The via includes conductive sintered material. The semiconductor element is connected with another end of the via on an opposite side of one end of the via, the one end being connected with the wiring layer, on another surface of the insulating layer.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
33.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A semiconductor device includes an insulation base material, a wiring layer, a via, and a semiconductor element. The insulation base material includes an insulating layer including an adhesive agent layer formed on one surface of the insulating layer. The wiring layer is formed on the one surface of the adhesive agent layer. The via is separately formed from the wiring layer and penetrates through the insulating layer and the adhesive agent layer, to be connected with the wiring layer. The semiconductor element is connected, via a sintered material, with another end of the via on an opposite side of one end of the via, the one end being connected with the wiring layer, on another surface of the insulating layer.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
An optical waveguide component includes optical fibers each having a first end and a second end, and a support member configured to support the optical fibers. The support member includes a base including a first surface, a first protruding portion protruding from the first surface in a first direction perpendicular to the first surface, and a second protruding portion protruding from the first surface in the first direction at a position separated from the first protruding portion. The first protruding portion includes first grooves respectively configured to accommodate the first end of each optical fiber, and the second protruding portion includes second grooves respectively configured to accommodate the second end of each optical fiber. A pitch of the second grooves is larger than a pitch of the first grooves.
An interconnect substrate includes a first insulating layer having a cavity formed therein, an electronic component including an insulating substrate and a pad provided on one side of the insulating substrate, the electronic component being arranged in the cavity, with the pad facing an opening of the cavity, and a second insulating layer disposed on the first insulating layer and in the cavity, wherein an upper surface and side surfaces of the pad have areas situated outside the insulating substrate, wherein at least a part of the areas is covered with the second insulating layer, and wherein a roughness a surface of the pad covered with the second insulating layer is larger than a roughness of a surface of the pad not covered with the second insulating layer.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/528 - Layout of the interconnection structure
36.
OPTICAL WAVEGUIDE DEVICE AND SUBSTRATE WITH OPTICAL WAVEGUIDES
An optical waveguide device includes a first and a second silicon photonics chip, an optical waveguide, and an encapsulation resin. The optical waveguide includes a core layer and a first and a second cladding layer. The core layer has a first and a second end portion optically coupled with a first and a second silicon waveguide, respectively, on surfaces of the first and the second silicon photonics chip. The first cladding layer covers a surface of the core layer between the first and the second end portion, and is thinner than the first and the second silicon photonics chip. The second cladding layer is stacked on the first cladding layer and covers the surfaces of the first and the second silicon photonics chip and the core layer. The encapsulation resin is stacked on the first cladding layer and covers the first and the second silicon photonics chip.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
A semiconductor device includes a wiring substrate, a semiconductor element mounted on the wiring substrate, and a heat dissipation plate arranged above the semiconductor element. The semiconductor device further includes an encapsulation resin that encapsulates the semiconductor element and fills a gap between the wiring substrate and the heat dissipation plate. The heat dissipation plate includes a main body that overlaps the semiconductor element in plan view, and a lead that projects outward from the main body. The lead is thinner than the main body. The encapsulation resin includes an upper surface located downward from an upper surface of the main body. The encapsulation resin covers an upper surface of the lead and part of a side surface of the main body. The encapsulation resin exposes an entirety of the upper surface of the main body and an upper portion of the side surface of the main body.
A wiring board has a first interconnect structure including a first interconnect layer, a first insulating layer, and an electronic component embedded in the first insulating layer, and a second interconnect structure including a second interconnect layer and a second insulating layer, and laminated on one side of the first interconnect structure. The second interconnect layer has an interconnect density higher than an interconnect density of the first interconnect layer. The first interconnect layer includes a pad having a portion exposed from the first insulating layer. In a plan view, the first insulating layer includes a first region in which the pad is disposed, and a second region located on an outer periphery of the first region. The electronic component is disposed in the second region, and is electrically connected to the second interconnect layer.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
A semiconductor device includes a semiconductor element, a first organic substrate covering an edge of an electrode pad of the semiconductor element, a first wiring layer arranged on an upper surface of the first organic substrate, and a conductive layer formed on a lower surface of the semiconductor element. The semiconductor device further includes a second organic substrate covering an edge of the conductive layer, and an encapsulation resin encapsulating the semiconductor element between the first and second organic substrates. The conductive layer includes an electrode pad. The first organic substrate includes a first substrate body and a first adhesive layer formed on the first substrate body and adhered to the upper surface of the semiconductor element. The second organic substrate includes a second substrate body and a second adhesive layer formed on the second substrate body and adhered to a lower surface of the conductive layer.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
An interconnect substrate includes n insulating layers (n≥2), two opposing conductors arranged across the n insulating layers, and first and second post-walls each connecting the two a conductors, wherein post-wall waveguide is constituted at least by the two conductors and the first and second post-walls, which define a zone serving as a transmission path, wherein each of the first and second post-walls includes columnar portions each made by stacking pads and via interconnects penetrating the insulating layers, each pad being positioned between two vertically adjacent via interconnects, the columnar portions being arranged at a predetermined interval along a first direction for transmitting electromagnetic waves, and wherein in each of the first and second post-walls, the pads include two or more connecting pads, each being arranged in contact with an m-th insulating layer (1≤m≤n−1) and connecting two or more via interconnects arrayed along the first direction in the m-th insulating layer.
An optical waveguide device has a first optical waveguide, a second optical waveguide, and an adhesive layer. The first optical waveguide has: a first cladding; and a first core having a distal end portion exposed from the first cladding. The second optical waveguide has: a second cladding; and a second core having a distal end portion exposed from the second cladding. The adhesive layer adheres the first optical waveguide and the second optical waveguide in a state where the distal end portions of the first core and of the second core have been arranged to partially overlap each other. The adhesive layer covers lateral surfaces of the distal end portions of the first core and of the second core and has a refractive index closer to refractive indexes of the first cladding and the second cladding than to refractive indexes of the first core and the second core.
An electrostatic chuck includes a base body having a first surface and a second surface opposite to the first surface, a plurality of first electrodes and a plurality of second electrodes embedded in the base body, and a plurality of third electrodes exposed from the first surface and provided between the first electrodes and the second electrodes adjacent to each other in the base body. A plurality of protrusions are formed on the first surface. The third electrodes are provided at positions offset from the protrusions in a plan view perpendicular to the first surface.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
An electronic component-incorporating substrate includes a first substrate, a second substrate arranged above the first substrate, a spacer member electrically connecting the first substrate and the second substrate, an electronic component mounted on the first substrate and disposed between the first substrate and the second substrate, a heat dissipation plate disposed between the first substrate and the second substrate, and an encapsulation resin filling a gap between the first substrate and the second substrate and encapsulating the electronic component. The encapsulation resin includes a first outer side surface. At least both of an upper surface and a lower surface of the heat dissipation plate are embedded in the encapsulation resin. The heat dissipation plate does not overlap the spacer member in plan view. The heat dissipation plate includes a second outer side surface exposed from the first outer side surface of the encapsulation resin.
H01L 23/433 - Auxiliary members characterised by their shape, e.g. pistons
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/16 - Fillings or auxiliary members in containers, e.g. centering rings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
An optical waveguide device includes a substrate and an optical waveguide on a surface of the substrate. The optical waveguide includes a first core layer, a second core layer, and a cladding layer covering the first core layer and the second core layer. The first core layer includes a first part at a first height from the surface of the substrate and a second part at a second height from the surface of the substrate. The second height is smaller than the first height. The second core layer is spaced apart from the first core layer and crosses the first core layer in a plan view.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
An electronic component-incorporating substrate includes a first substrate, a second substrate, a spacer member, an electronic component, and an encapsulation resin. The first substrate includes a first connection pad. The second substrate includes a second connection pad that faces the first connection pad. The spacer member electrically connects the first connection pad and the second connection pad. The electronic component is mounted on the first substrate and is disposed between the first substrate and the second substrate. The encapsulation resin fills a gap between the first substrate and the second substrate and encapsulates the electronic component. The spacer member includes a spherical solder core ball and a solder layer that covers a circumference of the solder core ball. A melting point of the solder layer is lower than a melting point of the solder core ball.
An optical waveguide device includes a silicon photonic chip having a main surface and including a silicon waveguide and an electrode, the silicon waveguide and the electrode being disposed on a same side of the silicon photonic chip as the main surface, and an optical waveguide laminated on the main surface of the silicon photonic chip, wherein the optical waveguide includes a core layer optically coupled to the silicon waveguide, a cladding layer having a first surface and a second surface opposite the first surface, the first surface being in contact with the main surface, the cladding layer covering at least a portion of the core layer, and a through interconnect penetrating the cladding layer and having one end surface connected to the electrode and another end surface exposed at the second surface.
An interconnect substrate includes a first interconnect layer, an insulating layer formed on the interconnect layer and containing a filler, a via hole penetrating the insulating layer and reaching an upper surface of the first interconnect layer, and a second interconnect layer filling the via hole and electrically connected to the first interconnect layer, wherein the insulating layer includes a first layer covering the first interconnect layer and a second layer laminated on, and thinner than, the first layer, an amount of the filler in the second layer being smaller than in the first layer, an inner surface of the via hole being inclined relative to a direction perpendicular to the upper surface, an angle of the inner surface of the via hole in the first layer with respect to the upper surface being larger than an angle of the inner surface of the via hole in the second layer.
A wiring board includes a layered structure and a waveguide. The layered structure include multiple insulating layers that are laminated. The waveguide is formed inside the layered structure. The waveguide includes a pair of conductive layers, and multiple conductive pillars. The pair of the conductive layers face each other in a lamination direction of the insulating layers. The multiple conductive pillars are arranged in two rows along a propagation direction of electromagnetic waves between the pair of the conductive layers, and connects the pair of the conductive layers. The respective conductive pillars include multiple connection pads and a via. The connection pads are laminated between the pair of the conductive layers. The via connects the connection pads of adjacent layers, and has a cross-section perpendicular to the lamination direction in a rectangular shape.
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits
A lead frame has inner leads arranged in a first direction, and each inner lead includes a first main surface parallel to the first direction, an end surface connecting to the first main surface, a first side surface connecting to the first main surface and to the end surface, and a second side surface connected to the first main surface and to the first side surface. In a plan view perpendicular to the first main surface, an angle between a first imaginary straight line including a first line of intersection between the first main surface and the end surface, and a second imaginary straight line including a second line of intersection between the first main surface and the second side surface, is less than 90 degrees on a side of each inner lead.
A wiring board includes a first interconnect structure including a first interconnect layer and a first insulating layer, a second interconnect structure, including a second interconnect layer and a second insulating layer, and laminated on one side of the first interconnect structure, and a third interconnect structure, including a third interconnect layer and a third insulating layer, and laminated on the other side of the first interconnect structure. The second interconnect layer has an interconnect density higher than those of the first and the third interconnect layers. The first insulating layer has a through hole penetrating the first insulating layer, and an electronic component electrically connected to the second interconnect layer is disposed inside the through hole. An embedding resin covering the electronic component is provided inside the through hole, and extends to cover the first insulating layer and fills in between the first and second insulating layers.
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
A substrate fixing device includes a ceramic base plate, a ceramic electrostatic chuck having a mounting surface on which a target object to be adsorbed is mounted, and an adhesion layer bonding the base plate and the electrostatic chuck.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
53.
INTERCONNECT SUBSTRATE AND METHOD OF MAKING INTERCONNECT SUBSTRATE
An interconnect substrate includes a first interconnect layer having a surface, the surface including a first region and a second region, an adhesion enhancing film covering the second region, an insulating layer formed on the adhesion enhancing film, a via hole formed through the insulating layer and the adhesion enhancing film to reach the first region, and a second interconnect layer formed on the insulating layer and in contact with the first region through the via hole, wherein a roughness of the first region is higher than a roughness of the second region.
A wiring board includes a core board, a first interconnect structure, a second interconnect structure, and a through-hole. The core board includes an interconnect layer that is formed on an upper surface and a lower surface of a substrate. The first interconnect structure includes an interconnect layer and an insulating layer that are layered on the core board. The second interconnect structure includes an interconnect layer and an insulating layer that are layered on the core board. The through-hole penetrates the insulating layer of the second interconnect structure and the substrate of the core board to a pad that is contained in the interconnect layer of the core board or penetrates the insulating layer of the second interconnect structure, the substrate of the core board, and the insulating layer of the first interconnect structure to a pad that is contained in the interconnect layer of the first interconnect structure.
An optical waveguide device includes a substrate, a first waveguide disposed on or in the substrate, and a second waveguide disposed on a first surface of the substrate, wherein the second waveguide includes a core and a cladding covering the core, wherein throughout an entirety of a predetermined region, a portion of the core overlaps the first waveguide when viewed from a direction normal to the first surface, in wherein the predetermined region, the core has a bottom surface in contact with the first surface and a convex surface connected to the bottom surface, and wherein the core includes a portion whose thickness gradually decreases from a widthwise center to widthwise ends in a transverse cross-sectional view.
A semiconductor device includes a first substrate, a second substrate spaced apart from the first substrate, a first semiconductor element mounted on an upper surface of the first substrate and an upper surface of the second substrate so as to extend across the first substrate and the second substrate, a second semiconductor element mounted on the upper surface of the second substrate, and a third semiconductor element mounted on a lower surface of the second substrate. The third semiconductor element overlaps the second semiconductor element in plan view.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
A semiconductor device includes a semiconductor element provided on a wiring board including a first signal pad, and a pair of first ground pads spaced apart from the first signal pad, arranged so as to sandwich the first signal pad and oppose each other in a plan view. The semiconductor element includes a second signal pad, and a pair of second ground pads spaced apart from the second signal pad and sandwiching the second signal pad and oppose each other. The second signal pad includes a first bump electrically connected to the first signal pad through a first bonding part. The pair of second ground pads includes second and third bumps. The third bump is closer to the second signal pad than the second bump, and at least the second bump is electrically connected to each of the pair of first ground pads through a second bonding part.
A stacked wiring substrate includes a first wiring substrate and a second wiring substrate mounted on the first wiring substrate. The first wiring substrate includes a first wiring layer, a first insulating layer covering the first wiring layer, a second wiring layer stacked on an upper surface of the first insulating layer and electrically connected to the first wiring layer, a second insulating layer stacked on the upper surface of the first insulating layer and covering the second wiring layer, and a first electrode pad stacked on an upper surface of the second insulating layer and electrically connected to the second wiring layer. The second wiring substrate includes a wiring structure having a higher wiring density than the first wiring substrate, and a second electrode pad connected to the first electrode pad. The second insulating layer is thinner than the first insulating layer.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A wiring board includes a first wiring structure and a second wiring structure. The first wiring structure includes: a mounting surface for a semiconductor element; and a back surface on an opposite side of the mounting surface. The second wiring structure is formed on the back surface of the first wiring structure. The first wiring structure further includes thin film layers, a cavity, an electronic component, and a filling resin layer. The thin film layers include laminated wiring layers and laminated insulating layers. The cavity is formed by cutting out at least one of the insulating layers of the thin film layers in a direction toward the mounting surface. The electronic component is located in the cavity. The filling resin layer fills the cavity, and further covers the electronic component.
A wiring board includes a first insulating layer, a first interconnect layer formed on the first insulating layer, a second insulating layer formed on the first interconnect layer, an opening penetrating the second insulating layer and exposing an upper surface of the first interconnect layer, and a second interconnect layer that is an outermost interconnect layer disposed inside the opening and electrically connected to the first interconnect layer.
A heat storage device includes a ceramic part having a closed space therein, a latent heat storage provided inside the closed space, an electric heater provided inside the ceramic part and configured to heat the latent heat storage, a heat insulating member covering the ceramic part, and a power supply part configured to supply electric power to the electric heater.
A wiring board includes a first wiring structure and a second wiring structure. The first wiring structure includes a mounting surface for a semiconductor element and a back surface on an opposite side of the mounting surface. The second wiring structure is formed on the back surface of the first wiring structure. The second wiring structure includes a reinforcing insulating layer, a cavity, an electronic component, and a filled resin layer. The reinforcing insulating layer is formed on the back surface of the first wiring structure. The cavity is formed by cutting off the reinforcing insulating layer in a direction toward the back surface of the first wiring structure. The electronic component is arranged in the cavity. The filled resin layer is filled in the cavity and covers the electronic component.
A semiconductor device includes a wiring substrate and a semiconductor element. The wiring substrate includes an insulating layer and a wiring layer. The semiconductor element includes a first electrode and is fixed to the wiring substrate with the first electrode facing the wiring substrate. The wiring layer includes a first wiring pattern on a surface of the insulating layer on the opposite side from the semiconductor element. The wiring layer further includes a first via interconnect. The first via interconnect is formed of a sintering material of metal and fills in a first through hole piercing through the first wiring pattern and the insulating layer to expose the first electrode. The first via interconnect electrically connects the first wiring pattern and the first electrode.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A wiring substrate includes an insulating layer and a protruding electrode. The insulating layer has a recess formed in the upper surface of the insulating layer. The protruding electrode is partly buried in the insulating layer to protrude in the recess. The width of the protruding electrode is constant in a sectional view of the protruding electrode. The upper surface of the protruding electrode is positioned lower than the upper surface of the insulating layer.
A semiconductor apparatus includes three or more semiconductor devices connected in parallel with each other and an interconnect substrate arranged on the semiconductor devices, wherein the semiconductor devices have respective control electrodes and are switched by a voltage applied to the control electrodes, wherein the interconnect substrate includes an insulating layer and a first interconnect pattern arranged on an opposite side of the insulating layer from the semiconductor devices and connecting the control electrodes of the semiconductor devices, wherein the first interconnect pattern includes a same number of interconnects of equal length as the semiconductor devices, and a voltage input point configured to receive a voltage applied to the control electrodes via the interconnects of equal length, and wherein the control electrodes of the semiconductor devices are connected to the voltage input point only by the interconnects of equal length, which extend in different directions from the voltage input point.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
A wiring substrate includes a first wiring layer, a first insulating layer, and a second wiring layer. The first insulating layer covers the first wiring layer. The second wiring layer is formed on an upper surface of the first insulating layer and is electrically connected to the first wiring layer. The upper surface of the first insulating layer includes a first roughened surface, and a second roughened surface having a greater roughness than the first roughened surface. The second roughened surface includes a wrinkle pattern resulting from buckling. A volume percent of the first wiring layer located in a first region that overlaps the first roughened surface in plan view is greater than a volume percent of the first wiring layer located in a second region that overlaps the second roughened surface in plan view.
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
67.
LEAD FRAME, SEMICONDUCTOR DEVICE, AND LEAD FRAME MANUFACTURING METHOD
A lead frame includes a lead, a connection portion, and a plating film. The lead includes an upper surface and a lower surface, and a width of the upper surface is larger than a width of the lower surface. The connection portion is arranged on the upper surface and serves as a connection portion for a semiconductor element. The plating film covers a surface of the lead.
A wiring board includes an insulating layer and a connection terminal that is formed on a surface of the insulating layer. The connection terminal includes a metal pad that is embedded in the insulating layer and a plated layer that covers an end face of the pad that is exposed on the surface of the insulating layer. The end face of the pad is depressed in a concave surface form to a position lower than the surface of the insulating layer and a surface of the plated layer on a side opposite to a surface making contact with the end face of the pad is depressed in the concave surface form toward the end face.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
A latent heat storage unit includes a ceramic part made of a polycrystalline body and having a closed space formed therein and a metal part provided in the closed space and containing boron, wherein a melting point of the metal part is 1100° C. or higher.
A latent heat storage unit includes a ceramic part made of a polycrystalline body and having a closed space formed therein and a metal part provided in the closed space and containing 50% or more silicon by mass.
A wiring substrate includes a first wiring layer, a first insulating layer covering the first wiring layer, a second wiring layer formed on the first insulating layer and connected to the first wiring layer, a second insulating layer formed on the first insulating layer, and a third wiring layer formed on the second insulating layer and connected to the second wiring layer. The second wiring layer includes a first connection pad connectable to a first electronic component, and a wiring pattern connected to the third wiring layer. The second insulating layer includes an open portion extending through the second insulating layer in a thickness-wise direction and exposing the first connection pad and part of the first insulating layer. The third wiring layer includes a second connection pad connectable to a second electronic component. The first wiring layer includes wiring that electrically connects the first and second connection pads.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
An electrostatic chuck includes a first base body, a first adhesive layer, a second base body stacked on the first base body with the first adhesive layer interposed therebetween, and an electrostatic electrode embedded in the second base body. The first base body is made of aluminum oxide ceramics. The second base body is made of aluminum oxide ceramics with a higher purity of aluminum oxide than that of the first base body.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
A substrate fixing device includes a base plate, an adhesive layer provided on the base plate, a heat insulating layer provided on the adhesive layer, and an electrostatic chuck provided on the heat insulating layer. The electrostatic chuck includes a base and an electrostatic electrode provided in the base, and the heat insulating layer has a lower thermal conductivity than the base and the adhesive layer.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
An optical module includes a first cladding layer formed on a substrate, a first groove extending through the first cladding layer in a thickness direction, and a second cladding layer formed on the first cladding layer. The optical module further includes a second groove extending through the first cladding layer and the second cladding layer in the thickness direction, a silicon photonics component mounted on the first cladding layer, and a single-mode fiber fitted into the second groove. The silicon photonics component includes a main body and an optical axis located below the main body. The lower surface of the main body is in contact with the upper surface of the first cladding layer. The optical axis is retained within the first groove. A circumferential surface of the single-mode fiber is in contact with a bottom surface of the second groove and a wall surface of the second groove.
A leadframe includes a die pad having a surface that includes a region for mounting a semiconductor chip, and a flat film and a roughened film on the surface of the die pad. In a plan view, the flat film is along and outside the outer edge of the region and the roughened film is inside and outside the flat film. The roughened film includes a roughened plating film and a plating film on the roughened plating film. The plating film follows the shape of the roughened plating film to have a roughened surface. The flat film has a flatter surface than the roughened film, and includes a first metal film formed of the same material as the roughened plating film and a second metal film on the first metal film. The second metal film is an alloy film including metals of the roughened plating film and the plating film.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A terminal structure includes a first wiring layer, an insulation layer covering the first wiring layer, an opening extending through the insulation layer, via wiring formed in the opening, a second wiring layer electrically connected to the via wiring on the insulation layer, a protective metal layer formed on the second wiring layer, a solder layer formed on the protective metal layer, and an intermetallic compound layer formed between the protective metal layer and the solder layer. The protective metal layer includes a projection projecting further outward from a side surface of the second wiring layer. The intermetallic compound layer covers only the upper surface of the protective metal layer. The solder layer covers only an upper surface of the intermetallic compound layer and exposes the side surfaces of the intermetallic compound layer, the protective metal layer, and the second wiring layer.
A wiring board includes a first insulating layer provided on an interconnect layer, a second insulating layer provided on the first insulating layer, a first opening formed in the first insulating layer and reaching the interconnect layer, a second opening formed in the second insulating layer and having a lower end connected to an upper end of the first opening, a third opening formed in the second insulating layer and having a lower end connected to an upper end of the second opening, and a connection terminal formed inside the first, second, and the third openings, and making contact with an upper surface of the interconnect layer. The lower end diameter of the second opening is equal to the upper end diameter of the first opening, and the lower end diameter of the third opening is larger than the upper end diameter of the second opening.
A wiring substrate includes a metallic plate, a first through-hole, an insulating layer, a second through-hole, a wiring layer, and feedthrough wiring. The first through-hole is formed in the metallic plate. The insulating layer covers both surfaces of the metallic plate and an inner wall surface of the first through-hole. The second through-hole is formed on an inner side of the insulating layer in the first through-hole. The wiring layer is laminated on the insulating layer on both surface sides of the metallic plate. The feedthrough wiring is formed in the second through-hole, and connects the wiring layer disposed on both surface sides of the metallic plate. The metallic plate includes a bent portion that is bent in a bottomed box shape and that forms a space on one of the surface sides of the metallic plate.
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
79.
WIRING BOARD, SEMICONDUCTOR DEVICE, AND WIRING BOARD MANUFACTURING METHOD
A wiring board includes an insulating layer, a connection terminal, and a wiring structure. The insulating layer includes a first surface and a second surface on an opposite side of the first surface, and includes an opening portion that is formed so as to penetrate through the first surface and the second surface. The connection terminal is arranged in the opening portion. The wiring structure is connected to the connection terminal. The connection terminal includes a pad that is formed in the opening portion and that has a bottom surface located on a same plane as the second surface of the insulating layer, and a surface treatment layer that covers the pad. The pad protrudes from the first surface of the insulating layer, and the surface treatment layer forms a gap between the surface treatment layer and an inner wall surface of the opening portion.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
An optical waveguide device includes a first cladding layer, a core layer disposed on the first cladding layer and forming cores, and a second cladding layer disposed on the first cladding layer and selectively covering the core layer, wherein a first region not covered by the second cladding layer is provided on the first cladding layer, wherein the cores include signal cores, one end of which is disposed in the first region, for inputting or outputting signal light, and an inspection core, both ends of which are exposed at an outer perimeter surface of the optical waveguide device, for inputting or outputting inspection light, and wherein the inspection core is made of a same material as the signal cores, and a cross-sectional shape of the inspection core in a short-hand direction is identical to a cross-sectional shape of each of the signal cores in a short-hand direction.
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
81.
CERAMIC SUBSTRATE, METHOD OF MANUFACTURING THE SAME, ELECTROSTATIC CHUCK, SUBSTRATE FIXING DEVICE, AND SEMICONDUCTOR DEVICE PACKAGE
A ceramic substrate includes a base, and a conductor pattern incorporated in the base. The base is a ceramic, and the conductor pattern includes, as a main component, a solid solution of a body-centered cubic lattice structure in which nickel and manganese are solid solved in tungsten, a solid solution of a body-centered cubic lattice structure in which nickel and niobium are solid solved in tungsten, or a solid solution of a body-centered cubic lattice structure in which nickel and indium are solid solved in tungsten.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
C04B 35/10 - Shaped ceramic products characterised by their compositionCeramic compositionsProcessing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxides based on aluminium oxide
C04B 41/00 - After-treatment of mortars, concrete, artificial stone or ceramicsTreatment of natural stone
An optical waveguide device includes an interconnect substrate, a first cladding layer disposed on the interconnect substrate, a core layer disposed on the first cladding layer, a second cladding layer disposed on the first cladding layer and selectively covering the core layer, and one or more elevated supports disposed on the first cladding layer and apart from the core layer, wherein one longitudinal-direction end of the core layer and the elevated supports are situated in a component mounting region exposed from the second cladding layer, and wherein the elevated supports are made of a same material as the core layer and have a same thickness as the core layer.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/42 - Coupling light guides with opto-electronic elements
An optical waveguide device includes an optical waveguide substrate, and an optical semiconductor element including a silicon waveguide and mounted on the optical waveguide substrate. The optical waveguide substrate includes a substrate, a first cladding layer formed on the substrate, a first core layer formed on the first cladding layer, and a second cladding layer formed on the first cladding layer and the first core layer. The silicon waveguide includes a second core layer optically coupled to the first core layer, and the optical semiconductor element is fixed to the substrate by the second cladding layer.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
84.
OPTICAL WAVEGUIDE DEVICE AND METHOD OF MAKING THE SAME
An optical waveguide device includes an optical waveguide substrate including a first cladding layer disposed on a support, a core layer disposed on the first cladding layer, and a second cladding layer selectively covering the core layer, and a silicon photonic chip including a silicon substrate and a silicon waveguide disposed on one side of the silicon substrate, wherein part or all of a thickness of one end of the silicon waveguide is embedded in the core layer exposed from the second cladding layer, wherein a thickness of the core layer in a place covered with the silicon substrate is less than that of the core layer in a place not covered with the silicon substrate, and wherein a width of the core layer at a point of contact with the silicon substrate is wider than that of the core layer in a place covered with the second cladding layer.
G02B 6/036 - Optical fibres with cladding core or cladding comprising multiple layers
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
85.
OPTICAL WAVEGUIDE MOUNTED SUBSTRATE AND METHOD OF MAKING THE SAME
An optical waveguide mounted substrate includes an interconnect substrate having a recess that opens on a first surface thereof, and an optical waveguide device including: an optical waveguide substrate including a support and a core layer disposed on the support; and a silicon photonic chip including a silicon substrate and a silicon waveguide disposed on the silicon substrate, the silicon waveguide being optically coupled with the core layer, wherein the optical waveguide substrate is mounted on the interconnect substrate such that the core layer faces away from the recess and at least a part of a thickness of the support is situated inside the recess.
A lead frame includes a die pad having an upper surface and a lower surface, and a curved part disposed outside the die pad in a bottom view, and having one end connected to an outer edge of the die pad. The curved part has a groove that opens toward the lower surface of the die pad, and the curved part is curved toward the upper surface of the die pad at the groove.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
A wiring board has a built-in post wall waveguide having a region surrounded by two mutually opposing conductors and first and second post walls connecting the two conductors and serving as a transmission path for electromagnetic waves. The conductors oppose each other with insulating layers interposed therebetween. The first post wall has first columnar portions, formed by a laminate of via interconnects penetrating the insulating layers, arranged at predetermined intervals in a first direction in which the electromagnetic waves are transmitted. The second post wall has second columnar portions similar to the first columnar portions. In a cross sectional view taken in a second direction perpendicular to the first direction, an interval between adjacent via interconnects in one of the insulating layers not in contact with the conductor is wider than an interval between adjacent via interconnects in two of the insulating layers in contact with the two conductors, respectively.
A semiconductor device includes a wiring substrate, a semiconductor chip, and a sealing resin. The semiconductor chip is mounted on the wiring substrate. The sealing resin is filled in a gap between the wiring substrate and the semiconductor chip and extends to an upper surface of the semiconductor chip. The semiconductor chip includes a groove that is formed in an outer peripheral area that is located around a circumference of a predetermined area disposed on the upper surface of the semiconductor chip and that includes a peripheral edge of the upper surface of the semiconductor chip, and that captures an extending portion of the sealing resin extends.
A wiring substrate includes a first wiring layer, an insulation layer covering a side surface of the first wiring layer and exposing part of the first wiring layer, and a second wiring layer formed on the first wiring layer exposed from the insulation layer. The insulation layer includes a resin and a filler. The insulation layer includes an upper surface having a structure in which the filler is exposed from the resin. The second wiring layer includes a first metal film, covering the upper surface of the insulation layer and the wiring layer exposed from the insulation layer, and a metal layer, formed above the first metal film. The first metal film is formed from a CuNiTi alloy and has a Ni content rate of 5 wt % or greater and 30 wt % or less and a Ti content rate of 5 wt % or greater and 15 wt % or less.
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
90.
OPTICAL WAVEGUIDE DEVICE AND MANUFACTURING METHOD THEREOF
An optical waveguide device includes a substrate, a first cladding layer disposed on the substrate, a core layer disposed on the first cladding layer, and a recess formed in the core layer along a longitudinal direction of the core layer and opened on a first surface of the core layer facing away from the first cladding layer.
A semiconductor device includes a wiring substrate, a semiconductor chip including conductive pillars, and a conductive bonding material. The wiring substrate includes electrode pads and via lands electrically connected to each other at a surface of the wiring substrate. A through hole and a cut continuous with the through hole are formed in each electrode pad. In a plan view perpendicular to the surface, the cut of a first electrode pad extends toward a space between a second electrode pad and a third electrode pad adjacent to each other and adjacent to the first electrode pad, a first via land and a second via land adjacent to each other and adjacent to the first electrode pad, or a fourth electrode pad and a third via land adjacent to each other and adjacent to the first electrode pad. The conductive bonding material bonds the electrode pads and the conductive pillars.
A semiconductor device includes a wiring substrate, a semiconductor element mounted on the wiring substrate, a heat dissipating plate arranged above the semiconductor element, and an encapsulation resin that encapsulates the semiconductor element and fills a space between the wiring substrate and the heat dissipating plate and a space between the semiconductor element and the heat dissipating plate. The heat dissipating plate includes a main body arranged overlapping the semiconductor element in plan view, and a lead projecting outward from the main body. The lead is thinner than the main body. The lead includes an upper surface covered by the encapsulation resin, and an outer side surface located at an outer edge of the semiconductor device and exposed from an outer side surface of the encapsulation resin. The main body includes an upper surface exposed from an outer surface of the encapsulation resin.
H01L 23/433 - Auxiliary members characterised by their shape, e.g. pistons
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/367 - Cooling facilitated by shape of device
A substrate fixing device includes a base plate, a heating portion provided on the base plate, a metal layer provided on the heating portion, and an electrostatic chuck provided on the metal layer. In the substrate fixing device, the metal layer is made of the same material as the base plate.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
94.
WAVEGUIDE SUBSTRATE AND METHOD OF MAKING WAVEGUIDE SUBSTRATE
A waveguide substrate includes a core substrate through which first through holes and second through holes are formed, a first conductive layer covering an inner wall of the first through holes and both sides of the core substrate, a second conductive layer covering an inner wall of the second through holes and both sides of the core substrate, a first filler material filling a space surrounded by the first conductive layer inside the first through holes, a second filler material filling a space surrounded by the second conductive layer inside the second through holes, and third conductive layers disposed on respective sides of the core substrate, the third conductive layers overlapping the first and second through holes in a plan view, and the third conductive layers being electrically connected to the first and second conductive layers, wherein the second conductive layer overlaps the first through holes in the plan view.
A wiring substrate includes: a wiring layer; an insulating layer that is laminated on the wiring layer; an opening portion that passes through the insulating layer to the wiring layer; and an electric conductor film that is formed at the opening portion of the insulating layer. A surface of the insulating layer includes a smoothed portion that is not covered by the electric conductor film, and a roughened portion that includes an inner wall surface of the opening portion covered by the electric conductor film and that have surface roughness that is greater than surface roughness of the smoothed portion.
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
A wiring board includes a wiring layer, an insulating layer, an oxide thin film, a seed layer, and a conductive layer. The insulating layer is laminated on the wiring layer and includes an opening portion that penetrates until the wiring layer. The oxide thin film is formed on a surface of the insulating layer including an inner wall surface of the opening portion. The seed layer is made of metal and that is laminated on the oxide thin film at a position of the opening portion. The conductive layer is formed on the seed layer. The oxide thin film is a thin film that has a thickness of 1 to 100 angstroms and covers a surface of the insulating layer including the inner wall surface of the opening portion and a surface of the wiring layer exposed from a bottom portion of the opening portion.
H05K 3/14 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material
A wiring board includes an insulating layer covering upper and side surfaces of a first interconnect layer, a via hole penetrating the insulating layer and reaching the first interconnect layer, a second interconnect layer filling the via hole and extending on the insulating layer, and a cavity provided in the first interconnect layer, communicating with the via hole and extending outside than a lower end of an inner side surface of the via hole in a plan view. The second interconnect layer includes a first seed layer provided on the insulating layer, a second seed layer continuously covering upper and inner side surfaces of the first seed layer, the inner side surface of the via hole, and surfaces of the insulating layer and the first interconnect layer exposed inside the cavity, and an electrolytic plating layer provided on the second seed layer thicker than the first seed layer.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
A wiring board includes an insulating layer, first and second pads provided on the insulating layer and including a first surface in contact with the insulating layer, a second surface opposite to the first surface, and a side surface connecting the first and second surfaces, respectively, and a protective insulating layer provided above the insulating layer. The first and second pads have a portion exposed inside an opening in the protective insulating layer. The first pad has a portion opposing the second pad without the protective insulating layer interposed between the first and second pads. A region of the second surface of the first and second pads exposed from the protective insulating layer is covered with a plating layer. A region of the side surface of the first and second pads exposed from the protective insulating layer is exposed from the plating layer.
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
An evaporator includes a first metal layer having a first inner surface and a first outer surface, a second metal layer having a second inner surface bonded to the first inner surface and a second outer surface, and a porous body provided between the first outer surface and the second outer surface. The porous body includes first bottomed holes provided in the first inner surface, second bottomed holes provided in the second inner surface, a fine pore, a first groove portion provided in the first inner surface, and a second groove portion provided in the second inner surface. The first groove portion and the second groove portion are provided not to overlap each other in a plan view. The first outer surface and the second outer surface serve as an outer surface of the evaporator.
F28D 15/02 - Heat-exchange apparatus with the intermediate heat-transfer medium in closed tubes passing into or through the conduit walls in which the medium condenses and evaporates, e.g. heat-pipes
F28D 15/04 - Heat-exchange apparatus with the intermediate heat-transfer medium in closed tubes passing into or through the conduit walls in which the medium condenses and evaporates, e.g. heat-pipes with tubes having a capillary structure
A substrate fixing device includes a base plate having a first surface in which a plurality of first bottomed holes are formed, an electrostatic chuck mounted on the first surface of the base plate and having a second surface facing the first surface, the second surface being formed therein with a plurality of second bottomed holes each connected to each of the first bottomed holes, and a plurality of fixing members each fit into one first bottomed hole and one second bottomed hole.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
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