A system and method for allocating instructions and data in a common memory device that uses aliased addresses is disclosed. The linker uses a linker script that tracks the amount of space that is allocated in the common memory device. It then uses this information to properly adjust the starting addresses for the different address ranges to ensure that no information is overwritten or corrupted. This technique allows instructions to be disposed in the same memory device as other data, but be accessed using an aliased address. This is particularly beneficial for processing units that utilize different busses for instructions and data.
In one example, a method includes: receiving, in a second wireless device of a mesh network, a first message directed to a first wireless device of the mesh network, where the second wireless device is designated as a mailbox device for the first wireless device; determining whether the first wireless device is available; and in response to determining that the first wireless device is not available, storing the first message in a first queue of the second wireless device, the first queue associated with the first wireless device.
In one embodiment , a gateway includes: a host main processing unit (MPU), the host MPU having at least one core and at least one first transceiver to communicate with one or more first wireless devices in a wireless local area network (WLAN) according to a Wi-Fi protocol; and an Internet of Things (IoT) end device coupled to the host MPU via a wired interface, the IoT end device having at least one second transceiver to communicate with one or more second wireless devices in a mesh network according to at least one mesh protocol. The IoT end device is configured to cause the host MPU to exit a sleep mode in response to a trigger event from at least one of the one or more second wireless devices.
H04L 67/12 - Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
In one embodiment, a method includes: receiving, in a level shifter, an input signal from a first voltage domain that operates according to a first supply voltage; level shifting the input signal to at least one level-shifted signal having a second voltage greater than the first supply voltage; based on the at least one level-shifted signal, generating a first pulse signal and a second pulse signal; latching the first pulse signal through a latch circuit to form an output signal; and outputting the output signal to a second voltage domain, the second voltage domain to operate according to a second supply voltage greater than the first supply voltage.
A technique for reducing effects of variations in process, voltage, and temperature (PVT) on the performance of a fractional-N frequency synthesizer includes making loop parameters, e.g., damping factor ζ and loop bandwidth ωN, first-order independent of PVT variations. In an embodiment of a fractional-N frequency synthesizer, a voltage-controlled oscillator is implemented using a ring-oscillator realized by an odd number of inverter stages. By making the loop parameters a multiple of frequency fREF and a ratio of components (e.g., C1/Cst, where capacitance Cst represents the load of each stage of the ring oscillator) and self-biasing the phase-locked loop, the technique makes the ratio of loop bandwidth ωn to the operating frequency fCLKOUT constant in response to PVT variations.
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/107 - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
A down-sampling function folds the thermal noise into a lower frequency band. A capacitor samples a voltage during a period of bus inactivity and supplies the sampled voltage to an input of operational amplifier in a loop filter of a phase-locked loop when the bus is active. The sampling frequency determines the reduction in thermal noise that can be achieved. The PLL generates a clock signal for a bus. A voltage generator charges the capacitor through a transistor when the bus is inactive. The transistor turns on responsive to the bus being inactive to allow the capacitor to charge and the transistor turns off responsive to the bus being active to isolate the capacitor and operational amplifier from the voltage generator. When the bus is active, the voltage across the capacitor is supplied to the operational amplifier.
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
7.
CHARGE INJECTION REDUCTION IN A FRACTIONAL-N FREQUENCY SYNTHESIZER
A technique for reducing the effects of charge injection when a charge pump in a fractional-N frequency synthesizer switches from an error cancellation phase of error current generation to a full-scale phase of error current generation uses a dummy digital-to-analog converter to steer excess current from the error cancellation phase to a voltage regulated node. As a result, the voltage swing of an inactive branch of a digital-to-analog converter of the charge pump is the same as the voltage swing of the active branch of the charge pump, i.e., the device overlap capacitance charge injection is in phase for the branches of a digital-to-analog converter in the charge pump.
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
In one embodiment, a method includes: determining, for each of a plurality of first channels of a wireless link between an initiator device and a reflector device, a channel response metric; providing, for each of a plurality of second channels comprising advertisement channels, a predetermined value for a channel response metric; calculating a group delay for each of the plurality of first channels and each of the plurality of second channels based on the channel response metric for the corresponding channel and the channel response metric for a neighboring channel; determining a group delay metric based on the group delay for the plurality of first channels and the plurality of second channels; and calculating, for each of the plurality of second channels, a channel response metric based on the channel response metric for the neighboring channel and the group delay metric.
A system and method of reducing the power consumption of a connected Bluetooth LE peripheral device is disclosed. Rather than responding to every packet transmitted from the central device, the peripheral device judiciously responds, sending a response in those situations where a response is required by the central device. In this way, the peripheral device is able to conserve battery life by not responding to most of the empty packets that are transmitted by the central device. The peripheral device also includes mechanisms to ensure that the connection is not terminated by the central device due to a lack of response from the peripheral device.
In one embodiment, an apparatus includes: a complementary metal oxide semiconductor (CMOS) up-conversion passive mixer to receive and up-convert a baseband signal to a radio frequency (RF) signal; and Class-AB amplifier circuitry coupled to the CMOS up-conversion passive mixer to receive and amplify the RF signal.
A ring oscillator has a first group of inverters that receive respective frequency control signals to control delays through the inverters. The frequency of the ring oscillator is dithered according to least significant bits of a frequency control word supplied by a loop filter of a phase-locked loop. Most significant bits of the frequency control word are used to generate the frequency control signals. An accumulator is clocked by an output of the ring oscillator and accumulates the least significant bits of the frequency control word. A selector circuit selects either N most significant bits of the frequency control word or the N most significant bits of the frequency control word +1 according to the selector signal to generate the frequency control signals.
A system and method for determining the placement of software functions at link time is disclosed. The system utilizes special annotations that are included in software modules of the source code, which defines certain parameters associated with each function. These parameters may be referred to as code classification components, wherein each code classification component may include one or more code classes associated with that code classification component. These software modules are then compiled. A linker script is created based on the desired configuration. The linker then uses the linker script to determine which software modules should be placed in RAM for improved execution speed.
Modulation testing separately enables slices of an analog varactor array of an LC oscillator. For each enabled slice, a reference voltage supplying a resistor ladder is set to a plurality of different reference voltage values. Resistor ladder voltages generated for the different reference voltage values are supplied to the enabled slice and a control voltage coupled to the enabled slice is swept for each of the reference voltage values. Respective frequencies of an oscillator signal coupled to an output of the LC oscillator are measured for each enabled slice for each combination of the reference voltage values and the control voltage values. The linearity of LC oscillator gain is determined for each of the reference voltage values for each slice based on the respective frequencies and the control voltage values. Passing/failing the modulation testing is based on the linearity of the LC oscillator gain.
A lamp includes a single 1-layer metal core printed circuit board (PCB). The 1-layer metal core PCB includes a plurality of light emitting diodes (LEDs), an LED driver circuit, a microcontroller unit (MCU) providing wireless connectivity and control for the LED driver circuit, and a power supply circuit providing power for the LEDs and the MCU. The lamp includes an antenna, e.g., helical or monopole, mounted on the single 1-layer metal core PCB. Capacitor(s) and/or inductor(s) may be mounted on a bottom side of the 1-layer metal core PCB opposite a top side of the 1-layer metal core PCB on which the LEDs are mounted. The lamp is line powered. The LEDs are disposed on a periphery of a top side of the PCB and the MCU and other circuitry is disposed on the top side of the PCB inside of the periphery.
F21V 19/00 - Fastening of light sources or lamp holders
F21K 9/232 - Retrofit light sources for lighting devices with a single fitting for each light source, e.g. for substitution of incandescent lamps with bayonet or threaded fittings specially adapted for generating an essentially omnidirectional light distribution, e.g. with a glass bulb
F21K 9/238 - Arrangement or mounting of circuit elements integrated in the light source
F21V 23/00 - Arrangement of electric circuit elements in or on lighting devices
F21V 23/02 - Arrangement of electric circuit elements in or on lighting devices the elements being transformers or impedances
F21V 23/04 - Arrangement of electric circuit elements in or on lighting devices the elements being switches
F21Y 105/18 - Planar light sources comprising a two-dimensional array of point-like light-generating elements characterised by the overall shape of the two-dimensional array annularPlanar light sources comprising a two-dimensional array of point-like light-generating elements characterised by the overall shape of the two-dimensional array polygonal other than square or rectangular, e.g. for spotlights or for generating an axially symmetrical light beam
A crystal oscillator includes a current source that charges a capacitor. A charge on the capacitor is periodically injected into a crystal of the crystal oscillator. A switch couples the capacitor to the crystal and a timing circuit controls the switch to cause the charge to be injected beginning at approximately a peak of a crystal output signal. The timing circuit is configurable into a self-resonant mode for calibration of a delay through the timing circuit by coupling an output of the timing circuit to an input of the timing circuit. A comparator compares a magnitude of the crystal output signal to a reference voltage and supplies compare results to a gain control circuit. The gain control circuit adjusts the current from the current source to adjust the charge being injected into the crystal from the capacitor to thereby control the magnitude of the crystal output signal.
H03B 5/32 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
An embodiment of a timing-based signal valley detection technique improves efficiency and reduces electromagnetic emissions due to ringing by controlling the off-time of a power switch in an LED driver or power converter application. The timing-based technique estimates a time of occurrence of a valley in the drain voltage of the power switch. The timing-based technique uses an analog comparator to sense the drain voltage of a power switch. The timing-based technique uses digital circuits to estimate the time of occurrence of the valley in the drain voltage and to adjust the duty cycle (e.g., adjusts the off-time by terminating the off-time) of a gate control signal of the power switch. The technique may use off-chip resistive voltage divider circuits to sense the drain voltage of the power switch and to generate a reference voltage and other circuits are integrated in an integrated circuit device.
In one aspect, an apparatus includes: a low noise amplifier (LNA) to receive and amplify a radio frequency (RF) signal; a mixer coupled to the LNA to downconvert the RF signal to a second frequency signal; a quadrature transimpedance amplifier (TIA) to convert a current of the second frequency signal to a voltage signal, the quadrature TIA having an in-phase (I)-channel having an I-channel DC offset and a quadrature-phase (Q)-channel having a Q-channel DC offset; and a DC offset calibration circuit coupled to the quadrature TIA. The DC offset calibration circuit is configured to calibrate a DC offset of the quadrature TIA. The DC offset calibration circuit may be configured to independently determine an I-channel DC offset setting and independently determine a Q-channel DC offset setting, where the I-channel and Q-channels have a DC offset interdependency.
In one embodiment, an apparatus includes: a receiver pad to receive an incoming radio frequency (RF) signal; a first inductor coupled to the receiver pad; a second inductor coupled to the first inductor at an inter-inductor node; a first electrostatic discharge (ESD) circuit coupled to the inter-inductor node; a second ESD circuit coupled to the second inductor; a low noise amplifier (LNA) coupled to the second inductor to receive and amplify the incoming RF signal; a transmit-receive (TR) switch coupled to the LNA, where in a receive mode, the TR switch is to enable the LNA to receive the incoming RF signal; a transmit pad to output an outgoing RF signal; and a power amplifier (PA) coupled to the transmit pad, where in a transmit mode, the TR switch is to decouple the LNA.
H04B 1/48 - Transmit/receive switching in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
A noise detector for use in a wireless network device is disclosed. The wireless network device may be used to scan a plurality of different frequency channels, which may be Bluetooth or Zigbee channels, for example. The noise detector is used to quickly detect the presence of noise on a frequency channel. This quick detection allows the wireless network device to switch to another frequency channel and continue scanning. In some embodiments, the noise detector uses a detection window and counts frequency outliers in that detection window to determine whether a valid signal is present on the wireless channel. The detection window may be fixed in duration, or may grow. Additionally, the detection window may be stationary or may be a sliding window.
A system and method for allocating memory is disclosed. The memory is made up of a plurality of banks, wherein the power to each is independently controlled. Two different types of requests are disclosed. The first type is used to allocate a memory block and also includes an indication of the lifespan of the requested memory block. The lifespan is used to determine where the memory block is allocated. Additionally, all allocated memory is retained during deep sleep mode. The second type of request is used to reserve a memory block. Memory reservations differ from memory allocations in that the reservation of the memory block is independent of whether that memory is retained during deep sleep mode. Further, because the memory block may be powered off during deep sleep mode, the metadata associated with memory reservations is located in a different portion of memory than the memory blocks.
An improved layout for volatile memory is disclosed. The volatile memory comprises a plurality of banks that may be independently powered during deep sleep mode. The memory layout attempts to locate all items and data that are retained near one end of the volatile memory, such as near the starting address of the volatile memory. These items include secure RAM, instructions that have been copied from a nonvolatile memory, and metadata associated with memory reservations. Additionally, buffers that do not need to be retained during deep sleep mode are disposed on the opposite end of the volatile memory, such as near the ending address. Memory that is allocated for the user level software is categorized as “long-term” and “short-term”. Allocations of “long-term” blocks are located near the metadata for the memory reservations, while allocations of “short-term” blocks are located near the opposite end of the memory.
A network of devices includes a power-constrained device that uses two separate physical channels associated with different wireless communications protocols to communicate with a device and to communicate directly or indirectly with a controller. In an embodiment, the two separate physical channels include a dedicated high-power, high-throughput physical channel of a primary wireless communications protocol that is used to communicate with the controller in a normal mode of operation and a side channel, which is a lower power, lower throughput physical channel of a secondary wireless communications protocol to receive triggers from sensors and that may be used to directly or indirectly communicate with the controller in the normal mode of operation or in a lower power mode of operation. In an embodiment, the dedicated high-power, high-throughput physical channel is configured in a lower power state (e.g., idle or off) while a sleepy node is in a power-saving mode.
In one example, an apparatus includes: an operational amplifier (opamp) to amplify a difference between a reference voltage and a feedback voltage and output a bias signal based on the difference; a replica device coupled to the opamp, the replica device having a gate terminal to receive the bias signal; and an output stage coupled to the replica device and to output a regulated voltage, the output stage having a pass device and a plurality of feedback devices coupled to the pass device. A selected number of the plurality of feedback devices can be enabled based at least in part on an output power level of a power amplifier that is to receive the regulated voltage.
A system and method for determining the distance between two wireless network devices is disclosed. The present system utilizes an algorithm that relies on the power ratio between the trial signal power and the remaining signal power. Remaining signal power is defined as the power that is left after subtracting the trial signal power from the total signal power. This algorithm computes the channel frequency response and uses the phase signal at each frequency and distance to calculate the line of sight distance between two wireless network devices. This approach does not rely on eigenvectors or any prior estimate of the number of signals, and can therefore be computed quickly and efficiently.
In one aspect, an apparatus comprises: a low noise amplifier (LNA) to receive and amplify a receive radio frequency (RF) signal; a power amplifier (PA) to amplify a transmit RF signal and output the amplified transmit RF signal at an output node of the PA; a blocking capacitor coupled to the output node of the PA; an input/output (I/O) pad coupled to the output node, the I/O pad to interface with an antenna; and a pad attenuator coupled to the output node of the PA, the pad attenuator to attenuate the receive RF signal in a receive mode and minimize a load on the PA in a transmit mode.
In one aspect, an apparatus includes: a delay line to receive a clock signal and a plurality of settings, each of the settings to indicate a selected tap of the delay line at which to output the clock signal. The delay line is to output a capture clock based on a first setting, and monitor clocks based on additional settings. The apparatus also includes: a data sampler to sample incoming data with the capture clock and output capture data; monitor samplers to sample the incoming data with the monitor clocks and output monitored data; and a monitor circuit to trigger an update to at least one of the settings based on comparison of the capture data to the monitored data.
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
27.
PLL USING A DCO PERIOD LENGTH FEEDBACK CLOCK PULSE TO DETERMINE PHASE ERROR AND TDC GAIN
A phase-locked loop (PLL) includes a digitally controlled oscillator (DCO) that generates a DCO output signal. A feedback divider is coupled to the DCO output signal, divides the DCO output signal, and generates a feedback clock signal. The feedback clock signal is generated as a pulse having a pulse width equal to one period of the DCO output signal. A time-to-digital converter (TDC) receives a reference clock signal and the feedback clock signal and generates a TDC output that indicates a phase difference between the reference clock signal and the feedback clock signal. The TDC output also provides gain information indicating how many delay elements correspond to the period of the DCO output signal. The gain information can be used to more accurately cancel quantization error in the PLL.
H03L 7/107 - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
G04F 10/00 - Apparatus for measuring unknown time intervals by electric means
H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
28.
Feedback divider in a PLL used as a phase/frequency detector
A phase-locked loop (PLL) uses a feedback divider to provide phase and frequency information for faster lock. The PLL includes a time to digital converter that generates first phase information indicative of a phase difference between a reference clock and a feedback clock. A digital filter receives the first phase information and generates an oscillator control signal used by an oscillator to generate an oscillator output. A feedback divider uses a ripple counter to divide the oscillator output to generate the feedback clock. One sample of the ripple counter provides second phase information and two samples of the ripple counter provide frequency information, which are used to generate the oscillator control signal. The one sample of the ripple counter is compared to an expected value when the PLL is locked to generate second phase information and a difference between the two samples is used to generate the frequency information.
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/083 - Details of the phase-locked loop the reference signal being additionally directly applied to the generator
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
29.
Devices and Systems for Learning Wi-Fi Access Point Behavior To Reduce Power Consumption
Methods and Wi-Fi devices that learn the behavior of an associated access point and modify their actions accordingly are disclosed. The low power Wi-Fi device may begin in a default state and observe the behavior of the access point. Based on this observed behavior, the low power Wi-Fi device may continue operating in the default state, or may modify its actions. Some of the behaviors of the access point that are monitored include its response to PS-Poll packets, its “keep alive” behavior and its use of aggregation. In each case, the low power Wi-Fi device is able to modify its actions if the access point operates in a manner that differs from that expected. As a result of the modifications, the low power Wi-Fi device may reduce its power consumption.
In one embodiment, an apparatus includes: a fabric circuit to couple between a plurality of managers and a memory; and multi-bank memory control circuitry coupled to the fabric circuit and to couple to a plurality of banks of the memory and including a plurality of first ports to receive memory requests from the plurality of managers, The multi-bank memory control circuitry is to enable each of the plurality of managers to access the memory in parallel. A global monitor is coupled to the multi-bank memory control circuitry and includes a plurality of second ports and a plurality of state machines, each of the plurality of state machines to be associated with one of the plurality of managers. Each of the plurality of state machines is configured to enforce exclusivity of a memory region on behalf of a manager and concurrently enable non-exclusive access to the memory region.
An aging resilient level shifter has an increased lifetime as compared to a conventional level shifter. In at least one embodiment, a method for level-shifting a received signal from a first voltage domain to a second voltage domain includes controlling a cross-coupled pair of transistors according to an input signal and a complementary input signal to generate a signal on a pair of complementary nodes. The cross-coupled pair of transistors has a first doping type and the controlling uses a pair of transistors having a second doping type. The second doping type is complementary to the first doping type. The method includes isolating the pair of transistors from the pair of complementary nodes using a pair of isolation transistors and a pair of cascode transistors. The pair of cascode transistors is coupled between the pair of transistors and the pair of complementary nodes.
In one aspect, an apparatus includes: radio frequency (RF) circuitry to transmit and receive RF signals, the RF circuitry to operate with a local oscillator (LO) clock signal; clock circuitry to receive the LO clock signal and generate an LO-derived clock signal therefrom; first digital circuitry to communicate data according to a first digital clock signal; and a controller coupled to the first digital circuitry to select one of the LO-derived clock signal or a source clock signal to provide to the first digital circuitry as the first digital clock signal.
H04L 7/04 - Speed or phase control by synchronisation signals
G06F 1/12 - Synchronisation of different clock signals
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
A system and method for efficiently modifying the parameters of a Periodic Advertisement (PA) or Periodic Advertisement with Response (PAwR) train are disclosed. Rather than forcing all of the listening devices to reacquire synchronization to the new PAwR train, the periodic advertiser transmits the parameters associated with the new or revised train in the periodic advertisements of the existing train. The listening devices receive the new parameters and update their timers accordingly such that they exit low power mode in time to receive the periodic advertisement on the new or revised train. In some embodiments, the periodic advertiser generates a new train, while in other embodiments, the periodic advertiser changes the parameters associated with the PA or PAwR train without creating a new train.
H04H 60/40 - Arrangements for identifying or recognising characteristics with a direct linkage to broadcast information or to broadcast space-time, e.g. for identifying broadcast stations or for identifying users for identifying broadcast time or space for identifying broadcast time
H04H 60/37 - Arrangements for identifying or recognising characteristics with a direct linkage to broadcast information or to broadcast space-time, e.g. for identifying broadcast stations or for identifying users for identifying segments of broadcast information, e.g. scenes or extracting programme ID
H04H 60/92 - Wireless transmission systems for local area
In one aspect, a method includes: enabling, via a controller of a network device, a receiver of the network device for a plurality of receive fragments during a receive duration; analyzing a signal fragment received during at least one of the plurality of receive fragments to identify possible presence of a wake-up frame sent by a coordinator device; and in response to the identification of the possible presence of the wake-up frame, enabling the receiver to receive and detect another wake-up frame.
Methods and Wi-Fi devices that utilize the target wake time (TWT) feature of the Wi-Fi specification along with delayed TCP acknowledgment are disclosed. When using TWT and delayed TCP acknowledgment, the low power Wi-Fi device checks to see if the size of the payload is less than a predetermined value. By checking the size of the payload, the low power Wi-Fi device can quickly determine whether the received packet may be related to TCP connection/Application protocol connection maintenance. Based on this determination, if necessary, the low power Wi-Fi device can transmit an acknowledgment during the same TWT service period, thereby minimizing the chance that the TCP connection will be terminated.
A method for executing a program includes writing a program value to a corresponding accelerator program register of accelerator program registers of an accelerator circuit according to accelerator program difference information of a compiled program. The method includes executing an accelerator program by the accelerator circuit according to program values of the accelerator program registers of the accelerator circuit. In an embodiment of the method, the compiled program corresponds to a machine learning model. The machine learning model has at least one layer and an embodiment of the method further includes searching metadata of the compiled program for compiled data associated with each layer of the machine learning model. The accelerator program difference information may be included in the metadata of the compiled program.
In one aspect, an apparatus includes: a first amplifier coupled to a first node of a receiver signal processing path, the first amplifier to receive and amplify a radio frequency (RF) signal; a first resistive attenuator coupled to the first node, the first resistive attenuator programmable to reduce a level of the RF signal; a second amplifier coupled in parallel with the first amplifier, the second amplifier to receive and amplify the RF signal; and a second attenuator coupled between the first node and the second amplifier, the second attenuator programmable to reduce the level of the RF signal.
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
H03F 3/19 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
Techniques for observing energy consumption of a target device using battery power in a target application are described. These techniques use a development board and associated development software to sense voltage and current for computation of actual power and energy consumption and battery life during product development. The techniques provide application developers with information useful for developing software that reduces microcontroller current and power consumption to extend battery-life of a target device in a target application, which reduces battery waste and reduces expenses associated with servicing a product including the target device. The techniques enable an integrated development environment that does not need expensive, external equipment to measure the power consumption of the target device when powered by a battery or other power source.
A demodulator in a receiver performs timing detection timing by generating first and second correlation results based on correlation of a first and second training sequence received by the receiver against a known first and a known second training sequence. Third correlation results are generated based on correlation of the first training sequence combined with the second training sequence with the known first training sequence and the known second training sequence. The demodulator detects respective peaks in the first correlations results and the second correlations results and a plurality of peaks in the third correlation results. A true peak in the plurality of peaks corresponding to an end of the second training sequence is identified based on a first peak in the first correlation results and a second peak in the second correlation results.
In one embodiment, a method includes: setting, via a controller of a receiver, a plurality of gain components of the receiver for a maximum gain setting for an automatic gain control (AGC) sensitivity (SENS) mode; receiving, in a controller of the receiver, an indication that a power level of an intermediate frequency (IF) signal measured at an output of an IF amplifier of the receiver exceeds a first threshold; and transitioning from an AGC SENS mode to an AGC adjacent channel interference (ACI) mode in response to the indication that the power level of the IF signal exceeds the first threshold.
In one aspect, a receiver includes a digital processor having a digital signal processing path that comprises: a packet detector to detect a packet; a channel profile circuit coupled to the packet detector to determine a channel profile of a channel via which the packet is received; a fast Fourier transform (FFT) engine to convert time domain samples of the packet to frequency domain samples; and a plurality of smoothing filters. The receiver further includes a controller coupled to the channel profile circuit to select one of the plurality of smoothing filters to couple into the digital signal processing path based at least in part on the channel profile.
A technique for reducing power consumption and latency in wireless communications includes reducing communications of redundant or unwanted information during a discovery operation of a wireless communications protocol. The technique includes an excluded identifier field in a probe request frame to instruct an access point to forgo sending a probe response frame or to reduce information included in a probe response frame. The technique reduces the number of probe response frames communicated over the air or total amount of information communicated during the discovery operation, thereby reducing power consumption and likelihood of collisions that would impact system performance.
An embedded system includes hash message authentication code (HMAC) hardware. The HMAC hardware receives data in separate data transfers to compute a hash. The HMAC hardware receives data of unaligned lengths in at least one of the separate data transfers. The data of unaligned lengths includes fewer valid bytes than the transfer size. The HMAC hardware responds to a residue indication indicating valid bytes associated with the data transfer to fill in the residue from a subsequent data transfer. For each data transfer the HMAC hardware receives an indication of whether the data is final data or if more data will be transferred for computation of the hash. The embedded system loads a linear buffer directly from scatter buffers, which contain encrypted data from a network. Decrypted data in the linear buffer is sent to a host using a direct memory access (DMA) operation responsive to a host request.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
44.
Pseudo-spectrum Averaging for High Accuracy Distance Measurements
A system and method for determining the distance between two wireless network devices is disclosed. The present system utilizes a plurality of pseudo-spectrums to create a more accurate final pseudo-spectrum. The pseudo-spectrums are graphs, where peaks in the graphs are indicative of the magnitude of the signal received at a certain distance. In some embodiments, the pseudo-spectrums are generated using the MUSIC algorithm. The final pseudo-spectrum is generated by performing a mathematical operation on corresponding elements in each pseudo-spectrum. This mathematical operation may include multiplication and normalization. The final pseudo-spectrum provides a more accurate indication of the distance between the devices than can otherwise be achieved.
G01S 5/02 - Position-fixing by co-ordinating two or more direction or position-line determinationsPosition-fixing by co-ordinating two or more distance determinations using radio waves
G01S 5/14 - Determining absolute distances from a plurality of spaced points of known location
45.
Quality Indicator for High Accuracy Distance Measurements
A system and method for determining the quality of a distance measurement performed between two wireless network devices is disclosed. The present performs round trip system time calculations on a plurality of Bluetooth channels and compares the results from these various calculations. Based on these results, the system provides an indication of the perceived quality of the computed distance. In some embodiments, this quality indicator is expressed as a distance. In other embodiments, this quality indicator is expressed as a likelihood or confidence level.
A system and method for reducing power consumption in an advertiser in a Bluetooth network is disclosed. The advertiser transmits the advertisement in accordance with the Bluetooth protocol and listens for scan request packets. If a scan request packet is received from a remote device, the advertiser determines the signal strength of the incoming scan request packet and adjusts its transmit power based on this determination. This determination may allow the advertiser to reduce its transmit power if the remote device that transmits the scan request is believed to be nearby. The advertiser then transmits a scan response packet using this adjusted transmit power. This technique may be used for both legacy and extended advertising.
H04W 52/24 - TPC being performed according to specific parameters using SIR [Signal to Interference Ratio] or other wireless path parameters
H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets
A wireless communication device has a receiver to listen to a sequence of channels. A controller responds to a preamble being detected on a first channel while the receiver is tuned to the first channel by causing the receiver to stay on the first channel and decode packet(s) associated with the preamble. The controller responds to detection of a first symbol of a first transmission protocol and the preamble not being detected to cause the receiver to stay on the first channel for a predetermined time waiting for a retry. The controller responds to detection of a second symbol of a second transmission protocol and the preamble not being detected to cause the receiver to switch to an advertising channel of the second transmission protocol. If no preambles, noise, or symbols are detected, the receiver switches to listening to a next channel in the sequence after a fixed time.
H04W 74/0808 - Non-scheduled access, e.g. ALOHA using carrier sensing, e.g. carrier sense multiple access [CSMA]
H04L 5/00 - Arrangements affording multiple use of the transmission path
H04W 4/23 - Services signallingAuxiliary data signalling, i.e. transmitting data via a non-traffic channel for mobile advertising
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
In one embodiment, a method includes: receiving, in a sink device, profile information regarding a communication from a source device; based at least in part on the profile information, determining, in the sink device, a size for a buffer of the sink device, the buffer for storing streaming data of the communication; based at least in part on the profile information, determining, in the sink device, a synchronization interval for the communication; and controlling, via the sink device, the communication of the streaming data from the source device to the sink device via a first wireless protocol based at least in part on the synchronization interval, to cause the sink device to be a synchronized receiver for the communication.
A wideband power detector (peak or RMS) is placed in a base-band portion of a receiver chain implemented with a current mode RF front end. A differential transimpedance amplifier (TIA) includes a current sense circuit that replicates the input currents to the TIA as current sense output voltages without the current sense output voltages being affected by the filter characteristics of the TIA.
A technique for incorporating energy harvesting into a wireless network (e.g., an IoT network) of communications devices (e.g., IoT nodes) enables the nodes to harvest energy from neighboring nodes within the wireless network. The technique configures each node to identify its own energy requirements, to configure a node to be an energy harvesting node that scans the network of nodes for available wireless charger nodes, and to configure the energy harvesting node to harvest energy from available wireless charger nodes. In an embodiment, the technique increases reliability, reduces system costs, and extends the lifespan of battery powered IoT nodes. The node determines its own energy requirements, discovers available wireless charger nodes within the IoT network, configures the node for a wireless charging session, and initiates a wireless charging session between the node and an available wireless charger node.
Methods and Wi-Fi devices that utilize the target wait time (TWT) feature of the Wi-Fi specification are disclosed. These 5 methods reduce power consumption by selectively listening to only a portion of the beacons that are transmitted by the access point. In one scenario, the Wi-Fi device only listens to one beacon per TWT wake interval. In another embodiment, the Wi-Fi device may have knowledge of the application that is being executed, such as its allowable latency. The Wi-Fi device may use this allowable latency to determine which when to exit low power mode to receive a beacon. Further, mechanisms to ensure that the connection between the Wi-Fi device and the access point are also disclosed.
A system and method for characterizing the performance of an antenna array in a locator device is disclosed. The system comprises a chamber having a locator device and a beacon device. The beacon device is disposed on a rail so as to move in a predictable path while emitting the direction detecting signal. A controller is used to move the beacon device and record its actual position. Phase or direction information collected from the locator device is then supplied to the controller. The controller then compares the actual position to the information received from the locator device and provides this comparison to the user. The path of the rail may allow elevation angles from 0° to 90°. Further, the locator device may rotate, allowing azimuth angles from 0° to at least 180°.
A synchronization pattern detector is disclosed. The synchronization pattern detector includes a plurality of pattern detectors, which may be correlators or cost function engines which each calculate a partial metric, which may be a correlation score or cost value of a subset of the incoming data bits, respectively. The pattern detectors are arranged in a two dimensional array where each row processes data samples associated with a particular phase of the incoming data bits. These partial metrics are summed together to calculate a total metric for a particular symbol stream. Summing circuits are configured to calculate metrics for various scenarios, such as transmit baudrate equal to, slower than, or faster than the receiver baudrate. In addition to detecting the synchronization pattern, the detector may also provide information that is used to adjust parameters of the read circuit to better align the receiver baudrate to the transmit baudrate.
Methods and Wi-Fi devices that utilize the target wait time (TWT) feature of the Wi-Fi specification are disclosed. These methods reduce power consumption by selectively listening to only a portion of the beacons that are transmitted by the access point. In one scenario, the Wi-Fi device only listens to one beacon per TWT wake interval. In another embodiment, the Wi-Fi device may have knowledge of the application that is being executed, such as its allowable latency. The Wi-Fi device may use this allowable latency to determine when to exit low power mode to receive a beacon. Further, mechanisms to ensure that the connection between the Wi-Fi device and the access point are also disclosed. Additionally, techniques to maintain synchronization between the Wi-Fi device and the access point are disclosed.
A synchronization pattern detector is disclosed. The synchronization pattern detector includes a plurality of cost function engines which each calculate a partial cost of a subset of the incoming data bits. The cost function engines are arranged in a two dimensional array where each row processes data samples associated with a particular phase of the incoming data bits. These partial costs are summed together to calculate a total cost for a particular symbol stream. Summing circuits are configured to calculate costs for various scenarios, such as transmit baudrate equal to the receiver baudrate; transmit baudrate slower than the receiver baudrate; and transmit baudrate faster than the receiver baudrate. In addition to detecting the synchronization pattern, the detector may also provide information that is used to adjust parameters of the read circuit to better align the receiver baudrate to the transmit baudrate.
A technique for reducing or eliminating effects of frequency and phase offset in a communications system includes implementing a demodulator having a Kalman filter based phase-locked loop for phase-shift keying or quadrature amplitude modulated signals. In an acquisition mode of operation, the Kalman filter based phase-locked loop continuously updates an error correction signal until an error between a received version of a predetermined signal transmitted using phase-shift keying or quadrature amplitude modulation and the predetermined signal is at or near zero. In a tracking mode of operation, the Kalman filter based phase-locked loop adjusts the error correction signal to maintain the error between the received signal and a predicted signal at or near zero.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
57.
Kalman filter based phase-locked loop with re-encoding based phase detector
A wireless communications device includes a receiver having a phase detector configured to extract frequency offset and provide a corresponding error signal generated based on a baseband version of a received radio frequency signal and an expected transmitted data signal. The receiver has a phase-locked loop configured to generate an error correction signal based on a phase of the error signal and a predicted instantaneous phase of the error signal. The receiver has a correction circuit configured to provide a corrected baseband version of the received radio frequency signal based on the baseband version of the received radio frequency signal and the error correction signal. The receiver may have a re-encoding-based processing circuit configured to provide the expected transmitted data signal based on a preliminarily decoded symbol.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H03M 13/41 - Sequence estimation, i.e using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
In one aspect, an apparatus includes: a first feedback digital-to-analog converter (DAC) to receive a first feedback signal from a first successive approximation register (SAR) and output a first analog signal; a comparator to compare the first analog signal with a reference voltage; the first SAR to store a digital value based on the comparison and provide the first feedback signal to the first DAC; a second feedback DAC to receive a modulated quantized residual error based on the comparison and output a second analog signal; a second SAR to store a quantized residual error; and a delta-sigma modulator (DSM) to modulate the quantized residual error and provide the modulated quantized residual error to the second feedback DAC.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
59.
SYSTEM, METHOD AND APPARATUS FOR REDUCING INTERFERENCE DURING CONCURRENT WIRELESS ACTIVITY IN COMMON BAND
In one embodiment, an apparatus includes: a first radio frequency (RF) circuit to transmit and receive at a 2.4 GHz band according to a first wireless communication protocol; a second RF circuit to transmit and receive at a 2.4 GHz band according to a second wireless communication protocol; and a selection filter coupled to the first RF circuit and the second RF circuit. The selection filter may include: a first filter to couple to the first RF circuit, the first filter configured for a first wireless channel within the 2.4 GHz band; and a second filter to couple to the second RF circuit, the second filter configured for a second wireless channel within the 2.4 GHz band.
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
A system and method of reducing data loss in a system utilizing a bus protocol that does not support flow control is disclosed. The peripheral device utilizes a spill buffer which is used to capture any data sent by the host before the peripheral device is able to properly configure the DMA controller. Additionally, the peripheral device includes a recovery routine, which is a software program that parses the spill buffer and extracts any headers or payloads that are contained therein. Using the spill buffer and recovery routine, the baud rate of the bus interface may be increases without incurring any increase in data loss.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
Positive and negative glitch detectors detect glitches on a supply voltage node. The positive glitch detector has a capacitor and a resistor serially coupled between the supply voltage node and ground. An amplifier is coupled to a first node between the capacitor and resistor. A positive glitch results in the glitch on the first node (normally biased low) and generation of a clock pulse by the amplifier that causes a latch to assert its output to indicate the positive glitch. The negative glitch detector has a capacitor and resistor coupled in parallel between the supply voltage node and a second node. A negative glitch on the supply voltage node decreases the voltage on the second node (normally biased high) and an inverting amplifier coupled to the second node generates a clock pulse to cause a latch to assert its output to indicate the negative voltage glitch.
G06F 21/75 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation, e.g. to counteract reverse engineering
62.
Handling Attribute Updates and Commands Between a Digital Twin and Wi-Fi IoT Power Constrained Device with an Extended Sleep Duration
A system and various methods to implement a Digital Twin with a low power Wi-Fi device is disclosed. The low power Wi-Fi device seeks a Digital Twin at the time of commissioning to serve as its proxy node while it is in sleep mode. Additionally, techniques to address the situation where the Digital Twin becomes unavailable are also disclosed. Finally, techniques to create and update a chain of Digital Twins are also disclosed.
A system and method for uploading a new firmware image to a distributor node is disclosed. The distributor node is part of a Bluetooth mesh network. In some embodiments, one of an initiator node or the distributor node includes a GATT database. A GATT client (which may be the distributor node or the initiator node) connects with the GATT database and BLE messages are used to transmit the firmware image. These BLE messages do not have the constraints that are imposed on mesh messages, and therefore the upload occurs much more quickly. This technique is compliant with the Upload Firmware Out of Band (OOB) procedure defined in the Bluetooth Mesh specification. In another embodiment, the firmware image is transmitted from the initiator node to the distributor node using a L2CAP channel.
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
64.
FAST RF POWER MEASUREMENT APPARATUS FOR PRODUCTION TESTING
A system and method for performing production testing on high power semiconductor devices is disclosed. The system includes signal generators, RF meters, sockets, couplers and connectors which also function as switches when connected to an external cable. A calibration process is executed which allows the controller to create a correlation between measurements taken by the RF meter and the actual voltages, and power levels present at the device under test. By performing this calibration, it is possible to perform production testing of devices much more quickly and reliably.
Methods of performing updates to a software image that is disposed in a read only memory or a one time programmable memory device are disclosed. The method includes causing an ECC error at the beginning of a function that has been modified. This ECC error causes an exception. The exception handler determines the address where the ECC error was detected was located and searches a dictionary. This dictionary contains entries that each have an original address in the ROM or OTP Memory and the patch address in a nonvolatile writable memory. The exception handler then causes the processing unit to jump to the patch address, where a modified function is located.
A technique for adding a new information rate to a legacy physical interface of a communications system includes using a rate switch packet including a distinct rate select start-of-frame delimiter that indicates a newly defined physical interface packet. The rate switch packet uses the same modulation scheme as a base rate packet (e.g., a packet using an information rate defined by a standard communications protocol) and the same preamble pattern as the base rate packet. The preamble length of the rate switch packet can be the same as or different from the preamble length of the base rate packet. An embodiment uses antenna diversity by selecting the antenna in the rate switch packet and using the selected antenna to receive an adjusted rate packet. Additional rate switch start-of-frame delimiters can be used to indicate more than one adjusted rate packet, e.g., to support multiple adjusted information rates.
In one aspect, a method includes: detecting, in a receiver of a wireless device, an energy of a first wireless channel; determining whether the detected energy is within a range between a first threshold and a second threshold; and in response to determining that the detected energy is within the range, transmitting, from a transmitter of the wireless device, a first radio frequency (RF) signal within the first wireless channel at a power level less than a maximum power level.
H04W 52/24 - TPC being performed according to specific parameters using SIR [Signal to Interference Ratio] or other wireless path parameters
H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets
H04W 52/50 - TPC being performed in particular situations at the moment of starting communication in a multiple access environment
68.
SCALABLE PACKET COMMUNICATION IN A LONG RANGE WIRELESS SYSTEM
In one embodiment, a transmitter includes: a circuit to generate a packet having a preamble, a header, and a data portion, where the preamble and the header are dynamically adaptable based at least in part on a range between the transmitter and a receiver; and a radio frequency (RF) front end circuit coupled to the circuit to process and transmit the packet.
A dual band antenna structure is disclosed. The dual band antenna structure utilizes features from loop ground edge radiating antennas and inverted-F antennas to create an antenna that has two resonance frequencies. The dual band antenna structure includes a loop ground edge radiating antenna, which has a first resonance frequency. A monopole branch is also located at the end of the feeding trace to provide a second resonance frequency. The dual band antenna structure is useful for network devices that operate at multiple frequencies, such as those using the WiFi/BLE/IEEE802.15.4 protocols.
H01Q 5/49 - Combinations of two or more dipole type antennas with parasitic elements used for purposes other than for dual-band or multi-band, e.g. imbricated Yagi antennas
H01Q 9/30 - Resonant antennas with feed to end of elongated active element, e.g. unipole
70.
Non-coherent DSSS demodulator with fast signal arrival detection and improved timing and frequency offset estimation
A receiver includes a demodulator having a configurable correlator bank that helps with fast and robust signal detection. The demodulator detects arrival of a first preamble symbol using a first correlator bank configuration. The demodulator makes a course coarse frequency offset estimation after detection of the first preamble signal and the receiver adjusts a frequency used by a mixer based on the coarse frequency offset estimation. The demodulator confirms signal arrival detection with detection of a second preamble symbol. A coarse timing estimation is generated using a second correlator bank configuration using a multi-symbol observation period. A fine frequency offset estimation is made using a third correlation bank configuration. A fine timing estimation is made using a fourth correlation bank configuration. The demodulator then despreads received symbols using a fifth correlator bank configuration.
H04L 5/00 - Arrangements affording multiple use of the transmission path
H04L 25/497 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels by correlative coding, e.g. partial response coding or echo modulation coding
71.
Configurable correlator bank for a non-coherent DSSS demodulator
A demodulator has a correlator bank with multiple correlators. The correlator bank has multiple configurations, including a signal arrival configuration, a coarse timing configuration, and a despreading configuration. The various configurations are used to correlate function transformations of received symbols to template signals. Each correlator has elements with a number of delay blocks corresponding to a number of chips in a symbol. The output of each delay block is multiplied by a bit of a template signal by negating or not negating the output and the multiplications results are summed. A function transformations block receives phase information to generate the function transformations, which are supplied to the correlators. The function transformations include a transformation with a one chip differential, transformations with multi-chip differentials, an average transformation that includes an average of a one-chip phase difference between two adjacent samples, and a second order phase differentiation used for frequency deviation correlation.
H04L 5/00 - Arrangements affording multiple use of the transmission path
H04L 25/497 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels by correlative coding, e.g. partial response coding or echo modulation coding
72.
TECHNIQUES FOR ROBUST PREAMBLE GENERATION FOR SCALABLE PACKETS IN LONG RANGE WIRELESS NETWORK
In one aspect, a circuit includes a preamble generator to generate a preamble having a first field and a second field, the first field having a first sequence that is repeated a plurality of times, a length of the first sequence and a number of the plurality of times based at least in part on a range between a transmitter and a receiver.
In one embodiment, a method includes: receiving, in a receiver of a gateway, from a wireless device a radio frequency (RF) signal including a packet and processing the RF signal to obtain a digital stream; detecting and synchronizing, in the gateway, the packet based at least in part on a preamble of the packet; decoding, in the gateway, a header of the packet to obtain information associated with the packet; demodulating, in the gateway, a data portion of the packet into soft information; and sending at least a portion of the decoded header and the soft information from the gateway to a server coupled to the gateway, to enable the packet to be decoded using the soft information.
In one embodiment, an apparatus includes: a replica sampler circuit to sample a first voltage that is based on a reference voltage, the replica sampler circuit to at least approximate a non-linearity of a bias generator. The replica sampler circuit may include: a switch circuit, when enabled, to pass the first voltage; and a capacitor coupled to the switch circuit, the capacitor to be charged by the first voltage. The apparatus also may include a comparator coupled to the replica sampler circuit, the comparator having a first input terminal to receive the sampled first voltage and a second input terminal to receive the reference voltage, where the comparator is to output a first signal having a first value when the sampled first voltage departs from the reference voltage by at least a threshold amount, to cause a refresh of at least a portion of the bias generator.
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 11/406 - Management or control of the refreshing or charge-regeneration cycles
G11C 11/4099 - Dummy cell treatmentReference voltage generators
75.
Interrupt latency and error resilient full-duplex SPI driver
A system and method of transmitting data between a host and a peripheral device using Serial Peripheral Interface protocol is disclosed. The host and peripheral device redefine the interrupt signal so that it serves as a traditional interrupt signal during most times, but during certain parts of the transmission, it serves as a READY signal, indicating that the host should wait before sending the payload. In this way, transmissions are performed where the likelihood of data loss is greatly reduced or eliminated. Further, because the peripheral device is able to stall the host, full duplex transmissions are made possible.
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
76.
METHOD FOR REDUCING CRITICAL DIMENSION OF PATTERNS GENERATED USING A LITHOGRAPHY TOOL
A technique for forming semiconductor structures having a critical dimension (CD) smaller than the minimum lithographic CD capability of an available lithography tool used to form structures on a substrate forms structures having that minimum lithographic CD and reduces the CD of those structures using non-lithographic techniques. A method for manufacturing an integrated circuit includes forming a first hard mask on a substrate by patterning a first layer of a first material. The method includes forming a second hard mask of a second material on the substrate by chemically modifying the first hard mask. The method includes forming a third hard mask by patterning a second layer of the first material on the substrate. The method includes forming a fourth hard mask of the second material on the substrate by chemically modifying the third hard mask.
A device enclosure for a wafer level chip scale package (WLCSP) device that is particularly useful for package qualification testing includes a base for receiving the WLCSP device and a removable cover. The device enclosure allows testing to occur without handling of the device. The base has through holes in a center portion of a bottom of the base to allow electrical contacts of the WLCSP device to be exposed when the WLCSP device is mounted in the device enclosure. The cover attaches to the base with screws and has a plurality of openings to provide ingress of air into the device enclosure. A peripheral of the bottom of the cover is recessed from a center portion of the bottom of the cover and the center portion engages the WLCSP device to secure the WLCSP device in the device enclosure when the base and cover are secured together.
A fractional-N phase-locked loop (PLL) that maintains phase coherence for an output signal with a plurality of possible output frequencies. The fractional-N PLL includes an oscillator, a phase detector to receive a reference clock signal and a feedback signal, and a multi-modulus divider coupled in a feedback path between the oscillator and the phase detector. A multi-modulus pattern generator supplies a drive pattern to the multi-modulus divider to achieve a desired change in frequency of the output signal. The multi-modulus pattern generator initiates the drive pattern at a boundary time to cause the output signal to have a substantially repeatable phase when restarting switching from any one of the output frequencies to any other of the output frequencies.
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03B 5/32 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
A plurality of techniques that can reduce the power consumed by a low power node in a Bluetooth Mesh network are disclosed. One technique allows the low power node to receive more than one queued message from a friend node in a single packet, thereby reducing the number of transmissions required of the low power node. Another technique allows the low power node to utilize link layer device filtering so that messages that are not of interest are not processed by the low power node. A third technique allows the low power node to readily determine whether potential friend nodes are available before initiating the friendship establishment procedure.
In one embodiment, an apparatus includes: a wake-up radio to issue a trigger signal in response to detection of a wake-up message in a radio frequency (RF) signal; and a second radio coupled to the wake-up radio, the second radio to wake up in response to receipt of the trigger signal. The wake-up radio may be coupled to the second radio without substantial loading, and may be configured with stacked circuits to reuse currents.
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
An apparatus includes an array processor to process array data. The array data are arranged in a memory. The array data are specified with programmable per-dimension size and stride values. A method for processing array data includes executing at least one loop by at least one corresponding loop controller of a plurality of loop controllers in an array processor. Each loop of the at least one loop is executed according to a corresponding begin flag and a corresponding end flag. The method may include generating an instruction stream by decoding a loop control field of a corresponding macro-instruction. The method may include configuring the corresponding begin flag and the corresponding end flag according to a corresponding begin flag field in the instruction stream and a corresponding end flag field in the instruction stream.
A technique for configuring multi-protocol nodes for IoT applications initially configures the multi-protocol nodes in a PAN network (e.g., a BLE mesh network). In response to a trigger, the multi-protocol nodes self-configure into a heterogeneous network accessible by a smart device. Each multi-protocol node enables LAN communications and searches for a LAN networking device for a predetermined interval. Nodes directly reachable by a LAN networking device reconfigure themselves to serve as a proxy to nodes that are out of range of the LAN networking device. The multi-protocol nodes publish their LAN connectivity status to neighboring nodes. After each of the multi-protocol nodes have received the connectivity status of corresponding neighboring nodes, the nodes determine their role in a heterogeneous network, e.g., a pure Wi-Fi node, a Wi-Fi-to-BLE mesh bridge connectivity node, or a pure BLE mesh node, and self-configure in a corresponding connectivity mode.
Techniques for providing a representation of densities of layer material in an integrated circuit layout design without revealing actual layout design data to protect a vendor's proprietary design data are described. The representation of the density information is used to reduce or eliminate density violations at borders of distinct portions of the integrated circuit design. By exchanging standardized data in a density view database, the techniques described herein can be independent of the vendor. A method for manufacturing an integrated circuit includes generating a design density view database representing a first integrated circuit layout design by using layer density information associated with the first integrated circuit layout design as a proxy for actual layout design information.
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
A voltage reference circuit can operate in a large supply voltage range, including a low supply voltage, and can operate with high PSRR. The voltage reference circuit supplies a voltage reference with a near zero temperature coefficient (TC) across a wide-temperature range. The voltage reference circuit develops a first current with a positive temperature coefficient from a first transistor and a second current with a negative temperature coefficient from a second transistor. The control terminals of the two transistors are supplied by respective outputs of two error amplifiers. The two currents are combined to develop a voltage reference across a resistor. The voltage reference has a near zero temperature coefficient.
G05F 3/24 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations wherein the transistors are of the field-effect type only
G05F 1/567 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
A method updates a low frequency count value at a first frequency in an active mode and maintains the low frequency count value in the low power mode. Updating the low frequency count value includes updating a fractional counter in response to a first clock signal, updating an integral counter in response to a second clock signal, and generating the second clock signal based on the fractional count and the first clock signal. The first clock signal has a second frequency. The first frequency is lower than the second frequency. Updating the low frequency count value may include adjusting the low frequency count value in response to exiting the low power mode based on a difference between a current value of a real time clock counter and a prior value of the real time clock counter stored upon entry into the low power mode.
A multi-thread communication system has several communications processors operative over a single interface for transmitting and receiving packets. The multi-thread communications processor is operative to sequentially handle multiple thread processes for each communications processor on a cycle by cycle basis according to a thread map register which determines the order of execution and how many cycles of a particular thread occur during a canonical interval.
H04W 28/02 - Traffic management, e.g. flow control or congestion control
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
A system and method of synchronizing the clocks between two connected Bluetooth devices is disclosed. The two devices exchange packets that contain a timestamp that is indicative of the time that each device received a packet from the other device. By exchanging this information, each device may determine the offset between its internal clock and the internal clock of the other device. Once clock synchronization is achieved, the central device may transmit packets to the peripheral requesting that particular actions be taken at specific times.
A system and method for reducing the probability of collisions in a Bluetooth wireless sensor network is disclosed. The system and method utilize Periodic Advertising with Response to receive status information from the plurality of wireless sensor devices. Therefore, rather than sending the Sensor Status message at random times, the wireless sensor devices are all assigned a response slot in one of the subevents. The relay device receives all of the sensor status messages and forwards the information to the next hop device using measurement collection packets. In some embodiments, the relay device compacts the information before transmitting the measurement collection packets.
H04W 4/38 - Services specially adapted for particular environments, situations or purposes for collecting sensor information
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
H04W 28/06 - Optimising, e.g. header compression, information sizing
89.
Reducing power and latency in coexisting transmissions protocols with overlapping channels
A traffic arbitration technique enables a wireless personal area network (WPAN) protocol to use channel assessment performed by a wireless personal area network protocol (WLAN) and to transmit associated data immediately following completion of a WLAN transmission without an intervening channel assessment or backoff event. This technique reduces power consumption and latency introduced by backoff events of coexistence techniques of the WPAN protocol and increases intermittent transmission of WPAN data. The WPAN protocol may enter a sleep mode after transmission thereby further reducing power consumption of a system with co-located wireless communications protocols.
A clock doubler circuit doubles the frequency of an input clock signal. The input clock signal is supplied to a duty cycle corrector (DCC) circuit, which generates a DCC output signal having a duty cycle corrected to fifty percent and has a frequency that equals the input frequency. A T/4 delay circuit receives the input clock signal and generates a T/4 delay output signal that has a delay of T/4 from the DCC output signal and has the same frequency as the input clock signal. T/4 is one quarter of a period of the input clock signal. An XOR gate combines the DCC output signal and the T/4 delay output signal to generate an output clock signal that is twice the frequency of the input clock signal. A duty cycle estimator generates correction factors used to generate the T/4 delay output signal and the DCC output signal.
A relay network of wireless devices extends the range of synchronized playback of broadcast audio signals. A method for delivering isochronous data using a relay network includes receiving first data of an isochronous data stream from a first wireless communications device of the relay network having a first presentation delay. The first data is received by a second wireless communications device of the relay network having a second presentation delay. The method includes presenting the first data by the first wireless communications device and the second wireless communications device at a time after transmission of the first data in a second isochronous data stream by the second wireless communications device. The first data may be presented by each wireless communications device in the relay network after transmission of the first data by a last wireless communications device in the relay network.
A receiver includes: an analog front end (AFE) circuit to receive and process an incoming radio frequency (RF) signal comprising a packet; an analog-to-digital converter (ADC) to receive and digitize the processed incoming RF signal into a digital signal; a packet detector to detect the packet; an estimation circuit to determine a carrier frequency offset (CFO) estimate based at least in part on a preamble of the packet; an averager to determine a CFO average value for a plurality of packets communicated between a device pair combination of the receiver and a transmitter; and a compensation circuit to compensate for CFO between the device pair combination based at least in part on the CFO average value.
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
H04B 1/12 - Neutralising, balancing, or compensation arrangements
93.
System and Method to Reduce Packet Error Rates for Larger Fragments through Payload Normalization
A system and method for reducing packet error rates for L2CAP PDUs with large payloads is disclosed. The Bluetooth device fragments the large payload in several packets in accordance with well known algorithms. However, prior to transmission, the Bluetooth device redistributes the payload among these packets to reduce the maximum payload that is transmitted in one packet. In one embodiment, the Optimum Slot Utilization algorithm is used to determine the number and types of packets to be used, as well as the payloads in each packet. Once this is determined, the Bluetooth device then redistributes the payload across these packets to reduce the size of the largest payload that is transmitted in any packet, while still maintaining the same number of packets.
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
In one embodiment, an apparatus includes a circuit to: modulate a symbol with a sequence; extend the modulated symbol to obtain a plurality of modulated symbols; and perform, on the plurality of modulated symbols, a plurality of operations according to a Recipe of operations, to obtain extended and modulated symbols. The apparatus may further include a radio frequency (RF) front end circuit coupled to the circuit to process and transmit the extended and modulated symbols.
In one aspect, an apparatus comprises: a radio frequency (RF) front end circuit to receive and process an RF signal comprising a packet, the RF front end circuit to output a digital signal comprising the packet; and a baseband circuit coupled to the RF front end circuit. The baseband circuit may comprise: a demodulator to receive the digital signal comprising a plurality of extended and modulated symbols and to: perform a plurality of operations on at least some of a first block of the plurality of extended and modulated symbols according to a reverse recipe of operations to obtain a processed first block of the plurality of extended and modulated symbols; aggregate the processed first block of the plurality of extended and modulated symbols into an aggregated symbol; and demodulate the aggregated symbol to obtain at least one soft value.
In one example, an apparatus includes: an analog front end (RF) circuit to receive and process, from a first antenna and a second antenna, a radio frequency (RF) signal to obtain a digital signal, the RF circuit having a single RF signal processing path; a baseband circuit coupled to the RF circuit to process the digital signal, the baseband circuit to determine a first metric for a first packet of the RF signal received via the first antenna; and an antenna selection controller coupled to the baseband circuit, the antenna selection controller to cause the RF circuit to switch from receipt of the RF signal via the second antenna to receipt of the RF signal via the first antenna based at least in part on the first metric.
H04B 7/08 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
97.
Providing temperature compensation to an RC oscillator
In one aspect, an apparatus includes an oscillator to generate a clock signal, where the oscillator includes: at least one resistor; at least one capacitor; and a circuit coupled to the at least one resistor and the at least one capacitor, the circuit to generate the clock signal. The apparatus further includes a voltage regulator coupled to the oscillator to provide a regulated voltage to the oscillator, and a bulk voltage generator coupled to the voltage regulator. The bulk voltage generator may provide first and second bulk voltages to the voltage regulator to provide temperature compensation to the oscillator.
H03B 5/24 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
H03B 5/04 - Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
H03K 3/011 - Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
H03K 4/501 - Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor the starting point of the flyback period being determined by the amplitude of the voltage across the capacitor, e.g. by a comparator
H03L 1/02 - Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
98.
SYSTEM AND METHOD TO OPTIMIZE BLUETOOTH MESH NETWORKS
A system and method to improve latency in a Bluetooth mesh network is disclosed. In many Bluetooth mesh networks, devices may not be available due to power saving mode or participation in other networks. This behavior slows the propagation of packets through the Bluetooth mesh network. To address this shortcoming, the method includes transmitting a periodic advertisement from a first, or originating, device. Contained within that periodic advertisement is schedule information associated with the transmission of mesh packets, which are typically transmitted at random times. The first device later transmits mesh packets in accordance with the schedule. This is referred to as a synchronized listening window configuration. Further, other devices in the mesh network also implement the synchronized listening configuration. In this way, packets are able to propagate through the mesh network more quickly.
A voltage regulator includes a first circuit to generate a difference signal based on an input reference voltage, a regulated output voltage, and a signal on a feedback node. The voltage regulator includes a second circuit to provide the regulated output voltage on the output node based on the difference signal. The second circuit includes a first transistor coupled to receive the difference signal, a first feedback circuit to provide a first feedback signal to the feedback node, and a second feedback circuit to provide a second feedback signal to the feedback node. An open loop frequency response of the voltage regulator has a first pole and a second pole and the first feedback signal may adjust the frequency of the second pole based on a load current. The second feedback signal may adjust loop gain based on the load current.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
100.
System and method to reduce power consumption by using adaptive transmit power during sniff attempts
Systems and methods for reducing power consumption by using adaptive transmit power during sniff intervals are disclosed. The central device transmits the first packet of the sniff interval using the previously negotiated transmit power. After the central device receives a response from the peripheral device, the central device uses a lower transmit power for subsequent POLL packets during that sniff interval. This scheme may reduce the power consumption of the central device significantly, especially when a large number of packets are transmitted during each sniff interval.
H04W 52/28 - TPC being performed according to specific parameters using user profile, e.g. mobile speed, priority or network state, e.g. standby, idle or non-transmission
