Abstract

A silicon crystal, a silicon crystal defect treatment method, and a defect characterization method. The silicon crystal defect treatment method comprises: providing a silicon crystal, wherein the silicon crystal includes self-interstitial defects; and executing a rapid heat treatment process on the silicon crystal, so as to at least eliminate self-interstitial defects within a preset distance from a surface of the silicon crystal. By means of executing a rapid heat treatment process on a silicon crystal, self-interstitial defects in the silicon crystal can be quickly and effectively reduced or even completely eliminated.

IPC Classes  ?

• C30B 33/02 - Heat treatment
• C30B 29/06 - Silicon
• C30B 33/10 - Etching in solutions or melts
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
• G01N 21/95 - Investigating the presence of flaws, defects or contamination characterised by the material or shape of the object to be examined

Abstract

The present invention provides a monocrystalline silicon wafer and a forming method therefor. The monocrystalline silicon wafer has an upper surface and a first area within a predetermined distance from the upper surface, and there is no self-interstitial defect in the first area. For a semiconductor device manufactured from the monocrystalline silicon wafer without a self-interstitial defect, the leakage current of the device is reduced and the breakdown voltage is increased, thereby improving the performance of the semiconductor device. Furthermore, the forming method for the monocrystalline silicon wafer eliminates the self-interstitial defect in the monocrystalline silicon wafer by means of a heat treatment process, and the heat treatment process comprises a rapid heat treatment process and/or a long-time heat treatment process. In other words, the monocrystalline silicon wafer without a self-interstitial defect can be obtained by means of the heat treatment process, improving the performance of the semiconductor device.

IPC Classes  ?

• C30B 33/02 - Heat treatment
• C30B 29/06 - Silicon
• C30B 33/00 - After-treatment of single crystals or homogeneous polycrystalline material with defined structure
• H01L 29/30 - Semiconductor bodies having polished or roughened surface
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

The present application provides a method and an apparatus for measuring ingot diameter, and a device for growing the ingot. The method comprises controlling a first calibration light source and a second calibration light source to emit light; obtaining coordinates of the calibration light sources; obtaining a diameter measurement coefficient based on the coordinates; obtaining diameter coordinates of two ends of the ingot diameter; and obtaining a measured value of the diameter based on the diameter coordinates and the diameter measurement coefficient. Accordingly, the measurement error of the ingot diameter can be reduced, and the accuracy of ingot diameter control during the growth process can be improved, thereby the production efficiency of Czochralski silicon ingot can be increased.

IPC Classes  ?

• C30B 15/26 - Stabilisation or shape controlling of the molten zone near the pulled crystalControlling the section of the crystal using television detectorsStabilisation or shape controlling of the molten zone near the pulled crystalControlling the section of the crystal using photo or X-ray detectors
• C30B 29/06 - Silicon
• C30B 35/00 - Apparatus not otherwise provided for, specially adapted for the growth, production or after-treatment of single crystals or of a homogeneous polycrystalline material with defined structure

Abstract

Provided in the present invention is a magnetic control apparatus, comprising: a coil assembly, the coil assembly being sleeved on the outer side of a monocrystalline silicon device, and the coil assembly being movable in the axial direction of the monocrystalline silicon device. The coil assembly comprises a plurality of main coils, the plurality of main coils being arranged in the circumferential direction of the monocrystalline silicon device, and the component intensity of a magnetic field generated by the main coils in the radial direction of the monocrystalline silicon device being greater than the component intensity of same in the axial direction of the monocrystalline silicon device. By means of the configuration, the component intensity of said magnetic field in the radial direction of the monocrystalline silicon device is greater than the component intensity of same in the axial direction of the monocrystalline silicon device, so that the radial component intensity of the magnetic field is improved, thus effectively suppressing natural convection at the edge of a melt and flexibly controlling the content of impurities such as oxygen and carbon in crystals and radial uniformity. In addition, the coil assembly can move in the axial direction of the monocrystalline silicon device, thereby further improving the practicability and flexibility of the magnetic control apparatus.

IPC Classes  ?

• C30B 15/20 - Controlling or regulating
• H01F 7/06 - ElectromagnetsActuators including electromagnets

Abstract

The present application provides a structure of HR-SOI embedded with a charge capture layer and manufacture thereof. The process for manufacturing a structure of HR-SOI embedded with a charge capture layer comprises: providing a first substrate, wherein the first substrate has a first surface to be subjected to a roughness treatment to form an uneven morphology on the first surface; forming a surface treatment layer, wherein the surface treatment layer has an uneven surface morphology; and forming a polysilicon layer on the surface treatment layer. By the roughness treatment to the first substrate, the first surface and the surface treatment layer both have uneven surface morphology, such that the formed polysilicon layer has stable orientation evolution and grain size, and an increased grain boundary density. Thereby a highly efficient charge trapping polysilicon film can be obtained.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions
• H01L 21/763 - Polycrystalline semiconductor regions

Abstract

The present application provides a structure of HR-SOI embedded with a charge capture layer and manufacture thereof. The process for manufacturing a structure of HR-SOI embedded with a charge capture layer comprises: providing a first substrate, wherein the first substrate has a first surface, and a pinning layer is formed on the first surface by a deposition process, and homogenizing the pinning layer surface by dry etching to adjust a thickness uniformity of the pinning layer. Accordingly, the thickness uniformity of the obtained polysilicon film is able to reach a good state.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/3065 - Plasma etchingReactive-ion etching
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

The present invention provides a crystal growing method, an apparatus and a RF-SOI substrate for growing a crystal. The crystal growing method may comprise: controlling a first superconducting coil to generate a first current, and controlling a second superconducting coil to generate a second current, wherein a value of the first current is not equal to a value of the second current, the first superconducting coil and the second superconducting coil are superconducting coils positioned oppositely outside a crucible to generate a magnetic field in the crucible; and pulling upwards to grow a monocrystalline in an asymmetric magnetic field generated by the first current and the second current in the crucible.

IPC Classes  ?

• C30B 30/04 - Production of single crystals or homogeneous polycrystalline material with defined structure characterised by the action of electric or magnetic fields, wave energy or other specific physical conditions using magnetic fields
• C30B 15/20 - Controlling or regulating
• C30B 29/06 - Silicon
• H01F 6/06 - Coils, e.g. winding, insulating, terminating or casing arrangements therefor

Abstract

The present invention discloses a method, apparatus, system and computer storage medium of controlling crystal growth. The method may comprise: obtaining a target piecewise curve of a heater power at different crystal lengths, a segment dividing point being positioned at an intersection point of adjacent segments of the target piecewise curve; based on the crystal lengths, interpolation calculating a value of the heater power at a length as a control value of the heater power; based on the control value of the heater power at different crystal lengths, obtaining a target control curve of the heater power, the target control curve of the heater power being smooth at the segment dividing point.

IPC Classes  ?

• C30B 15/20 - Controlling or regulating

Abstract

The present application provides an epitaxy susceptor, an epitaxy growth apparatus and a manufacturing method of semiconductor device. The epitaxy susceptor comprises a pocket, wherein the pocket comprises plural lift-pin holes for setting lift-pins, and each lift-pin hole is surrounded by at least one auxiliary through hole penetrating the pocket. By setting plural auxiliary through holes with various diameters and/or various distributions surrounding the lift-pin holes in the pocket of the epitaxy susceptor, the physical properties near the lift-pin hole can be similar with that of auxiliary through holes, such that the abnormal thickness of the epitaxial film of the wafer at the site corresponding the lift-pin hole can be eliminated or reduced.

IPC Classes  ?

• C30B 25/12 - Substrate holders or susceptors
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The present invention provides a method for determining the type of defects in a monocrystalline silicon wafer, which includes the steps of: using LST to measure particles in an as-grown silicon wafer and thereby obtaining a first measurement, and determining a V-rich region based on the first measurement and a first preset density value; and subjecting the silicon wafer to a thermal treatment, again using LST to measure particles in the silicon wafer and thereby obtaining a second measurement, and determining a Pv region, an I-rich region and a Pi region based on the second measurement, a second preset density value and a third preset density value. As a result, a particle density can be utilized as a basis for accurately and efficiently determining a region of interest of a monocrystalline silicon wafer as one of a V-rich region, a Pv region, a Pi region and an I-rich region.

IPC Classes  ?

• G01N 21/95 - Investigating the presence of flaws, defects or contamination characterised by the material or shape of the object to be examined
• G01N 21/49 - Scattering, i.e. diffuse reflection within a body or fluid

Abstract

A SOI wafer is disclosed. The SOI wafer may be characterized by surface roughness of a top silicon layer of the SOI wafer is less than 4 Å, thickness uniformity of the top silicon layer is within ±1%, and a total number of particles on a surface of the top silicon layer of the SOI wafer, measured with setting of 37 nm of SPx detection threshold, is less than 100.

IPC Classes  ?

• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 21/762 - Dielectric regions

Abstract

The present application provides a method for detecting temperature of thermal chamber comprising: conducting a thermal treatment at a predicted temperature to a selected silicon wafer within a thermal chamber, wherein the predicted temperature comprises plural temperature points set in order; obtaining a haze value corresponding to the predicted temperature; obtaining a linear relationship I between the temperature and the haze; polishing and washing the silicon wafer; conducting a thermal treatment at a predicted temperature to the polished silicon wafer within the thermal chamber; obtaining a linear relationship II between the temperature and the haze; calculating a difference of the haze at same temperature point between the two thermal treatments, and obtaining an actual temperature difference of the thermal chamber based on the difference of the haze. The present application increases efficiency and accuracy of temperature detection of the thermal chamber, reduce fluctuations caused by silicon wafer thickness and resistivity, increase utilization of silicon wafer, and reduce cost.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• G01K 3/10 - Thermometers giving results other than momentary value of temperature giving differences of valuesThermometers giving results other than momentary value of temperature giving differentiated values in respect of time, e.g. reacting only to a quick change of temperature
• G01K 11/00 - Measuring temperature based on physical or chemical changes not covered by group , , , or

Abstract

The present invention provides a method of growing a single-crystal silicon, comprising: loading a batch of polysilicon material in a crucible of a furnace, heating the crucible to melt the polysilicon material into a mass of silicon melt, confirming a liquid surface of the mass of silicon melt, applying a superconducting magnetic field to the mass of silicon melt with a magnetic field generator and adjusting a position of the magnetic field generator to position a maximum point of the superconducting magnetic field within a predetermined range under the liquid surface, and dipping a seed crystal into the silicon melt, and pulling the seed crystal during rotation of the seed crystal to crystallize the single crystal under the seed crystal until forming an ingot of single-crystal silicon. Oxygen content in the ingot is controlled through positioning the maximum point of the superconducting magnetic field under the liquid surface. According to the present invention, it is needless to change heat field, cost is low and success rate to pull the single crystal is high.

IPC Classes  ?

• C30B 15/20 - Controlling or regulating
• C30B 29/06 - Silicon
• C30B 30/04 - Production of single crystals or homogeneous polycrystalline material with defined structure characterised by the action of electric or magnetic fields, wave energy or other specific physical conditions using magnetic fields

Abstract

The present invention provides standard wafers, a method of making the same and a calibration method. The method of making a standard wafer comprise providing a silicon substrate having a first conductive type; forming a reverse epitaxy layer having a second conductive type; forming a target epitaxy layer having the first conductive type; measuring a measurement of a resistivity of the target epitaxy layer with four point probing, the measurement being utilized as a standard resistivity of the standard wafer. In the present invention, the method of making a standard wafer is low-cost and convenient because the standard wafer is made with electrical isolation formed with the reverse epitaxy layer positioned between the silicon substrate and the target epitaxy layer formed after forming the reverse epitaxy layer facilitates in presenting a resistivity of the target epitaxy layer greater than 50 ohm/cm at first and then utilizing the four point probing to measure the resistivity of the target epitaxy layer as the resistivity of the standard wafer.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The present application provides a semiconductor substrate and a preparation process thereof. In the present application, the polysilicon layer includes the first polysilicon layer and the second polysilicon layer formed separately to generate the less stress, the more random grain orientation and the smaller grain size, maintain the high grain boundary density, and enhance the charge capture. By the combination of different deposition temperature and the combination of two cooling steps after each isothermal annealing treatment, the rate of contraction between the first polysilicon layer and the second polysilicon layer and the initial semiconductor substrate is decreased, and the thermal mismatch of semiconductor substrate is reduced. The stretch between the polysilicon layer and the initial semiconductor substrate can be reduced to prevent the warpage of the semiconductor substrate. Thereby, the stress generated during the growth process of the polysilicon layer can be further reduced.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

A SOI wafer and a method of final processing the same is disclosed. Rapid thermal annealing comprises a first heating process in an atmosphere of a mixture of argon gas and hydrogen gas, volume of the hydrogen gas being less than 10% of whole volume of the mixture, and a first annealing process in an atmosphere of argon gas and optionally hydrogen gas, volume of the hydrogen gas being no greater than 10% of whole volume of the mixture. Long-time thermal annealing comprises a second heating process in an atmosphere of a mixture of argon gas and hydrogen gas, volume of the hydrogen gas being less than 10% of whole volume of the mixture, and a second annealing process in an atmosphere of argon gas and optionally hydrogen gas, volume of the hydrogen gas being no greater than 10% of whole volume of the mixture.

IPC Classes  ?

• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 21/762 - Dielectric regions

Abstract

The present application provides a method of surface treatment of a SOI wafer comprising: providing a SOI wafer comprising a substrate, atop silicon layer and an insulating buried layer, wherein the insulating buried layer is located between the back substrate and the top silicon layer, and the top silicon layer has a surface roughness of larger than 10 Å; removing a native oxide layer from a surface of the top silicon layer by conducting a first isothermal annealing process at a first target temperature, wherein the first isothermal annealing process is under atmosphere of a mixture of argon and hydrogen; and planarizing the surface of the top silicon layer by conducting a second isothermal annealing process at a second target temperature, wherein the second target temperature is higher than the first target temperature, and the second isothermal annealing process is under atmosphere of argon. The present method can optimize the atmosphere for batch annealing to achieve better planarization than the conventional technologies. Specifically, the obtained top silicon layer of the SOI wafer has a surface roughness of less than 4 Å.

IPC Classes  ?

• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• C30B 29/06 - Silicon
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

Abstract

A SOI structured semiconductor silicon wafer and a method of making the same is disclosed, comprising: loading a semiconductor silicon wafer in a first batch vertical furnace, and conducting a long-time thermal treatment; conducting a sacrificial oxidation process in a second batch vertical furnace after the long-time thermal treatment; conducting a rapid thermal annealing treatment after the second step ; wherein during the long-time thermal treatment, the semiconductor silicon wafer is kept in a protection atmosphere of pure , heated-up until meet a target temperature after changing the atmosphere of pure argon into a mixture gas of 1-n % Ar and n % H2, and then annealed in the atmosphere of a mixture of 1-n % Ar and n % hydrogen gas or pure Ar, and n is a value no greater than 10.

IPC Classes  ?

• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 21/762 - Dielectric regions

Abstract

The present application provides a method for verification of conductivity type of a silicon wafer. The method comprises measuring the resistivity of the silicon wafer to obtain a first resistivity, placing the silicon wafer under atmosphere of air for a predicted time period, measuring the resistivity of the silicon wafer to obtain a second resistivity, and determining conductivity type of the silicon wafer by comparing the first resistivity and the second resistivity. The method can be applied to a silicon wafer having a high resistivity such as higher than 500 ohm-cm to rapidly and accurately determine conductivity type of the silicon wafer. Advantages of the method of the present application include accurate test results, easy operation, simple device requirement, and reduced cost.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
• G01N 27/12 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body in dependence upon absorption of a fluidInvestigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body in dependence upon reaction with a fluid

Abstract

The invention provides a measuring method of resistivity of a wafer, comprising: choosing a wafer to be measured, conducting a thermal treatment for the wafer to remove a thermal doner in the wafer, conducting an oxidation process for the wafer to form an oxidized surface on the wafer, and measuring resistivity of the wafer. In the method, firstly, the wafer is oxidized to get the oxidized surface, so as to restrict surface variation when placing the wafer in a later process. Therefore, the resistivity measurement of the wafer surface only slightly varies.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• G01R 27/02 - Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant

Abstract

The invention provides a method of detecting crystallographic defects, comprising: sampling wafer of an ingot in complying with a predetermined wafer sampling frequency; identifying crystallographic defects of the wafer to show the crystallographic defects of the wafer; characterizing observation of the crystallographic defects of the wafer and extracting a value characterizing the crystallographic defects; through a result of characterizing the crystallographic defects, obtaining a radial distribution of density of the wafer and categorizing the crystallographic defects; and obtaining an isogram of the crystallographic defects of the wafer to show a crystallographic defect distribution of the whole ingot according to the value characterizing the crystallographic defects and categories of the crystallographic defects. It is no need to break the ingot to obtain the crystallographic defect distribution of the whole ingot, through which the technology for growing the ingot may be effectively adjusted to obtain the ingot with required characteristics of defect.

IPC Classes  ?

• C30B 15/20 - Controlling or regulating
• C30B 29/06 - Silicon

Abstract

The present application provides a method for characterizing defects in silicon crystal comprising the following steps: etching a surface of the silicon crystal to remove a predicted thickness of the silicon crystal; conducting a LLS scanning to a surface of the etched silicon crystal to obtain a LLS map of the surface, a LSE size of defects, and defect bulk density; based on at least one of the LLS map of the surface, the LSE size of defects and the defect bulk density, determining a type of defect existing in the silicon crystal and/or a defect zone of each type of defect on the surface. By applying the method, the characterizing period and the characterizing cost can be reduced, plural defects such as vacancy, oxygen precipitate and dislocation can be characterized simultaneously, the characterizing accuracy can be enhanced, and the defect type and the defect zone can be determined with high reliability. In addition, the method can be applied to all crystal defect types, is easy to operate, and is an environmentally friendly method for determination of grown-in defects.

IPC Classes  ?

• C30B 29/06 - Silicon
• G01N 21/956 - Inspecting patterns on the surface of objects
• G01N 21/88 - Investigating the presence of flaws, defects or contamination

Abstract

A semiconductor crystal growth method and device are provided. The method comprises: obtaining an initial position of a graphite crucible when used in a semiconductor crystal growth process for the first time; obtaining a current production batch of the graphite crucible which characterizes a number of times of growth processes performed by the graphite crucible so far; and loading polysilicon raw materials into a quartz crucible sleeved in the graphite crucible based on the current production batch, wherein a total weight of the materials is called a charging amount, and the charging amount is adjusted based on the current production batch to keep an initial position of a silicon melt liquid surface in the quartz crucible stable while keeping the initial position of the graphite crucible unchanged. The present invention ensures the stability of each parameter in the crystal pulling process, and enhances the crystal pulling speed and quality.

IPC Classes  ?

• C30B 15/14 - Heating of the melt or the crystallised materials
• C30B 15/10 - Crucibles or containers for supporting the melt
• C30B 15/20 - Controlling or regulating
• C30B 29/06 - Silicon

Abstract

The present application provides a detection method of metal impurity in wafer. The method comprises conducting a medium temperature thermal treatment for a first predicted time period to the wafer, cooling the wafer and conducting a low temperature thermal treatment for a second predicted time period, cooling the wafer to ambient temperature; providing a liquid of vapor phase decomposition on the wafer to collect metal impurities; atomizing the liquid containing the collected metal impurities, conducting an inductively coupled plasma mass spectrometry analysis and obtaining concentrations of the metal impurities. The present application applies the combination of various thermal treatment without an interrupt of cooling to ambient temperature to contemplate diffusions of various metal impurities to the wafer surface. Accordingly, the detection of metal impurities can be conducted with reduced time cost and enhanced efficiency.

IPC Classes  ?

• H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
• H01J 49/00 - Particle spectrometers or separator tubes
• H01J 49/10 - Ion sourcesIon guns
• H01L 21/66 - Testing or measuring during manufacture or treatment

Abstract

The present invention provides a method of making a silicon on insulator (SOI) structure, comprising steps of: providing a bonded structure, the bonded structure comprises a first substrate, a second substrate and an insulating buried layer, the insulating buried layer is positioned between the first substrate and the second substrate; peeling off a layer of removing region of the first substrate from the bonded structure to obtain a SOI structure; and processing the SOI structure with isothermal annealing technology at a pressure which is lower than atmospheric pressure.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections

Abstract

A method of making a silicon on insulator structure comprises: providing a bonded structure, the bonded structure comprises the first substrate, the second substrate and the insulating buried layer, the insulating buried layer is positioned between the first substrate and the second substrate; peeling off a layer of removing region of the first substrate from the bonded structure to obtain a first film; at a first temperature, performing a first etching to etch the first film to remove a first thickness of the first film; at a second temperature, performing a second etching to etch the first film to planarize the first film and remove a second thickness of the first film, the first temperature being lower than the second temperature, the first thickness being greater than the second thickness, and a sum of the first thickness and the second thickness being a total etching thickness of the first film.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• H01L 21/762 - Dielectric regions

Abstract

The present invention provides a method for calculating the liquid-solid interface morphology during growth of the ingot. The method comprises providing a wafer, selecting plural sampling locations on the wafer and detecting electrical resistivity at the plural sampling locations, calculating height differences between the sampling locations based on the detected electrical resistivity, and illustrating the morphology of the liquid-solid interface based on the calculated height differences. The method of the invention has advantages including easy operation and low cost.

IPC Classes  ?

• C30B 15/22 - Stabilisation or shape controlling of the molten zone near the pulled crystalControlling the section of the crystal
• G01N 27/04 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance

Abstract

The present invention provides a method and an apparatus of monocrystal growth. The method comprises providing an apparatus comprising a crucible, a first lifting device for lifting the crucible, a deflector tube and a second lifting device for lifting the deflector tube; setting a theoretical distance between the deflector tube and the melt surface, determining a theoretical ratio of the crucible lifting rate relative to the monocrystal lifting rate based on sizes of the crucible and the monocrystal, and starting to grow the monocrystal. During the growth, the position of one or more of the crucible, the deflector tube and the monocrystal is adjusted, the actual distance between the deflector tube and the melt surface is real-time detected, the deviation value between the theoretical and the actual distances is calculated, a variation of the ratio is obtained by the deviation value, and the theoretical ratio is adjusted based on the variation. Based on the variation of the ratio of the crucible lifting rate relative to the monocrystal lifting rate, the speeds of the lifting devices are adjusted to maintain the process lifting rate during the crystal growth without change. The process lifting rate is the lifting rate of the monocrystal ingot relative to the melt surface. The present invention can facilitate to produce the monocrystal with high quality.

IPC Classes  ?

• C30B 15/20 - Controlling or regulating
• C30B 15/14 - Heating of the melt or the crystallised materials

Abstract

A seeding method for crystal growth comprising: a first seeding step: rotating a crucible with a first rotation speed to grow the crystal to a first length; a second seeding step: gradually increasing the rotation speed of the crucible from the first rotation speed to a second rotation speed, and growing the crystal to a second length; a third seeding step: rotating the crucible with the second rotation speed to growing the crystal to a predicted length. By separating the seeding stage to three steps and gradually increasing the rotation speed in the second step of the crucible, the silicon melt convection is enhanced and the temperature at center of the silicon melt is kept to be not lower than the starting temperature of the seeding. Thereby, the removal of dislocation within the seed crystal can be increased, and the growth problems such as broken or polycrystallization can be prevented.

IPC Classes  ?

• C30B 15/20 - Controlling or regulating
• C30B 15/30 - Mechanisms for rotating or moving either the melt or the crystal
• C30B 15/10 - Crucibles or containers for supporting the melt

Abstract

The present application provides a method for detecting temperature of thermal chamber comprising: conducting a thermal treatment at a predicted temperature to a selected silicon wafer within a thermal chamber, wherein the predicted temperature comprises plural temperature points set in order; obtaining a haze value corresponding to the predicted temperature; obtaining a linear relationship I between the temperature and the haze; polishing and washing the silicon wafer; conducting a thermal treatment at a predicted temperature to the polished silicon wafer within the thermal chamber; obtaining a linear relationship II between the temperature and the haze; calculating a difference of the haze at same temperature point between the two thermal treatments, and obtaining an actual temperature difference of the thermal chamber based on the difference of the haze. The present application increases efficiency and accuracy of temperature detection of the thermal chamber, reduce fluctuations caused by silicon wafer thickness and resistivity, increase utilization of silicon wafer, and reduce cost.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• G01K 3/10 - Thermometers giving results other than momentary value of temperature giving differences of valuesThermometers giving results other than momentary value of temperature giving differentiated values in respect of time, e.g. reacting only to a quick change of temperature
• G01K 11/00 - Measuring temperature based on physical or chemical changes not covered by group , , , or

Abstract

The present invention provides a semiconductor crystal growth device, comprising: a furnace body; a crucible disposed inside the furnace body for containing a silicon melt; a pulling unit disposed at a top portion of the furnace body for pulling out a silicon ingot from the silicon melt; and a heat shield unit including a flow tube that is barrel-shaped and disposed around the silicon ingot for rectifying argon gas input from the top portion of the furnace body and adjusting thermal field distribution between the silicon ingot and the silicon melt liquid surface, wherein, the heat shield unit further includes an adjustment unit disposed at a lower end inside the flow tube for adjusting a minimum distance between the heat shield unit and the silicon ingot. According to the present invention, by providing the adjustment unit at the lower end inside the flow tube, it is possible to adjust the distance between the silicon ingot and the adjacent heat shield unit and thereby boost the crystal growth speed and quality, without changing the shape and position of the flow tube.

IPC Classes  ?

• C30B 15/14 - Heating of the melt or the crystallised materials
• C30B 15/00 - Single-crystal growth by pulling from a melt, e.g. Czochralski method
• C30B 29/06 - Silicon

Abstract

The present invention provides a polishing pad, a polishing apparatus and a polishing method for a silicon wafer. The polishing pad comprises a polishing surface in contact with the silicon wafer. The polishing surface is provided with at least one groove. When polishing the silicon wafer, the edge of the silicon wafer is at least partially suspended above the groove. The polishing pad, polishing apparatus and silicon wafer polishing method according to the present invention can reduce the polishing rate at the edge of the silicon wafer while keeping the polishing rate of the entire wafer basically unchanged, thereby improving the flatness of the edge thickness of the silicon wafer as well as improving the production yield.

IPC Classes  ?

• B24B 37/04 - Lapping machines or devicesAccessories designed for working plane surfaces
• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• B24B 37/26 - Lapping pads for working plane surfaces characterised by the shape of the lapping pad surface, e.g. grooved

Abstract

The present application provides an apparatus and a method for ingot growth. The apparatus for ingot growth comprises a growth furnace, a crucible, a heater, a lifting mechanism, an infrared detector, a dividing disc, a sensor and a control device. The crucible is located within the growth furnace. The lifting mechanism comprises a lifting wire and a driving device, wherein the lifting wire connects to the top of the ingot via one terminal and to the driving device via another terminal. The bottom of the ingot puts inside the crucible, and the ingot has plural crystal lines thereon. The infrared detector is located outside the growth furnace. The dividing disc is above the growth furnace, connects to the lifting mechanism, and rotates with the ingot synchronously under the driving of the lifting mechanism, and an orthographic projection of bisector of the dividing disc is between two adjacent crystal lines. The sensor is located on the periphery of the dividing disc. The control device connects to the infrared detector and the sensor in order to control the infrared detector to detect the ingot diameter while the sensor senses the bisector of the dividing disc. The present application is able to increase ingot quality and enhance product yield.

IPC Classes  ?

• C30B 15/30 - Mechanisms for rotating or moving either the melt or the crystal
• C30B 15/14 - Heating of the melt or the crystallised materials
• C30B 15/20 - Controlling or regulating
• C30B 29/06 - Silicon

Abstract

Disclosed a heat shield structure for a single crystal production furnace, which is provided above a melt crucible of a single crystal production furnace and comprises an outer housing and a heat insulation plate disposed within the outer housing. A bottom outer surface of the outer housing faces an interior of the melt crucible, and an angle formed between a plane in which the heat insulation plate is located and a plane in which a bottom of the outer housing is located is an acute angle and faces an outer surface of single crystal silicon. The heat shield design is changed, a heat absorbing plate is additionally provided for transferring heat absorbed to the single crystal silicon, a heat channel is formed in the heat shield, so that a pulling rate is controlled, which improves radial mass uniformity of the single crystal silicon.

IPC Classes  ?

• C30B 15/14 - Heating of the melt or the crystallised materials
• C30B 15/10 - Crucibles or containers for supporting the melt
• C30B 29/06 - Silicon

Abstract

The invention provides a method for positioning a wafer and a semiconductor manufacturing apparatus, which are applied to thin film processes. The method includes: Step S1: Obtain the state distribution of the first surface of the first wafer after the thin film process is performed on the first wafer, wherein the first surface is the surface opposite to a surface that the thin film formed thereon in the thin film process; Step S2: Determine whether the first wafer is located at the ideal positioning center according to the state distribution of the first surface, when the first wafer is not located at the ideal positioning center, according to the state distribution of the first surface adjusts the positioning position of the second wafer to be subjected to the thin film process, so that the second wafer is positioned at the ideal positioning center during the thin film process. According to the present invention, the wafer is positioned at the ideal positioning center during the thin film process, thereby improving the quality of the thin film layer and the entire wafer (epitaxial wafer) after the thin film process, and improving the effect of the thin film process.

IPC Classes  ?

• G06T 7/77 - Determining position or orientation of objects or cameras using statistical methods
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
• H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
• H01L 21/66 - Testing or measuring during manufacture or treatment

Abstract

The invention provides a semiconductor crystal growth device comprising a furnace body; a crucible; a pulling device; a horizontal magnetic field applying device; and a deflector, being barrel-shaped and disposed above the silicon melt in the furnace body in a vertical direction, and the pulling device pulls the silicon ingot through the deflector in the vertical direction; wherein the bottom of the deflector has different thermal reflection coefficients at different positions, and the thermal reflection coefficient of the bottom of the deflector in the direction of the horizontal magnetic field is smaller than that in the direction perpendicular to the horizontal magnetic field. According to the semiconductor crystal growth device of the present invention, the temperature distribution inside the melt silicon and quality of the semiconductor crystal are improved.

IPC Classes  ?

• C30B 15/22 - Stabilisation or shape controlling of the molten zone near the pulled crystalControlling the section of the crystal
• C30B 29/06 - Silicon
• C30B 15/10 - Crucibles or containers for supporting the melt

Abstract

The present invention provides a semiconductor crystal growth method and apparatus. The semiconductor crystal growth method comprises: obtaining an initial position CP0 of a graphite crucible when being used in a semiconductor crystal growth process for the first time; obtaining the current production batch N of the graphite crucible, wherein the current production bath N represents the number of times that the graphite crucible currently is used in the semiconductor crystal growth process; and according to the current production batch N, filling a polysilicon raw material in a quartz crucible embedded in the graphite crucible, wherein the total weight of the polysilicon raw material is a loading amount W(N), and the loading amount W(N) is adjusted according to the current production batch N, so that the initial position of a silicon melt liquid level in the quartz crucible remains stable while the initial position CP0 of the graphite crucible remains unchanged. Therefore, the present invention ensures the stability of each parameter in a crystal pulling process, enhances a crystal pulling speed, and improves the quality of crystal pulling.

IPC Classes  ?

• C30B 15/22 - Stabilisation or shape controlling of the molten zone near the pulled crystalControlling the section of the crystal
• C30B 29/06 - Silicon

Abstract

Disclosed is a semiconductor crystal growth device comprising: a furnace (1), a crucible (11), the crucible (11) is disposed inside the furnace (1) and configured to contain a silicon melt (13); a drawing unit (14), the drawing unit (14) is disposed at a top portion of the furnace (1) and configured to draw a silicon ingot (10) out of the silicon melt (13); and a heat shield unit. The heat shield unit comprises a draft tube (16), the draft tube (16) is barrel-like and disposed peripherally around the silicon ingot (10), and is configured to regulate a flow of an argon gas drawn from a top portion of the furnace (1) and to adjust a thermal field distribution between the silicon ingot (10) and a liquid surface of the silicon melt (13). The heat shield unit also comprises an adjustment unit (17) disposed at an inner side of a lower end of the draft tube (16) and configured to adjust a minimum distance (Drc) between the heat shield unit and the silicon ingot (10). The disposition of the adjustment unit (17) at an inner side of a lower end of the draft tube (16) enables increased crystal growth speed and quality by adjusting the distance (Drc) between the silicon ingot (10) and the adjacent heat shield unit, without altering a shape and a position of the draft tube (16).

IPC Classes  ?

• C30B 15/20 - Controlling or regulating
• C30B 29/06 - Silicon

Abstract

A complementary metal-oxide-semiconductor field-effect transistor comprises a semiconductor substrate, N-type and P-type field-effect transistors positioned in the semiconductor substrate. Each of the field-effect transistors includes a germanium nanowire, a III-V compound layer surrounding the germanium nanowire, a potential barrier layer mounted on the III-V compound layer, a gate dielectric layer, a gate, a source region and a drain region mounted on two sides of the gate. The field-effect transistor can produce two-dimensional electron gases and two-dimensional electron hole gases, and enhance the carrier mobility of the complementary metal-oxide-semiconductor field-effect transistor.

IPC Classes  ?

• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/786 - Thin-film transistors
• H01L 29/49 - Metal-insulator semiconductor electrodes
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The present invention relates to a method for preparing vacuum tube flash memory structure, to form a vacuum channel in the flash memory, and using oxide-nitride-oxide (ONO) composite materials as gate dielectric layer, wherein the nitride layer serves as a charge-trap layer to provide a blocking insulating between the gate electrode and the vacuum channel. The present structure exhibits superior program and erase speed as well as the retention time. It also provide with excellent gate controllability and negligible gate leakage current due to adoption ONO as the gate dielectric layer.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 27/11568 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region
• H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor

Abstract

Present embodiments provide for a FinFET and fabrication method thereof. The fabrication method includes two selective etching processes to form the channel. The FinFET includes a substrate, a shallow trench isolation (STI) layer, a buffer layer, a III-V group material, an oxide-isolation layer, a high-K dielectric layer and a conductor material. The STI is formed on the substrate with a trench. The buffer layer is formed on the substrate in the trench. The III-V group material is formed on the buffer layer in vertical stacked bowl shape. The oxide-isolation layer is formed between the substrate and the III-V group material. The high-K dielectric layer is formed on the STI layer and surrounding the III-V group material. The conductor material is formed surrounding the high-K dielectric layer.

IPC Classes  ?

• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/66 - Types of semiconductor device
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/51 - Insulating materials associated therewith
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups

Abstract

The present invention relates to a thermal processing method for wafer. A wafer is placed in an environment filled with a gas mixture comprising oxygen gas and deuterium gas, and a rapid thermal processing process is performed on a surface of the wafer. As a result, a denuded zone is formed on the surface of the wafer, deuterium atoms, which may be released to improve characteristics at an interface of semiconductor devices in a later fabrication process, are held in the wafer, and bulk micro-defects are formed far from the semiconductor devices.

IPC Classes  ?

• H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections

Abstract

This invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; irradiating the first semiconductor substrate via a ion beam for forming a doping layer to a pre-determined depth from a top surface of the first insulating layer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer at a deuterium atmosphere; separating a part of the first wafer from the second wafer; and forming a deuterium doped layer on the second wafer.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 29/34 - Semiconductor bodies having polished or roughened surface the imperfections being on the surface

Abstract

This invention provides a method for growing monocrystalline silicon by applying Czochralski method comprising forming a melt of silicon-containing materials in a crucible and pulling the melt for monocrystalline silicon growth, which is characterized by, the silicon-containing materials comprising a deuterium-implanted nitride-deposited silicon and a monocrystalline silicon, introducing a gas containing argon during formation of the melt, and, applying a magnetic field during the pulling step. This invention also provides a method for producing a wafer based on the above monocrystalline silicon.

IPC Classes  ?

• C30B 29/06 - Silicon
• C30B 15/00 - Single-crystal growth by pulling from a melt, e.g. Czochralski method
• C30B 15/20 - Controlling or regulating
• C30B 30/04 - Production of single crystals or homogeneous polycrystalline material with defined structure characterised by the action of electric or magnetic fields, wave energy or other specific physical conditions using magnetic fields

Abstract

The present invention relates to a method for preparing vacuum tube flash memory structure, to form a vacuum channel in the flash memory, and using oxide-nitride-oxide (ONO) composite materials as gate dielectric layer, wherein the nitride layer serves as a charge-trap layer to provide a blocking insulating between the gate electrode and the vacuum channel. The present structure exhibits superior program and erase speed as well as the retention time. It also provide with excellent gate controllability and negligible gate leakage current due to adoption ONO as the gate dielectric layer.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 27/11568 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region
• H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

The present invention relates to a thermal processing method for wafer. A wafer is placed in an environment filled with a non-oxygenated gas mixture comprising deuterium gas and at least one kind of low active gas, and a rapid heating processing process is performed on a surface of the wafer to heat the wafer to a predetermined high temperature. Then, the wafer is placed in an environment filled with an oxygenated gas mixture, and a rapid cooling processing process is performed on a surface of the wafer. As a result, a denuded zone is formed on the surface of the wafer, deuterium atoms, which may be released to improve characteristics at an interface of semiconductor devices in a later fabrication process, are held in the wafer, and bulk micro-defects are formed far from the semiconductor devices.

IPC Classes  ?

• H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

This invention provides a method for growing monocrystalline silicon by applying Czochralski method comprising forming a melt of silicon-containing materials in a crucible and pulling the melt for monocrystalline silicon growth, which is characterized by, introducing a gas containing argon during formation of the melt, and, applying a magnetic field during the pulling step. This invention also provides a method for producing a wafer based on the above monocrystalline silicon.

IPC Classes  ?

• B24B 7/22 - Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfacesAccessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
• C30B 15/22 - Stabilisation or shape controlling of the molten zone near the pulled crystalControlling the section of the crystal
• B24B 9/06 - Machines or devices designed for grinding edges or bevels on work or for removing burrsAccessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain
• C30B 15/04 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt adding doping materials, e.g. for n–p-junction
• C30B 15/20 - Controlling or regulating
• C30B 29/06 - Silicon
• C30B 30/04 - Production of single crystals or homogeneous polycrystalline material with defined structure characterised by the action of electric or magnetic fields, wave energy or other specific physical conditions using magnetic fields
• C30B 33/00 - After-treatment of single crystals or homogeneous polycrystalline material with defined structure

Abstract

Present embodiments provide for a complementary nanowire semiconductor device and fabrication method thereof. The fabrication method comprises providing a substrate, wherein the substrate has a NMOS active region, a PMOS active region and a shallow trench isolation (STI) region; forming a plurality of first hexagonal epitaxial wires on the NMOS active region and the PMOS active region by selective epitaxially growing a germanium (Ge) crystal material; selectively etching the substrate to suspend the pluralities of first hexagonal epitaxial wires on the substrate; forming a plurality of second hexagonal epitaxial wires on the NMOS active region by selective epitaxially growing a III-V semiconductor crystal material surrounding the pluralities of first hexagonal epitaxial wires on the NMOS active region; depositing a dielectric material on the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires, wherein the dielectric material covers the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires; and depositing a conducting material on the dielectric material for forming a gate electrode surrounding the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires, wherein the pluralities of first hexagonal epitaxial wires are a plurality of first nanowires and the pluralities of second hexagonal epitaxial wires are a plurality of second nanowires.

IPC Classes  ?

• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/786 - Thin-film transistors
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

Present embodiments provide for a complementary nanowire semiconductor device and fabrication method thereof. The fabrication method comprises providing a substrate, wherein the substrate has a NMOS active region, a PMOS active region and a shallow trench isolation (STI) region; forming a plurality of first hexagonal epitaxial wires on the NMOS active region and the PMOS active region by selective epitaxially growing a germanium (Ge) crystal material; selectively etching the substrate to suspend the pluralities of first hexagonal epitaxial wires on the substrate; forming a plurality of second hexagonal epitaxial wires on the NMOS active region by selective epitaxially growing a III-V semiconductor crystal material surrounding the pluralities of first hexagonal epitaxial wires on the NMOS active region; depositing a dielectric material on the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires, wherein the dielectric material covers the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires; and depositing a conducting material on the dielectric material for forming a gate electrode surrounding the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires, wherein the pluralities of first hexagonal epitaxial wires are a plurality of first nanowires and the pluralities of second hexagonal epitaxial wires are a plurality of second nanowires.

IPC Classes  ?

• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/786 - Thin-film transistors

Abstract

The present invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; implanting a deuterium and hydrogen co-doping layer at a certain pre-determined depth of the first wafer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer; separating a part of the first wafer from the second wafer; and forming a deuterium and hydrogen co-doping semiconductor layer on the second wafer.

IPC Classes  ?

• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 21/762 - Dielectric regions
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
• H01L 29/207 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
• H01L 29/227 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds further characterised by the doping material

Abstract

The present invention provides a method of manufacturing nanowire semiconductor device. In the active region of the PMOS the first nanowire is formed with high hole mobility and in the active region of the NMOS the second nanowire is formed with high electron mobility to achieve the objective of improving the performance of nanowire semiconductor device.

IPC Classes  ?

• H01L 21/283 - Deposition of conductive or insulating materials for electrodes
• H01L 29/66 - Types of semiconductor device
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/49 - Metal-insulator semiconductor electrodes
• H01L 29/51 - Insulating materials associated therewith
• H01L 29/786 - Thin-film transistors
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body

Abstract

The present invention provides a field effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first III-V compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first III-V compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first III-V compound layer. According to the present invention, the band width of the barrier layer is greater than that of the first III-V compound layer, and the band curvatures of the barrier layer and the first III-V compound layer are different, therefore, a two-dimensional electron gas (2DEG) is formed in the first III-V compound layer near the barrier layer boundary. Since the 2DEG has higher mobility, the performance of the filed effect transistor improved. Besides, the performance of the filed effect transistor also improved due to the structure is a gate-all-around structure.

IPC Classes  ?

• H01L 27/118 - Masterslice integrated circuits
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/786 - Thin-film transistors
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/51 - Insulating materials associated therewith
• H01L 29/49 - Metal-insulator semiconductor electrodes
• H01L 29/66 - Types of semiconductor device

Abstract

The present invention discloses a method of forming a high voltage junctionless device with drift region. The drift region formed between the semiconductor channel and the dielectric layer enables the high voltage junctionless device to exhibit higher punch-through voltages and high mobility with better performance and reliability.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds

Abstract

Present embodiments provide for a FinFET and fabrication method thereof. The fabrication method includes two selective etching processes to form the channel. The FinFET includes a substrate, a shallow trench isolation (STI) layer, a buffer layer, an III-V group material, a high-K dielectric layer and a conductor material. The STI is formed on the substrate with a trench. The buffer layer is formed on the substrate in the trench. The III-V group material is formed on the buffer layer in vertical stacked bowl shape. The high-K dielectric layer is formed on the STI layer and surrounding the III-V group material. The conductor material is formed surrounding the high-K dielectric layer as a gate electrode.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 29/66 - Types of semiconductor device

Abstract

A vertical transistor and the fabrication method. The transistor comprises a first surface and a second surface that is opposite to the first surface. A drift region of the first doping type, this drift region is located between the first surface and the second surface; at least one source region of the first doping type and the source region being located between the drift region and the first surface, with a first dielectric layer located between adjacent source regions; at least one drain region with said first doping type and said drain region being located between said drift region and said second surface, a gate being provided between adjacent drain regions. Said gate includes a gate electrode and a gate dielectric layer disposed between said gate electrode and said drift region, and the second dielectric layer being positioned between said gate electrode and said second surface.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/51 - Insulating materials associated therewith
• H01L 29/66 - Types of semiconductor device

Abstract

A method for making III-V-on-insulator on large-area Si Substrate wafer by confined epitaxial lateral overgrowth (CELO) has been disclosed. This method, based on selective epitaxy, starting from defining an epitaxy seed window to the Si substrate in a thermal oxide, from which the III-V material will grow.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/311 - Etching the insulating layers

Abstract

A structure and a method of fabrication are disclosed of a high voltage junctionless field effect device. A channel layer and a barrier layer are formed sequentially underneath the gate structure. The width of energy band gap of the barrier layer is wider than that of the channel layer. Thus the two dimensional electron gas (2-DEG) generated in the interface between the channel layer and the barrier layer of this junctionless field effect device has higher electron mobility. The structure of the device of this disclosure has a higher breakdown voltage which is advantageous for a high voltage junctionless field device. The structure offers advantages in device performance and reliability.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 27/108 - Dynamic random access memory structures
• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
• H01L 29/66 - Types of semiconductor device
• H01L 29/24 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups , ,  or
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 29/51 - Insulating materials associated therewith
• H01L 21/443 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
• H01L 29/49 - Metal-insulator semiconductor electrodes
• H01L 21/4763 - Deposition of non-insulating-, e.g. conductive-, resistive-, layers on insulating layersAfter-treatment of these layers
• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

Abstract

Embodiments provide a quantum well device and the method for forming this device with high mobility and higher punch through voltages. For forming the quantum well device, a buffer layer can be formed on a patterned substrate of a quantum well device. A fin-like structure can be formed through an etching process performed to the buffer layer. A quantum well layer, a barrier layer, a cover layer and a dielectric layer can be successively deposited on the buffer layer and surface of the fin-like structure. A metal layer can then be formed on the surface of the said dielectric layer. Metal gate electrode and gate dielectric layer can be formed on the metal layer and dielectric layer. The cover layer, the barrier layer and the quantum well can then be etched to form recessed source and drain regions. Such a quantum well device can have better performance and reliability.

IPC Classes  ?

• H01L 21/336 - Field-effect transistors with an insulated gate
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
• H01L 29/66 - Types of semiconductor device
• H01L 21/3065 - Plasma etchingReactive-ion etching
• H01L 21/311 - Etching the insulating layers
• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/15 - Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 29/49 - Metal-insulator semiconductor electrodes
• H01L 29/207 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
• H01L 21/8234 - MIS technology
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched

Abstract

The present invention provides a filed effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first III-V compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first III-V compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first III-V compound layer. According to the present invention, the band width of the barrier layer is greater than that of the first III-V compound layer, and the band curvatures of the barrier layer and the first III-V compound layer are different, therefore, a two dimensional electron gas (2DEG) is formed in the first III-V compound layer near the barrier layer boundary. Since the 2DEG has higher mobility, the performance of the filed effect transistor improved. Besides, the performance of the filed effect transistor also improved due to the structure is a gate-all-around structure.

IPC Classes  ?

• H01L 27/118 - Masterslice integrated circuits
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
• H01L 29/45 - Ohmic electrodes
• H01L 29/49 - Metal-insulator semiconductor electrodes
• H01L 29/786 - Thin-film transistors
• H01L 29/66 - Types of semiconductor device
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 21/283 - Deposition of conductive or insulating materials for electrodes

Abstract

A complementary metal-oxide-semiconductor field-effect transistor comprises a semiconductor substrate, N-type and P-Type field-effect transistors positioned in the semiconductor substrate. Each of the field-effect transistor includes a germanium nanowire, a III-V compound layer surrounding around the germanium nanowire, a potential barrier layer mounted on the III-V compound layer, a gate dielectric layer, a gate, a source region and a drain region mounted on two sides of the gate. The field-effect transistor can produce two-dimensional electron gases and two-dimensional electron hole gases, and enhance the carrier mobility of the complementary metal-oxide-semiconductor field-effect transistor.

IPC Classes  ?

• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/786 - Thin-film transistors
• H01L 29/49 - Metal-insulator semiconductor electrodes
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof