Abstract

An image processing method includes following operations: receiving a visible-light image; receiving an infrared image; determining a shooting scene according to the infrared image; determining whether to perform a high dynamic range processing on the visible-light image according to the shooting scene; and when it is determined to perform the high dynamic range processing on the visible-light image, generating and outputting a high dynamic range image for a back-end system to display.

IPC Classes  ?

• G06T 5/92 - Dynamic range modification of images or parts thereof based on global image properties
• G06T 5/50 - Image enhancement or restoration using two or more images, e.g. averaging or subtraction
• G06T 11/00 - 2D [Two Dimensional] image generation
• G06V 20/00 - ScenesScene-specific elements
• G06V 40/10 - Human or animal bodies, e.g. vehicle occupants or pedestriansBody parts, e.g. hands

Abstract

A synchronization method of image sensors includes: obtaining a first current time of a first current frame of a first image sensor; obtaining a first previous time of a first previous frame and a second current time of a second current frame of a second image sensor; calculating a first difference between the first current time and the second current time; calculating a second difference between the first current time and the first previous time; and adjusting a line length or a frame length of the second image sensor according to a first determination result of the first difference and the second difference to synchronize the first image sensor and the second image sensor.

IPC Classes  ?

• H04N 23/60 - Control of cameras or camera modules
• H04N 23/45 - Cameras or camera modules comprising electronic image sensorsControl thereof for generating image signals from two or more image sensors being of different type or operating in different modes, e.g. with a CMOS sensor for moving images in combination with a charge-coupled device [CCD] for still images

Abstract

A successive approximation register analog-to-digital converter includes a digital-to-analog conversion circuit. The digital-to-analog conversion circuit includes a first set of switches and a first capacitor group. The first capacitor group samples an analog input signal during a sampling period and receives a first set of reference signals through the first set of switches during a holding period so as to accomplish charge redistribution and thereby generate a sampling-and-switching operation result. The first capacitor group includes a first subsidiary capacitor group and a second subsidiary capacitor group. Each capacitor of the first subsidiary capacitor group is composed of one or more first unit capacitor(s). Each capacitor of the second subsidiary capacitor group is composed of one or more second unit capacitor(s). The layouts of the first and the second unit capacitors are different. The designed capacitance value of the second unit capacitor is greater than that of the first unit capacitor.

IPC Classes  ?

• H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter

Abstract

An analog-to-digital conversion apparatus having signal calibration mechanism is provided. Capacitors in an odd and an even conversion circuits in a conversion circuit are switched to perform conversion on a signal feeding to generate odd and even digital signals such that an odd and an even calibration circuit performs mapping thereon according to odd and even capacitance offset tables to generate odd and even calibrated signals. A digital filtering circuit performs digital filtering on the odd and the even calibrated signals according to odd and even filtering parameters and merges the filtered results to generate a merged output digital signal such that a calibration parameter calculation circuit performs filtering thereon to generate an odd and an even inverted error signal and further performs calculation thereon with the corresponding odd and even digital signals to generate odd and even updating parameter to update the odd and the even capacitance offset tables.

IPC Classes  ?

• H03M 1/10 - Calibration or testing
• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters

Abstract

A radar device includes a frequency modulated continuous wave (FMCW) generator, a radio frequency (RF) circuit, a computing circuit, and a coherent subtractor. The FMCW generator is configured to generate an FMCW signal. The RF circuit is configured to modulate the FMCW signal into an RF signal and demodulate a reflection signal reflected at a target from the RF signal, so as to obtain a received signal. The computing circuit is configured to reconstruct a short-range leakage signal according to the FMCW signal and an estimated channel coefficient, a delay coefficient, a phase coefficient, and an amplitude coefficient obtained in a short-range leakage estimation stage of the radar device. The coherent subtractor is configured to compensate the received signal by the reconstructed short-range leakage signal.

IPC Classes  ?

• G01S 7/35 - Details of non-pulse systems
• G01S 7/02 - Details of systems according to groups , , of systems according to group

Abstract

A multiple charging path control device includes: first and second charging paths, respectively utilized for selectively providing first and second charging currents from first and second power sources to an electronic device based on first and second path switching signals; first and second path control circuits, respectively utilized for generating the first and second path switching signals based on at least first and second path main control signals; and a control signal generation unit utilized for generating the first and second path main control signals and adjusting the first and second path main control signals according to connection status of power sources and the electronic device. When the first power source is coupled to the electronic device, the control signal generation unit asserts the first path main control signal to enable the first charging path and disable the second charging path.

IPC Classes  ?

• H02J 1/08 - Three-wire systemsSystems having more than three wires
• H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries

Abstract

A hub includes a first up-stream port (USP), a second USP, a down-stream port (DSP), a first control unit, and a second control unit. The first USP is configured to connect to a first electronic device. The second USP is configured to connect to a second electronic device. The DSP is configured to connect to a third electronic device. The first control unit is connected to the first USP and the DSP, to select whether to bring the DSP into data communication with the first USP. The second control unit is connected to the second USP and the DSP, to select whether to bring the DSP into data communication with the second USP.

IPC Classes  ?

• G06F 13/40 - Bus structure

Abstract

A voltage calibration circuit arranged in a chip and comprising a voltage monitor circuit, a calibration circuit and a storage circuit is provided. The voltage monitor circuit is coupled to at least one power management unit of the chip and configured to: calculate a voltage-code graph based on a received reference voltage and a received divided voltage; and output at least one output code based on the voltage-code graph and at least one output voltage received from the power management unit(s). The calibration circuit is coupled to the voltage monitor circuit and the power management unit(s), and configured to receive the output code(s) and adjust an output level of the power management unit(s) based on the output code(s) and a target code. The storage circuit is coupled to the calibration circuit, and configured to store the voltage-code graph and the output level of the power management unit(s).

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• G01R 17/02 - Arrangements in which the value to be measured is automatically compared with a reference value

Abstract

A transistor-cascaded circuit is provided. The transistor-cascaded circuit includes a first transistor, a second transistor, a level shifter and an alternating current (AC) signal enhancement circuit. The level shifter is configured to receive a first input signal of a pair of differential input signals and shift the first input signal to a shifted bias voltage level, in order to generate a shifted input signal to at least one of a gate terminal of the first transistor and a gate terminal of the second transistor. In addition, the AC signal enhancement circuit is configured to enhance an AC signal of the shifted input signal according to a voltage difference between the first input signal and a second input signal of the pair of differential input signals. More particularly, one of the first transistor and the second transistor is an N-type transistor, and the other one is a P-type transistor.

IPC Classes  ?

• H03F 3/04 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
• H03K 19/0175 - Coupling arrangementsInterface arrangements

Abstract

A method for processing audio data and an audio data processing system are provided. The method is operated between a transmitter and a receiver. The transmitter receives audio data, and forms a data set that includes multiple data points. The data points are rearranged in an interlaced manner, and are packetized to form multiple groups of network packets. The network packets are assigned with sequence-identifiable numbers according to a formation sequence. Further, delays can be added in between different groups of the network packets, and then the network packets are rearranged. The multiple groups of the network packets are transmitted to the receiver after data rearrangement, packetization, and packet rearrangement. The receiver then de-packetizes the network packets, and performs data recovery with error handling, so as to generate output audio data.

IPC Classes  ?

• H04L 49/55 - Prevention, detection or correction of errors
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received
• H04L 49/9057 - Arrangements for supporting packet reassembly or resequencing

Abstract

A display device includes at least one video connection terminal, a display screen, a memory, and a processing circuit. The video connection terminal is arranged to receive at least one video source from at least one device. The display screen is arranged to display at least one divided frame corresponding to the device on an original frame corresponding to the display device. The memory is arranged to store a program code. The processing circuit is arranged to read and execute the program code from the memory, in order to share resources in the divided frame between the display device and the device according to a user input.

IPC Classes  ?

• G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
• G06F 3/14 - Digital output to display device
• G06F 9/54 - Interprogram communication

Abstract

A method of using optimized pitch for installing a processing circuit at a printed circuit board (PCB) and associated apparatus are provided. The method may include: providing a set of first terminals on a predetermined surface of a package of the processing circuit, the set of first terminals corresponding to a set of first pads within a first sub-region of a predetermined installation region of the PCB, where a first pitch of the set of first terminals along a predetermined direction is equal to a first predetermined value; and providing a set of second terminals on the predetermined surface of the package of the processing circuit, the set of second terminals corresponding to a set of second pads within a second sub-region of the predetermined installation region, where a second pitch of the set of second terminals along the predetermined direction is equal to a second predetermined value.

IPC Classes  ?

• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H01L 23/498 - Leads on insulating substrates
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits

Abstract

A semiconductor capacitor structure includes a part on a routing-direction-non-turnable metal layer and a part on a routing-direction-turnable metal layer. The semiconductor capacitor structure includes: a first electrode unit layout located on the routing-direction-non-turnable metal layer, wherein all metal traces of the first electrode unit layout are parallel to a first direction; a second electrode unit layout located on the routing-direction-turnable metal layer, wherein each of a first potential part and a second potential part of the second electrode unit layout includes metal lines parallel to the first direction and metal lines parallel to a second direction; and a dielectric located between the first and the second potential parts of the second electrode unit layout, wherein at least a part of the metal traces of the first electrode unit layout is coupled to the first potential part of the second electrode unit layout through at least one via.

IPC Classes  ?

• H10D 1/68 - Capacitors having no potential barriers

Abstract

A wireless communication device includes a buffer memory and a media access control (MAC) circuit. The MAC circuit is coupled to the buffer memory, and is configured to divide the buffer memory according to system information messages required by the wireless communication device, such that the buffer memory includes hybrid automatic repeat request (HARQ) buffer blocks, and assign HARQ processes for the system information messages required by the wireless communication device, so as to receive the system information message in parallel from a base station in a Narrowband Internet of Things (NB-IoT) downlink scheduling period, in which the HARQ processes respectively correspond to the HARQ buffer blocks.

IPC Classes  ?

• H04L 1/1812 - Hybrid protocolsHybrid automatic repeat request [HARQ]
• H04W 72/1273 - Mapping of traffic onto schedule, e.g. scheduled allocation or multiplexing of flows of downlink data flows

Abstract

A fingerprint data processing method is used for a wireless communication system including a host device and a wireless device, which communicate through a wireless communication interface. The method includes steps of: generating, by the host device, a fingerprint recognition command; driving, by the host device, a first wireless communication circuit to transmit a fingerprint recognition request to the wireless device through the wireless communication interface according to the fingerprint recognition command; receiving, by the wireless device, the fingerprint recognition request through the wireless communication interface, and obtaining, by the wireless device, fingerprint data according to the fingerprint recognition request; driving, by the wireless device, a second wireless communication circuit to transmit the fingerprint data to the host device through the wireless communication interface. The wireless communication interface forwards at least one of the fingerprint recognition request and the fingerprint data using an encrypted communication protocol.

IPC Classes  ?

• G06V 40/50 - Maintenance of biometric data or enrolment thereof
• G06V 10/74 - Image or video pattern matchingProximity measures in feature spaces
• G06V 10/94 - Hardware or software architectures specially adapted for image or video understanding
• G06V 40/12 - Fingerprints or palmprints
• H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
• H04W 12/03 - Protecting confidentiality, e.g. by encryption
• H04W 12/06 - Authentication

Abstract

A method and a system for automated speaker enrollment are provided. In the method, a camera is used to capture image data so that a facial position of a person can be recognized, a microphone array is used to generate speech data, and a sound localization technology is used to estimate a sound source direction. A target speaker can be determined by matching the facial position and the direction toward the sound source, and more particularly whether the target speaker is within a valid geometric range. After that, the speech produced by the target speaker along a target speaker direction is recorded, and the speech can be enhanced for generating speaker features with respect to the target speaker for enrolling to a specific system.

IPC Classes  ?

• G10L 17/04 - Training, enrolment or model building
• G06T 7/521 - Depth or shape recovery from laser ranging, e.g. using interferometryDepth or shape recovery from the projection of structured light
• G06T 7/55 - Depth or shape recovery from multiple images
• G06T 7/70 - Determining position or orientation of objects or cameras
• G06V 40/16 - Human faces, e.g. facial parts, sketches or expressions
• G10L 17/02 - Preprocessing operations, e.g. segment selectionPattern representation or modelling, e.g. based on linear discriminant analysis [LDA] or principal componentsFeature selection or extraction
• G10L 17/18 - Artificial neural networksConnectionist approaches
• G10L 25/78 - Detection of presence or absence of voice signals
• G10L 25/90 - Pitch determination of speech signals

Abstract

A wireless communication device includes a communication module and a processor. The communication module is configured to perform radio frequency signal transmissions and receptions. The processor is coupled to the communication module and is configured to perform the following operations: performing a channel sounding procedure with another wireless communication device and receiving a channel quality indicator (CQI) feedback of 26-tone resources units in a resource unit (RU) structure from the another wireless communication device through the communication module; and performing an RU allocation on the another wireless communication device according to average signal-to-noise ratios (SNRs) in the CQI feedback, including determining a selected RU, a modulation and coding scheme (MCS) index, and a number of spatial streams for being allocated to the another wireless communication device.

IPC Classes  ?

• H04W 72/542 - Allocation or scheduling criteria for wireless resources based on quality criteria using measured or perceived quality
• H04W 72/04 - Wireless resource allocation

Abstract

A WiFi radar communication circuit includes a radio frequency front-end circuit, an analog-to-digital converter, and a digital signal processor. The radio frequency front-end circuit is coupled to a transmitting antenna and a receiving antenna for transmitting a radar frame and receiving reflected echoes. The analog-to-digital converter is configured to convert the reflected echoes into radar echo digital signals. The digital signal processor is configured to operate an interference detector. The interference detector is configured to determine whether each reflected chirp among the reflected chirps is subject to interference based on a cumulative power difference between adjacent reflected chirps. The interference detector is further configured to determine whether the radar frame is subject to interference based on a statistical result of whether the reflected chirps are subject to interference. Accordingly, interference detection results for the radar frame and the reflected chirps are generated.

IPC Classes  ?

• G01S 7/35 - Details of non-pulse systems
• G01S 7/40 - Means for monitoring or calibrating

Abstract

A WiFi radar control method includes following steps. In a first radar transceiving slot, first radar frames are sequentially transmitted, and first reflections corresponding to the first radar frames are received. Waveforms of the first reflections are analyzed to determine whether the first radar frames are subject to interference. When interference is detected in the first radar frames, a retry count is incremented. When the retry count is not zero, at least one retry radar frame is transmitted in the first radar transceiving slot or in a second radar transceiving slot following the first radar transceiving slot.

IPC Classes  ?

• G01S 13/02 - Systems using reflection of radio waves, e.g. primary radar systemsAnalogous systems
• G01S 13/90 - Radar or analogous systems, specially adapted for specific applications for mapping or imaging using synthetic aperture techniques

Abstract

A multi-instance single loop topology adjustment method and network switch are provided. The single loop networks of each instance have distinct back-up ports, defaulted to a blocking state. Thus, when abnormalities occur in a link of the single loop network, the topology of each instance is adjusted by changing the back-up ports of each instance to a forwarding state.

IPC Classes  ?

• H04L 41/12 - Discovery or management of network topologies
• H04L 41/0654 - Management of faults, events, alarms or notifications using network fault recovery

Abstract

A calculation device and a calculation method are provided. The calculation method includes: selecting, by a selection unit, at least one first element from a one-axis tensor which satisfies a selection condition; selecting and loading, by a control unit, at least one second element from a two-axis tensor based on an operation between the two-axis tensor and the one-axis tensor and at least one position of the at least one first element in the one-axis tensor; and obtaining and outputting, by a calculation unit, an operation result corresponding to the operation between the two-axis tensor and the one-axis tensor based on the at least one first element and the at least one second element.

IPC Classes  ?

• G06F 17/16 - Matrix or vector computation

Abstract

A bandgap voltage reference circuit comprises a current mirror circuit, a first sub-circuit and an output circuit. The current mirror circuit is coupled between an input source and a ground, is configured to generate a first current, and comprises first and second bipolar junction transistors (BJTs) and a first resistor. The two BJTs' bases are coupled together. The first resistor is coupled between the first BJT's emitter and the ground. The first sub-circuit comprises a transistor coupled to the first BJT's base and collector, comprises a second resistor coupled between the transistor and the ground, and is configured to generate a second current based on the second resistor and a base-emitter potential difference of the second BJT. The output circuit is coupled between the input source and the ground, and is configured to generate an output reference voltage based on the first, second currents and a third resistor.

IPC Classes  ?

• G05F 3/22 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations wherein the transistors are of the bipolar type only
• G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC

Abstract

The present disclosure discloses an oscillating circuit having a temperature compensation mechanism. A NAND gate receives an input signal transiting from a low state level to a maintaining high state to initialize an oscillating behavior and a delayed control signal to generate an output oscillating signal. A first inverter having a negative temperature coefficient resistance inverts the output oscillating signal to generate an inverted output oscillating signal to be received and delayed by a RC delay circuit, including an oscillating resistor having a positive temperature coefficient resistance and an oscillating capacitor to generate a delayed and inverted control signal. A second inverter inverts the delayed and inverted control signal to generate a delayed control signal. A third inverter inverts the output oscillating signal to generate a final oscillating signal. The negative temperature coefficient resistance and the positive temperature coefficient resistance together determine an oscillating circuit temperature coefficient.

IPC Classes  ?

• H03K 5/134 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices with field-effect transistors
• H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass

Abstract

An audio system control method, comprising: (a) establishing an OOB wireless communication channel between a first audio playing device and a second audio playing device; (b) computing a first time difference between a current time point and a first expected playing time point, when the first audio playing is ready to play the audio data; (c) sending a ready notification to the second audio playing device through the OOB wireless communication channel if the current time point is before the first expected playing time point; (d) sending a start playing notification to notify the first audio playing device to start playing, if the second audio playing device has received the ready notification, has received the audio data output by the audio source device and is ready to play the audio data; and (e) playing the audio data after the first audio playing device receiving the start playing notification.

IPC Classes  ?

• H04R 3/12 - Circuits for transducers for distributing signals to two or more loudspeakers

Abstract

A multi-instance single loop topology adjustment method and network switch are provided. The single loop networks of each instance have distinct back-up ports, defaulted to a blocking state. Thus, when abnormalities occur in a link of the single loop network, the topology of each instance is adjusted by changing the back-up ports of each instance to a forwarding state.

IPC Classes  ?

• H04L 41/12 - Discovery or management of network topologies
• H04L 41/0654 - Management of faults, events, alarms or notifications using network fault recovery

Abstract

A multi-link device includes a multi-link controller, and first and second MAC controllers. The first MAC controller includes a first link queue to buffer a first set of packets from the common queue. The second MAC controller includes a second link queue to buffer a second set of packets from the common queue. In response to the first MAC controller being granted a first transmission opportunity of a first link, and the second MAC controller not being granted a second transmission opportunity of a second link, the multi-link controller determines whether to enable a link redirect mode according to an aspect of the second set of packets. In response to the link redirect mode being enabled, the first MAC controller receives a packet in the second set of packets from the second link queue, and transmits the packet in the second set of packets via the first link.

IPC Classes  ?

• H04W 74/0816 - Non-scheduled access, e.g. ALOHA using carrier sensing, e.g. carrier sense multiple access [CSMA] with collision avoidance
• H04W 48/02 - Access restriction performed under specific conditions
• H04W 88/12 - Access point controller devices

Abstract

A deep learning accelerator includes a controller circuit, a processing elements (PE) array circuit, and a memory access circuit. The controller circuit generates a control signal according to traffic data. The PE array circuit operates a neural network model. A layer computation of the neural network model includes first and second paths, and the PE array circuit selects a path from the first and second paths according to the control signal to execute the layer computation via the selected path. The PE array circuit accesses a memory circuit via the memory access circuit to execute the layer computation. When the layer computation is executed via the first path, the PE array circuit accesses the memory circuit with first bandwidth. When the layer computation is executed via the second path, the PE array circuit accesses the memory circuit with second bandwidth. The first bandwidth is higher than the second bandwidth.

IPC Classes  ?

• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Abstract

The present disclosure an electronic apparatus having firmware overlay mechanism. A shared section of firmware and a first version section of the firmware corresponding to the first version firmware are retrieved from a firmware storage terminal to a memory circuit of a memory by a processing circuit. An address redirection process is performed on the first version firmware by an address decoding circuit of the memory to redirect first access addresses to physical addresses of the memory circuit. The first version firmware is executed through the address decoding circuit. A firmware version switching process is performed to retrieve a second version section of the firmware corresponding to the second version firmware to the memory circuit. The address re-defined process is performed on the second version firmware to redirect second access addresses to the physical addresses of the memory circuit. The second version firmware is executed through the address decoding circuit.

IPC Classes  ?

• G06F 8/71 - Version control Configuration management
• G06F 9/32 - Address formation of the next instruction, e.g. by incrementing the instruction counter
• G06F 11/362 - Debugging of software

Abstract

An integrated transformer, substantially symmetrical about an axis of symmetry, having first to fourth terminals and including primary and secondary coils and first and second crossing structures. The primary coil, whose two terminals are the first and second terminals, includes a first trace. The secondary coil, whose two terminals are the third and fourth terminals, includes a second trace and a third trace. The first crossing structure is formed by the second trace and a first portion of the first trace. The second crossing structure is formed by the third trace and a second portion of the first trace. The first and second terminals are on two sides of the axis of symmetry. The third and fourth terminals are on two sides of the axis of symmetry. The first and second crossing structures are substantially symmetrical about the axis of symmetry.

IPC Classes  ?

• H01F 27/28 - CoilsWindingsConductive connections
• H01F 19/00 - Fixed transformers or mutual inductances of the signal type
• H03H 7/42 - Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns

Abstract

A method for intelligent posture detection, an intelligent posture detection apparatus, and a circuit system are provided. The circuit system is disposed in the intelligent posture detection apparatus, and the method is performed in the circuit system. In the method, the circuit system retrieves an image from an image-retrieval circuit, and operates an intelligence model by an operating circuit for determining an object window that covers an object in the image and multiple key points of the object. Next, a first correlation among a whole or part of the key points of a current posture of the object, and a second correlation between the object window and the whole or part of the key points are established. The first correlation, the second correlation, and/or geometric information of the object window can be referred to for determining whether or not the current posture of the object is poor.

IPC Classes  ?

• G06T 7/73 - Determining position or orientation of objects or cameras using feature-based methods
• G06V 10/44 - Local feature extraction by analysis of parts of the pattern, e.g. by detecting edges, contours, loops, corners, strokes or intersectionsConnectivity analysis, e.g. of connected components
• G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects

Abstract

A video super resolution system includes a motion estimation device, a warping device, and a neural network super resolution (NNSR) device. The motion estimation device calculates an optical flow according to a current frame and a previous frame. The warping device executes a warping process to the previous frame and a previous output to generate a warping frame and a warping output. The NNSR device executes a feature extraction to the current frame, the warping frame, the warping output, and a count value to generate at least one feature, executes a deep learning process to the at least one feature and a previous hidden state to generate a current hidden state and a deep learning result, and executes the feature extraction to the deep learning result to generate a current output. The NNSR device stores the current frame, the current hidden state, and the current output to a memory.

IPC Classes  ?

• G06T 3/4046 - Scaling of whole images or parts thereof, e.g. expanding or contracting using neural networks
• G06T 3/18 - Image warping, e.g. rearranging pixels individually
• G06T 3/4053 - Scaling of whole images or parts thereof, e.g. expanding or contracting based on super-resolution, i.e. the output image resolution being higher than the sensor resolution
• G06T 7/269 - Analysis of motion using gradient-based methods

Abstract

The present invention provides an impedance calibration method of a RF transmitter, wherein the impedance calibration method includes the steps of: (a) generating a two-tone test signal to the RF transmitter to generate a RF signal; (b) calculating a IMD3 according to the RF signal; (c) calculating a IMD3 difference between the IMD3 and a default IMD3; and (d) if the IMD3 difference is not less than a threshold value, tuning an impedance of the RF transmitter, and repeating step (b) and step (c), until the IMD3 difference is less than the threshold value.

IPC Classes  ?

• H04B 17/13 - MonitoringTesting of transmitters for calibration of power amplifiers, e.g. of gain or non-linearity
• H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages

Abstract

An operation method of a router which switches between a first network and a second network includes the following steps: advertising a packet including a network duration and a network switching period. The network duration represents a first duration for which the router continuously operates in the first network. The network switching period is substantially equal to the first duration plus a second duration for which the router continuously operates in the second network.

IPC Classes  ?

• H04L 45/02 - Topology update or discovery
• H04L 45/122 - Shortest path evaluation by minimising distances, e.g. by selecting a route with minimum of number of hops

Abstract

A signal conflict detecting method, which comprises: (a) the signal transceiving device performing a first detecting operation to detect whether a signal conflict may occur in a target frequency band; (b) the signal transceiving device transmitting a target signal if the signal conflict will not occur in the target frequency band; (c) the signal transceiving device performing a second detecting operation to detect whether the signal conflict may occur in the target frequency band, after transmitting the target signal in the step (b); (d) the signal transceiving device performing a third detecting operation to detect whether the signal conflict may occur in the target frequency band, if the step (c) determines that the signal conflict may occur in the target frequency band; and (e) the signal transceiving device retransmitting the target signal if the step (d) determines that the signal conflict will not occur in the target frequency band.

IPC Classes  ?

• G01S 7/02 - Details of systems according to groups , , of systems according to group

Abstract

An electrical connector for reducing electromagnetic interference (EMI) and an associated wireless communication device are provided. The electrical connector includes multiple metal terminals, a plastic component, a wave absorbing material and a metal shell. The multiple metal terminals are configured to transmit at least one pair of differential signals from a host device to a wireless communication circuit via a printed circuit board (PCB). The plastic component is configured to fix positions of the multiple metal terminals in the electrical connector. The wave absorbing material is configured to absorb an electromagnetic wave signal sent from the multiple metal terminals. The metal shell is configured to cover the multiple metal terminals, the plastic component and the wave absorbing material. More particularly, the wave absorbing material overlaps at least a portion of the plastic component.

IPC Classes  ?

• H01R 12/71 - Coupling devices for rigid printing circuits or like structures
• H01R 4/02 - Soldered or welded connections
• H01R 13/6461 - Means for preventing cross-talk
• H01R 13/6581 - Shield structure

Abstract

A phase interpolation circuit for generating a phase interpolation signal, comprising: a capacitor; a first charging circuit for selectively charging the capacitor according to a first clock signal and a first weighting control code; a second charging circuit for selectively charging the capacitor according to a second clock signal and a second weighting control code; a first discharge circuit for selectively discharging the capacitor according to the first clock signal and a third weighting control code; and a second discharge circuit for selectively discharging the capacitor according to the second clock signal and a fourth weighting control code. The first, second, third and fourth weighting control codes respectively control the weightings of the first clock signal and the second clock signal in the phase interpolation signal.

IPC Classes  ?

• H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
• H03K 5/08 - Shaping pulses by limiting, by thresholding, by slicing, i.e. combined limiting and thresholding

Abstract

A method and a packet detector for detecting a target detection packet are provided. The method includes: utilizing a match filter of the packet detector to perform match filtering on an input signal based on a reference sequence in order to generate a match filtering output, where the reference sequence corresponds to the target detection packet; utilizing a post-calculation circuit of the packet detector to perform calculation on the match filtering output to generate a calculation result; utilizing a comparator of the packet detector to compare the calculation result with a predetermine threshold to generate a comparison result; and determining whether the input signal is the target detection packet or not according to the comparison result.

IPC Classes  ?

• H04L 43/16 - Threshold monitoring
• H04L 27/26 - Systems using multi-frequency codes

Abstract

A package structure includes a first substrate, a die, a molding layer, a second substrate, vias, and a heat-dissipation layer. The first substrate has first lower contacts on its lower surface, and the first substrate has first upper contacts on its upper surface and electrically connected to the first lower contacts. A die is electrically connected to the first upper contacts. The molding layer laterally encapsulates the die. The second substrate on the molding layer has second upper contacts on its upper surface, and the second substrate has second lower contacts on its lower surface and electrically connected to the second upper contacts. Each of the vias is in the molding layer to electrically connect the first upper contacts and the second lower contacts. The heat-dissipation layer is on the die. The upper surface of the second substrate is higher or lower than an upper surface of the heat-dissipation layer.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/498 - Leads on insulating substrates
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

Abstract

A WPT circuit is provided. The WPT circuit includes a radio frequency (RF) front-end circuit, a power path circuit, an auxiliary path circuit, a control circuit and a switch circuit. The RF front-end circuit is configured to convert a single-end input signal received by an antenna into differential input signals. The power path circuit is configured to convert the differential input signals into a direct current (DC) output voltage. The auxiliary path circuit is configured to convert the differential input signals into a DC supply voltage. The control circuit is configured to utilize the DC supply voltage as a power source and generate a control signal according to the DC output voltage. The switch circuit is configured to determine whether to conduct the DC output voltage to the energy storage element according to the control signal.

IPC Classes  ?

• H02J 50/20 - Circuit arrangements or systems for wireless supply or distribution of electric power using microwaves or radio frequency waves
• H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• H02J 7/34 - Parallel operation in networks using both storage and other DC sources, e.g. providing buffering
• H02J 50/00 - Circuit arrangements or systems for wireless supply or distribution of electric power
• H02M 1/00 - Details of apparatus for conversion
• H02M 1/44 - Circuits or arrangements for compensating for electromagnetic interference in converters or inverters

Abstract

A voltage detection circuit is provided. A first and a second detection inverters of a detection circuit outputs an inverted detection signal and an output detection signal to a first and a second detection output terminals. A feedback detection circuit outputs an inverted feedback detection signal. A first transistor is coupled between the first detection output terminal and a ground terminal. A second transistor is coupled between the second detection output terminal and a first gate. A second gate is controlled by the inverted feedback detection signal. A third transistor is coupled between the first gate and the ground terminal. A third gate is controlled by the inverted feedback detection signal. The detection signal at a high state makes the inverted feedback detection signal turn on the second transistor and turn off the third transistor such that the first transistor turns on.

IPC Classes  ?

• H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]

Abstract

A voice scoring system is configured to be computed through a processing unit to execute: transforming an audiovisual audio of an audiovisual data and a user audio into a spectral intensity of the audiovisual data and a spectral intensity of the user audio respectively through a transformation module; separating the spectral intensity of the audiovisual audio into a spectral intensity of an accompaniment audio and a spectral intensity of a singer audio through an audio separation module; analyzing the spectral intensity of the singer audio and the spectral intensity of the user audio to obtain a singer pitch and a user pitch through a pitch analysis module; and in real time comparing whether the user pitch is close to the singer pitch to calculate a user score through the score calculation module. A karaoke device having the voice scoring system is also provided.

IPC Classes  ?

• G10H 1/00 - Details of electrophonic musical instruments
• G09B 15/00 - Teaching music
• G10H 1/36 - Accompaniment arrangements
• G10L 21/0308 - Voice signal separating characterised by the type of parameter measurement, e.g. correlation techniques, zero crossing techniques or predictive techniques
• G10L 25/18 - Speech or voice analysis techniques not restricted to a single one of groups characterised by the type of extracted parameters the extracted parameters being spectral information of each sub-band
• G10L 25/30 - Speech or voice analysis techniques not restricted to a single one of groups characterised by the analysis technique using neural networks

Abstract

A communication device includes a transmitting circuit, for transmitting at least one first packet to other communication device in at least one first interval, and for transmitting at least one of at least one first channel reservation signal and at least one second channel reservation signal to the another communication device in the at least one first interval; and a receiving circuit, for receiving at least one second packet from the other communication device in at least one second interval; wherein the at least one first interval and the at least one second interval are staggered and do not overlap with each other.

IPC Classes  ?

• H04W 74/0816 - Non-scheduled access, e.g. ALOHA using carrier sensing, e.g. carrier sense multiple access [CSMA] with collision avoidance
• H04W 28/26 - Resource reservation
• H04W 74/08 - Non-scheduled access, e.g. ALOHA

Abstract

An electronic device includes a first functional circuit, a second functional circuit, a memory, and a clock asynchronous processor. The first functional circuit operates at a first clock and generates a read command. The second functional circuit operates at a second clock. The memory is coupled to the first functional circuit and the second functional circuit. The clock asynchronous processor is coupled to the first functional circuit and the memory and configured to check, according to the first clock and the second clock, whether the read command exists. When the read command exists, the clock asynchronous processor provides the read command to the memory.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

The present invention discloses a chipset apparatus communication method that includes steps outlined below. A processor connection terminal having a total bandwidth is coupled to a processor. External apparatus connection terminals are coupled to external apparatuses. Individual packet transmission amounts and a total packet transmission amount of the external apparatus connection terminals between a first time point and a second time point are calculated, in which the external apparatus connection terminals have original bandwidth proportions. Amount ratios each between one of the individual packet transmission amounts and the total packet transmission amount are calculated. Weighting calculation is performed on the original bandwidth proportions and the amount ratios to generate un-normalized updated bandwidth proportions to be normalized to generate updated bandwidth proportions corresponding to the second time point. The total bandwidth is distributed according to the updated bandwidth proportions such that the external apparatus performs data transmission accordingly.

IPC Classes  ?

• G06F 13/38 - Information transfer, e.g. on bus

Abstract

A wireless transceiver device includes a communication module and a processor. The processor is used for performing the following operations: determining whether to perform an active spatial reuse transmission when detecting an overlapping basic service set packet; entering a backoff phase when determining that the active spatial reuse transmission is to be performed; pausing the backoff phase when detecting a data packet of which a destination is the wireless transceiver device before the backoff phase ends, and receiving the data packet; determining a lower one of a minimum transmission power of a response frame in response to the data packet and an active transmission power corresponding to the wireless transceiver device as a passive transmission power of the response frame; and transmitting the response frame with the passive transmission power in a short inter-frame space after the data packet is received.

IPC Classes  ?

• H04W 74/0833 - Random access procedures, e.g. with 4-step access
• H04L 5/00 - Arrangements affording multiple use of the transmission path
• H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets

Abstract

A non-volatile memory device includes a non-volatile memory, a random number generator, a power supply, and a memory access controller. The non-volatile memory is configured to store at least one data. The random number generator is configured to generate a random number. The power supply is configured to generate a random power according to the random number, and provide the random power to the non-volatile memory. The memory access controller is configured to generate a random sequence according to the random number, obtain a random sequence data from the non-volatile memory according to the random sequence, and reconstruct the random sequence data according to the random sequence to generate the at least one data.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

An inquirer-side circuit of an automotive Ethernet system includes: a hybrid circuit arranged to operably couple with an MDI circuit to conduct data communication with a respondent-side circuit; a transmitting circuit coupled with a hybrid circuit and arranged to operably generate and provide a transmission signal to the hybrid circuit; a receiving circuit coupled with the hybrid circuit and arranged to operably receive and parse a received signal transmitted from the hybrid circuit to generate a data signal; a processing circuit coupled with the receiving circuit and arranged to operably process the data signal; a physical coding sublayer circuit coupled with the processing circuit and arranged to operably control the operations of the transmitting circuit; and an echo cancellation circuit coupled between the transmitting circuit and the receiving circuit, and arranged to operably generate an echo cancellation signal.

IPC Classes  ?

• H04B 3/23 - Reducing echo effects or singingOpening or closing transmitting pathConditioning for transmission in one direction or the other using a replica of transmitted signal in the time domain, e.g. echo cancellers
• H04B 1/40 - Circuits

Abstract

A method for operating a card reader is provided. The card reader is part of an electronic device. The method includes the following steps: executing a plurality of pieces of code or program instructions to detect a state of the electronic device; and controlling the card reader to operate in a target power-saving mode according to the state.

IPC Classes  ?

• G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system
• G06F 1/3212 - Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level
• G06F 1/3218 - Monitoring of peripheral devices of display devices
• G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage

Abstract

An electronic device and a clock jitter analysis method are provided. The electronic device includes a storage device and a processing device. The processing device is configured to: read timing simulation information and voltage drop information of a plurality of clock paths from the storage device; obtain a maximum voltage drop and a minimum voltage drop of each clock path based on the voltage drop information; perform a first static timing analysis (STA) with the maximum voltage drop based on the timing simulation information, to obtain a first timing report; perform a second STA with the minimum voltage drop based on the timing simulation information, to obtain a second timing report; calculate time information corresponding to each clock path based on the first timing report and the second timing report; and select largest time information of the plurality of pieces of time information as a clock jitter.

IPC Classes  ?

• G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom

Abstract

A media access control address table updating device is provided. The device includes a processor, a storage, a learning controller, a packet generator, and a traffic manager. The traffic manager determines whether to generate a first back pressure signal based on a current traffic corresponding to a plurality of queues. In response to determining that the first back-pressure signal is generated, the traffic manager transmits the first back-pressure signal to the packet generator. In response to receiving the first back pressure signal from the traffic manager, the packet generator stops generating a notification packet corresponding to a notification event.

IPC Classes  ?

• H04L 47/30 - Flow controlCongestion control in combination with information about buffer occupancy at either end or at transit nodes
• H04L 47/12 - Avoiding congestionRecovering from congestion
• H04L 69/324 - Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC

Abstract

The present disclosure discloses an access point communication method having dynamic channel selection mechanism used in an access point apparatus that includes steps outlined below. A wireless communication is performed with a station apparatus through a neighboring relay access point apparatus. Communication parameters related to the wireless communication are collected periodically. A required data flow amount of the station apparatus is calculated according to the communication parameters and available data flow amounts of wireless channels between the access point apparatus and the relay access point apparatus are calculated. Ratios between the required data flow amount and the available data flow amounts are calculated as channel crowding parameters. One of the wireless channels corresponding to one of the channel crowding parameters having a smallest value is selected to be a selected wireless channel to perform packet transmission to the station apparatus through the relay access point apparatus.

IPC Classes  ?

• H04W 28/02 - Traffic management, e.g. flow control or congestion control
• H04W 88/08 - Access point devices

Abstract

A media docking device includes an input interface controller, an output interface controller, and a processor. The input interface controller is connected to a media source device. The output interface controller is connected to media player devices and obtains device data of each media player device. The processer calculates a display bandwidth required by each media player device to display image based on the device data, and sums the display bandwidths of the media player devices to obtain a total display bandwidth. The processor determines an optimal support mode for connecting a video interface unit of the input interface controller to the media source device based on the total display bandwidth. A transmission bandwidth corresponding to the optimal support mode is greater than the total display bandwidth, and a difference between the transmission bandwidth and the total display bandwidth is less than a threshold.

IPC Classes  ?

• G09G 5/00 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators

Abstract

An inquirer-side circuit of an automotive Ethernet system includes: a hybrid circuit arranged to operably conduct data communication with a respondent-side circuit through an MDI circuit; a transmitting circuit coupled with a hybrid circuit and arranged to operably generate and provide a transmission signal to the hybrid circuit; a receiving circuit coupled with the hybrid circuit and arranged to operably receive and parse a received signal transmitted from the hybrid circuit to generate a data signal; a processing circuit coupled with the receiving circuit and arranged to operably process the data signal; a physical coding sublayer circuit coupled with the processing circuit and arranged to operably conduct a physical coding operation according to the instruction of the processing circuit to control the operations of the transmitting circuit; and an echo cancellation circuit coupled between the transmitting circuit and the receiving circuit, and arranged to operably generate an echo cancellation signal.

IPC Classes  ?

• H04B 3/23 - Reducing echo effects or singingOpening or closing transmitting pathConditioning for transmission in one direction or the other using a replica of transmitted signal in the time domain, e.g. echo cancellers
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

A method for optimizing model operation through weight arrangement and a computing system are provided. The method is operated in an operating device. In the method, a model framework is decided, and a training set is provided according to the model framework for training a model through a learning algorithm. A plurality of weights are computed for the model. The computing system relies on characteristics of the weights to select one of weight-arrangement rules, or a combination of the weight-arrangement rules, so that the locations of all or part of the weights can be re-arranged based on the selected weight-arrangement rule. The re-arranged weights are referred to for designating a corresponding loss function for simplifying the algorithm of the model. An application device can accordingly operate the model.

IPC Classes  ?

• G06N 3/0985 - Hyperparameter optimisationMeta-learningLearning-to-learn

Abstract

An onlooker detection system and an onlooker detection method are provided. The onlooker detection system includes: a person detection module, configured to receive an image, and obtain, in response to presence of persons in the image, person information of each person, where the person information includes distance information relative to a device; and an onlooker determination module, configured to: determine whether the persons include at least one non-user present in a range based on the distance information of the person information of each person; and determine, in response to presence of the at least one non-user in the range, a security classification to which each non-user belongs based on the person information of each non-user, where the security classification includes an onlooker category.

IPC Classes  ?

• G06V 40/16 - Human faces, e.g. facial parts, sketches or expressions
• G06F 21/60 - Protecting data
• G06T 7/73 - Determining position or orientation of objects or cameras using feature-based methods
• G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks

Abstract

A memory control circuit includes a plurality of main terminal circuits, a monitoring unit, an arithmetic unit, and a memory controller. The main terminal circuits output a plurality of control commands. The monitoring unit generates an operation record based on each of the control commands. The arithmetic unit includes a recurrent neural network module. The arithmetic unit generates a corresponding first feature vector based on the operation record and generates a plurality of second feature vectors based on the first feature vectors corresponding to a plurality of candidate combinations. The recurrent neural network module obtains estimated efficiency information based on the second feature vectors and selects a candidate combination corresponding to one piece of the estimated efficiency information as a selected main terminal combination. The memory controller is configured to execute the control command corresponding to each main terminal circuit in the selected main terminal combination for a memory.

IPC Classes  ?

• G06F 12/02 - Addressing or allocationRelocation

Abstract

An image processing method includes: training a first neural network model configured to execute a first image processing, according to multiple training data, to generate multiple first parameters associated with the first neural network model, in which the multiple first parameters includes multiple weights; training a second neural network model configured to execute a second image processing, which is different from the first image processing, according to the multiple training data and the multiple weights, to generate multiple second parameters associated with the second neural network model; and mixing the multiple first parameters with the multiple second parameters, to generate multiple blending parameters for a blending neural network model, in which the blending neural network model is configured to execute the first image processing and the second image processing on an input image, to output an optimized image.

IPC Classes  ?

• G06T 5/60 - Image enhancement or restoration using machine learning, e.g. neural networks

Abstract

An audio processing system and an audio processing method are provided. The audio processing system includes a receiving circuit and a processing circuit. The receiving circuit is configured to adjust original extended display capability identification data for generating optimized extended display capability identification data. The audio source device reads the optimized extended display capability identification data. The audio source device responds to the receiving circuit with a first multi-channel signal according to the optimized extended display capability identification data, and a quantity of sound channels of the first multi-channel signal is greater than a maximum quantity of sound channels supported by the audio processing system. The processing circuit is configured to convert the first multi-channel signal into a second multi-channel signal, and a quantity of sound channels of the second multi-channel signal is different from that of the first multi-channel signal.

IPC Classes  ?

• H04S 7/00 - Indicating arrangementsControl arrangements, e.g. balance control
• H04S 3/00 - Systems employing more than two channels, e.g. quadraphonic

Abstract

A method, a mesh network controller and a topology center device for performing channel allocation in a mesh network are provided. The method includes: utilizing the mesh network controller to send a channel scan request to multiple mesh network agent devices; utilizing the multiple mesh network agent devices to detect wireless communication information in response to the channel scan request in order to generate multiple channel scan reports, respectively; utilizing the mesh network controller to receive the multiple channel scan reports from the multiple mesh network agent devices, respectively; and utilizing the mesh network controller to send corresponding channel selection requests to the multiple mesh network agent devices according to the multiple channel scan reports, in order to make the multiple mesh network agent devices select corresponding wireless communication channels according to the corresponding channel selection requests, respectively.

IPC Classes  ?

• H04W 72/542 - Allocation or scheduling criteria for wireless resources based on quality criteria using measured or perceived quality
• H04W 72/04 - Wireless resource allocation
• H04W 84/18 - Self-organising networks, e.g. ad hoc networks or sensor networks

Abstract

An inductor device including a first ring-type structure, a second ring-type structure, and a third ring-type structure is disclosed. The second ring-type structure is coupled to the first ring-type structure and formed an 8-shaped loop with the first ring-type structure. The third ring-type structure is coupled to the second ring-type structure. The first ring-type structure and the second ring-type structure are located at an area surrounded by the third ring-type structure.

IPC Classes  ?

• H01F 27/29 - TerminalsTapping arrangements
• H01F 27/40 - Structural association with built-in electric component, e.g. fuse

Abstract

The present application discloses a speech enhancement device. The speech enhancement device includes an audio input circuit and a processor. The audio input circuit is configured to convert an audio input signal to a first audio data. The processor is configured to: generate a plurality of audio frames according to the first audio data; perform formant analysis on the audio frames to determine whether to combine adjacent audio frames of the audio frames into an audio segment; apply gain processing to the audio segment including the combined audio frames; and combine the audio segment and one or more uncombined audio frames of the audio frames into a second audio data.

IPC Classes  ?

• G10L 21/007 - Changing voice quality, e.g. pitch or formants characterised by the process used
• G10L 25/15 - Speech or voice analysis techniques not restricted to a single one of groups characterised by the type of extracted parameters the extracted parameters being formant information

Abstract

A low-dropout regulator system includes a low-dropout regulator. A comparator circuit generates a comparison voltage according to a reference voltage and a feedback voltage. An amplifier circuit generates an amplifying voltage according to the comparison voltage. A transistor receives an input voltage and is controlled by the amplifying voltage to generate an output voltage at an output terminal. A first resistor circuit is coupled between a first node and a ground terminal. A second resistor circuit is coupled between the output terminal and the first node. At a start-up timing point of the low-dropout regulator, a resistance value of the second resistor circuit is a first resistance value. After the input voltage reaches a maximum voltage, the resistance value of the second resistor circuit is a second resistance value. The second resistance value is larger than the first resistance value.

IPC Classes  ?

• G05F 1/59 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load
• G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
• G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Abstract

The present invention discloses an image decoding method. Error report information related to an error block in an N-th image frame generated according to an inter-frame coding technology is received by an image encoding apparatus when the image decoding apparatus receives a block of an N+P−1-th image frame. The N+P-th image frame is encoded according to the inter-frame coding technology. Blocks in the N-th image frame before the error block are decoded according to the inter-frame coding technology. A panning motion vector of an N−1-th image frame serves as the motion vector information and the residue information is set to be zero to decode the blocks from the error block to the N+P−1-th image frame according to the inter-frame coding technology. The motion vector information and the residue information of the inter-frame coding blocks in the N+P-th image frame are retrieved to perform decoding according to the inter-frame coding technology.

IPC Classes  ?

• H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• H04N 19/159 - Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
• H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
• H04N 19/65 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using error resilience
• H04N 19/89 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving methods or arrangements for detection of transmission errors at the decoder

Abstract

The present invention discloses an image decoding method. Error report information related to an error block in an N-th image frame generated according to an inter-frame coding technology is received by an image encoding apparatus at a time spot that the image decoding apparatus receives a corresponding block of an N+P−1-th image frame and an N+P-th image frame is encoded according to an inter-frame coding technology. Blocks in the N-th image frame before the occurrence of the error block are decoded according to the inter-frame coding technology. Motion vector information and residue information are set to be zero to decode the blocks from the error block to the N+P−1-th image frame according to the inter-frame coding technology. The motion vector information and the residue information of the inter-frame coding blocks in the N+P-th image frame are retrieved to decode the blocks therein according to the inter-frame coding technology.

IPC Classes  ?

• H04N 19/00 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
• H04N 19/159 - Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
• H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
• H04N 19/65 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using error resilience
• H04N 19/89 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving methods or arrangements for detection of transmission errors at the decoder

Abstract

A display system and a firmware updating method are provided. The display system includes displays connected in series to form a daisy-chain topology. Each of the displays includes firmware, and one of the displays is configured to be a publishing display. The publishing display is configured to execute a publishing program to provide a target version number of the firmware of the publishing display to each of the displays excluding the publishing display through the daisy-chain topology. Each of the displays excluding the publishing display is configured to execute a local program to determine whether or not the firmware needs to be updated based on a current version number of the firmware of the display and the target version number, and, in response to determining that the firmware needs to be updated, the firmware is updated based on a target file content provided by the publishing display.

IPC Classes  ?

• G06F 8/65 - Updates

Abstract

An amplifying circuit includes a floating inverter amplifier and a voltage generating circuit. A threshold voltage of transistors in the floating inverter amplifier varies corresponding to an environmental condition. The voltage generating circuit is coupled with the floating inverter amplifier. The voltage generating circuit is configured to provide an operating voltage to the floating inverter amplifier. The operating voltage provided by the voltage generating circuit is linearly correlated to the threshold voltage, and the voltage generating circuit modulates a variation of the operating voltage to keep track with a variation of the threshold voltage.

IPC Classes  ?

• G05F 3/26 - Current mirrors
• H03F 3/02 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with tubes only

Abstract

A rearview mirror adjustment system, a rearview mirror adjustment method, and an electronic rearview mirror assembly are provided. An image capture module is configured to capture a main image. A first rearview mirror set includes a first camera, a first display screen, and a first driver. The first camera is configured to capture a first image of a first predetermined region. The first display screen is configured to display the first image. The first driver is configured to adjust the first predetermined region when driven. A controller is configured to obtain a line of sight and a moving vector according to the main image. The controller is configured to drive the first driver according to the moving vector in response to the line of sight corresponding to the first display screen and the moving vector not falling in an unmoved region.

IPC Classes  ?

• H04N 7/18 - Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
• B60R 1/26 - Real-time viewing arrangements for drivers or passengers using optical image capturing systems, e.g. cameras or video systems specially adapted for use in or on vehicles for viewing an area outside the vehicle, e.g. the exterior of the vehicle with a predetermined field of view to the rear of the vehicle
• H04N 23/695 - Control of camera direction for changing a field of view, e.g. pan, tilt or based on tracking of objects
• H04N 23/90 - Arrangement of cameras or camera modules, e.g. multiple cameras in TV studios or sports stadiums

Abstract

The presented method has a channel identifying mechanism including steps outlined below. Signal receiving is performed by signal channels, each including differential signal lines, of a signal receiving interface. A signal amount of each of the signal channels is detected in a link training process by a signal processing circuit to determine the signal channels having the signal amount matching predetermined criteria to be actual communication signal channels. Test data sequences transmitted by the actual communication signal channels are detected in the link training process by the signal processing circuit to identify a polarity order of the different signal lines and a channel number order of the actual communication signal channels according to a data pattern. Actual data receiving is performed through a signal transmission line according to the polarity order and the channel number order by the signal processing circuit after the link training process is finished.

IPC Classes  ?

• H04L 25/02 - Baseband systems Details
• H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks

Abstract

A beacon adjustment method is applied in a wireless access point (AP). The beacon adjustment method includes following steps: detecting at least one signal or at least one signal collision event; calculating an adjustment base according to the at least one signal or the at least one signal collision event; and adjusting a target beacon transmission time (TBTT) according to the adjustment base, or adjusting a timing value of a timing synchronization function (TSF) according to the adjustment base.

IPC Classes  ?

• H04W 74/0833 - Random access procedures, e.g. with 4-step access
• H04W 74/08 - Non-scheduled access, e.g. ALOHA

Abstract

A video processing device and a video processing method supporting free pairing of a picture-in-picture mode and a picture-by-picture mode are provided. The video processing device includes a first hub, a second hub, and a scaling control module. The first hub obtains a first video stream from a first signal source, and the second hub obtains a second video stream from a second signal source. The scaling control module obtains the first video stream and the second video stream respectively from the first hub and the second hub. When the scaling control module receives a picture-in-picture mode command, the scaling control module combines the first video stream and the second video stream to generate a picture-in-picture video stream. When the scaling control module receives a picture-by-picture mode command, the scaling control module combines the first video stream and the second video stream to generate a picture-by-picture video stream.

IPC Classes  ?

• H04N 5/45 - Picture in picture
• H04N 5/262 - Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects

Abstract

An image processing system, an image processing method, and a training system are provided. The image processing method includes: receiving, by a preprocessing module in an image processing module, an image, and downsampling the image to obtain a downsampled tensor; processing, by a neural network module in the image processing module based on a plurality of first parameters, the downsampled tensor and generating an output tensor; upsampling, by an upsampling module in the image processing module, the output tensor to generate an upsampled tensor having same dimensions as the image; and performing, by an addition module, element-by-element addition on the upsampled tensor and the image to obtain an output image.

IPC Classes  ?

• G06T 3/4046 - Scaling of whole images or parts thereof, e.g. expanding or contracting using neural networks
• G06T 7/00 - Image analysis

Abstract

A data transmitting method includes following steps: executing a channel availability check to multiple channels to check whether the channels comprise a radar signal; if a noise channel of the channels comprises the radar signal, executing a preamble puncturing to the noise channel corresponding to the radar signal in order to stop transmitting data through the noise channel; transmitting data through part channels excluding the noise channel of the channels, wherein a first bandwidth of the noise channel is less than or equal to a second bandwidth of the part channels; after a non-occupancy period ends, executing the channel availability check to the noise channel to check whether the noise channel comprises the radar signal; and if the noise channel does not comprise the radar signal, recovering the noise channel, and transmitting data through the noise channel and the part channels of the plurality of channels.

IPC Classes  ?

• H04W 16/14 - Spectrum sharing arrangements

Abstract

A communication network device includes at least one first connection port and a core controller. The core controller is coupled to the at least one first connection port. The core controller includes a noise monitor and a rate controller. The noise monitor is configured to monitor an environmental noise for the at least one first connection port to generate a noise result. The rate controller is configured to adjust a connection rate of the at least one first connection port according to the noise result.

IPC Classes  ?

• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

A wireless communication device is provided. A wireless communication device includes a first antenna, a second antenna and a power combiner. The first antenna, the second antenna, and a disturbance source have a fixed position relationship. The power combiner is coupled with the first antenna and the second antenna through a first signal path and a second signal path, respectively. The power combiner receives a first noise and a second noise induced by the disturbance source through the first signal path and the second signal path, respectively. The power combiner further combines the first noise and the second noise. Based on the fixed position relationship, the first noise and the second noise received by the power combiner have a target phase difference and a target amplitude ratio so that the first noise and the second noise form a destructive interference at the power combiner.

IPC Classes  ?

• H04B 1/10 - Means associated with receiver for limiting or suppressing noise or interference

Abstract

A method for performing image decompression with limited hardware resource, associated image processing circuit and electronic device are provided. The method may include: utilizing an inverse quantization circuit to perform inverse quantization processing according to a bitstream to generate a first processing result, where the bitstream carries compressed data of a predetermined image; and utilizing an up-sampling circuit to perform up-sampling processing on the first processing result to generate a second processing result, for generating a decompressed image as a reproduced version of the predetermined image. During generating the decompressed image according to the bitstream, the image processing circuit is arranged to prevent using any entropy decoding circuit, any quantization table, any de-zigzag circuit, and any inverse transform circuit associated with the aforementioned any entropy decoding circuit, the aforementioned any quantization table and the aforementioned any de-zigzag circuit.

IPC Classes  ?

• H04N 19/44 - Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• H04N 19/124 - Quantisation
• H04N 19/30 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using hierarchical techniques, e.g. scalability
• H04N 19/423 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements

Abstract

A microwave sensing device includes: a generation circuit, for generating a generation signal; a first processing circuit, for processing the generation signal, to generate a first processed signal; a transmitting circuit, for transmitting the first processed signal; a receiving circuit, for receiving a received signal corresponding to the first processed signal; a second processing circuit, for processing the received signal, to generate a second processed signal; a first transferring circuit, for transferring the second processed signal to a first transferred signal; a removing circuit, for removing a direct current (DC) component of the first transferred signal, to generate a removed signal; a third processing circuit, for processing the removed signal, to generate a third processed signal; and a second transferring circuit, for transferring the third processed signal to a second transferred signal.

IPC Classes  ?

• G01S 7/487 - Extracting wanted echo signals
• G01S 7/484 - Transmitters
• G01S 7/4861 - Circuits for detection, sampling, integration or read-out

Abstract

The present invention provides a control method of a display device, wherein the control method includes the steps of: connecting with a first image source device, transmitting an original Extended Display Identification Data (EDID) to the first image source device, and receiving first image data from the first image source device; connecting with a second image source device, and receiving second image data from the second image source device, wherein the first image data and the second image data are displayed on the display device simultaneously, and the first image data and the second image data are displayed on a first display area and a second display area of the display device, respectively; modifying the original EDID to generate a modified EDID according to a size/resolution of the first display area; and providing the modified EDID to the first image source device.

IPC Classes  ?

• G09G 5/14 - Display of multiple viewports
• G06F 3/14 - Digital output to display device

Abstract

A transmitter and a method for reducing local oscillation (LO) leakage in the transmitter are provided. The transmitter includes an amplifier, a mixer, a self-mixer, a first calibration signal source, a second calibration signal source and a calibration logic circuit. The amplifier generates an amplified baseband signal, and the mixer performs an up-conversion upon the amplified baseband signal to generate a radio frequency (RF) signal, wherein the self-mixer performs self-mixing according to the RF signal to generate a feedback signal. In a first phase, the calibration logic circuit controls a first signal output from the first calibration signal source to the amplifier, to minimize a direct-current (DC) signal within the amplified baseband signal. In a second phase, the calibration logic circuit controls a second signal output from the second calibration signal source to the mixer, to minimize a feedback baseband signal within the feedback signal.

IPC Classes  ?

• H04B 1/525 - Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa with means for reducing leakage of transmitter signal into the receiver
• H03G 3/30 - Automatic control in amplifiers having semiconductor devices
• H04B 17/12 - MonitoringTesting of transmitters for calibration of transmit antennas, e.g. of amplitude or phase

Abstract

A network communication system includes a first communication device and a second communication device. The first communication device includes a processor and a first network interface controller. The processor operates multiple virtual machines. The first network interface controller simulates a virtual network interface having a virtual network address. The first network interface controller includes a buffer for temporally storing a packet to be transmitted to the virtual machine. In response to that an available space in the buffer being insufficient, the first network interface controller generates and transmits a pause frame. The first network interface controller records the virtual network address in a source address column in the pause frame. When a second network interface controller of the second communication device receives the pause frame, the second network interface controller suspends a traffic flow to be transmitted to the virtual network address.

IPC Classes  ?

• H04L 43/55 - Testing of service level quality, e.g. simulating service usage
• H04L 43/062 - Generation of reports related to network traffic
• H04L 49/00 - Packet switching elements

Abstract

A two-stage complementary amplifier (TSCA) includes a common-source input stage comprising a stack-up of a n-type common-source amplifier and a p-type common-source amplifier configured to receive a first signal and a second signal and output a third signal and a fourth signal across a first inductor and a second inductor, respectively; a common-gate output stage having a stack-up of a n-type common-gate amplifier and a p-type common-gate amplifier configured to receive the third signal and the fourth signal via a first capacitor and a second capacitor, respectively, and output a fifth signal and a sixth signal across a third inductor and a fourth inductor, respectively; and a fifth inductor terminated with a load, wherein the third inductor, the fourth inductor, and the fifth inductor are laid out tightly and substantially parallel to have strong mutual coupling.

IPC Classes  ?

• H03F 1/32 - Modifications of amplifiers to reduce non-linear distortion
• H03F 3/16 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices

Abstract

A communication chip includes a digital baseband circuit, a reference signal generation circuit, a power amplifier driver (PAD), a power amplifier (PA), and a digital-to-analog converter (DAC). The digital baseband circuit is used to generate a control signal and a control code. The reference signal generation circuit is coupled to the digital baseband circuit and is used to generate a reference signal and change the frequency of the reference signal according to the control signal. The PAD is coupled to the reference signal generation circuit. The PA is coupled to the PAD. The DAC is coupled to the digital baseband circuit and is used to control the output power of at least one of the PAD and the PA according to the control code. The PAD and the PA amplify the reference signal. The control signal is not equal to the control code.

IPC Classes  ?

• H04B 1/04 - Circuits
• H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
• H04B 1/40 - Circuits

Abstract

A detection method for USB communication interface disconnection includes: (a) detecting a first amplitude voltage of a chirp pair signal passing through the USB communication interface and setting a value of a threshold voltage to be less than the first amplitude voltage during a speed negotiation handshake stage; (b) detecting a second amplitude voltage of a packet passing through the USB communication interface during a data transmission stage; and (c) determining that a disconnection event has occurred in response to detecting that the second amplitude voltage is greater than the threshold voltage. A USB control circuit is also provided.

IPC Classes  ?

• G01R 31/69 - Testing of releasable connections, e.g. of terminals mounted on a printed circuit board of terminals at the end of a cable or a wire harnessTesting of releasable connections, e.g. of terminals mounted on a printed circuit board of plugsTesting of releasable connections, e.g. of terminals mounted on a printed circuit board of sockets, e.g. wall sockets or power sockets in appliances
• G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values

Abstract

An electronic device is used to transmit a radio frequency (RF) output signal or receive an RF input signal and includes an antenna and a communication chip. The communication chip includes a pin, an impedance matching circuit, a digital baseband circuit, a reference signal generation circuit, a transmitter circuit, and a receiver circuit. The pin is electrically connected to the antenna. The impedance matching circuit is coupled to the pin. The reference signal generation circuit is coupled to the digital baseband circuit. The transmitter circuit is used to generate the RF output signal. The receiver circuit is used to process the RF input signal. The communication chip transmits the RF output signal through the pin or receives the RF input signal through the pin.

IPC Classes  ?

• H04B 1/40 - Circuits
• H03M 1/66 - Digital/analogue converters

Abstract

The present invention discloses a network apparatus having slave circuit broadcast accessing mechanism. Each of lower layer slave circuits has an independent device address. An upper layer master circuit transmits a broadcast mode activation command including a broadcast address to lower layer slave circuits to configure the lower layer slave circuits with the broadcast address to enter a broadcast mode, transmit a broadcast mode write command including the broadcast address and broadcast write data to the lower layer slave circuits such that the lower layer slave circuits configured to have the broadcast address perform data writing according to the broadcast write data and transmit a broadcast mode read command including the broadcast address to the lower layer slave circuits to request one of the lower layer slave circuits having a device address being the same as the broadcast address to perform data reading and return individual read data.

IPC Classes  ?

• G06F 13/20 - Handling requests for interconnection or transfer for access to input/output bus
• G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation

Abstract

A universal serial bus device includes a resistor, a decision circuit, and a control circuit. The resistor is configured to receive a power supply voltage selectively. The decision circuit is configured to determine whether to remove the resistor based on at least one state of the universal serial bus device. If the decision circuit determines to remove the resistor based on the at least one state of the universal serial bus device, the decision circuit generates a removing signal. The control circuit is configured to remove the resistor based on the removing signal.

IPC Classes  ?

• G06F 13/38 - Information transfer, e.g. on bus

Abstract

A method for performing memory access control with limited search range size during video encoding includes: loading partial data of non-encoded video data corresponding to a picture into a search memory of a video processing circuit for performing at least one motion estimation (ME) operation of the video encoding; and configuring at least one ME search range corresponding to at least one ME region within memory space of the search memory for performing the at least one ME operation, wherein the at least one ME search range includes the at least one ME region, and the video processing circuit is arranged to perform the at least one ME operation with an extended search range greater than the at least one ME search range in the memory space for enhancing ME performance.

IPC Classes  ?

• H04N 19/433 - Hardware specially adapted for motion estimation or compensation characterised by techniques for memory access
• H04N 19/127 - Prioritisation of hardware or computational resources
• H04N 19/167 - Position within a video image, e.g. region of interest [ROI]
• H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
• H04N 19/57 - Motion estimation characterised by a search window with variable size or shape

Abstract

A transmission rate decision method, for a wireless transmission system that adopts a latency strategy, the transmission rate decision method comprises (a) at a first time point, obtaining a first packet error rate and a first transmission rate corresponding to a first current scene of the wireless transmission system; (b) at the first time point, determining a first candidate packet error rate according to a first candidate transmission rate corresponding to a first candidate scene of the wireless transmission system; and (c) determining a second transmission rate at a second time point according to the first packet error rate, the first transmission rate, the first candidate packet error rate and the first candidate transmission rate; wherein the wireless transmission system performs a wireless transmission using the second transmission rate at the second time point; wherein the second time point lags behind the first time point.

IPC Classes  ?

• H04W 28/22 - Negotiating communication rate
• H04W 28/02 - Traffic management, e.g. flow control or congestion control
• H04W 28/08 - Load balancing or load distribution

Abstract

An image processing method includes following operations. An environmental image is captured by a webcam. An automatic photography parameter is calculated according to the environmental image by the webcam. The automatic photography parameter includes an auto white balance parameter, an auto exposure parameter or an auto focus parameter. The automatic photography parameter is transmitted from the webcam to a controller chip of a displayer. A modulation function is performed by the controller chip according to the automatic photography parameter, so as to change a display screen on the displayer.

IPC Classes  ?

• G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source
• H04N 23/60 - Control of cameras or camera modules

Abstract

An own voice detection method includes a training phase and a detection phase. The training phase includes: receiving a first audio signal and a second audio signal from a first sound receiver and a second sound receiver; performing a voice activity detection to determine whether a voice activity is present; and training a filter based on the first and second audio signals when the voice activity is present, thereby finding optimal filter coefficients. The detection phase includes: receiving the first audio signal and the second audio signal from the first and second sound receivers; inputting the first audio signal to the filter with the optimal filter coefficients to obtain a third audio signal; and comparing to obtain a similarity index between the third and second audio signals, and determining that own voice is present when the similarity index is greater than a threshold.

IPC Classes  ?

• G10L 17/06 - Decision making techniquesPattern matching strategies

Abstract

A microwave sensing device includes: a generation circuit, for generating a microwave sensing packet according to a wireless communication protocol; a detecting circuit, for detecting whether a channel is idle; a transmitting circuit, coupled to the generation circuit and the detecting circuit, for transmitting the microwave sensing packet in response to the channel being idle; a receiving circuit, coupled to the detecting circuit, for receiving a received microwave sensing packet corresponding to the microwave sensing packet; and a processing circuit, coupled to the receiving circuit, for determining whether the received microwave sensing packet comprises an interference.

IPC Classes  ?

• H04W 74/0816 - Non-scheduled access, e.g. ALOHA using carrier sensing, e.g. carrier sense multiple access [CSMA] with collision avoidance
• H04W 24/08 - Testing using real traffic

Abstract

A fast operating system login method and a system are provided. A computer system is activated to enter a login procedure of an operating system. The operating system drives an infrared light source of a camera system to be turned on or off. In particular, the infrared light source of the camera system is driven to be turned off at a first time. An infrared camera is driven to photograph a user for generating continuous frames that include dark frames and bright frames. A first dark frame of the continuous frames is therefore obtained. A scene can be determined according to brightness distribution of the first dark frame, thereby obtaining an exposure setting corresponding to the scene. The infrared camera generates a biometric image according to the exposure setting, and the biometric image is referred to for logging in the operating system through a biometric image identification procedure.

IPC Classes  ?

• H04N 23/71 - Circuitry for evaluating the brightness variation
• G06F 21/32 - User authentication using biometric data, e.g. fingerprints, iris scans or voiceprints
• G06T 7/70 - Determining position or orientation of objects or cameras
• G06V 10/141 - Control of illumination
• G06V 10/50 - Extraction of image or video features by performing operations within image blocksExtraction of image or video features by using histograms, e.g. histogram of oriented gradients [HoG]Extraction of image or video features by summing image-intensity valuesProjection analysis
• G06V 20/00 - ScenesScene-specific elements
• G06V 40/16 - Human faces, e.g. facial parts, sketches or expressions
• H04N 23/72 - Combination of two or more compensation controls
• H04N 23/73 - Circuitry for compensating brightness variation in the scene by influencing the exposure time
• H04N 23/74 - Circuitry for compensating brightness variation in the scene by influencing the scene brightness using illuminating means

Abstract

A self-biasing inverter and a control method thereof related to the self-biasing inverter are provided. The self-biasing inverter includes a power terminal configured to receive a working power, an input terminal configured to receive an input signal, an output terminal configured to output an output signal related to the input signal, a first transistor electrically connected between the power terminal and the output terminal, a second transistor electrically connected between the output terminal and a ground terminal, a capacitor electrically connected between the input terminal and a node, a switch unit connected to the capacitor in parallel, and an impedance assembly electrically connected between the node and the output terminal. A control terminal of the first transistor is electrically connected to node. A control terminal of the second transistor is electrically connected to the node.

IPC Classes  ?

• H02M 7/53846 - Control circuits
• H02H 7/122 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for convertersEmergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for rectifiers for static converters or rectifiers for inverters, i.e. DC/AC converters
• H02M 7/00 - Conversion of AC power input into DC power outputConversion of DC power input into AC power output

Abstract

A packaged chip includes a die pad and a die. The die pad includes a first sub-die pad and a second sub-die pad. The die is disposed on the die pad. The first sub-die pad and the second sub-die pad are electrically isolated. The first sub-die pad serves as a digital ground. The second sub-die pad serves as an analog ground.

IPC Classes  ?

• H01L 23/495 - Lead-frames
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An analog-to-digital converting device includes a capacitive digital-to-analog converter, a comparator, and a controller. The capacitive digital-to-analog converter respectively generates a first and a second sample voltage according to a non-inverting output voltage and an inverting output voltage of a programmable gain amplifier during a sample period. The comparator generates a comparing signal by comparing the first and the second sample voltages during a converting period. The controller controls the capacitive digital-to-analog converter to generate a converting voltage according to the comparing signal during the converting period. The controller controls the capacitive digital-to-analog converter such that the capacitive digital-to-analog converter is pre-charged to a pre-charge voltage during a pre-charge period. The pre-charge voltage is between a maximum value and a minimum value of the non-inverting output voltage and the inverting output voltage of the programmable gain amplifier.

IPC Classes  ?

• H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter

Abstract

A signal group delay computation method uses a signal group delay computation system including a signal generation device and a signal analysis device. The signal group delay computation method includes: (a) the signal generation device generates a first input signal to the signal analysis device; (b) the device under test receives the first input signal to generate a first output signal; (c) the signal analysis device performs time-domain alignment on the first output signal and the first input signal to generate a second output signal; (d) the signal analysis device performs frequency alignment on the second output signal and the first input signal to generate a third output signal; and (e) the signal analysis device computes a relative signal group delay based on the first input signal and the third output signal.

IPC Classes  ?

• G01S 7/40 - Means for monitoring or calibrating

Abstract

An ultra-wideband (UWB) circuit includes a first pin, a second pin, a control register, a baseband circuit, a switch, a transmission circuit, a receiving circuit, a first low noise amplifier (LNA), and a second LNA. The control register stores a plurality of control values. The baseband circuit is coupled to the control register and configured to set the control values. The switch is coupled to the first pin. The transmission circuit is coupled to the control register and the switch and operates according to one of the control values. The receiving circuit is coupled to the control register and operates according to one of the control values. The first LNA is coupled to the switch and the receiving circuit. The second LNA is coupled to the second pin and the receiving circuit.

IPC Classes  ?

• H04B 1/719 - Interference-related aspects

Abstract

A radio frequency (RF) transceiver circuit includes a pre-distortion processing circuit, wherein the pre-distortion processing circuit includes a first filter, a mixer, a second filter, an analog-to-digital converter, and a digital processing circuit. The first filter filters a feedback signal to filter out harmonic components of the feedback signal in order to generate a filtered signal. The mixer performs a down-conversion operation upon the filtered signal via an oscillation signal to generate a mixed signal. The second filter performs a low-pass filtering operation upon the mixed signal to generate a low-pass filtered signal. The analog-to-digital converter performs an analog-to-digital conversion operation upon the low-pass filtered signal to generate a digital signal, in order for the digital processing circuit to generate a compensation signal for performing a pre-distortion compensation operation.

IPC Classes  ?

• H04B 1/40 - Circuits

Abstract

This invention provides a memory card reading device, which includes a communication interface, one or more slots, and a controller. The slot is used for electrically connecting to a memory card. When executing an access command on the memory card, the controller determines whether an error has occurred based on busy duration. When multiple memory cards are disposed and the error meets a switching condition, the controller will switch to another memory card for further usage.

IPC Classes  ?

• G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• G06F 11/16 - Error detection or correction of the data by redundancy in hardware
• G06F 11/32 - Monitoring with visual indication of the functioning of the machine

Abstract

A transceiver device includes a conversion circuit, a phase-locked loop, a transmission processing circuit, a reception processing circuit, and a selection circuit. The conversion circuit performs a digital-to-analog conversion for a modulation data to generate a first control signal. The phase-locked loop includes a control circuit and a voltage-controlled oscillator. The control circuit generates a second control signal according to the modulation data, a reference signal, and a frequency signal. The voltage-controlled oscillator determines an oscillation frequency according to the first control signal and the second control signal to generate the frequency signal. The transmission processing circuit performs a transmission processing according to the frequency signal. The reception processing circuit performs a reception processing according to the frequency signal. The selection circuit selectively transmits the frequency signal to the transmission processing circuit or the reception processing circuit according to the modulation data.

IPC Classes  ?

• H04L 27/152 - Demodulator circuitsReceiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements using controlled oscillators, e.g. PLL arrangements
• H04L 27/12 - Modulator circuitsTransmitter circuits
• H04L 27/148 - Demodulator circuitsReceiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements using filters, including PLL-type filters

Abstract

The present disclosure discloses a data receiving apparatus having data valid window expanding mechanism. An AND gate and an OR gate respectively perform logic operation on an input data signal and a delayed data signal delayed therefrom. A rising edge data multiplexer selects the OR gate processed signal and the AND gate processed signal respectively when a previous falling edge sampling result is at a low state and a high state to be outputted as a current rising edge data. A falling edge data multiplexer selects the OR gate processed signal and the AND gate processed signal respectively when a previous rising edge sampling result is at a low state and a high state to be outputted as a current falling edge data. A sampling circuit respectively performs rising and falling edge sampling on the current rising and the falling edge data to generate sampling results.

IPC Classes  ?

• H03K 5/1534 - Transition or edge detectors
• G11C 11/4076 - Timing circuits
• H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
• H03K 5/13 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits