Abstract

An image stream transmission apparatus having a dynamic image encoding mechanism is provided that includes an image encoding circuit, a communication circuit and a control circuit configured to perform steps outlined below. The image encoding circuit is controlled to generate test image frames having different test bit rates in an environment test stage. The communication circuit is controlled to transmit the test image frames to a remote apparatus through a network to be decoded and receive operation signals from the remote apparatus through the network. Round-trip times are calculated according to the transmission of the test image frames and the receiving of the operation signals. The image encoding circuit is controlled to determine an encoding strategy according to a smallest round-trip time and a decoding ability of the remote apparatus to generate and transmit game image frames to the remote apparatus in a game performing stage.

IPC Classes  ?

• H04N 19/146 - Data rate or code amount at the encoder output
• A63F 13/355 - Performing operations on behalf of clients with restricted processing capabilities, e.g. servers transform changing game scene into an encoded video stream for transmitting to a mobile phone or a thin client
• A63F 13/358 - Adapting the game course according to the network or server load, e.g. for reducing latency due to different connection speeds between clients
• A63F 13/52 - Controlling the output signals based on the game progress involving aspects of the displayed game scene
• H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
• H04N 19/513 - Processing of motion vectors

Abstract

A network communication apparatus having a dynamic packet transmission sorting mechanism is provided. A packet categorization circuit sets each of low-latency packets as a selected low-latency packet to be stored in a corresponding selected low-latency queue circuit. A transmission sorting circuit calculates a queue time parameter of the selected low-latency packet to be sorted with the other low-latency packets to update a sorting list. The queue time parameter is a ratio of an exceeding time and a dynamic service time threshold value configured by the corresponding selected low-latency queue circuit. A communication circuit transmits the low-latency packets according to the sorting list. A dynamic adjusting circuit calculates a difference of a total packet transmission time of the selected low-latency packet from a target delay threshold value to dynamically adjust the dynamic service time threshold value according to the difference.

IPC Classes  ?

• H04L 47/56 - Queue scheduling implementing delay-aware scheduling

Abstract

A comparator includes a comparator circuit, an offset calculation circuit, a hybrid offset voltage generation circuit, and an offset cancellation circuit. The comparator circuit is configured to generate a decision signal according to an input signal. The offset calculation circuit is configured to calculate an offset of the comparator circuit according to the decision signal to generate a plurality of control signals. The hybrid offset voltage generation circuit is configured to select a first reference voltage and a second reference voltage from a plurality of reference voltages according to the control signals and utilize the first reference voltage and the second reference voltage to perform a charge transfer operation to generate a plurality of calibration voltages. The offset cancellation circuit is configured to cancel the offset according to the plurality of calibration voltages.

IPC Classes  ?

• H03M 1/10 - Calibration or testing

Abstract

An LC (inductor-capacitor) oscillator includes a first NMOS (n-channel metal oxide semiconductor) transistor, a first PMOS (p-channel metal oxide semiconductor) transistor, a second NMOS transistor, and a second PMOS transistor, wherein: the source of the first NMOS transistor is shorted to the source of the first PMOS transistor; the source of the second NMOS transistor is shorted to the source of the second PMOS transistor; the first NMOS transistor and the second NMOS transistor are cross coupled via a first gate inductor and a first drain inductor; the first and second PMOS transistors are cross coupled via a second gate inductor and a second drain inductor; the first NMOS transistor and the first PMOS transistor are coupled via a first gate capacitor and a first drain capacitor; and the second NMOS transistor and the second PMOS transistor are coupled via a second gate capacitor and a second drain capacitor.

IPC Classes  ?

• H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device

Abstract

An oscillator circuit having a voltage-withstanding mechanism is provided that includes a first inductor circuit, a cross-coupled transistor circuit, a second inductor circuit and a capacitor circuit. The first inductor circuit is electrically coupled to a pair of connection terminals. The cross-coupled transistor circuit is electrically coupled to the pair of connection terminals. The second inductor circuit is electrically coupled between the pair of connection terminals and a pair of oscillating output terminals. The capacitor circuit is electrically coupled between the pair of oscillating output terminals.

IPC Classes  ?

• H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device

Abstract

A time-to-digital converter and a calibration method for performing time-to-digital conversion on an input signal are provided. The time-to-digital converter includes a time counter, a calibration circuit and an adder. The time counter starts counting in response to a first edge of the input signal and stops counting in response to a second edge of the input signal, to generate a preliminary counting value. The calibration generates a first determination bit according to the first edge of the input signal and a first edge of a clock signal, generates a second determination bit according to the second edge of the input signal and a second edge of the clock signal, and generates a calibration value according to the first determination bit and the second determination bit. In addition, the adder adds the calibration value to the preliminary counting value to generate a final counting value.

IPC Classes  ?

• G04F 10/00 - Apparatus for measuring unknown time intervals by electric means
• H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical

Abstract

A signal sampling device includes a first buffer circuit, a second buffer circuit, and a first bootstrap switch circuit. The first buffer circuit is configured to generate a first buffer signal according to an input signal. A second buffer circuit is configured to generate a second buffer signal according to the input signal, in which a specification requirement of the second buffer circuit is lower than that of the first buffer circuit. The first bootstrap switch circuit is configured to generate a control voltage according to the second buffer signal and to sample the first buffer signal according to the control voltage to generate a first sampling signal.

IPC Classes  ?

• H03M 1/12 - Analogue/digital converters
• H03M 1/50 - Analogue/digital converters with intermediate conversion to time interval

Abstract

The present invention provides an encoding method, which includes steps of: determining a first quantization parameter of a first superblock of an image frame; determining a binary code for the first superblock; determining whether binary code information of the first superblock is greater than a first threshold; and if the binary code information of the first superblock is greater than the first threshold, increasing a second quantization parameter of a second superblock.

IPC Classes  ?

• H04N 19/146 - Data rate or code amount at the encoder output
• H04N 19/174 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
• H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock

Abstract

The present invention provides an encoder including M core circuits. The M core circuits are configured to encode a first row of superblocks to a M-th row of superblocks of an image frame, and to update a cumulative distribution function (CDF) table during an encoding process of each superblock, where M is a positive integer greater than 1. The M core circuits are further configured to encode a (M+1)-th row of superblocks to a (2*M)-th row of superblocks of the image frame, and to update the CDF table during the encoding process of each superblock, wherein a first core circuit of the M core circuits uses the CDF table generated during the encoding process of a last superblock of the first row of superblocks to encode a first superblock of the (M+1)-th row of superblocks.

IPC Classes  ?

• H04N 19/127 - Prioritisation of hardware or computational resources
• H04N 19/152 - Data rate or code amount at the encoder output by measuring the fullness of the transmission buffer
• H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
• H04N 19/436 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements

Abstract

A front‑end circuitry includes a first buffer circuit, a first switch, an analog-to-digital converter circuit, a digital-to-analog converter circuit, a second switch, and a subtractor circuit. The first buffer circuit is configured to generate a first buffer signal according to an input signal. The first switch is configured to be turned on according to a control signal, in order to output the first buffer signal as a first signal. The analog‑to‑digital converter circuit is configured to generate a digital code according to the first signal. The digital‑to‑analog converter circuit is configured to generate a feedback signal according to the digital code. The second switch is configured to be turned on according to the control signal, in order to output a second signal according to the input signal. The subtractor circuit is configured to subtract the feedback signal from the second signal to generate an output signal.

IPC Classes  ?

• H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise

Abstract

A signal generator and a method for verifying an asynchronous interface circuit are provided, where the signal generator includes a frame modulator, a clock generator, an interface selector and a checking module. The frame modulator generates a modulated signal according to a frame control parameter, and the clock generator generates a clock signal according to a clock control parameter. The interface selector generate a receiving test signal according to an interface control parameter, the modulated signal and the clock signal, where the signal generator utilize a reference model to generate a reference signal according to the receiving test signal, and the asynchronous interface circuit generates a transmitting test signal according to the receiving test signal. In addition, the checking module generates at least one verification result according to the reference signal and the transmitting test signal.

IPC Classes  ?

• G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom

Abstract

A lookup table selection method is provided, comprising: dividing received image data into training image data and validation image data; performing, by an artificial intelligence model, a neural network training based on the training image data, so as to generate a plurality of lookup tables, wherein each of the lookup tables has a node number, and the node numbers of the lookup tables are different from each other; converting the validation image data into a plurality of converted validation image data based on the lookup tables; comparing the plurality of converted validation image data with the validation image data, so as to generate a plurality of conversion scores corresponding to the plurality of converted validation image data; and selecting one of the lookup tables as a selected lookup table according to the conversion scores and a plurality of memory scores respectively corresponding to the conversion scores.

IPC Classes  ?

• G06T 11/00 - 2D [Two Dimensional] image generation
• G06T 3/4046 - Scaling of whole images or parts thereof, e.g. expanding or contracting using neural networks
• G06T 7/00 - Image analysis
• G06T 7/90 - Determination of colour characteristics

Abstract

An image processing device is used to receive an input image data that includes multiple frames, and at least one of the frames contains at least one packet. The image processing device includes a receiving circuit, a storage circuit, a transmission circuit, and a control circuit. The receiving circuit receives the input image data. The storage circuit is used to store the at least one packet. The transmission circuit is used to output a current output image data. The control circuit is used to read at least one target packet from the storage circuit according to the current output image data, adjust the at least one target packet, and then output the at least one target packet through the transmission circuit.

IPC Classes  ?

• G06T 1/60 - Memory management

Abstract

A differential sampling circuit is configured to sample a differential circuit. The differential circuit includes a first output and a second output, and the differential sampling circuit includes an amplifier and a switch circuit. The switch circuit includes a capacitor, a pair of sampling switches, and a pair of output switches. One end of the capacitor is coupled to the first output of the differential circuit through one of the pair of sampling switches, and is coupled to a reference terminal through the one of the pair of output switches. The other end of the capacitor is coupled to the second output of the differential circuit through the other of the pair of sampling switches, and is coupled to an input terminal of the amplifier through the other of the pair of output switches.

IPC Classes  ?

• G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
• G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation

Abstract

A Bluetooth communication method having dynamic bandwidth allocation mechanism is provided including steps outlined below. A Bluetooth central apparatus and a Bluetooth peripheral apparatus perform a CIS communication according to a CIS technology. The Bluetooth central apparatus performs normal transmission mode packet communication behaviors with the Bluetooth peripheral apparatus operating under a normal transmission mode such that the Bluetooth peripheral apparatus performs an ACK signal transmission behavior in response. The Bluetooth central apparatus performs high bandwidth transmission mode packet communication behaviors with the Bluetooth peripheral apparatus operating under a high bandwidth transmission mode such that the Bluetooth peripheral apparatus selects at least one selected high bandwidth transmission mode packet communication behaviors and does not perform the ACK signal transmission behavior corresponding to the selected high bandwidth transmission mode packet communication behaviors.

IPC Classes  ?

• H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication

Abstract

A vehicle adjustment method executed by a processor reading at least command stored in a memory is disclosed herein. The vehicle adjustment method includes: determining whether at least one object under a vehicle is a living being; if the at least one object under the vehicle is not the living being, decreasing a height of the vehicle; and if the at least one object under the vehicle is the living being, and a pressure applied to the at least one object by the vehicle is smaller than a predetermined pressure, increasing the height of the vehicle.

IPC Classes  ?

• B60G 17/018 - Resilient suspensions having means for adjusting the spring or vibration-damper characteristics, for regulating the distance between a supporting surface and a sprung part of vehicle or for locking suspension during use to meet varying vehicular or surface conditions, e.g. due to speed or load the regulating means comprising electric or electronic elements characterised by the use of a specific signal treatment or control method

Abstract

A transconductance gain calibration circuit includes a constant voltage source, a first transconductance amplifier, a second transconductance amplifier, and a comparison module. The constant voltage source is configured to generate a reference voltage. The first transconductance amplifier responds to the reference voltage to produce a constant current. The second transconductance amplifier responds to the reference voltage to produce a variation current. The comparison module includes a first potentiometer, a reference resistor, and a comparison circuit. The first potentiometer is coupled to the first transconductance amplifier and is configured to generate a variation voltage based on the constant current and an adjustable resistance. The reference resistor is coupled to the second transconductance amplifier and is configured to generate a constant voltage based on the variation current and a designed resistance value. The comparison circuit is configured to compare the variation voltage with the constant voltage to adjust the adjustable resistance.

IPC Classes  ?

• H03G 3/30 - Automatic control in amplifiers having semiconductor devices
• H03F 1/30 - Modifications of amplifiers to reduce influence of variations of temperature or supply voltage
• H03F 3/45 - Differential amplifiers

Abstract

The disclosure provides a radio frequency rectifier device, including a first input node, a first capacitor, a second input node, a second capacitor, a first transistor element, a second transistor element, a third capacitor, a fourth capacitor, a third transistor element, a fourth transistor element, a fifth capacitor, a sixth capacitor, a first conductive element, a second conductive element, a third conductive element, a fourth conductive element, a load resistor and a load capacitor. When the first conduction element, the second conduction element, the third conduction element and the fourth conduction element are turned on, a gate voltage of the first transistor element, a gate voltage of the second transistor element, a gate voltage of the third transistor element and a gate voltage of the fourth transistor element are reduced respectively. These operations reduce a leakage current and a discharge interval of the transistor element, thereby improving power conversion efficiency.

IPC Classes  ?

• H02J 50/27 - Circuit arrangements or systems for wireless supply or distribution of electric power using microwaves or radio frequency waves characterised by the type of receiving antennas, e.g. rectennas
• H02J 50/00 - Circuit arrangements or systems for wireless supply or distribution of electric power
• H02M 1/00 - Details of apparatus for conversion
• H02M 7/217 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

Abstract

A Bluetooth communication method having bi-directional communication mechanism is provided including steps outlined below. A Bluetooth central apparatus and a Bluetooth peripheral apparatus perform a broadcast isochronous stream (BIS) communication according to a BIS technology. The Bluetooth central apparatus initiates one-way first packet communication behaviors performed with the Bluetooth peripheral apparatus operating under a normal transmission mode such that the Bluetooth peripheral apparatus does not react in response to the one-way first packet communication behaviors. The Bluetooth central apparatus initiates two-way second packet communication behaviors performed with the Bluetooth peripheral apparatus operating under a bi-directional transmission mode such that the Bluetooth peripheral apparatus such that the Bluetooth peripheral apparatus selects at least one selected two-way second packet communication behavior and actively initiates a signal transmission behavior performed with the Bluetooth central apparatus in response to the at least one selected two-way second packet communication behavior.

IPC Classes  ?

• H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication

Abstract

A cloud gaming terminal device includes a playback quality evaluation unit and a feedback engine client. The playback quality evaluation unit is configured to generate at least one playback quality evaluation parameter based on information provided by at least one of a network interface control unit, a media decoding unit, and a media rendering unit within the cloud gaming terminal device. The feedback engine client is configured to transmit at least one playback quality evaluation parameter to a cloud gaming server through a network. The cloud gaming server is configured to adjust at least one media encoding parameter of a media stream according to the received playback quality evaluation parameter.

IPC Classes  ?

• A63F 13/355 - Performing operations on behalf of clients with restricted processing capabilities, e.g. servers transform changing game scene into an encoded video stream for transmitting to a mobile phone or a thin client
• A63F 13/493 - Resuming a game, e.g. after pausing, malfunction or power failure

Abstract

A data transmission system includes a transmitter and a receiver. The transmitter receives an image data of a signal source at a first time, generate a transmitter signal event according to a transmitter timing information, and transmit the transmitter signal event and the image data through a network. The receiver receives the transmitter signal event and the image data through the network, and obtain the transmitter timing information according to the transmitter signal event. The receiver adjusts a receiver data transmission speed of the receiver according to the transmitter timing information, so that a transmitter data transmission speed of the transmitter and the receiver data transmission speed of the receiver are consistent. The receiver transmits the image data at a second time, and a time difference between the first time and the second time is smaller than three frames of the image data.

IPC Classes  ?

• H04W 56/00 - Synchronisation arrangements
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

A method and a system for processing images with pixel mask insertion are provided. The system is operated in a control circuit of a display system by firmware or a circuitry. The display system preferably adopts an organic light-emitting diode (OLED) display panel. For improving burn-in phenomenon caused by aging of the display panel, the control circuit performs the method for processing images with pixel mask insertion. In the method, the control circuit firstly receives frame images from a source, each of the frame images is divided into multiple blocks with the same or different sizes, and one or more masks with the same or different sizes are set for each of the blocks. Every mask is used to scan the block, and a color-reduction procedure is performed on the block by masking. The color-reduced frame image is outputted to the display panel.

IPC Classes  ?

• G09G 3/3225 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Abstract

The present invention provides a method for testing a chip, which includes the steps of: receiving a clock signal and a data signal from a verification module; shaping the clock signal and/or the data signal to generate a constructed clock signal and a constructed data signal; inputting the constructed clock signal and the constructed data signal into the chip; receiving an output clock signal and an output data signal from the chip; and performing timing checks on the output clock signal and the output data signal to generate an output check clock signal and a checked data signal to the verification module.

IPC Classes  ?

• G06F 11/263 - Generation of test inputs, e.g. test vectors, patterns or sequences
• G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Abstract

A central office device includes a feedback circuit and a bandwidth allocation circuit. The feedback circuit is configured to receive a buffer size signal from a terminal device, and perform a feedback process on the buffer size signal to generate a feedback signal. The bandwidth allocation circuit is configured to provide a bandwidth to the terminal device according to the feedback signal.

IPC Classes  ?

• H04L 41/0896 - Bandwidth or capacity management, i.e. automatically increasing or decreasing capacities
• H04L 5/00 - Arrangements affording multiple use of the transmission path

Abstract

A method for controlling a wireless communication module includes: causing the wireless communication module to establish a first connection and a second connection with a plurality of specific wireless communication modules, respectively; respectively maintaining a first timer for a first connection port corresponding to the first connection and a second timer for a second connection port corresponding to the second connection; selecting a target port from the first connection port and the second connection port according to a request from an application program interface corresponding to the wireless communication module; and in response to the request from the application program interface, returning a time value provided by the timer corresponding to the target port.

IPC Classes  ?

• H04W 56/00 - Synchronisation arrangements
• H04W 92/18 - Interfaces between hierarchically similar devices between terminal devices

Abstract

A spread spectrum clocking (SSC) settings adjusting method includes: expanding candidate SSC settings for a system scenario; applying the candidate SSC settings to an integrated circuit (IC) device that stores a predefined look-up table (LUT); measuring candidate signal-to-noise ratios (SNRs) of the IC device respectively under the candidate SSC settings; selecting a selected SSC setting that has a highest SNR of the candidate SNRs from the candidate SSC settings corresponding to the system scenario; and substituting an SSC setting of the predefined LUT corresponding to the system scenario with the selected SSC setting, so as to update the predefined LUT stored in the IC device.

IPC Classes  ?

• H04B 15/04 - Reducing interference from electric apparatus by means located at or near the interfering apparatus the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
• H04B 1/69 - Spread spectrum techniques

Abstract

An oscillator includes a logic circuit and an oscillation circuit. The logic circuit is configured to receive an enable signal and a feedback signal and generate a first control signal according to the enable signal and the feedback signal. The oscillation circuit is coupled to the logic circuit and is configured to generate the feedback signal and an oscillation output signal according to the first control signal.

IPC Classes  ?

• H03K 3/014 - Modifications of generator to ensure starting of oscillations

Abstract

A circuit design method executed by an electronic device includes the following steps: performing an IR drop analysis based on circuit placement data; selecting a target cell; replacing the target cell with a sub-cell; setting up a buffer cell; placing the buffer cell in an area; and connecting the sub-cell and the buffer cell with a routing.

IPC Classes  ?

• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Abstract

A channel loss compensation circuit utilized in a receiving end of an electronic device includes a load, first and second transistors, first and second current sources, an adjustable capacitor, and an adjustable resistor. The first transistor has a first, second, and third terminals. The first terminal receives an input signal, and the second terminal is coupled to a power supply voltage through the load. The second transistor has a fourth, fifth terminal, and sixth terminals. The fourth terminal receives the input signal, and the fifth terminal is coupled to the power supply voltage through the load. The first current source is coupled between the third terminal and a reference voltage. The second current source is coupled between the sixth terminal and the reference voltage. The adjustable capacitor and the adjustable resistor are coupled between the third terminal and the sixth terminal.

IPC Classes  ?

• H03K 5/1252 - Suppression or limitation of noise or interference
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• H04B 1/16 - Circuits
• H04L 27/01 - Equalisers

Abstract

A packaging carrier includes an insulating layer and two metal layers embedded in the insulating layer. One of the two metal layers arranged adjacent to an outer surface of the insulating layer includes an antenna layout segment and a plurality of frequency adjustment pads. The antenna layout segment has a slot antenna recessed from an edge thereof and a plurality of layout holes that are located at two opposite sides of the slot antenna. The frequency adjustment pads are respectively located in the layout holes and are not in contact with the antenna layout segment. The frequency adjustment pads are exposed from the outer surface. The antenna layout segment has a plurality of slot-shape adjustment pads exposed from the outer surface. The slot-shape adjustment pads are arranged adjacent to a bottom of the slot antenna and are located at the two opposite sides of the slot antenna.

IPC Classes  ?

• H01Q 1/22 - SupportsMounting means by structural association with other equipment or articles
• H01Q 13/10 - Resonant slot antennas
• H10W 74/10 -

Abstract

A communication device includes a transceiver circuit and a controller circuit. The transceiver circuit is configured to receive packets from electronic devices. The controller circuit is configured to: parse the packets to obtain power delay profile of each of the electronic devices; set a guard interval of each of the electronic devices according to the power delay profile; divide the electronic devices into a first group of devices and a second group of devices; and sending, through the transceiver circuit, a trigger frame to at least one group of devices in the first or the second group of devices, such that the at least one group of devices upload data to the transceiver circuit.

IPC Classes  ?

• H04L 27/26 - Systems using multi-frequency codes
• H04L 5/00 - Arrangements affording multiple use of the transmission path

Abstract

An integrated circuit includes a first pin and a second pin. A spike suppression circuit of the integrated circuit includes a switch and a detection circuit. The switch is coupled between the first pin and the second pin. The detection circuit is coupled to the first pin and a control terminal of the switch and is used to detect a spike on the first pin. When the detection circuit detects the spike, the detection circuit controls the switch to turn on.

IPC Classes  ?

• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
• H02H 1/00 - Details of emergency protective circuit arrangements

Abstract

A data dumping circuit is coupled to a combinational logic circuit, and includes a sensing and locking circuit and a scan chain circuit. The sensing and locking circuit is arranged to sense a characteristic value of the combinational logic circuit, and generate a scan enabling signal in response to the characteristic value being determined to be changed. The scan chain circuit is coupled to multiple flip-flops, and operates in a scan mode in response to the scan enabling signal, wherein in the scan mode, the scan chain circuit sequentially outputs a value stored in each of the multiple flip-flops for acting as dumping data.

IPC Classes  ?

• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
• G01R 31/317 - Testing of digital circuits

Abstract

An interface card device and repairing method thereof is related to the interface card device including a transmission interface, a timing module, and a control module. The transmission interface is electrically connected to a host device. The timing module is electrically connected to the transmission interface. The control module is electrically connected to the transmission interface and the timing module. The transmission interface includes at least one layer corresponding to at least one finite state machine. The timing module is configured to time a state-stop time for any of the at least one finite state machine to stop working, and to generate a reset signal when the state-stop time exceeds a threshold to reset the state-stop time. The control module is configured to switch a state of the at least one finite state machine, and to switch the state to a reset state according to the reset signal.

IPC Classes  ?

• G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation

Abstract

An analog buffer device includes a first source follower circuit and a second source follower circuit. The first source follower is circuit configured to generate a first output signal according to a first input signal. The second source follower circuit is configured to generate a second output signal according to a second input signal, in which the first source follower circuit and the second source follower circuit are coupled in series and coupled between a first power node and a second power node, the first power node receives a first power voltage, and the second power node receives a second power voltage.

IPC Classes  ?

• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only

Abstract

A dynamic amplifier includes a power supply circuit and first to fourth transistors. The power supply circuit is configured to provide power voltages. The first transistor is configured to be biased by a first auxiliary signal and to receive a first power voltage in the power voltages. The second transistor is configured to be biased by a second auxiliary signal and to receive the first power voltage. The third transistor is configured to receive the power voltages and generate a first output signal according to a first input signal. The fourth transistor is configured to receive the power voltages and generate a second output signal according to a second input signal, in which the third transistor is configured to receive the first power voltage via the first transistor, and the fourth transistor is configured to receive the first power voltage via the second transistor.

IPC Classes  ?

• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• H03F 3/04 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only

Abstract

A charge pump circuit includes a charge pump stage and a filtering stage. The charge pump stage has an output terminal, and the filtering stage is coupled to the output terminal. The filtering stage includes a plurality of low-pass filters coupled in series. Each low-pass filter includes a capacitor assembly. Each capacitor assembly includes a plurality of interdigitated capacitors, and the interdigitated capacitors in one capacitor assembly have a first interdigitated spacing. The interdigitated capacitors of another capacitor assembly have a second interdigitated spacing different from the first interdigitated spacing.

IPC Classes  ?

• H02M 1/44 - Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
• H02M 3/00 - Conversion of DC power input into DC power output
• H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode

Abstract

An analog-to-digital converter (ADC) and a method for calibrating a comparator within the ADC are provided. The ADC includes a sampling capacitor array, the comparator, an offset calibration control switch and a control logic, where the offset calibration control switch is coupled between the sampling capacitor array and the comparator. In a sampling phase, the sampling capacitor array samples an input signal, the offset calibration control switch is turned off, input terminals of the comparator are pulled to a same level, and the control logic performs calibration of the comparator according to a comparison result generated by the comparator. In a conversion phase, the offset calibration control switch is turned on, and the control logic output an analog-to-digital conversion result of the input signal according to the comparison result.

IPC Classes  ?

• H03M 1/10 - Calibration or testing

Abstract

A self-adaptation method for optimizing multiple communication modules coexisting in frequency-division duplexing is provided. The method is operated in a communication system having at least two communication modules. Communication data generated by the communication modules is obtained when the communication system is operated under a time-division duplexing mode. The communication data is used to establish a standard comparison value for a frequency-division duplexing mode. The communication system then enters a parameter-adjustment phase, and radio-frequency parameters for the communication modules can be obtained. Thus, based on the standard comparison value, key performance indicator check is periodically performed for assessing whether to start or to stop a frequency-divisional duplexing training process according to one or more reference indicators so as to determine whether the radio-frequency parameters need to be adjusted. A set of radio-frequency parameters suitably operating the communication system under the frequency-division duplexing mode are finally obtained.

IPC Classes  ?

• H04L 5/14 - Two-way operation using the same type of signal, i.e. duplex

Abstract

A redistribution layer substrate includes a top layer, a bottom layer, a plurality of intermediate layers, and a protective layer. The top layer includes a plurality of first conductive pads. The bottom layer includes a plurality of second conductive pads. The plurality of intermediate layers are deployed between the top layer and the bottom layer, and the plurality of intermediate layers includes a plurality of interlayer traces, respectively connecting each of the plurality of first conductive pads to each of the plurality of second conductive pads. The protective layer covers the top layer and includes via holes; and the via holes define a projection range on the top layer, and a portion of the plurality of first conductive pads are within the projection range.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An amplifier circuit has first and second input terminals and first and second output terminals, and includes first and second inverter-based amplifiers and first and second output stages. The first inverter-based amplifier has third and fourth output terminals. The second inverter-based amplifier has fifth and sixth output terminals. The first and the second input terminal are the two input terminals of the first and second inverter-based amplifier. The first and second inverter-based amplifiers are respectively coupled to first and second voltages. The first output stage is coupled to the third and fourth output terminals. The second output stage is coupled to the fifth and sixth output terminals. The first and second output terminals are the output terminals of the first and second output stages, respectively.

IPC Classes  ?

• H03F 3/45 - Differential amplifiers

Abstract

This invention relates to a mobile device in which an image processing circuit is electrically connected to two buses. A processor sends an instruction to the image processing circuit through the second bus. The instruction indicates execution of an image processing procedure, including a geometric transformation process and a blending process, on input images. Upon receiving the instruction, the image processing circuit calculates the coordinates of input pixels based on the coordinate of an output pixel, thereby reading the input pixels from a memory through the first bus. The image processing circuit also executes the image processing procedure and writes the output pixel into the memory through the first bus.

IPC Classes  ?

• G06T 5/50 - Image enhancement or restoration using two or more images, e.g. averaging or subtraction
• G06F 3/14 - Digital output to display device
• G06T 3/4007 - Scaling of whole images or parts thereof, e.g. expanding or contracting based on interpolation, e.g. bilinear interpolation

Abstract

An image search method includes: providing a human-machine interface to receive an input of a user; performing an image object detection operation according to the input of the user sent from the human-machine interface to generate a specific image; performing an image-to-semantic operation based on the specific image to perform an irreversible encryption encoding upon the specific image to generate a specific semantic vector; sending the generated specific semantic vector into a cloud semantic search engine of a cloud server so that the cloud semantic search engine searches multiple semantic vectors stored in the cloud server according to the specific semantic vector so as to select image information corresponding to an approximate semantic vector and send the image information into the human-machine interface; and, controlling the human-machine interface to display the image information for the user.

IPC Classes  ?

• G06F 21/60 - Protecting data
• G06F 16/732 - Query formulation
• G06V 10/94 - Hardware or software architectures specially adapted for image or video understanding
• G06V 20/40 - ScenesScene-specific elements in video content

Abstract

A communication device includes a wireless communication module and a processor. The wireless communication module transmits or receives multiple wireless signals, and provides a hotspot, wherein the wireless communication module receives a connection request indicating to connect to the hotspot from a peer communication device, and establishes a wireless connection with the peer communication device in response to the connection request. The processor is coupled to the wireless communication module, and controls operations of the communication device, wherein after the wireless connection is successfully established, the processor utilizes a captive portal mechanism to transmit information associated with a download link to the peer communication device via the wireless communication module; and in response to a download request being received from the peer communication device, the processor transmits predetermined data to the peer communication device via the wireless communication module.

IPC Classes  ?

• H04W 76/14 - Direct-mode setup
• H04L 67/02 - Protocols based on web technology, e.g. hypertext transfer protocol [HTTP]
• H04L 67/06 - Protocols specially adapted for file transfer, e.g. file transfer protocol [FTP]
• H04W 76/12 - Setup of transport tunnels

Abstract

An amplifier device having buffer function includes an amplifier circuit and a buffer circuit. The amplifier circuit is configured to amplify a first input signal to generate a first amplified output signal and to amplify a second input signal to generate a second amplified output signal. The buffer circuit is configured to generate a first buffered output signal according to a third input signal and to generate a second buffered output signal according to a fourth input signal. The amplifier circuit and the buffer circuit are coupled in series and coupled between a first power supply node and a second power supply node, the first power supply node receives a first power supply voltage, and the second power supply node receives a second power supply voltage.

IPC Classes  ?

• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• H03F 3/04 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only

Abstract

An amplifier device includes a first input pair circuit, a second input pair circuit, and a latch circuit. The first input pair circuit amplifies a first set of input signals. The second input pair circuit amplifies a second set of input signals, in which a conductivity type of the first input pair circuit is different from that of the second input pair circuit. The first input pair circuit and the second input pair circuit are further coupled in series through output nodes and generate amplified signals through the output nodes, the first input pair circuit and the second input pair circuit are coupled between a first power supply node and a second power supply node, and the first power supply node and the second power supply node receive different power supply voltages. The latch circuit generates output signals according to the amplified signals.

IPC Classes  ?

• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• H03F 3/45 - Differential amplifiers
• H03K 3/037 - Bistable circuits

Abstract

A dynamic amplifier includes first to sixth transistors and a power supply circuit. The first transistor is configured to amplify a first input signal. The second transistor amplifies a second input signal. The third transistor amplifies a third input signal, in which the first to the third transistors collectively generate a first output signal at a first output node in response to the first to third input signals. The fourth transistor amplifies a fourth input signal. The fifth transistor amplifies a fifth input signal. The sixth transistor amplifies a sixth input signal, in which the fourth to the sixth transistors collectively generate a second output signal at a second output node in response to the fourth to sixth input signals. The power supply circuit dynamically provides power voltages to drive the first to the sixth transistors.

IPC Classes  ?

• H03F 3/00 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• H03F 1/26 - Modifications of amplifiers to reduce influence of noise generated by amplifying elements

Abstract

A method for modulating a liquid crystal display and a circuit system. In the method, the circuit system receives image data from an image source, and each of the frames of the image data is divided into multiple blocks. After the image data is frame-by-frame analyzed, a maximum brightness and an average brightness of each of pixels of the blocks are obtained. Accordingly, a target backlight value of a backlight module can be determined and a control signal is generated for driving each of the blocks of the backlight module to illuminate according to the target backlight value. A set of code values for a display panel can be obtained according to a target brightness set by the circuit system and the target backlight value, so that the code values for reaching the target brightness corresponding to every pixel in the block can be determined.

IPC Classes  ?

• G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source
• G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals

Abstract

A crystal oscillator having a PMOS, an NMOS transistor, a feedback capacitor positioned between the source node and one of the first gate node and the second gate node; a shunt capacitor positioned between the source node and one of the power supply node and the ground node, an AC coupling capacitor positioned between the first gate node and the second gate node, and a crystal positioned between one of the first gate node and the second gate node and one of the ground node and the power supply node. A first DC coupling network couples a first bias node to the first gate node according to a state of a first gate voltage at the first gate node, and a second DC coupling network couples a second bias node to the second gate node according to a state of a second gate voltage at the second gate node.

IPC Classes  ?

• H03B 5/36 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
• H03B 5/24 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device

Abstract

A transceiver device includes a transmitter circuit and a receiver circuit. The transmitter circuit is configured to couple an antenna and includes a first mixer and a first buffer circuit. The first mixer is configured to output a first radio frequency signal according to a first baseband signal and a first local oscillator signal. The first buffer circuit is configured to output the first local oscillator signal to the first mixer and includes a plurality of first buffers. The receiver circuit is configured to couple the antenna. A first buffers-coupled-in-parallel quantity of the first buffer circuit is adjusted according to an operation condition.

IPC Classes  ?

• H04B 1/408 - Circuits using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency the transmitter oscillator frequency being identical to the receiver local oscillator frequency

Abstract

A four-phase clock generator includes a four-stage ring including four MOS transistors of a first conductivity type, each configured in a common-source arrangement and interconnected in a ring topology to sequentially and cyclically de-assert phases of a four-phase output clock, respectively; a first alternate-phase cross-coupling pair of MOS transistors of the first conductivity type configured to cross couple the first phase and the third phase of the four-phase output clock; a second alternate-phase cross-coupling pair of MOS transistors of the first conductivity type configured to cross couple the second phase and the fourth phase of the four-phase output clock; and an assertion network having four MOS transistors of a second conductivity type configured to sequentially and cyclically assert phases of the output clock in accordance with four gated clock signals generated by alternately gating phases of input and output clocks.

IPC Classes  ?

• H03K 3/017 - Adjustment of width or dutycycle of pulses
• G06F 1/08 - Clock generators with changeable or programmable clock frequency
• H03K 3/356 - Bistable circuits
• H03K 17/13 - Modifications for switching at zero crossing

Abstract

A high thermal conductive and electromagnetic interference shielding electronic package structure and a method for manufacturing the same. The electronic package structure includes a circuit substrate, a die, an electromagnetic shielding layer, a passivation layer, a dielectric layer, a welding composite layer, a thermal-conductive metal layer, and a heat dissipation cover. The electromagnetic shielding layer is arranged on the die. The passivation layer is disposed on the electromagnetic shielding layer. The dielectric layer is disposed on the passivation layer. The heat dissipation cover is disposed on the thermal-conductive metal layer. An inner tin layer of the heat dissipation cover and the thermal-conductive metal layer jointly form an intermetallic compound layer to firmly connect the heat dissipation cover to a welding base layer of the welding composite layer.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/498 - Leads on insulating substrates
• H01L 23/552 - Protection against radiation, e.g. light

Abstract

A communication apparatus having a frequency tracking mechanism is provided. A phase compensation circuit performs phase compensation on a packet according to a frequency offset to generate a phase-compensated symbol section for a symbol processing circuit to descramble and equalize thereon to generate a phase difference and a difference from a previous symbol section such that a residual frequency offset estimation circuit calculates a ratio to generate an instant frequency offset estimation value. A frequency offset smoothing calculation circuit performs calculation according to a function having a positive correlation with the difference to generate a modification coefficient to be multiplied by the instant frequency offset estimation value and a smoothing coefficient to generate a smoothed frequency offset estimation value and adds a previous frequency offset estimation value by the smoothed frequency offset estimation value to generate a current frequency offset estimation value to update the frequency offset.

IPC Classes  ?

• H04L 27/00 - Modulated-carrier systems

Abstract

The present invention provides an electronic device including a first circuit module, a second circuit module and a transmission module is disclosed. The transmission module is coupled between the first circuit module and the second circuit module, wherein the first circuit module transmits multiple data to the second circuit module through the transmission module, and the transmission module includes at least one stage of driving circuits. Each stage of driving circuit includes multiple retimed pipeline flip-flops, and during clock tree synthesis, only the flip-flops within each stage of the driving circuit are clock balanced, and if there are multiple stages of driving circuits, no clock balance is performed between the multiple stages of driving circuits.

IPC Classes  ?

• H03K 3/037 - Bistable circuits
• H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Abstract

A universal serial bus type-C (USB-C) connecter chip, a test system and a calibration method of the USB-C connecter chip are provided. The USB-C connecter chip includes the determination circuit and a calibration control circuit, wherein the determination circuit is configured to determine whether a detection voltage on a detection pin of the USB-C connecter chip reaches a threshold voltage. In a first calibration phase, the calibration control circuit sets the detection voltage to a first direct current (DC) level to obtain a first calibration value of the threshold voltage. In a second calibration phase, the calibration control circuit sets the detection voltage to a second DC level to obtain a second calibration value of the threshold voltage. More particularly, the calibration control circuit determines a final calibration value of the threshold voltage according to the first calibration value and the second calibration value.

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
• G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
• G01R 35/00 - Testing or calibrating of apparatus covered by the other groups of this subclass

Abstract

A method for detecting a speech rate is disclosed. The method for detecting the speech rate includes: obtaining a digital audio signal; acquiring a plurality of audio frames from the digital audio signal and setting an observation window that includes a plurality of first audio frames in the audio frames; determining whether the observation window belongs to speech or not; if the observation window belongs to speech, performing a local peak detection on the first audio frames; accumulating a syllable count if the local peak detection shows that the first audio frames include a discontinuous peak; and calculating the speech rate based on the syllable count.

IPC Classes  ?

• G10L 25/78 - Detection of presence or absence of voice signals
• G10L 25/45 - Speech or voice analysis techniques not restricted to a single one of groups characterised by the type of analysis window
• G10L 25/93 - Discriminating between voiced and unvoiced parts of speech signals

Abstract

An analog to digital conversion device includes a first slope signal generator circuit, a second slope signal generator circuit, and a comparator circuit. The first slope signal generator circuit is configured to generate a first slope signal, wherein the first slope signal repeatedly ramps up and down within a first voltage range with at least one first slope. The second slope signal generator circuit is configured to generate a second slope signal, wherein the second slope signal repeatedly ramps up and down within a second voltage range with at least one second slope. The comparator circuit is configured to generate an output signal according to the first slope signal, the second slope signal, and an input signal.

IPC Classes  ?

• H03M 1/34 - Analogue value compared with reference values

Abstract

An analog to digital conversion device includes a first slope signal generator circuit, a second slope signal generator circuit, and a comparator circuit. The first slope signal generator circuit is configured to generate a first slope signal, wherein the first slope signal repeatedly ramps up and down within a voltage range with at least one first slope. The second slope signal generator circuit is configured to generate a second slope signal, wherein the second slope signal repeatedly ramps up and down within the voltage range with at least one second slope, and the at least one first slope and the at least one second slope are negatively related. The comparator circuit is configured to generate an output signal according to the first slope signal, the second slope signal, and an input signal.

IPC Classes  ?

• H03M 1/50 - Analogue/digital converters with intermediate conversion to time interval

Abstract

The present disclosure discloses a home network system. A first network node includes a high-speed home network transmitting device to split, process and perform frequency up-shifting on a data signal to generate up-shifted data signals corresponding to radio frequency bands different and independent from each other so as to be combined to generate a transmitting data signal to be transmitted through a wired transmission media. A second network node includes a high-speed home network receiving device to separate, perform frequency down-shifting on and process the transmitting data signal to generate processed data signals to be reconstructed to generate the data signal.

IPC Classes  ?

• H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
• H04L 27/26 - Systems using multi-frequency codes
• H04L 47/125 - Avoiding congestionRecovering from congestion by balancing the load, e.g. traffic engineering
• H04W 28/10 - Flow control
• H04W 72/0453 - Resources in frequency domain, e.g. a carrier in FDMA

Abstract

A log-likelihood ratio scaling method includes: during a preamble period, determining a channel gain of a corresponding subcarrier and an average channel gain value of all subcarriers according to the preamble of a packet, determining a log-likelihood ratio average value according to the average channel gain value and the scaling parameter, and determining a scaling factor according to the average channel gain value, the channel gain and a scaling parameter; and during a payload period, generating an original log-likelihood ratio sequence according to the payload of the packet, adjusting the original log-likelihood ratio sequence according to the log-likelihood ratio average value and the scaling factor to generate a first log-likelihood ratio sequence, and adjusting the first log-likelihood ratio sequence according to the scaling factor to generate a second log-likelihood ratio sequence, where the second log-likelihood ratio sequence is quantized and decoded to provide the relevant information of the payload.

IPC Classes  ?

• H04B 7/0426 - Power distribution
• H04B 17/318 - Received signal strength

Abstract

A cache circuit is provided. A write counter circuit cyclically generates a counting value in turn corresponding to one of reference values. In an address storage circuit, an address storage demultiplexer receives and writes an valid write address to one of address registers according to the counting value, each of comparison circuits compares a read address content and a stored address content to generate a comparison result, and a priority decoding circuit determines a latest matched comparison result according to the counting value to generate a selection signal. In a data storage circuit, a data storage demultiplexer receives and writes a valid write data corresponding to the valid write address to one of data registers according to the counting value and a selection circuit receives the selection signal to select stored data or read data outputted from a memory to be actual read data.

IPC Classes  ?

• G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Abstract

An analog to digital conversion device includes a slope signal generator circuit and a comparator circuit. The slope signal generator circuit is configured to generate a slope signal within a first sub-voltage range of a voltage range according to a first current source, and generate the slope signal within a second sub-voltage range of the voltage range according to a second current source, wherein the slope signal repeatedly ramps up and down within the voltage range with at least one slope. The comparator circuit is configured to generate an output signal according to the slope signal and an input signal.

IPC Classes  ?

• H03M 1/50 - Analogue/digital converters with intermediate conversion to time interval

Abstract

A method for using in a circuit design process includes: deriving information regarding a specific cell from a cell library; generating an initial dataset based on the information regarding the specific cell; constructing or optimizing a machine learning model based on the initial dataset; and generating one or more target characteristic data regarding the specific cell based on the constructed or optimized machine learning model.

IPC Classes  ?

• G06N 20/00 - Machine learning
• G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A power consumption level measurement device includes a time-division multiplexing meter and a time-division multiplexing calculator. The time-division multiplexing meter includes a plurality of measurement terminals. The plurality of measurement terminals are configured to measure a plurality of power consumption levels of a plurality of devices under test. The time-division multiplexing calculator is configured to set the plurality of power consumption levels to a common time reference, and calculate a plurality of measurement values of the plurality of power consumption levels.

IPC Classes  ?

• G01R 21/133 - Arrangements for measuring electric power or power factor by using digital technique

Abstract

A data receiving apparatus having a data valid window expanding mechanism is provided. A data pre-processing circuit performs AND and OR logic operations on an input data signal and a delayed data signal to generate an AND gate processed signal and an OR gate processed signal. A sampling circuit performs sampling according to a sampling rising edge and a sampling falling edge of a data strobe signal to generate AND gate rising and falling edge sampling results and OR gate rising and falling edge sampling results such that a rising edge selection circuits and a falling edge selection circuit determine a current rising edge sampling result and a current falling edge sampling result to control a rising edge data multiplexer and a falling edge data multiplexer to output current rising edge data and current falling edge data accordingly.

IPC Classes  ?

• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches

Abstract

An audio device includes an input/output interface, a search circuit, a memory, and a processor. The input/output interface is configured to receive at least one SDCA audio topology control item from an audio system host. The search circuit is configured to search a target index from an address correspondence table according to a plurality of key information of at least one SDCA audio topology control item, to point to a target control item and a target storage addresses through the target index, and to transmit an interrupt signal corresponding to the target control item. The processor is configured to obtain the operation program corresponding to the interrupt signal from the memory according to the interrupt signal, and to execute operations at the target storage address corresponding to the target control item based on the operation program to control the audio device.

IPC Classes  ?

• G06F 3/16 - Sound inputSound output

Abstract

The present invention provides a processing circuit of a display, which includes a statistical circuit, a backlight brightness calculation circuit and a local dimming control circuit. The statistical circuit is configured to calculate brightness characteristic of each region of multiple regions in image data. The backlight brightness calculation circuit is configured to determine backlight brightness of each region according to ambient light brightness of the display and the brightness characteristics of each region. The local dimming control circuit is coupled to the backlight brightness calculation circuit, and is configured to generate a corresponding backlight control signal according to the backlight brightness of each region to control at least one backlight source in a display panel of the display corresponding to the region.

IPC Classes  ?

• G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source

Abstract

An audio input circuit includes a single-ended signal input circuit, a differential signal input circuit, a first amplifier circuit, and a second amplifier circuit. The single-ended signal input circuit is enabled by switches in a single-ended mode to output a single-ended audio signal to the first amplifier circuit. The differential signal input circuit is enabled by switches in a differential mode to output a differential audio signal to the first amplifier circuit. The first amplifier circuit outputs an inverted audio output signal to the second amplifier circuit according to signals it received. The second amplifier circuit outputs a non-inverted audio output signal according to signals it received. In the single-ended and differential modes, the signals inputted to non-inverting inputs of the first and second amplifier circuits are DC signals to stabilize the on-resistance linearity of the switches and prevent the deterioration of the audio input circuit's total harmonic distortion.

IPC Classes  ?

• H03F 3/45 - Differential amplifiers
• H04R 3/00 - Circuits for transducers

Abstract

A circuit detection method executed by a processor reading at least command stored in a memory is disclosed herein. The circuit detection method includes following steps: detecting whether a destination power domain corresponding to a destination circuit is in an active state; detecting whether an intermediate power domain corresponding to an intermediate circuit preceding the destination circuit is in an inactive state; and if the intermediate power domain corresponding to the intermediate circuit is in the inactive state and the destination domain corresponding to the destination circuit is in the active state, generating a circuit detection report.

IPC Classes  ?

• G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Abstract

A system and a method for training a multimodal behavior prediction model. The method is performed in a computing device that includes a processor and a neural processor. The processor retrieves multiple types of sensor data generated by one or more untrusted sensors and trusted sensors, and the neural processor uses multiple types of models corresponding to the multiple types of sensor data to predict behaviors of a user. The sensor data generated by the trusted sensors can be used to train the sensor data that are generated by the one or more untrusted sensors at the same time so as to train one or more prediction models. Therefore, the neural processor uses the trained prediction models and the trusted model to jointly establish the multimodal behavior prediction model that can be used to predict behaviors of the user and send a reminder for a specific event.

IPC Classes  ?

• G06N 3/08 - Learning methods
• G06F 40/284 - Lexical analysis, e.g. tokenisation or collocates
• G06V 40/20 - Movements or behaviour, e.g. gesture recognition

Abstract

A communication method adopted by a Bluetooth system is provided. The Bluetooth system includes a master device and a slave device. The communication method includes the master device and the slave device establishing a connection, the master device sending a power-saving command to the slave device, in response to the power-saving command, the slave device sending a power-saving acknowledgement command to the master device, then terminating the connection and entering a slave power-saving mode, and in response to the power-saving acknowledgement command, the master device entering a master power-saving mode.

IPC Classes  ?

• H04W 52/02 - Power saving arrangements
• H04W 76/20 - Manipulation of established connections

Abstract

A class-D amplifier includes a loop filter configured to receive first and second feedback signals, to receive first and second input signals through first and second resistors respectively, and to filter the first and second input signals and the first and second feedback signals to generate first and second filtered signals; a triangle wave generator configured to generate a triangle wave according to first and second reference voltages; first and second comparators configured to compare the first and second filtered signals with the triangle wave respectively to generate the first and second pulse width modulation (PWM) signals, respectively; first and second driver circuits configured to generate first and second output signals according to the first and second PWM signals, respectively; and a reference voltage generation circuit configured to generate the first and second reference voltages according to a control signal.

IPC Classes  ?

• H03F 3/217 - Class D power amplifiersSwitching amplifiers
• H03F 1/30 - Modifications of amplifiers to reduce influence of variations of temperature or supply voltage

Abstract

A latency first-in-first-out (FIFO) circuit having a low power dissipation mechanism is provided that includes a counting circuit, FIFO buffers, an input circuit and an output circuit. The counting circuit in turn generates a counting value corresponding to one of reference values in a circular manner. Each of the FIFO buffers corresponds to a corresponding one of the reference values and includes stored data. The input circuit receives and writes the input data to one of the FIFO buffers according to the counting value. The output circuit selects the stored data of one of the FIFO buffers according to the counting value to be outputted as delayed data.

IPC Classes  ?

• G06F 5/06 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising

Abstract

A communication device includes a first transmitting signal processing circuit, a first receiving signal processing circuit, a baseband signal processing circuit, and a control unit. The first transmitting signal processing circuit is enabled in a sensing mode, and transmits a first radio frequency (RF) signal within a wireless communication environment, wherein the first RF signal comprises a predetermined packet. The first receiving signal processing circuit is enabled in the sensing mode, and receives a second RF signal, wherein the second RF signal includes a first packet originating from the predetermined packet. The baseband signal processing circuit generates the predetermined packet according to bit stream data, receives the first packet from the first receiving signal processing circuit, and performs a channel estimation operation according to the first packet in order to generate channel information. The control unit determines an object characteristic within the wireless communication environment according to the channel information.

IPC Classes  ?

• G01S 13/76 - Systems using reradiation of radio waves, e.g. secondary radar systemsAnalogous systems wherein pulse-type signals are transmitted

Abstract

A multi-link operation transmission system includes a transmission information device, a reinforcement learning device, and a feedback device. The transmission information device is configured to transmit a plurality of packages to a receiving device with an initial transmission state through a plurality of channels. The feedback device is configured to feed back the initial transmission state and a transmission result. The reinforcement learning device is configured to provide a transmission rate to the transmission information device according to the initial transmission state and the transmission result provided by the feedback device such that the transmission rate of the transmission information device conforms to the plurality of channels.

IPC Classes  ?

• H04W 28/02 - Traffic management, e.g. flow control or congestion control
• H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
• H04L 43/0823 - Errors, e.g. transmission errors

Abstract

A communication method for a communication system includes a first device sending a device power-on packet to the second device, in response to the device power-on packet, resetting a second device, after the second device is reset, the second device sending a first handshake packet to the first device, and in response to the first handshake packet, the first device returning a second handshake packet to the second device.

IPC Classes  ?

• H04L 1/18 - Automatic repetition systems, e.g. Van Duuren systems
• H04L 5/00 - Arrangements affording multiple use of the transmission path
• H04L 69/22 - Parsing or analysis of headers

Abstract

The present disclosure is related to a mobile device, of which an image processing circuit is electrically connected to two buses, and a processor transmits an instruction and multiple coefficients of an inverse matrix to the image processing circuit through the second bus. The instruction instructs to perform a transformation process on an input image. Based on the inverse matrix and the coordinates of an output pixel, the image processing circuit calculates the coordinates of an input pixel of the input image, thereby reading the input pixel from a memory through the first bus. The image processing circuit also writes the output pixel to the memory through the first bus.

IPC Classes  ?

• G06T 3/4007 - Scaling of whole images or parts thereof, e.g. expanding or contracting based on interpolation, e.g. bilinear interpolation
• G06T 3/02 - Affine transformations
• G06T 5/50 - Image enhancement or restoration using two or more images, e.g. averaging or subtraction

Abstract

A switch circuit operating beyond a component withstand voltage condition includes a bias circuit, at least one first transistor, a plurality of second transistors, and a third transistor. The bias circuit includes a plurality of bias components connected in series, and is coupled to a voltage source, to form a plurality of voltage drop nodes through the bias components. The second transistors are connected in series, are coupled to the voltage source, and are coupled to the voltage drop nodes in a one-to-one manner. A first transistor is arranged between any two adjacent second transistors among the second transistors. The third transistor is connected in series with the second transistors to form a switch path. When the third transistor receives a control signal and is turned on, the first transistors are turned off, and the second transistors are turned on, thereby turning on the switch path.

IPC Classes  ?

• H03K 17/10 - Modifications for increasing the maximum permissible switched voltage

Abstract

A DisplayPort (DP) output adapter and a method for controlling a clock signal of the DP output adapter are disclosed. The DP output adapter includes a clock generator, a storage device and a controller, wherein the storage device is coupled to the clock generator, and the controller is coupled to the clock generator and the storage device. The clock generator outputs the clock signal according to a control code, wherein the control code is associated with a frequency of the clock signal. The storage device stores input data received from a DP source device by the DP output adapter, and transmits output data stored in the storage device to a DP sink device according to the clock signal. In addition, the controller controls the control code according to a data amount of the storage device.

IPC Classes  ?

• G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom

Abstract

An oscillator circuit having voltage-withstanding mechanism is provided. An inductor circuit is coupled to a pair of oscillating output terminals. A cross-coupled transistor circuit is coupled between the oscillating output terminals and a first terminal. A capacitor circuit is coupled between the oscillating output terminals. A first source degeneration circuit includes a first inductor, a first capacitor, a second capacitor and a first source degeneration circuit. The first inductor is coupled between the first terminal and a first power voltage. The first capacitor is coupled between the first terminal and a second terminal. The second capacitor is coupled between the first power voltage and a third terminal that is coupled to a second power voltage. The first source degeneration is coupled between the second terminal and the third terminal and is turned on based on a first feeding voltage.

IPC Classes  ?

• H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device

Abstract

An oscillator circuit having phase-noise decreasing mechanism is provided. An inductor circuit includes an inductor coil surrounding a central area and coupled between oscillating output terminals. A capacitor circuit is coupled between the oscillating output terminals. A cross-coupled CMOS circuit is disposed between the inductor circuit and the capacitor circuit to be coupled to the oscillating output terminals. A first wire and a second wire stretch along with an axis to traverse the central area to divide the central area into two sub areas. A first and a second source degeneration circuits are disposed at the second side of the inductor coil and are respectively disposed at two symmetrical sides of the axis. The first and the second source degeneration circuits respectively are coupled to the cross-coupled CMOS circuit through the first and the second wires.

IPC Classes  ?

• H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device

Abstract

The present invention provides a control method of an in-loop filter, which includes steps of: sequentially receiving multiple CTUs of image data; for a specific CTU of the multiple CTUs, dividing the specific CTU into multiple blocks; performing a deblocking-filtering operation on a first portion of vertical boundaries and horizontal boundaries of the multiple blocks to generate filtered pixel values; not performing the deblocking-filtering operation on a second portion of the vertical boundaries and the horizontal boundaries of the multiple blocks to generate non-filtered pixel values; performing the deblocking-filtering operation on a third portion of the vertical boundaries and the horizontal boundaries of the multiple blocks to generate partially filtered pixel values; and generating parameters according to the filtered pixel values, the non-filtered pixel values and the partially filtered pixel values, for use by a next filter.

IPC Classes  ?

• H04N 19/86 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving reduction of coding artifacts, e.g. of blockiness
• H04N 19/117 - Filters, e.g. for pre-processing or post-processing
• H04N 19/167 - Position within a video image, e.g. region of interest [ROI]
• H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
• H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding

Abstract

A wireless network operation method having power saving mechanism is provided. Packet storage states of node apparatuses are retrieved by a root node apparatus from an access point apparatus. For each of the node apparatuses, a node packet storage state table indicating the packet storage states is configured and a beacon signal including the node packet storage state table is broadcasted in an independent periodic broadcast time. For each of the node apparatuses, the beacon signals are received and the node packet storage state table included by the beacon signal is analyzed to update the node packet storage state table. For each of the node apparatuses entering a sleep mode, a predetermined schedule is performed to wake up to perform a packet transmitting process when the packet storage state of any one of the node apparatuses and the child node apparatus thereof has a storage indication level.

IPC Classes  ?

• H04W 52/02 - Power saving arrangements

Abstract

A sigma-delta modulator (SDM) is coupled to a driving circuit through a first input terminal and receives an intermediate signal outputted by the driving circuit. The SDM includes an operational amplifier, first and second sampling capacitors, and first and second integrating capacitors. The operational amplifier has a second input terminal, a third input terminal, and an output terminal. Two terminals of the first sampling capacitor are respectively coupled to the first and second input terminals for sampling the intermediate signal. Two terminals of the second sampling capacitor are respectively coupled to the first and second input terminals for sampling the intermediate signal. Two terminals of the first integrating capacitor are respectively coupled to the second input terminal and the output terminal. Two terminals of the second integrating capacitor are respectively coupled to the second input terminal and the output terminal.

IPC Classes  ?

• H03M 3/00 - Conversion of analogue values to or from differential modulation

Abstract

An analog-to-digital conversion device includes a switch, a capacitor array, a comparator, and a logical control circuit. The switch is configured to sample at least one input signal according to a sampling signal. The capacitor array includes a plurality of capacitors. The plurality of capacitors are configured to store the at least one input signal. The comparator is configured to generate a comparing result according to the at least one input signal stored in the plurality of capacitors of the capacitor array. The logical control circuit is configured to respectively reset the plurality of capacitors according to a conversion end signal or the sampling signal.

IPC Classes  ?

• H03M 1/44 - Sequential comparisons in series-connected stages with change in value of analogue signal

Abstract

A network nodes pairing method having an anti-spoofing mechanism is provided used in a mesh network system. Each of node apparatuses in the mesh network system uses group information of the mesh network system as a key to encrypt network system identification information and self-identification information to broadcast a beacon signal including encrypted information. A scan process is executed by a child node apparatus to select a target father node. A validity verification process is performed on the beacon signal of the target father node according to the group information so as to determine the target father node passes the validity verification process when the target father node and the child node apparatus has the same network system identification information and when the self-identification information of the target father node is valid. A pairing request signal is transmitted to the target father node to request for pairing.

IPC Classes  ?

• H04W 12/122 - Counter-measures against attacksProtection against rogue devices
• H04W 12/037 - Protecting confidentiality, e.g. by encryption of the control plane, e.g. signalling traffic
• H04W 12/041 - Key generation or derivation
• H04W 12/106 - Packet or message integrity
• H04W 76/14 - Direct-mode setup
• H04W 84/20 - Leader-follower arrangements

Abstract

A network configuration updating method having configuration stabilizing mechanism used in a mesh network system is provided. Network configuration information including father node identification information, child node identification information recorded in an assistance table, length information and a configuration information identification code is configured by each of node apparatuses to further broadcast a broadcast signal including the network configuration information. The broadcast signal of any other node apparatuses is received by each of the node apparatuses to determine that the broadcast signal includes the network configuration information according to the configuration information identification code, determine an initial position of the child node identification information according to the length information, and retrieve the father node identification information and the child node identification information. The assistance table is updated according to the father node identification information and the child node identification information.

IPC Classes  ?

• H04L 41/12 - Discovery or management of network topologies
• H04L 67/12 - Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks

Abstract

The present invention provides a method applied to an electronic device supporting NB-IoT, The method comprises steps of: selecting a cost function; simulating a first PDF of the cost function at a target center frequency, a second PDF of the cost function at a first adjacent center frequency of the target center frequency, a third PDF of the cost function at a second adjacent center frequency of the target center frequency, and a fourth PDF of the cost function at a pure noise center frequency, wherein the target center frequency is a center frequency of a frame transmitted by a base station; and calculating a probability that the electronic device successfully detects the target center frequency of the frame from the base station through a frequency scanning, according to the first PDF, the second PDF, the third PDF and the fourth PDF.

IPC Classes  ?

• H04B 17/373 - Predicting channel quality parameters

Abstract

A clock self-control circuit, comprising: a clock signal generation circuit, configured to generate a target clock signal according to a clock enable signal; and a target circuit, configured to receive the target clock signal, and configured to operate according to the target clock signal and to generate the clock enable signal.

IPC Classes  ?

• G06F 1/08 - Clock generators with changeable or programmable clock frequency
• H03K 5/13 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals

Abstract

An operation method of an electronic display device includes: receiving multiple data sources; providing a display screen to respectively display the multiple data sources of the multiple data source devices by activating multiple different windows; providing a peripheral control circuit to receive a user control signal from an external peripheral device to transfer the user control signal into the controller circuit; and, controlling the display screen based on the user control signal to control the display screen respectively displaying the multiple data sources through multiple different windows, to respectively and dynamically control and manage the picture positions on the display screen and dynamically controlling the window sizes of the multiple different windows.

IPC Classes  ?

• G06F 3/14 - Digital output to display device
• G06F 3/0354 - Pointing devices displaced or positioned by the userAccessories therefor with detection of 2D relative movements between the device, or an operating part thereof, and a plane or surface, e.g. 2D mice, trackballs, pens or pucks
• G06F 3/16 - Sound inputSound output

Abstract

A time-to-charge converter (TCC) includes a phase detector configured to receive a first clock and a second clock and output a phase error signal indicative of the time difference between the second clock and the first clock; a current source configured to generate a tail current; a current directing network configured to direct the tail current towards either a first node or a second node based on the phase error signal; a synchronous clock generator configured to receive the first clock and generate a third clock that is synchronous to the first clock but has an independently determined duty cycle; an integration capacitor having a top plate connected to the second node and a bottom plate driven by an inversion of the third clock; a switch positioned between a third node and the second node, controlled by the third clock; and a load capacitor attached to the third node.

IPC Classes  ?

• H03L 7/06 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop
• G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
• H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses

Abstract

The present invention provides a voice recognition method, which includes the steps of: receiving a plurality of voice signals; performing a time-domain to frequency-domain conversion operation on the plurality of voice signals to generate a plurality of frequency-domain signals; using a morphological filter to perform filtering operations on the plurality of frequency-domain signals to generate a plurality of filtered backgrounds; generating a plurality of initial voice fingerprints according to the plurality of filtered backgrounds, wherein each of the plurality of initial voice fingerprints comprises times and frequency points corresponding to a plurality of peaks in the corresponding filtered background; generating at least one voice fingerprint according to the plurality of initial voice fingerprints; and storing the at least one voice fingerprint in a memory for subsequent voice recognition operation.

IPC Classes  ?

• G10L 17/02 - Preprocessing operations, e.g. segment selectionPattern representation or modelling, e.g. based on linear discriminant analysis [LDA] or principal componentsFeature selection or extraction
• G10L 17/04 - Training, enrolment or model building
• G10L 17/06 - Decision making techniquesPattern matching strategies
• G10L 21/0232 - Processing in the frequency domain

Abstract

A capacitor array includes a first bottom plate, at least one top plate, at least one strip-shaped bottom plate, a first via, a second bottom plate, and a second via. The at least one top plate is disposed above the first bottom plate. The at least one strip-shaped bottom plate is disposed above the first bottom plate, and disposed outside the at least one top plate. The first via connects the first bottom plate to the at least one strip-shaped bottom plate. The second bottom plate is disposed above the at least one top plate and the at least one strip-shaped bottom plate. The second via connects the at least one bottom plate to the second bottom plate.

IPC Classes  ?

• H01G 4/38 - Multiple capacitors, i.e. structural combinations of fixed capacitors
• H01G 4/228 - Terminals
• H01G 4/30 - Stacked capacitors
• H01G 4/40 - Structural combinations of fixed capacitors with other electric elements not covered by this subclass, the structure mainly consisting of a capacitor, e.g. RC combinations

Abstract

A training system, a training method, a dimming system, a dimming method, a computer-readable recording medium with a stored program, and a non-transitory computer program product are provided. The training method is used for training a to-be-trained neural network module and is performed by a processing module. The to-be-trained neural network module includes a target image generation module, a to-be-trained neural network, and a light distribution generation module. The training method includes: performing the following steps in one training epoch: repeatedly performing: using a training image in a training set as an input image, performing a convolution operation on an intermediate compensation image of the training image and light distribution to generate a convolutional image, and obtaining a loss based on the convolutional image and a target image; and updating a plurality of parameters based on an average of all losses obtained in the foregoing step and an updated algorithm.

IPC Classes  ?

• G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
• G06N 3/045 - Combinations of networks
• G06N 3/0464 - Convolutional networks [CNN, ConvNet]
• G06T 5/60 - Image enhancement or restoration using machine learning, e.g. neural networks
• G06T 5/92 - Dynamic range modification of images or parts thereof based on global image properties
• G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source

Abstract

The presented harmonic compensation apparatus includes a harmonic compensation circuit, a conversion circuit, an analog output circuit and a compensation control circuit. The harmonic compensation circuit performs a harmonic generation process and a compensation adjusting process on a digital input signal according to a compensation parameter control signal to generate a harmonic compensation digital signal. The conversion circuit performs a harmonic compensation and a signal conversion on the digital input signal according to the harmonic compensation digital signal to generate an analog input signal. The analog output circuit generates an analog output signal to an external circuit according to the analog input signal and detects a loading state of the external circuit to generate a loading state detection signal, wherein the harmonic compensation eliminates a harmonic component of the analog output signal. The compensation control circuit generates the compensation parameter control signal according to the loading state.

IPC Classes  ?

• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters

Abstract

A semiconductor device includes a substrate, a circuit layer, a dielectric layer, a trace layer, a metal buffer layer, and a metal wire bonding pad. The circuit layer is on an upper surface of the substrate. The dielectric layer is on an upper surface of the circuit layer. The trace layer is on an upper surface of the circuit layer and in the dielectric layer. The metal buffer layer is on an upper surface of the trace layer and in the dielectric layer. The metal wire bonding pad is on an upper surface of the metal buffer layer.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An image processing method comprises: receiving an initial image by an image processor; setting a first core image and a first peripheral image according to a regional parameter and the initial image, wherein the region parameter is configured to indicate the size of the first core image; and adjusting the size of the first core image and the first peripheral image respectively to generate a second core image and a second peripheral image, wherein the adjustment ratios of the first core image and the first peripheral image are different.

IPC Classes  ?

• G06T 3/40 - Scaling of whole images or parts thereof, e.g. expanding or contracting
• G06T 11/00 - 2D [Two Dimensional] image generation

Abstract

A channel tracking control method, applied to a multiple-input multiple-output orthogonal frequency-division multiplexing communication system, includes the following operations: during a preamble period of a packet, determining a noise power according to a preamble of the packet, in which the preamble is transmitted via sub-carriers; during the preamble period, determining a clipping level value corresponding to a sub-carrier in the sub-carriers according to a noise reduction factor of a channel detection circuit; during the preamble period, determining a signal-to-noise ratio of the sub-carrier according to the clipping level value and the noise power; and according to the signal-to-noise ratio and a target signal-to-noise ratio, controlling a channel tracking circuit to stop tracking a channel response of the sub-carrier during a payload period of the packet.

IPC Classes  ?

• H04B 7/0413 - MIMO systems
• H04L 5/00 - Arrangements affording multiple use of the transmission path
• H04L 25/02 - Baseband systems Details

Abstract

A semiconductor device includes a substrate, a plurality of bumps, and a chip. The substrate has an upper surface and a lower surface. The substrate includes a plurality of lower contacts, a plurality of upper contacts, a first trace layer, a second trace layer, a metal heat dissipation unit, a cavity, and a voltage regulator. The first trace layer is between the upper surface and the lower surface. The second trace layer is on the first trace layer. The metal heat dissipation unit is between the first trace layer and the second trace layer. The cavity is on one side of the substrate. A portion of the first trace layer is exposed at a bottom of the cavity. The voltage regulator is in the cavity and electrically connected to the first trace layer. Each of the bumps is electrically connected to a corresponding one of the upper contacts.

IPC Classes  ?

• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/03 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

An electronic device includes a carrier, a first die, and a second die. The first die is disposed on the carrier and includes a first bonding pad and a second bonding pad. The second die is disposed on the carrier and includes a third bonding pad and a fourth bonding pad. The first bonding pad is directly connected to the third bonding pad through a first bonding wire, and the second bonding pad is directly connected to the fourth bonding pad through a second bonding wire. The first bonding pad has a recessed space, and the second bonding pad is disposed in the recessed space.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices