For bit errors caused by intrinsic cell variations, the bit errors are scattered across a page of memory. However, for bit errors caused by a physical issue in memory, the bit errors cluster together within the same memory area. In an example data storage device, a page of memory is divided into sections, and counters are used to count the number of errors in each section. A physical error location is detected if the number exceeds a parameter, and as compared to the number of errors in the other sections. In another example data storage device having an error correction code (ECC) engine, a histogram and binomial probability are used to detect physical errors. This has the advantage of detecting weak memory blocks that are about to fail, so the blocks can be retired early as a grown bad block.
Instead of using address translation cache (ATC) to translate addresses for host queues, bypass the ATC and directly use translated addresses. When creating the submission queues (SQ) or completion queues (CQ), the controller receives the untranslated addresses from the host, and the device is responsible for translating the untranslated addresses before accessing the host queues. The host queue pointers will directly use the translated addresses while bypassing the ATC. When bypassing the ATC, different flows can be used such as create queue command flow and invalidate operations. In a create queue command flow, the firmware (FW) performs address translation by interacting with a translation agent (TA) to receive the translated addresses. With an invalidate flow, the controller scans all untranslated addresses provided by the host at the queue creation time and compares the untranslated addresses against the invalidated address.
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and configured to store a threshold voltage. A control means is coupled to the plurality of word lines and is configured to apply at least one programming pulse of a program voltage to selected ones of the plurality of word lines during at least one programming loop of a programming operation. The control means is also configured to reduce the threshold voltage of the memory cells targeted for an erased state during a bit-level erase operation following the programming operation.
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
The present disclosure generally relates to spin-orbit torque (SOT) device comprising a first bismuth antimony (BiSb) layer having a (001) orientation. The SOT device comprises a first BiSb layer having a (001) orientation and a second BiSb layer having a (012) orientation. The first BiSb layer having a (001) orientation is formed by depositing an amorphous material selected from the group consisting of: B, Al, Si, SiN, Mg, Ti, Sc, V, Cr, Mn, Y, Zr, Nb, AlN, C, Ge, and combinations thereof, on a substrate, exposing the amorphous material to form an amorphous oxide surface on the amorphous material, and depositing the first BiSb layer on the amorphous oxide surface. By utilizing a first BiSb layer having a (001) orientation and a second BiSb having a (012) orientation, the signal through the SOT device is balanced and optimized to match through both the first and second BiSb layers.
Instead of using programmable block size aggregation, a lower multiple of page, and down to a page size aggregation is used. A bad block prediction unit in a controller is able to predict when a programmable block has a bad page. The bad block prediction unit can lower the aggregation size of a programmable block by monitoring the life cycle of the programmable block through bad block statistic collection. When the accumulation size passes a threshold, the bad block prediction unit lowers the aggregation size. The bad block prediction unit can also predict when to lower aggregation size based on the number of reconstructions. An aggregate size level is set at a page boundary, and once the number of reconstructions reaches that page boundary, the bad block prediction unit lowers the aggregation size to page aggregation. The bad block prediction unit is able to predict both life cycle threshold changes and reconstructions changes.
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. A control means applies verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines and counts the memory cells having the threshold voltage below each of the program verify voltages targeted for each of the memory cells being programmed during each of a plurality of verify loops of a program-verify operation. The control means terminates the plurality of verify loops for the memory cells targeted for one of the data states in response to the count of the memory cells exceeding a predetermined count threshold. The predetermined count threshold is different for at least one of the data states compared to other ones of the data states.
A streaming data interface or a ‘telemetry tap’ in conjunction with a host defined telemetry program is used to regulate the type and amount of telemetry data sent to the host device. The amount of telemetry data provided to the host is based on a request. The controller will receive and execute valid host generated programs which define which telemetry operations should occur and be forwarded to the host via the streaming telemetry mechanism. The controller will use the user/host programmable mechanisms that will collaborate with internal drive logging mechanisms. The controller will watch for the host-defined programmable mechanisms and send the requested amount of telemetry data to the host once the programmable mechanisms have executed.
The present disclosure generally relates to a bismuth antimony (BiSb) based STO (spin torque oscillator) sensor. The STO sensor comprises a SOT device and a magnetic tunnel junction (MTJ) structure. By utilizing a BiSb layer within the SOT device, a larger spin Hall angle (SHA) can be achieved, thereby improving the efficiency and reliability of the STO sensor.
The present disclosure generally relates to spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices comprising a doped bismuth antimony (BiSbE) layer having a (012) orientation. The devices may include magnetic write heads, read heads, or MRAM devices. The dopant in the BiSbE layer enhances the (012) orientation. The BiSbE layer may be formed on a texturing layer to ensure the (012) orientation, and a migration barrier may be formed over the BiSbE layer to ensure the antimony does not migrate through the structure and contaminate other layers. A buffer layer and interlayer may also be present. The buffer layer and the interlayer may each independently be a single layer of material or a multilayer of material. The buffer layer and the interlayer inhibit antimony (Sb) migration within the doped BiSbE layer and enhance uniformity of the doped BiSbE layer while further promoting the (012) orientation of the doped BiSbE layer.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
The present disclosure generally relates to a dual free layer (DFL) read head and methods of forming thereof. In one embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a stripe height of the DFL sensor, depositing a rear bias (RB) adjacent to the DFL sensor, defining a track width of the DFL sensor and the RB, and depositing synthetic antiferromagnetic (SAF) soft bias (SB) side shields adjacent to the DFL sensor. In another embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a track width of the DFL sensor, depositing SAF SB side shields adjacent to the DFL sensor, defining a stripe height of the DFL sensor and the SAF SB side shield, depositing a RB adjacent to the DFL sensor and the SAF SB side shield, and defining a track width of the RB.
Methods of detecting molecules using an apparatus comprising a plurality of magnetic sensors are disclosed. A method may include binding a first molecule to a proximal wall of a fluid chamber of the apparatus, and adding, to the fluid chamber, a magnetically-labeled molecule comprising a cleavable magnetic label, wherein the magnetically-labeled molecule is configured to bind to or be incorporated by the first molecule. The method may use at least one address line and at least one selector element of the apparatus to detect a characteristic of at least a portion of the plurality of magnetic sensors, wherein the characteristic indicates whether the magnetically-labeled molecule has bound to or been incorporated by the first molecule.
G01N 27/08 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a liquid which is flowing continuously
G01N 27/74 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating magnetic variables of fluids
G01N 33/58 - Chemical analysis of biological material, e.g. blood, urineTesting involving biospecific ligand binding methodsImmunological testing involving labelled substances
Embodiments of the disclosed technology relate to the operation of memory devices, and more particularly to sub-block mode (SBM) pre-charge operation sequences. One example embodiment provides a novel logic design of the control circuitry of a memory device using comments/instructions for the control circuitry. By virtue of the features of the disclosed technology, the control circuitry can effect pre-charging of an inner or middle vertical sub-block of a NAND string in a memory array. In some examples the NAND string has at least three vertical sub-blocks of non-volatile memory cells.
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, an array of memory openings vertically extending through the alternating stack, memory-opening-free areas located in the array of the memory openings in a plan view, an array of memory opening fill structures located in the array of memory openings, and layer contact assemblies located within the memory-opening-free areas in the plan view. Each of the memory opening fill structures includes a respective vertical semiconductor channel and respective memory elements located at levels of the electrically conductive layers. Each of the layer contact assemblies includes a respective layer contact via structure contacting a respective one of the electrically conductive layers, and a respective insulating spacer that laterally surrounds the respective layer contact via structure.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
15.
SHOCK ABSORBER ASSEMBLY FOR A PRINTED CIRCUIT BOARD
A shock absorber for a printed circuit board (PCB) includes a first portion and a second portion. The first portion is positioned on a first side of the PCB at or near a connector that extends from the PCB. The second portion is positioned on a second side of the PCB, opposite the first portion. The first and second portions prevent the PCB from moving when the PCB is coupled to a host device. As the PCB is subjected to various movements, strains and stresses, the shock absorber prevents the PCB from cracking or breaking, especially at or near the connector, which is susceptible to cracking and breaking.
A device carrier mechanism configured for attachment to an electronic device such as a hard disk drive includes a pair of rotatable handles interlocked at a common first pivot at a proximal end of each handle and a respective second pivot at a distal end, a pair of pin mechanisms each coupled at the second pivot of a respective handle and having a protruding latch pin, and a frame with which each pin mechanism is translatably coupled. Such a linkage system operates as an over-center mechanism, in a device handling state responsive to an upward handling force and with the latch pins in a retracted position within the frame, a neutral state with the latch pins in an extended position extending external to the frame, and a locked over-center state with the latch pins clamped in the extended position for locking into a data storage system.
A method of manufacturing hard disk drives (HDDs) includes assembling a first HDD including a first slider having a first air bearing surface (ABS) configuration, configuring the first HDD to rotate its disk media at a first revolutions-per-minute (RPM), and sealing the first HDD with a first internal pressure level. Continuing, the method includes assembling a second HDD including a second head slider having the same first ABS configuration, configuring the second HDD to rotate its disk media at a second RPM that is lower than the first RPM, and sealing the second HDD with a second internal pressure level that is higher than the first pressure level. Thus, in the context of using a common slider among different RPM drives, a higher internal pressure for the lower RPM drive can compensate for loss in fly height that might otherwise occur due to the lower operational RPM.
Improved automation can be achieved using command-parts. Rather than using a command to determine which key to use, command partitioning will generate a task-ID based on a key index table to determine what key to use. Based on the task-ID, an encryption engine (XTS) will know which key to use. The command is split into partitions with the same attributes. The amount of task-IDs created will equal the amount of partitions. Automation will be based on the task-IDs to create a completion for a host. The controller will then return to the key index table to count the completed commands and send the completion to the host.
A semiconductor structure includes a logic die containing a word line switching circuit containing a fin field effect transistor having at least one semiconductor fin, and a planar field effect transistor, and a memory die containing a three-dimensional memory device bonded to the logic die.
H01L 23/528 - Layout of the interconnection structure
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
20.
CROSS-POINT MAGNETORESISTIVE MEMORY ARRAY CONTAINING CARBON-BASED LAYER AND METHOD OF MAKING THE SAME
A device structure includes first electrically conductive lines that are laterally spaced apart from each other, second electrically conductive lines that are vertically spaced apart from the first electrically conductive lines and are laterally spaced apart from each other, a two-dimensional array of magnetoresistive random access memory (MRAM) pillars located between the first electrically conductive lines and the second electrically conductive lines, and each of the MRAM pillars includes a respective reference layer, a respective nonmagnetic tunnel barrier layer, and a respective free layer, and a two-dimensional array of carbon-based layers contacting surfaces of the first electrically conductive lines and surfaces of the two-dimensional array of MRAM pillars.
A memory device includes an alternating stack of insulating layers and electrically conductive layers containing stepped surfaces in a contact region, a first stepped dielectric material portion overlying the stepped surfaces of the alternating stack, a memory opening vertically extending at least through each layer within the alternating stack, a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel, and a bundled contact via structure vertically extending through the first stepped dielectric material portion and through a plurality of bottommost electrically conductive layers of the electrically conductive layers, and laterally contacting each of the plurality of the bottommost electrically conductive layers.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
22.
ASYMMETRIC VREADK TO REDUCE NEIGHBORING WORD LINE INTERFERENCE IN A MEMORY DEVICE
The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. The plurality of word lines include a selected word line, a pair of neighboring word lines that are immediately adjacent the selected word line, and a plurality of non-neighboring word lines that are not immediately adjacent the selected word line. Circuitry can perform a sensing operation on at least one memory cell in the selected word line. During the sensing operation, the circuitry is configured to apply a reference voltage to the selected word line, apply different first and second pass voltages to the neighboring word lines, and apply a third pass voltage that is different than the first and second pass voltages to the plurality of non-neighboring word lines. The circuitry is further configured to sense a threshold voltage of the at least one memory cell.
A storage device is communicatively coupled to a host that stores data on a primary memory package on the storage device. A controller on the storage device may monitor the temperature of components on the storage device and determine when the temperature exceeds a thermal temperature limit. When the temperature exceeds a thermal temperature limit, the controller may suspend certain operations on the primary memory package and write host data to the secondary memory package on the storage device. The controller may continue to monitor the temperature on the storage device, determine when the temperature on the storage device returns to an acceptable level, transfer data from the secondary memory package to the primary memory package, and resume writing host data to primary memory package.
Performance on a storage device may be improved when executing a write command with sequential host data. The storage device optimizes logical-to-physical table updates for fixed granularity logical-to-physical tables that are populated when writing the sequential host data. A host interface module on the storage device may receive, from a host, a command to store the host data on a memory device and classify the host data as sequential host data or random host data. A flash translation layer on the storage device predetermines open contiguous blocks on the memory device where the sequential host data is to be written and provides a beginning address of the open contiguous blocks to the host interface module. The host interface module populates an address translation table with logical-to-physical mappings starting at the beginning address with an appropriate offset. Each entry in the address translation table corresponds to a fixed granularity.
A memory device includes layer stacks, each including a respective alternating stack of respective insulating layers and respective electrically conductive layers and a respective contact-level dielectric layer, memory openings vertically extending through a respective one of the alternating stacks. memory opening fill structures located in a respective one of the memory openings and including a respective vertical stack of memory elements and a respective vertical semiconductor channel, and dielectric bridges structures located within access trenches that laterally separate the layer stacks. Each of the dielectric bridge structures includes a respective pair of contoured sidewalls. Each contoured sidewall of the dielectric bridge structures includes at least two vertically-straight and horizontally-convex surface segments that are adjoined by a vertically-extending edge. Access trench fill structures are located in the access trenches and each access trench fill structure embed a respective subset of the dielectric bridge structures.
H01L 23/00 - Details of semiconductor or other solid state devices
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
26.
THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF USING ION IMPLANTED ETCH STOP LAYER ON A SACRIFICIAL FILL MATERIAL
A method includes forming a first alternating stack of first insulating layers and first sacrificial material layers over a substrate, forming a first in-process inter-tier dielectric layer over the first alternating stack, forming a first memory opening through the first in-process inter-tier dielectric layer and the first alternating stack, forming a sacrificial memory opening fill structure in the first memory opening, doping an upper portion of the sacrificial memory opening fill structure with atoms of at least one dopant species, forming a second alternating stack of second insulating layers and second sacrificial material layers over the first alternating stack, forming a second memory opening through the second alternating stack by performing an anisotropic etch process, and removing the sacrificial memory opening fill structure.
H01L 23/528 - Layout of the interconnection structure
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
27.
THREE-DIMENSIONAL MEMORY DEVICE WITH THROUGH-STACK CONTACT VIA STRUCTURES AND METHOD OF MAKING THE SAME
A memory device includes a first alternating stack of first insulating layers and first electrically conductive layers, a first dielectric material portion overlying first stepped surfaces of the first alternating stack, a memory opening vertically extending through the first alternating stack, a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a vertical stack of memory elements, and a first contact via structure vertically extending through the first alternating stack and the first dielectric material portion. The first contact via structure includes a conductive pillar portion and a conductive fin portion that laterally protrudes from the conductive pillar portion and having a first annular bottom surface segment contacting an annular top surface segment of one of the first electrically conductive layers.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
28.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING PERIPHERAL CIRCUIT WITH FIN FIELD EFFECT TRANSISTORS AND METHOD OF MAKING THE SAME
A semiconductor structure includes a memory die including a three-dimensional memory device, and a logic die bonded to the memory die. The logic die includes a word line switching circuit containing a fin field effect transistor including a semiconductor fin and a first gate dielectric having a first gate dielectric thickness, and further includes a first additional field effect transistor including a second gate dielectric having a second gate dielectric thickness that is different from the first gate dielectric thickness.
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Methods are provided for managing defects in Hard Disk Drive (HDD) storage devices. In particular, only a portion of the cylinders of an HDD is tested. Machine learning modeling is used to reconstruct the data for the untested cylinders. An HDD comprises a rotating disk and a read/write head actuated above the disk surface. The disk may be formatted into concentric data tracks, with each track being divided into sectors. The tracks may be organized into zones (groups of tracks called cylinders), and the axially parallel sectors in each cylinder may be organized into wedges. In a test mode, some portion of the cylinders is chosen for testing. Each wedge in the chosen cylinders is tested and labeled defective or non-defective. The test data for each defective wedge is run through a machine learning defect management logic, and inferences are made for the defective/non-defective status of the untested wedges.
G11B 19/04 - Arrangements for preventing, inhibiting, or warning against, double recording on the same blank, or against other recording or reproducing malfunctions
31.
MACHINE LEARNING DEFECT MANAGEMENT IN STORAGE DEVICES
Methods are provided for managing defects in Hard Disk Drive (HDD) storage devices. In particular, only a portion of the cylinders of an HDD is tested. A bag of machine learning models is used to reconstruct the data for the untested cylinders. A defect file for the HDD is generated, a classifier model may be applied to the defect file, and one or more neural network models may be applied. If the defects are unsuitable for use by the models, then a scan of the entire HDD is run instead. An HDD comprises a rotating disk and a read/write head actuated above the disk surface. The disk may be formatted into concentric data tracks, with each track being divided into sectors. The tracks may be organized into zones (groups of tracks called cylinders), and the axially parallel sectors in each cylinder may be organized into wedges.
A multi-actuator hard disk drive includes a lower actuator with a corresponding voice coil motor assembly (VCMA), a coaxial upper actuator with a corresponding VCMA, and a central support plate positioned between the upper and lower VCMAs and to which the upper VCMA is fastened. Use of a central support plate enables some control over the direct and coupled plant transfer functions, while effectively providing a base support structure for the upper VCMA and enabling use of conventionally-sized fasteners.
Various illustrative aspects are directed to a data storage device comprising a storage medium and a head configured to access the storage medium. The head comprises a first write assist element and a second write assist element. Control circuitry for driving the head is configured to apply a first write assist current Im that is synchronized to a write data current Iw to the first write assist element; and to apply a second DC write assist current Imdc to the second write assist element.
A flexible printed circuit (FPC) for a hard disk drive includes a plurality of electrical traces, whereby aggressor traces are isolated from victim traces to avoid crosstalk that could degrade signals. Aggressor traces may be positioned together at one of the edges of each of the top wiring layer and the bottom wiring layer, physically isolated from victim traces. Aggressor traces may be grouped together at either the top wiring layer or the bottom wiring layer, with the victim traces positioned on the layer opposing the aggressor traces. With aggressor and victim traces routed on the same wiring layer, aggressor traces may be routed away from the victim traces with multi-layer routing, by way of vias.
Disclosed herein are embodiments of single-molecule array sequencing (SMAS) devices and systems. Each sensor of an array of sensors of the SMAS device is capable of detecting labels attached to nucleotides incorporated into a single nucleic acid strand bound to a respective binding site. Each sensor can detect a single label (e.g., fluorescent, magnetic, organometallic, charged molecule, etc.) attached to the incorporated nucleotide. Also disclosed are methods of using SMAS devices and systems for highly-scalable nucleic acid (e.g., DNA) sequencing based on sequencing by synthesis (SBS) of multiple instances of clonally amplified DNA immobilized on such SMAS devices. Also disclosed are error correction methods that mitigate errors (e.g., errant label detections or non-detections) made in sequencing individual nucleic acid strands.
The present invention provides a coal-based solid waste transport and filling integrated machine mining system, comprising a filling hydraulic support (6) and a coal winning machine (7), said filling hydraulic support (6) comprises a hydraulic top plate and a base (601), said hydraulic top plate comprises a hinged front top beam (602) and a rear top beam (603), with a front probe beam (604) attached to front end of said front top beam (602) and a telescopic slide rod (1) connected to rear end of said rear top beam (603), a double transport and single filling non-stop equipment is fixed on the telescopic slide rod (1). The apparatus and method of the present invention weaken the impact of groundwater pollution on mine production and mine ecology, bring good economic and environmental benefits to the mine and promoting safe and green coal mining.
E21D 23/04 - Structural features of the supporting construction, e.g. linking members between adjacent frames or sets of propsMeans for counteracting lateral sliding on inclined floor
E21F 15/00 - Methods or devices for placing filling-up materials in underground workings
E21F 13/00 - Transport specially adapted to underground conditions
C04B 28/14 - Compositions of mortars, concrete or artificial stone, containing inorganic binders or the reaction product of an inorganic and an organic binder, e.g. polycarboxylate cements containing calcium sulfate cements
C04B 18/14 - Waste materialsRefuse from metallurgical processes
C04B 18/24 - Vegetable refuse, e.g. rice husks, maize-ear refuseCellulosic materials, e.g. paper
37.
In-kernel cache request queuing for distributed cache
A node includes at least one memory for use as a shared cache in a distributed cache. One or more other nodes on a network each provide a respective shared cache for the distributed cache. A request is received by a kernel of the node to access data in the shared cache and an Input/Output (I/O) queue is identified from among a plurality of I/O queues in a kernel space of the at least one memory for queuing the received request based on at least one of a priority indicated by the received request and an application that initiated the request. In another aspect, each I/O queue of the plurality of I/O queues corresponds to at least one of different respective priorities for requests to access data in the shared cache and different respective applications initiating requests to access data in the shared cache.
Disclosed herein are apparatuses for nucleic acid sequencing using magnetic labels (e.g., magnetic particles) and magnetic sensors. Also disclosed are methods of making and using such apparatuses. An apparatus for nucleic acid sequencing comprises a plurality of magnetic sensors, a plurality of binding areas disposed above the plurality of magnetic sensors, each of the binding areas for holding fluid, and at least one line for detecting a characteristic of at least a first magnetic sensor of the plurality of magnetic sensors, the characteristic indicating presence or absence of one or more magnetic nanoparticles coupled to a first binding area associated with the first magnetic sensor.
Disclosed herein are devices, systems, and methods for monitoring single-molecule biological processes using magnetic sensors and magnetic particles (MNP). A MNP is attached to a biopolymer (e.g., a nucleic acid, protein, etc.), and motion of the MNP is detected and/or monitored using a magnetic sensor. Because the MNP is small (e.g., its size is comparable to the size of the molecule being monitored) and is tethered to a biopolymer, changes in the volume of Brownian motion of the MNP in a solution can be monitored to monitor the movement of the MNP and, by inference, the tethered biopolymer. The magnetic sensor is small (e.g., nanoscale or having a size on the order of the sizes of the MNP and the biopolymer) and can be used to detect even small changes in the position of the MNP within the sensing region of the magnetic sensor.
System and method of verifying validity of a metadata modification request to prevent improper metadata operations. During initialization of a volume in a storage device and once a metadata area is reserved for a metadata structure, information characterizing the metadata structure and metadata area is stored in the storage device, which may be in the form of an area legend composed of descriptors such as a magic signature, a node size, a clump size of reservation, and extent of the metadata area. Responsive to a request for operating on metadata, relevant information provided in the request is verified against the stored characteristic information. If the verification discovers an inconsistency between the information provided in the request and the stored characteristic information, the request modification is treated as invalid and blocked from operation.
G06F 16/27 - Replication, distribution or synchronisation of data between databases or within a distributed database systemDistributed database system architectures therefor
41.
Nucleic acid sequencing by synthesis using magnetic sensor arrays
Disclosed herein are apparatuses for nucleic acid sequencing, and methods of making and using such apparatuses. In some embodiments, the apparatus comprises a magnetic sensor array comprising a plurality of magnetic sensors, each of the plurality of magnetic sensors coupled to at least one address line, at least one selector element, and a fluid chamber adjacent to the magnetic sensor array, the fluid chamber having a proximal wall adjacent to the magnetic sensor array.
A method of manufacturing sequencing device comprises fabricating a first addressing line on a substrate, fabricating a plurality of magnetic sensors such that the bottom portion of each sensor is coupled to the first addressing line, depositing a dielectric material between the sensors, fabricating additional addressing lines coupled to the top portions of the sensors, and removing a portion of the dielectric material adjacent to the sensors to create a fluid chamber.
B01L 3/00 - Containers or dishes for laboratory use, e.g. laboratory glasswareDroppers
G01N 27/08 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a liquid which is flowing continuously
G01N 27/74 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating magnetic variables of fluids
G01N 33/58 - Chemical analysis of biological material, e.g. blood, urineTesting involving biospecific ligand binding methodsImmunological testing involving labelled substances
An apparatus is provided that includes an array including m rows and n columns of nodes. Each column of nodes is coupled to one of n first conductive lines, and each row of nodes is coupled to one of m second conductive lines. Each node of the m rows and n columns of nodes includes a spin orbit torque-based spin torque oscillator circuit configured to oscillate at a corresponding intrinsic frequency. The spin orbit torque-based spin torque oscillator circuits are configured to generate m output signals at the m second conductive lines upon application of n input signals to corresponding n first conductive lines. The n input signals correspond to an n-element input vector, and each input signal includes a corresponding input signal frequency. Each of the m output signals include frequency domain components at the input signal frequencies. The magnitudes of the frequency domain components at the input signal frequencies depend on a degree of synchronization between the input signal frequencies and the intrinsic frequencies.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
43.
MATRIX-VECTOR MULTIPLICATION USING SOT-BASED NON-VOLATILE MEMORY CELLS
An apparatus is provided that includes an array including n rows and m columns of nodes, each row of nodes coupled to one of n first conductive lines, each column of nodes coupled to one of m second conductive lines, each node of the n rows and m columns of nodes including a spin orbit torque MRAM non-volatile memory cell configured to store a corresponding weight of an n×m array of weights each having a first weight value or a second weight value, and a control circuit configured to apply n input voltages each having a first input value or a second input value to corresponding n first conductive lines, the n input voltages corresponding to an n-element input vector. The spin orbit torque MRAM non-volatile memory cells are configured to generate m output currents at the m second conductive lines upon application of the n input voltages. The m output currents corresponding to a result of multiplying the input vector by the n×m array of weights.
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
G11C 11/18 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using Hall-effect devices
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
H01L 43/04 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details of Hall-effect devices
Systems and methods for increasing the endurance of a solid state drive are disclosed. The disclosed systems and methods can assign different levels of error protection to a plurality of blocks of the solid state drive. The disclosed methods can provide a plurality of error correction mechanisms, each having a plurality of corresponding error correction levels and associate a first plurality of blocks of the solid state drive with a first zone and a second plurality of blocks of the solid state drive with a second zone. The disclosed methods can assign a first error correction mechanism and a first corresponding error correction level to the first zone and can assign a second error correction mechanism and a second corresponding error correction level to the second zone.
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
H03M 13/35 - Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
G11C 29/04 - Detection or location of defective memory elements
45.
Method and system for decoding data based on association of first memory location and second memory location
An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. Bit patterns provided by multiple reads of reference memory locations can be counted and used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.
Embodiments disclosed herein generally relate to the use of Network-on-Chip architecture for solid state memory structures which provide for the access of memory storage blocks via a router. As such, data may be sent to and/or from the memory storage blocks as data packets on the chip. The Network-on-Chip architecture may further be utilized to interconnect unlimited numbers of memory cell matrices, spread on a die, thus allowing for reduced latencies among matrices, selective power control, unlimited memory density growth without major latency penalties, and reduced parasitic capacitance and resistance. Other benefits may include improved signal integrity, larger die areas available to implement memory arrays, and higher frequency of operation.
The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore, a failure in one unit does not affect the data stored in the other units. Parity information associated with the data stored in the memory blocks is stored in a separate memory block. If the data in a single memory block has been corrupted, the data stored in the remaining memory blocks and the parity information is used to retrieve the corrupted data.
Techniques are described for accessing data from a storage device. In one example, the storage device may include a storage medium comprising non-volatile memory, a network connection, and one or more processing entities. The one or more processors may be configured to receive a request from the network connection at the non-volatile memory storage device for accessing data associated with a file system object, the request comprising a virtual address offset, a file object identifier and a size of the data access, perform, at a flash translation layer of a storage device software stack executing on the one or more processing entities of the storage device, a translation from the virtual address offset to a physical address for the data stored on the non-volatile memory, using the virtual address offset and the file object identifier, and access the data from the physical address from the storage medium.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
In one aspect, the present disclosure relates to a method of de-duplicating data in a solid state storage device. The method can include receiving a block of data to be written to a solid state storage device, wherein the block of data comprises header portion and a payload, wherein the header portion comprises context information; and determining whether the payload should be de-duplicated prior to storage, based on the context information stored within the header portion; if the payload is determined to be de-duplicated, de-duplicating the payload; and storing the de-duplicated payload to the solid state storage device.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
50.
Data storage system and method for multiple communication protocols and memory access
A flash storage device provides direct memory access based on a first communication protocol. A host selects the first communication protocol and provides a request to the flash storage device for a direct memory access. Additionally, the host provides data blocks to the flash storage device for the direct memory access. In the first communication protocol, the host need not provide an address to the flash storage device for the direct memory access. The flash storage device stores the data blocks at sequential addresses starting at a predetermined address in the flash storage device. Another host may then select a second communication protocol and transfer the data blocks in the flash storage by using the second communication protocol.
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
A machine-implemented method for managing a flash storage system includes determining a projected life value for each of a plurality of flash memory devices in the flash storage system, wherein the projected life value for at least one of the plurality of flash memory devices is higher than the projected life value of at least another one of the plurality of flash memory devices. The method also includes determining operating parameters for each of the plurality of flash memory devices based on the respective projected life values for the plurality of flash memory devices. The method also includes configuring the plurality of flash memory devices based on the determined operating parameters.
A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
The present disclosure relates to caches, methods, and systems for using an invalidation data area. The cache can include a journal configured for tracking data blocks, and an invalidation data area configured for tracking invalidated data blocks associated with the data blocks tracked in the journal. The invalidation data area can be on a separate cache region from the journal. A method for invalidating a cache block can include determining a journal block tracking a memory address associated with a received write operation. The method can also include determining a mapped journal block based on the journal block and on an invalidation record. The method can also include determining whether write operations are outstanding. If so, the method can include aggregating the outstanding write operations and performing a single write operation based on the aggregated write operations.
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
G06F 12/121 - Replacement control using replacement algorithms
G06F 12/0866 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
A controller of a storage device is described for handling communications with a host device. In some examples, the storage device includes a wide port comprising a plurality of phys. The wide port is configured to receive, via a first phy of the plurality of phys, a signal. The controller is configured to select, based on a respective power factor associated with each respective phy of the plurality of phys and a respective performance factor associated with each respective phy of the plurality of phys, a second phy of the plurality of phys to utilize for performing an operation associated with the received signal. In such examples, the wide port is further configured to perform, using the second phy, the operation associated with the received signal.
A flash storage device provides direct memory access based on a first communication protocol. A host selects the first communication protocol and provides a request to the flash storage device for a direct memory access. Additionally, the host provides data blocks to the flash storage device for the direct memory access. In the first communication protocol, the host need not provide an address to the flash storage device for the direct memory access. The flash storage device stores the data blocks at sequential addresses starting at a predetermined address in the flash storage device. Another host may then select a second communication protocol and transfer the data blocks in the flash storage by using the second communication protocol.
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
A method for determining a utilization-based fee for storing data includes determining a number of write operations for writing a quantity of data to a solid state drive (SSD) and determining an amount of a fee based on the number of write operations for writing the quantity of data to the SSD. A lifetime of the SSD can be determined based on, for example, the number of blocks in the SSD and the maximum number of write operations per block. A utilization factor for a particular workload can be determined by dividing the number of write operations in the workload by the lifetime. The value of the utilization factor can then be used to determine the amount of the fee. A bill based on the amount of the fee can be generated and transmitted.
Embodiments of the present disclosure provide a memory-efficient mechanism for identifying memory blocks with a low wear count. More particularly, embodiments of the present disclosure provide a mechanism for identifying a memory block whose wear count is within the bottom p % of all wear counts associated with memory blocks in a storage system. If a memory controller performs the garbage collection operation on a memory block whose wear count is within the bottom p % of all wear counts, then the memory controller is expected to utilize the remaining memory blocks (e.g., memory blocks whose wear count is within the upper (100-p) % of all wear counts) efficiently and level the wear count of at least the remaining memory blocks.
The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore, a failure in one unit does not affect the data stored in the other units. Parity information associated with the data stored in the memory blocks is stored in a separate memory block. If the data in a single memory block has been corrupted, the data stored in the remaining memory blocks and the parity information is used to retrieve the corrupted data.
An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. Bit patterns provided by multiple reads of reference memory locations can be counted and used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.
Systems and methods for increasing the endurance of a solid state drive are disclosed. The disclosed systems and methods can assign different levels of error protection to a plurality of blocks of the solid state drive. The disclosed methods can provide a plurality of error correction mechanisms, each having a plurality of corresponding error correction levels and associate a first plurality of blocks of the solid state drive with a first zone and a second plurality of blocks of the solid state drive with a second zone. The disclosed methods can assign a first error correction mechanism and a first corresponding error correction level to the first zone and can assign a second error correction mechanism and a second corresponding error correction level to the second zone.
H03M 13/35 - Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
G11C 29/04 - Detection or location of defective memory elements
After a predetermined period of time in a life cycle of a flash memory device, a plurality of reliability values corresponding to a plurality of reads of one or more of the plurality of memory cells are generated; each of the reads using a variation of a predetermined read level voltage. An offset voltage is then identified, offset from the read level voltage. The offset voltage corresponds to a zero crossing point in the range of the reliability values. Once the offset voltage is identified, the read level voltage is set to a calibrated voltage based on the offset voltage.
G11C 16/26 - Sensing or reading circuitsData output circuits
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels; define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set; receive a unit of data to be stored; and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets.
Techniques for improved copy on write functionality within an SSD are disclosed. In some embodiments, the techniques may be realized as a method for providing improved copy on write functionality within an SSD including providing, in memory of a device, an indirection data structure. The data structure may include a master entry for cloned data, the master entry having a reference to one or more indexes and a clone entry for the cloned data, the cloned entry having at least one of: a reference to a master index, a reference to a next index, and a value indicating an end of a data structure. The techniques may include traversing, using a computer processor, one or more copies of the cloned data using one or more of the references.
An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. Bit patterns provided by multiple reads of reference memory locations can be counted and used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.
An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. 0-to-1 and 1-to-0 bit flip count data provided by multiple reads of reference memory locations can be used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.
G11C 16/08 - Address circuitsDecodersWord-line control circuits
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups
H03M 13/45 - Soft decoding, i.e. using symbol reliability information
66.
Soft-decision input generation for data storage systems
An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. 0-to-1 and 1-to-0 bit flip count data provided by multiple reads of reference memory locations can be used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.
G06F 3/06 - Digital input from, or digital output to, record carriers
G11C 16/08 - Address circuitsDecodersWord-line control circuits
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/45 - Soft decoding, i.e. using symbol reliability information
H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups
67.
System and method for direct memory access in a flash storage
A flash storage device provides direct memory access based on a first communication protocol. A host selects the first communication protocol and provides a request to the flash storage device for a direct memory access. Additionally, the host provides data blocks to the flash storage device for the direct memory access. In the first communication protocol, the host need not provide an address to the flash storage device for the direct memory access. The flash storage device stores the data blocks at sequential addresses starting at a predetermined address in the flash storage device. Another host may then select a second communication protocol and transfer the data blocks in the flash storage by using the second communication protocol.
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
System and method of verifying validity of a metadata modification request to prevent improper metadata operations. During initialization of a volume in a storage device and once a metadata area is reserved for a metadata structure, information characterizing the metadata structure and metadata area is stored in the storage device, which may be in the form of an area legend composed of descriptors such as a magic signature, a node size, a clump size of reservation, and extent of the metadata area. Responsive to a request for operating on metadata, relevant information provided in the request is verified against the stored characteristic information. If the verification discovers an inconsistency between the information provided in the request and the stored characteristic information, the request modification is treated as invalid and blocked from operation.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 16/27 - Replication, distribution or synchronisation of data between databases or within a distributed database systemDistributed database system architectures therefor
69.
System data storage mechanism providing coherency and segmented data loading
A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
70.
System and method for decoding iterations and dynamic scaling
A decoder is configured to perform, for a unit of data received by the decoder, a plurality of decoding iterations in which a plurality of messages are passed between a plurality of check nodes and a plurality of variable nodes, each message indicating a degree of reliability in an observed outcome of data. The decoder determines, for each of the plurality of decoding iterations, whether a trigger condition is satisfied based on an internal state of the decoder and, when a trigger condition is determined to be satisfied during a respective decoding iteration, scales one or more respective messages of the plurality of messages during a subsequent decoding iteration. The unit of data is decoded based on the plurality of decoding iterations and at least one scaled message resulting from the trigger condition being satisfied during the respective decoding iteration.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups
H03M 13/45 - Soft decoding, i.e. using symbol reliability information
A verification architecture described according to embodiments of the present invention validates changes made to metadata and may comprise one or more subsystems and phases. According to some embodiments, the “mkfs” volume creation utility works in cooperation with the device driver to create a file system volume by means of reservation and initialization space for metadata structures inside the device's partition that is reserved for the specific file system volume. The storage device uses a verified area legend when checking write requests after the file system volume has been created. The verified area legends may be stored in a dedicated partition or inside the master boot record (MBR) or Globally Unique Identifier (GUID) partition table (GPT) or special memory chip (NAND flash, for example). Write requests that overlap with any extent of reserved metadata area must be verified to prevent metadata corruption.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
72.
Data storage device providing data maintenance services
Systems and methods are disclosed for performing data maintenance and/or other data operations within a data storage device. A data storage device is disclosed including a device controller, non-volatile data storage, an interface for receiving data storage commands from a host system, a framework including a memory for storing xenocode code received from the host system, and a processor for executing the xenocode. The device controller is configured to write user data received from the host system to a first partition of the non-volatile data storage in response to a storage command received via the interface from the host system. The xenocode, when executed, causes the processor to read the user data from the first partition of the non-volatile data storage, perform data operations on the read user data, and write results associated with the data operations in a second partition of the non-volatile data storage.
Techniques are described for accessing data from a storage device. In one example, the storage device may include a storage medium comprising non-volatile memory, a network connection, and one or more processing entities. The one or more processors may be configured to receive a request from the network connection at the non-volatile memory storage device for accessing data associated with a file system object, the request comprising a virtual address offset, a file object identifier and a size of the data access, perform, at a flash translation layer of a storage device software stack executing on the one or more processing entities of the storage device, a translation from the virtual address offset to a physical address for the data stored on the non-volatile memory, using the virtual address offset and the file object identifier, and access the data from the physical address from the storage medium.
Disclosed embodiments are directed to systems and methods for improving garbage collection and wear leveling performance in data storage systems. The embodiments can improve the efficiency of static wear leveling by picking the best candidate block for static wear leveling and/or postponing static wear leveling on certain candidate blocks. In one embodiment, one or more source blocks for a static wear leveling operation are selected based at least on whether the one or more blocks have a low P/E count and contain static data, such as data that has been garbage collected.
A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels; define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set; receive a unit of data to be stored; and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets.
G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G06F 3/06 - Digital input from, or digital output to, record carriers
G11C 8/12 - Group selection circuits, e.g. for memory block selection, chip selection, array selection
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
A machine-implemented method for managing a flash storage system includes determining a projected life value for each of a plurality of flash memory devices in the flash storage system, wherein the projected life value for at least one of the plurality of flash memory devices is higher than the projected life value of at least another one of the plurality of flash memory devices. The method also includes determining operating parameters for each of the plurality of flash memory devices based on the respective projected life values for the plurality of flash memory devices. The method also includes configuring the plurality of flash memory devices based on the determined operating parameters.
A flash storage device includes a power hold circuit including a double layer capacitor. A power source supplies power to the flash storage device and charges the double layer capacitor. The double layer capacitor supplies power for maintaining integrity of data during a data transfer occurring in the flash storage device when the power supplied by the power source is disrupted. Additionally, the flash storage device can inhibit subsequent data transfers until the power supplied by the power source is restored.
In one aspect, the present disclosure relates to a method of de-duplicating data in a solid state storage device. The method can include receiving a block of data to be written to a solid state storage device, wherein the block of data comprises header portion and a payload, wherein the header portion comprises context information; and determining whether the payload should be de-duplicated prior to storage, based on the context information stored within the header portion; if the payload is determined to be de-duplicated, de-duplicating the payload; and storing the de-duplicated payload to the solid state storage device.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
79.
Characterizing and operating a non-volatile memory device
A sequence of contiguous pages in an erase block in a non-volatile memory device is programmed and erased. Next, all of the pages in the erase block are programmed with data. Then, the data is read back and verified to determine whether there is an error in the data. When there is an error in the data, then the last page in the sequence is identified as being unstable. If there is no error in the data, then the last page in that sequence is identified as being stable. Thus, the recorded information identifies a point of instability in the erase block. Instabilities can be stabilized by performing additional writes to fill the partially filled word line.
The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore, a failure in one unit does not affect the data stored in the other units. Parity information associated with the data stored in the memory blocks is stored in a separate memory block. If the data in a single memory block has been corrupted, the data stored in the remaining memory blocks and the parity information is used to retrieve the corrupted data.
Systems and methods for offloading processing from a host to one or more storage processing units using an interconnect network are provided. One such method includes receiving a processing task from the host at a first storage processing unit (SPU) of a plurality of SPUs via a host interface, performing, at the first SPU, the processing task, and transferring data from the first SPU to a second SPU via an interconnection network, where each of the plurality of SPUs includes a non-volatile memory (NVM) and a processing circuitry configured to perform the processing task.
An apparatus for non-volatile memory, and more specifically a ReRAM device with a buried resistive memory cell. The memory cell includes a first contact disposed on a substrate, an active layer, a second contact, a first diffused zone disposed within the active layer, a second diffused zone disposed within the active layer, and an active switching zone disposed within the active layer in between the first diffused zone and the second diffused zone. In one embodiment, the active zone may be doped by diffusion or ion implantation and/or may be fabricated utilizing a self-aligned process. In another embodiment, the memory cell may combine a deep implant and shallow diffusion well to create the active zone. The vertically and laterally isolated buried resistive memory cell concentrates the electric field away from the edges of the device and eliminates the effects of interface impurities and contaminants.
H01L 47/00 - Bulk negative resistance effect devices, e.g. Gunn-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
A base member includes a recessed portion extending in radial directions and recessed upward from a lower surface of the base member and a hole extending through the recessed portion in the vertical direction. The recessed portion includes a recessed portion loop-shaped surface defining a loop-shaped surface in the radial direction. A connector is located on a lower side of the recessed portion to cover the hole portion. An adhesive is located between the connector and the recessed portion. A minimum value of a gap distance in the radial direction between an outer end of the connector and an inner end of the recessed portion in which the outer end of the connector and the inner end of the recessed portion are opposed to each other with the adhesive therebetween is greater than a minimum value of a gap in the vertical direction distance between an upper surface of the connector and the recessed portion loop-shaped surface, in which the upper surface of the connector and the recessed portion loop-shaped surface are opposed to each other with the adhesive therebetween. The adhesive includes an inorganic filler.
G11B 33/12 - Disposition of constructional parts in the apparatus, e.g. of power supply, of modules
G11B 33/14 - Reducing influence of physical parameters, e.g. temperature change, moisture, dust
G11B 25/04 - Apparatus characterised by the shape of record carrier employed but not specific to the method of recording or reproducing using flat record carriers, e.g. disc, card
G11B 33/02 - CabinetsCasesStandsDisposition of apparatus therein or thereon
A base member includes a recessed portion arranged to extend in radial directions and recessed upward from a lower surface of the base member, the radial directions being directions perpendicular to a vertical direction or directions parallel to these directions; and a hole portion arranged to pass through the recessed portion in the vertical direction. The recessed portion includes a recessed portion loop-shaped surface being a loop-shaped surface perpendicular to the vertical direction. A connector is arranged on a lower side of the recessed portion to cover the hole portion. An adhesive is arranged between the connector and the recessed portion. A minimum value of a gap distance between an outer end of the connector and an inner end of the recessed portion in a radial direction in which the outer end of the connector and the inner end of the recessed portion are opposed to each other with the adhesive therebetween is greater than a minimum value of a gap distance between an upper surface of the connector and the recessed portion loop-shaped surface in the vertical direction, in which the upper surface of the connector and the recessed portion loop-shaped surface are opposed to each other with the adhesive therebetween.
G11B 33/14 - Reducing influence of physical parameters, e.g. temperature change, moisture, dust
G11B 25/04 - Apparatus characterised by the shape of record carrier employed but not specific to the method of recording or reproducing using flat record carriers, e.g. disc, card
G11B 33/02 - CabinetsCasesStandsDisposition of apparatus therein or thereon
G11B 33/12 - Disposition of constructional parts in the apparatus, e.g. of power supply, of modules
Embodiments of the present disclosure generally relate to electronic devices, and more specifically, to multi-level phase change devices. In one embodiment, a memory cell device is provided. The memory cell device generally includes a top surface, a bottom surface and a cell body between the top surface and the bottom surface. The cell body may include a plurality of phase change material layers, which may be used to store data of the cell. In another embodiment, a method of programming a memory cell is provided. The method generally may include applying a sequence of different pulses to each phase change material layer of the cell as the voltage of each pulse in the sequence is ratcheted down from the start of a write cycle to the end of a write cycle.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
A method includes transmitting, by a controller of a storage device, a first bit on a data line. The method further includes responsive to transmitting the first bit on the data line, determining, by the controller, a line level of the data line. The method further includes responsive to determining the line level of the data line, determining, by the controller, whether the line level of the data line corresponds to the first bit and responsive to determining that the line level of the data line does not correspond to the first bit, determining, by the controller, that a collision has occurred on the data line.
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 5/14 - Means for monitoring the fill levelMeans for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
Embodiments of the invention include systems and methods for recovering the system status and maintaining drive coherency after an unexpected power loss. In particular, these systems and methods reduce overhead for maintaining drive coherency by providing for pre-allocation of groups of write addresses and recording the pre-allocated groups of addresses to the non-volatile memory. Write processes can write to the pre-allocated group of addresses while the next group of addresses are pre-allocated and recorded to non-volatile memory.
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
Embodiments of the present disclosure provide a memory-efficient mechanism for identifying memory blocks with a low wear count. More particularly, embodiments of the present disclosure provide a mechanism for identifying a memory block whose wear count is within the bottom p % of all wear counts associated with memory blocks in a storage system. If a memory controller performs the garbage collection operation on a memory block whose wear count is within the bottom p % of all wear counts, then the memory controller is expected to utilize the remaining memory blocks (e.g., memory blocks whose wear count is within the upper (100−p) % of all wear counts) efficiently and level the wear count of at least the remaining memory blocks.
A method for managing data in a flash storage system includes reading multiple flash data units in the flash storage system. At least some host data units are stored in each flash data unit is associated with a workload by a metadata tag, and the host data units have dissimilar metadata tags. The method also includes identifying host data units having the same first metadata tag from the host data units read from the read flash data units. The same first metadata tag is stored with each identified host data unit at a time of writing each identified host data unit to a respective flash data unit, from which the identified host data unit was read. The identified host data units with same first metadata tag are written to a first available flash data unit in the flash storage system.
A data storage system implements out-of-order data transfer. In one embodiment, the data storage system can retrieve from a host system a scatter gather list (SGL) associated with a data read command and generate a memory access table based on the retrieved SGL. The data storage system can further retrieve data from memory, and at least some data may be retrieved out of order. Retrieved data can be provided to the host system using the memory access table, and at least some data may be provided out of order. Data retrieval performance can be increased.
A system comprising a processor and a memory storing instructions that, when executed, cause the system to receive a data stream including one or more data blocks; determine a size of the one or more data blocks; determine a number of mappings needed for a physical block based on the size of a data block and a size of the physical block, the number of mappings being variable for different physical blocks depending on the size of the one or more data blocks storing in the physical block; retrieve a dynamically sized reverse map, the dynamically sized reverse map being a dynamic tree structure; determine a starting location in the dynamically sized reverse map for mappings of the one or more data blocks; and create an entry for the physical block in the dynamically sized reverse map.
A controller of a storage device is described for handling communications with a host device. In some examples, the storage device includes a wide port comprising a plurality of phys. The wide port is configured to receive, via a first phy of the plurality of phys, a signal. The controller is configured to select, based on a respective power factor associated with each respective phy of the plurality of phys and a respective performance factor associated with each respective phy of the plurality of phys, a second phy of the plurality of phys to utilize for performing an operation associated with the received signal. In such examples, the wide port is further configured to perform, using the second phy, the operation associated with the received signal.
A flash storage device provides direct memory access based on a first communication protocol. A host selects the first communication protocol and provides a request to the flash storage device for a direct memory access. Additionally, the host provides data blocks to the flash storage device for the direct memory access. In the first communication protocol, the host need not provide an address to the flash storage device for the direct memory access. The flash storage device stores the data blocks at sequential addresses starting at a predetermined address in the flash storage device. Another host may then select a second communication protocol and transfer the data blocks in the flash storage by using the second communication protocol.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
A sequence of contiguous pages in an erase block in a non-volatile memory device is programmed and erased. Next, all of the pages in the erase block are programmed with data. Then, the data is read back and verified to determine whether there is an error in the data. When there is an error in the data, then the last page in the sequence is identified as being unstable. If there is no error in the data, then the last page in that sequence is identified as being stable. Thus, the recorded information identifies a point of instability in the erase block. Instabilities can be stabilized by performing additional writes to fill the partially filled word line.
An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. Bit patterns provided by multiple reads of reference memory locations can be counted and used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
96.
Reducing write-backs to memory by controlling the age of cache lines in lower level cache
A method and apparatus for reducing write-backs to memory is disclosed herein. The method includes determining whether a read/write request entering a lower level cache is a cache line containing modified data, and responsive to determining that the read/write request is not a cache line containing modified data, manipulating age information of the cache line to reduce a number of write-backs to memory.
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
G06F 12/123 - Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
G06F 12/0806 - Multiuser, multiprocessor or multiprocessing cache systems
G06F 12/122 - Replacement control using replacement algorithms of the least frequently used [LFU] type, e.g. with individual count value
G06F 12/128 - Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
A soft information module is coupled between one or more flash memory devices and a decoder. The soft information module receives a putative value of one or more memory cells of the one or more flash memory devices based on a read of the one or more memory cells at an initial read level, and one or more respective indicators of whether the putative value was read at one or more respective different read levels offset from the initial read level, and receives a page indicator for the read. The soft information module determines a cell program region for the read based on the putative value, the one or more respective indicators, and the page indicator, identifies a predetermined confidence value for the region, and provides the confidence value to the decoder for association with the putative value, the confidence value being representative of a likelihood that the one or more memory cells was programmed to the putative value.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 16/08 - Address circuitsDecodersWord-line control circuits
G06F 11/08 - Error detection or correction by redundancy in data representation, e.g. by using checking codes
Techniques for improved copy on write functionality within an SSD are disclosed. In some embodiments, the techniques may be realized as a method for providing improved copy on write functionality within an SSD including providing, in memory of a device, an indirection data structure. The data structure may include a master entry for cloned data, the master entry having a reference to one or more indexes and a clone entry for the cloned data, the cloned entry having at least one of: a reference to a master index, a reference to a next index, and a value indicating an end of a data structure. The techniques may include traversing, using a computer processor, one or more copies of the cloned data using one or more of the references.
A magnetic memory array and a method for implementing the magnetic memory array for use in Solid-State Drives (SSDs) are provided. A plurality of magnetic pillar memory cells is formed using a deposition and/or growth process to produce a magnetic memory array substantially avoiding milling of magnetic materials.
H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
H01L 43/12 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
H01L 43/02 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
G11C 11/18 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using Hall-effect devices
100.
System data management using garbage collection and logs
A data storage system is disclosed that utilizes garbage collection and logs for managing system data. In one embodiment, system data stored in a non-volatile memory is updated based on the character of changes to data stored in a data storage system (e.g., changes caused by host system activity). For example, when changes to stored data are scattered (e.g., changes are made to random memory locations), it may be beneficial to generate and accumulate more logs reflecting changes to the system data. As another example, when changes to stored data are substantially consolidated (e.g., changes are made to consecutive memory locations), it may be beneficial to update system data stored in the non-volatile memory more frequently. Reduction in write amplification, increase in efficiency, and reduction in start-up and initialization time can be attained. Reconstruction time of system data can also be reduced.