Embodiments of the present disclosure are directed towards circuits that may be used with various phase locked loop circuits. Circuits may include a phase and frequency detector circuit and a charge pump circuit operatively connected to the phase and frequency detector circuit. Circuits may further include a loop filter circuit operatively connected to the charge pump circuit, the loop filter circuit having a first transistor and a second transistor electrically connected with each other, a precharge switch and a capacitor operatively connecting the first and second transistor with a third transistor, and a node located between the third transistor and the capacitor, wherein the node corresponds to a pole in a common gate stage of a feedback path. Circuits may also include a voltage-controlled oscillator circuit configured to receive an input from the loop filter circuit and a divider circuit configured to receive an output from the voltage-controlled oscillator circuit.
H03L 7/00 - Automatic control of frequency or phaseSynchronisation
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
2.
Verification of data communication specification using sequence number-based monitor synchronization
Various embodiments provide for verifying operation of a circuit design with respect to a data communication specification, such as a Peripheral Component Interconnect Express (PCIe) specification, using sequence numbers (e.g., fixed byte-size unit (FLIT) sequence numbers) of data packets (e.g., FLITs) to synchronize monitoring of data transactions over a data bus.
H04L 1/18 - Automatic repetition systems, e.g. Van Duuren systems
H04L 43/20 - Arrangements for monitoring or testing data switching networks the monitoring system or the monitored elements being virtualised, abstracted or software-defined entities, e.g. SDN or NFV
Aspects of the present disclosure include system, methods, and software for buffer insertions. In one example, a method includes receiving a clock signal network layout, wherein the clock signal layout comprises a clock source electrically coupled to a plurality of clock sinks via a plurality of net segments, and creating a plurality of buffering solutions, wherein each buffering solution of the plurality of buffering solutions comprises a plurality of buffers inserted on one or more net segments of plurality of net segments. The method further includes assigning each buffering solution a timing delay value and an area value, and selecting a buffering solution of the plurality of buffering solutions based on the timing delay value and the area value. The method additionally includes committing the selected buffering solution into an integrated circuit design comprising the clock signal network.
Systems and methods for electronic design are provided. Embodiments may include causing a display of an electronic design at a graphical user interface and receiving via the graphical user interface, a user input connecting a first group including one or more scalar nets or buses with a symbolic representation of a second group including one or more scalar nets or buses. The first group and the second group may have an asymmetric structure. Embodiments may include performing an automatic connection assignment between the members of the first group and the second group.
Embodiments include herein are directed towards a method for automatic detection during a timing analysis. Embodiments may include reading, using a processor, design and power intent information associated with an electronic design and automatically identifying a plurality of inter-power domain paths from the design and power intent information. Embodiments may further include automatically filtering the plurality of inter-power domain paths to identify one or more faulty inter-power domain paths using a graph-based approach and automatically generating a report depicting the one or more faulty inter-power domain paths.
The present disclosure relates to a dual mode, low dropout regulator circuit and method of using the same. The circuit may include a multiplexer configured to switch between a high-speed mode and a low-power mode and an error amplifier configured to generate an amplifier output. The circuit may include a class AB circuit configured to receive the amplifier output and generate a class AB output and a unity feedback circuit in electrical communication with the class AB circuit, wherein a single reference voltage is applied to perform a dual mode operation.
G05F 1/563 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including two stages of regulation, at least one of which is output level responsive, e.g. coarse and fine regulation
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
7.
Circuit and method for charge device model protection
Embodiments included herein are directed towards a charge device model (“CDM”) protection circuit. The circuit may include a power supply, a power clamp operatively connected to the power supply, at least one diode connected with the power clamp, a field effect transistor (“FET”) operatively connected with the at least one diode and a trigger mechanism configured to activate the FET.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
8.
Hierarchically-aware buffering for clock structures
Aspects of the present disclosure include system, methods, and software for buffer insertions. In one example, a method includes receiving a clock signal network layout, the clock signal network layout comprising a clock source electrically coupled to a plurality of clock sinks via a plurality of net segments, a first hierarchy that bounds a first region of the clock signal network layout, and a second hierarchy that bounds a second region of the clock signal network layout. The method additionally includes creating a graph representative of the clock signal network layout, the graph comprising a plurality of logical edges, and identifying a to-be-inserted buffer location comprising a location on a net segment of the plurality of net segments to insert a buffer. The method further includes selecting a selected logical edge to insert the buffer based on the to-be-inserted buffer location, the first hierarchy, the second hierarchy, or a combination thereof.
Aspects of the present disclosure address systems and methods for zigzag detection and handling for integrated circuit designs. Data describing an integrated circuit is accessed. The integrated circuit design comprises a connection path between two or more pins of a net determined based on an initial routing of the net. A zigzag is detected in the connection path based on a local turn density constraint that specifies a ratio of a number of turns to a pathlength that corresponds to zigzagging in the net. In response to detecting the zigzag in the connection path, the zigzag is removed from the connection path by rerouting the net using a routing constraint that defines a maximum number of turns in the connection path.
Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using at least one processor, an electronic design layout and performing parasitic extraction on the electronic design layout. Embodiments may further include extracting an electromagnetic model from the electronic design layout and reconnecting at least one coupling capacitor associated with a net of the electromagnetic model. Embodiments may include performing a simulation including the reconnected at least one coupling capacitor.
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
G06F 119/02 - Reliability analysis or reliability optimisationFailure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
Embodiments included herein are directed towards a launch off shift circuit module. Embodiments included a first flip-flop configured to receive a clock signal and a scan enable signal. Embodiments may further include a combinational logic circuit configured to receive an input from the first flip-flop and a launch off shift mode signal. The first flip-flop and the combinational logic circuit may be located inside a launch off shift module boundary.
The present disclosure relates to an apparatus and method for decision feedback equalization. Embodiments include a sum amplifier having a differential tap network architecture wherein the sum amplifier includes at least one resistor, at least one transistor, and at least one source node, wherein the at least one source node is directly connected to a complete tap network.
Embodiments included herein are directed towards a passive equalization circuit. The circuit may include a transmitter, a receiver; and a passive equalization circuit that may be located between the transmitter and the receiver. A first inductor may be located between the transmitter and a primary node net, and a second inductor may be located between the primary node net and a pad, and a third inductor may be located between the primary node net and the receiver.
Embodiments include herein are directed towards various circuit topologies. A self-correcting latch circuit may include a plurality of memory loops, a plurality of clock inputs, a plurality of data inputs, and a plurality of outputs. Each of the plurality of memory loops may be configured to store data in parallel.
The present disclosure relates to a system and method for clock phase recovery. Embodiments may include sampling data using an in-phase clock and a quadrate phase clock. Embodiments may further include analyzing sampled data from the in-phase clock and the quadrate phase clock. Embodiments may also include determining a convergence point based upon, at least in part, the analyzed sampled data, wherein the convergence point corresponds to a point where a number of early sampled outcomes is approximately equal to a number of late sampled outcomes. Embodiments may also include dynamically updating an accumulator threshold based upon the convergence point.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
16.
Method, product, and system for a sequence generation ecosystem using machine learning
An approach is disclosed herein a sequence generation ecosystem using machine learning. The approach disclosed herein is a new approach to sequence generation in the context of validation that relies on machine learning to explore and identify ways to achieve different states. In particular, the approach divides the valid operations into different respective actions and action sequences. These actions are selected by machine learning models as they are being trained using online inference reinforcement learning. This online inference also is likely to result in the discovery of new states. Each state that has been identified is then used as a target to train a respective machine learning model. As part of this process a representation of all the states and actions or sequences of actions executed to reach those states is created. This representation, the respective machine learning models, or a combination thereof can then be used to generate different test sequences.
Systems and methods of collecting performance metrics of an emulated design are disclosed. A method includes receiving, by a processor in the emulation system from a host system, configuration data including one or more user defined parameters, connecting, by the processor, a performance monitor to a port between communicatively connected components in the emulation system, initiating, by the processor, an emulation of the DUT, receiving, by the processor, emulation data from the emulation system, calculating, by the processor, performance data based on the configuration data, filtering, by the processor, the emulation data based on the performance data, and outputting, by the processor, the filtered emulation data to the host system.
The present disclosure relates to a system and method for automated printed circuit board (PCB) component placement. Embodiments may include receiving a PCB outline, one or more constraints, and a netlist having PCB component details and applying a clustering algorithm to generate one or more clustered groups. Embodiments may further include applying a grid based local cluster placement algorithm to the one or more clustered groups. Embodiments may also include applying a global cluster placement algorithm and generating a fully optimized placed design.
Embodiments included herein are directed towards a method for visualizing an electronic circuit design. Embodiments may include causing a display of a portion of an electronic design at a graphical user interface and receiving, at the graphical user interface, a selection of an object to be moved, wherein the object is displayed in a first color. In response to a user input, embodiments may include moving the object at the graphical user interface nearer a target location, displaying at least one target type in a second color and snapping the object to the target location.
G06F 30/31 - Design entry, e.g. editors specifically adapted for circuit design
G06F 3/0482 - Interaction with lists of selectable items, e.g. menus
G06F 3/04845 - Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range for image manipulation, e.g. dragging, rotation, expansion or change of colour
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
20.
System, method, and computer program product for optimization-based printed circuit board design
The present disclosure relates to electronic circuit design, and more specifically, to training a neural network to serve as the reward function for optimization-based approaches to PCB design automation. Embodiments may include generating, using a processor, one or more placed designs using a genetic optimization methodology including a reward function and adjusting the one or more placed designs and the reward function during the generating. Embodiments may further include routing the one or more placed designs using an auto-router to assign a routability score label and training a neural network, using the one or more placed designs and the routability score label, to extract one or more intermediate features from the one or more placed designs. Embodiments may also include predicting a routability of the PCB design based upon, at least in part, the one or more intermediate features.
A technical solution is directed to a clock recovery apparatus for multi-level signaling on a single-lane communication interface. The apparatus can use bin-map logic to successfully recover a common clock per symbol received on the multi-level signal interface. The multi-level signal can be PAM4 signaling where two bits are encoded to represent four levels. The clock recovery apparatus can detect signal level through individual edge detectors for each of the two bits and can handle jitter up to half-clock period.
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
H04B 14/02 - Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
22.
Maximum turn constraint for routing of integrated circuit designs
Aspects of the present disclosure address systems and methods for routing an integrated circuit design based on a maximum turn constraint. Data describing an integrated circuit is accessed. The integrated circuit design comprises a net specifying a connection between a first pin and a second pin. A maximum turn constraint is accessed. The maximum turn constraint specifies a maximum number of turns for connection paths generated in routing the integrated circuit design. The net is routed based on the maximum turn constraint. The routing of the net results in a routed net comprising a connection path between the first pin and the second pin that includes a number of turns that satisfy the maximum turn constraint. A layout instance for the integrated circuit design is generated based in part on the routed net.
Methods and systems are provided for transmitting data using thin-oxide devices. The methods and system generate a first bias voltage and a second bias voltage based on a power supply voltage of the second voltage domain, the first bias voltage value representing a high-level voltage signal of the first voltage domain, and the second bias voltage representing a low-level voltage signal of the second voltage domain and its value corresponds to a difference between the second voltage domain and the first voltage domain. The methods and systems generate an output of the thin-oxide device interface using first and second thin-oxide devices, the output of the thin-oxide device interface having a range corresponding to the second voltage domain.
H03K 3/011 - Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
24.
System and method for verifying a cross-connection of lanes in a multi-lane environment using a single testbench
An approach for verifying a cross-connection of lanes in a multi-lane environment using a single testbench-is provided. The approach may include providing a physical receiver lane index associated with a local device and providing a physical transmitter lane index associated with a peer device. The approach may further include randomizing a number of connected receiver lanes associated with the local device and a number of connected receiver lanes associated with the peer device. The approach may further include randomizing the physical receiver lane index and the physical transmitter lane index to generate a unique cross connection including randomized values. The approach may also include assigning the randomized values to one or more randomized cross connection defines. The approach may further include passing the cross connection defines to the single testbench and verifying each possible cross connection using a protocol specific mechanism.
Various embodiments described herein provide for a read data strobe (RDQS) path having variation compensation (e.g., voltage and temperature compensation), delay lines, or both, where the RDQS path can be included by a physical (PHY) interface for a memory device, such as a Double Data Rate (DDR) Dynamic Random-Access Memory (DRAM) memory device.
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
G06F 1/12 - Synchronisation of different clock signals
G06F 13/20 - Handling requests for interconnection or transfer for access to input/output bus
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
Embodiments included herein are directed towards sampling circuits and methods of using the same. Embodiments may include a data sense amplifier circuit and a reference sense amplifier circuit directly connected with the data sense amplifier circuit. Embodiments may further include a latch circuit configured to receive a first input from the data sense amplifier circuit and a second input from the reference sense amplifier circuit. The latch circuit may be further configured to generate a least significant bit output based upon, at least in part, the first input and the second input.
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
A method can include obtaining, at a physical communication layer integrated with a communication interface, a data packet, detecting, by a detection circuit integrated with the physical communication layer, a portion of data in the data packet corresponding to a marker identifying the data packet, linking, by the physical communication layer based on the marker, a timestamp with the data packet, and transmitting, by the physical communication layer, the data packet linked with the timestamp.
A system for generating a single design data file may include a processor and a memory. The processor may obtain design data including a plurality of design units. The processor may determine a first order of the plurality of design units. The processor may translate each of the plurality of design units into a corresponding file fragment by executing multiple threads of a first process. The processor may aggregate each of the plurality of file fragments into the single design data file in the first order by executing a second process in parallel to the first process.
The present disclosure relates to a system and method for duty cycle correction is provided. The method may include receiving a signal at a duty cycle adjuster and performing serializer clock duty cycle correction at the duty cycle adjuster. The method may further include performing true clock duty cycle correction at a transmitter duty cycle adjuster and performing complementary duty cycle distortion correction at the transmitter duty cycle adjuster.
The present disclosure describes a circuit that may include a first amplifier portion configured to receive a first input signal corresponding to a first clock signal and a second input signal corresponding to a second clock signal. The circuit may include a first amplifier of the first amplifier portion. The first amplifier may be configured to receive a first amplifier input signal and a second amplifier input signal. The circuit may include a second amplifier portion configured to receive a first output signal from the first amplifier portion. In a first mode, the first amplifier input signal may be based upon the second input signal and the second amplifier input signal may be based upon the first input signal. In a second mode, the first amplifier input signal may be based upon the first input signal and the second amplifier input signal may be based upon the second input signal.
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
G01R 29/02 - Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
H03K 3/017 - Adjustment of width or dutycycle of pulses
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
A memory circuit may include both an array circuit and multiple register circuits, where the power to retrieve data from one of the register circuits may be less than the power to retrieve data from the array circuit. The array circuit may store multiple data words, and the multiple register circuits may be configured to store a subset of the multiple data words. During a first cycle, a read command and an address may be received. In response to a determination that the address corresponds to a given data word included in the subset of the multiple data words, the array circuit may be de-activated in a second cycle subsequent to the first cycle and an output signal may be generated by selecting data retrieved from a particular register circuit of the multiple register circuits in which the given data word may be stored.
Embodiments are directed towards a method for creating a relational memory designed for one or more key parameters in at least one memory part configurations library. The method may include identifying one or more high-level parameters (HLPs) within the at least one memory part configurations library, assigning each non-HLP parameter an HLP key, using the assigned HLP keys as a frame of reference to cross-correlate each non-HLP parameter with every other non-HLP parameter in the at least one memory part configurations library. The method may also include extracting a complete relational memory attribute set from the cross-correlated parameters in the at least one memory part configurations library, generating memory configuration metadata equivalent to the at least one memory part configurations library from the complete relational memory attribute set, and providing memory part automation from the generated memory configuration metadata.
A shared memory is provided between simulation processors and emulation processors within an emulation chip. The shared memory is configured to enable the simulation processors and the emulation processors to exchange simulation data and emulation data respectively with each other during simulation and emulation operations. The simulation processors and the emulation processors may update their respective simulation and emulation operations in response to the simulation data and the emulation data exchanged via the shared memory.
G06F 30/33 - Design verification, e.g. functional simulation or model checking
G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines
G06F 30/331 - Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
G06F 30/3323 - Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
An approach is disclosed herein to sequence selection in a UVM environment. Generally, this approach includes a training phase for each machine learning model of a plurality of machine learning models. Each model is trained to achieve a particular target state and is rewarded when a selected action or sequence of actions causes movement that might be beneficial to achieving that target state. Once a respective model is trained, the trained model can then be used to determine which one action or sequence of actions (or ordered multiple thereof) to take to achieve the corresponding target state. Thus, by training and using a plurality of machine learning models to achieve a plurality of target states, and stimulating those machine learning models once trained, one or more actions and/or sequences of actions are generated as the selected sequences to be used to verify functionality or operation of a design under test.
Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with an MOR-based envelope Fourier technique. Multiple training models may be determined at multiple time points for an electronic circuit by using at least the MOR-based envelope Fourier technique that comprises a harmonic balance technique. A training model of the multiple training models may be reduced into a reduced order training model in a reduced order space at least by applying at least model order reduction of the MOR-based envelope Fourier technique to the training model. A time varying system may be determined for the electronic circuit based by using at least the reduced order training model.
Implementations can include a system to trace and identify target signals by cross-correlation to a signal pattern for a circuit, the system including a data processing system including memory and one or more processors to identify a target signal among a plurality of signals propagating through a circuit, detect one or more reference signals associated with an input to the target signal, the reference signals satisfying a threshold based on a depth associated with the target signal and the circuit, generate a cross-correlation object between the target signal and the reference signals based on a waveform of the target signal and corresponding waveforms of the reference signals, generate a metric corresponding to a cross-correlation between at least a portion of the target signal and at least a portion of the cross-correlation object, and modify, based on the metric, a control object of the circuit, the control object associated with the target signal.
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
A control component transmits a timing strobe and associated write data burst to a memory component, extending the write data burst to include a quantity of successive bits in excess of active edges in the timing strobe to ensure that the write data burst is sampled under worst-case timing skew conditions.
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
09 - Scientific and electric apparatus and instruments
Goods & Services
Downloadable computer software for use to automate design
and building of integrated circuits, and manuals therewith
sold as a unit; computer hardware and recorded computer
software for electronics design; computers, downloadable
computer programs and computer software, namely,
downloadable computer aided design software for electronics,
downloadable computer aided design software for analog
electronics, downloadable computer aided design software for
radio frequency electronics, downloadable graphical user
interface software, downloadable computer aided design
software for electromagnetics, downloadable computer aided
design software for electronic systems, downloadable
computer aided design software for digital electronics,
downloadable interfacing software modules for computer aided
design software, downloadable computer aided design software
for physical objects, namely, mobile phones, mobile network
base stations, circuit boards, semiconductor chips,
micro-electro-mechanical sensors; computer hardware and
recorded computer software for use in computer-aided design
for electronic systems being comprised of one or more
semiconductor chips; computer hardware and recorded computer
software for use in computer chip design; downloadable cloud
computing software for designing, modeling, emulating,
fabricating, simulating, testing, installing, implementing,
and verifying electronic circuitry, integrated circuits,
semiconductors, printed circuit boards, related electronic
products, and electronic systems, and user documentation in
the nature of manuals sold as a unit therewith; downloadable
cloud computing software for modeling, emulating,
fabricating, simulating, testing, implementing, and
verifying electronic component design, and user
documentation in the nature of manuals sold as a unit
therewith; downloadable databases of electronic computer
aided design software; downloadable computer software
manuals for all of the aforementioned software.
39.
Port generation based on layout connectivity information
Various embodiments provide for port generation for a circuit design based on layout connectivity information, which can be used as part of an automatic or a semi-automatic process of an electronic design automation (EDA) system. For instance, various embodiments access connectivity information for one or more networks of a circuit design, and use the connectivity information to identify pins of signal networks as positive connections for ports, and geometric shapes on references networks as candidates for negative connections for ports.
Methods and systems are provided for performing voltage level shifting using thin-oxide devices. The methods and systems convert an input signal associated with a first voltage domain to output signals associated with the first and second voltage domains. A first set of thin-oxide devices generate a first output signal at the high-level voltage signal when the input signal comprises a high logic level and generate the first output signal at a ground level voltage signal when the input signal comprises a low logic level. A second set of thin-oxide devices generate a second output signal at a power supply voltage level of the second voltage domain when the input signal comprises the high logic level and generate the second output signal at the second bias voltage when the input signal comprises the low logic level.
An approach is disclosed herein for test sequence processing that is applicable to machine learning model generated test sequences as disclosed herein. The test sequence processing includes classification, grouping, and filtering. The classification is generated based on the execution of the test sequences. The grouping is performed based on information captured during the classification of the test sequences. The filtering is performed on a group by group basis to remove redundant test sequences.
Embodiments include herein are directed towards a system and method for glitch debugging in an electronic design. Embodiments may include receiving, using a processor, the electronic design and performing a formal glitch analysis of the electronic design to determine if one or more glitches are present in a clock logic of the electronic design. If a glitch is identified, embodiments may further include causing a generation of a graphical glitch debugger display. Embodiments may include receiving an edit to the electronic design and re-performing the formal glitch analysis of the electronic design to determine whether a glitch is present.
G06F 30/327 - Logic synthesisBehaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 11/36 - Prevention of errors by analysis, debugging or testing of software
G06F 30/331 - Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
43.
Circuit design modification using timing-based yield calculation
Various embodiments provide for using a timing-based yield calculation to modify a circuit design, which can be part of an electronic design automation (EDA) system. For instance, some embodiments use a timing-based yield calculation to modify one or more portions of the circuit design to improve timing of the circuit design (e.g., slack, slew, delay, etc.), the timing-based yield calculation of the circuit design, or both.
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 30/3315 - Design verification, e.g. functional simulation or model checking using static timing analysis [STA]
G06F 119/02 - Reliability analysis or reliability optimisationFailure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
44.
MODELING OF FOUR-STATE-AWARE MEMORIES IN AN EMULATION SYSTEM
The systems and methods described herein include emulators that implement wrappers comprising instrumentation logic for the emulator components (e.g., memories) to perform certain memory-related functions. These functions allow the physical binary memories of the emulator to behave as a ternary memory. The memory wrappers include instrumentation logic around logic of the physical binary memories. In some cases, embodiments generate the wrappers for the user memory, rather than performing conventional synthesis functions for user-design memories. The inputs include the user ternary RTL, as well as additional potential inputs for pre-compiler control. The wrappers instantiate the operations, such as MPRs or MPWs, and create the ternary-memory support logic to, for example, prevent unknown-value writes and to output unknown values X for unknown-value reads.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
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Computer hardware and recorded computer software for
electronics design; computer hardware and recorded computer
software for analyzing, designing, simulating, and
optimizing computational fluid and solid dynamics; computer
hardware and recorded computer software for multi-physics
and engineering analysis, design, simulation, and
optimization; downloadable cloud computing software for
multi-physics and engineering analysis, design, simulation,
and optimization; downloadable cloud computing software for
non-electronic design automation (EDA) tools, computational
fluid dynamics, multiphysics design, and turbomachinery
parts; computer hardware and recorded computer software for
the design, testing, fabrication, and installation of
turbomachinery and engines; downloadable cloud computing
software for the design, testing, fabrication, and
installation of turbomachinery and engines; downloadable
computer numerical software platform integrating
multiphysics design, simulation and optimization software
systems for computational fluid and solid dynamics;
downloadable cloud computing software for analyzing,
designing, simulating, and optimizing computational fluid
and solid dynamics; computers, downloadable computer
programs and computer software, namely, downloadable
computer aided design software for electronics, downloadable
computer aided design software for analog electronics,
downloadable computer aided design software for radio
frequency electronics, downloadable graphical user interface
software, downloadable computer aided design software for
electromagnetics, downloadable computer aided design
software for electronic systems, downloadable computer aided
design software for digital electronics, downloadable
interfacing software modules for computer aided design
software, downloadable computer aided design software for
physical objects, namely, mobile phones, mobile network base
stations, circuit boards, semiconductor chips,
micro-electro-mechanical sensors; computer hardware and
recorded computer software for use in computer-aided design
for electronic systems being comprised of one or more
semiconductor chips; computer hardware and recorded computer
software for use in computer chip design; downloadable cloud
computing software for designing, modeling, emulating,
fabricating, simulating, testing, installing, implementing,
and verifying electronic circuitry, integrated circuits,
semiconductors, printed circuit boards, related electronic
products, and electronic systems, and user documentation in
the nature of manuals sold as a unit therewith; downloadable
cloud computing software for modeling, emulating,
fabricating, simulating, testing, implementing, and
verifying electronic component design, and user
documentation in the nature of manuals sold as a unit
therewith; downloadable databases of electronic computer
aided design software, downloadable computer software
manuals for all of the aforementioned software. Providing temporary use of non-downloadable computer
software for use in analyzing, designing, simulating,
optimizing and computing applications across the
multiphysics system analysis space; design and development
of software and hardware for others for use in connection
with the design, development, fabrication, testing and
installation of electronic systems; design of new
electronics products for others; technical support, namely,
troubleshooting of computer software and hardware problems
and consultation services in connection therewith;
consultation services in the field of electronic product
design and design implementation; scientific and
technological services, namely, research and design in the
field of computer hardware, computer software and software
integration, computer chip hardware, microprocessors,
semiconductor devices, architecture instruction for computer
hardware and microprocessor, and processor and memory
architectures; providing technological information in the
field of computer hardware, computer processor chip design
and architecture, computer technology, software, instruction
set architectures, and processor architectures; computer
services, namely, semiconductor product modeling, design and
implementation; design and development of software and
hardware for others for use in connection with the design,
development, fabrication, testing and installation of
electronic systems; design of new electronics products for
others; technical support, namely, troubleshooting of
computer software and hardware problems and consultation
services in connection therewith; consultation services in
the field of electronic product design and design
implementation; design and development of cloud software for
numerical software platform integrating multiphysics design,
simulation and optimization software systems for
computational fluid and solid dynamics; design and
development of cloud computing software for analyzing,
designing, simulating, and optimizing computational fluid
and solid dynamics; design and development of cloud
computing software for multi-physics and engineering
analysis, design, simulation, and optimization; provision of
online non-downloadable cloud computing software for
non-electronic design automation (EDA) tools, computational
fluid dynamics, multiphysics design, and turbomachinery
parts.
46.
Post-CTS insertion delay and skew target reformulation of clock tree
Methods and systems for performing post clock tree synthesis (CTS) of a clock tree include accessing, from memory, an integrated circuit design comprising a clock tree interconnecting a clock source to a plurality of clock sinks. Each clock sink has an associated current insertion delay. A mean insertion delay of the plurality of clock sinks is determined based on the associated current insertion delays of the clock sinks. A target insertion delay for the clock sinks is set based on the mean insertion delay and a target insertion delay adjustment determined for each individual clock sink. One or more clock sinks are identified that have a target insertion delay adjustment exceeding a skew threshold value. The clock tree is modified to reduce the target insertion delay adjustment, for each identified clock sink of the one or more clock sinks, to less than or equal to the skew threshold value.
Methods and systems are provided for testing three-dimensional (3D) stacked dies of integrated circuits (ICs). The methods and systems receive, by test signal routing logic implemented on a first die, a first die test signal, the test signal routing logic operating in an elevate mode or turn mode. The methods and systems receive a second die test signal from a second die and route the first die test signal to an external device in the turn mode. The methods and systems route the second die test signal received from the second die to the external device in the elevate mode.
The present disclosure relates to a computer-implemented method for genetic placement of analog and mix-signal circuit components. Embodiments may include receiving an unplaced layout associated with an electronic circuit design and grouping requirements. Embodiments may also include identifying one or more instances that need to be placed in the unplaced layout and areas of the unplaced layout configured to receive the instances. Embodiments may further include analyzing one or more instances that need to be placed in the unplaced layout and the areas of the unplaced layout configured to receive the instances, wherein analyzing is based upon a row-based data structure. Embodiments may also include determining a location and an orientation for each of the one or more instances based upon the genetic algorithm and generating a placed layout based upon the determined location and orientation for each of the instances.
Embodiments included herein are directed towards a voltage-temperature drift resistant and power efficient clock distribution circuit. Embodiments may include a current generator and a voltage generator configured to receive an input from the current generator. Embodiments may also include a regulator which may be configured to receive a reference voltage from the voltage generator as an input and to generate regulated voltage as output. The clock distribution path may operate on a regulated voltage, the regulated voltage having a value proportional to a threshold value associated with a plurality of devices included in the clock distribution path.
The approach disclosed herein is a new approach to sequence generation in the context of validation that relies on machine learning to explore and identify ways to achieve different states. In particular, the approach uses machine learning models to identify different states and ways to transition from one state to another. Actions are selected by machine learning models as they are being trained using reinforcement learning. This online inference also is likely to result in the discovery of not yet discovered states. Each state that has been identified is then used as a target to train a respective machine learning model. As part of this process a representation of all the states and actions or sequences of actions executed to reach those states is created. This representation, the respective machine learning models, or a combination thereof can then be used to generate different test sequences.
This disclosure relates scan chain stitching. In one example, scan chain elements from a scan chain element space can be received for a scan chain partition. The scan chain elements can be grouped based on scan chain element grouping criteria to form scan chain groups. Scan chain data identifying a number of scan chains for the scan chain partition can be received. The scan chains can be scan chain balanced across the scan chain groups to assign each scan chain to one of the scan chain groups. The scan chain elements associated with each scan chain of the scan chains can be scan chain element balanced. Scan chain elements for each associated scan chain can be connected to form a scan chain data test path during a generation of scan chain circuitry in response to the scan chain element balancing.
Various embodiments provide for identifying and training a floating tap for decision feedback equalization. For some embodiments, the identification and training of the floating tap described herein can be part of a circuit for receiver block of a system, such as a memory system.
Methods and systems are provided for processing a signal over a serial link. The methods and systems receive, by an adjustable filter, a serial input signal, the adjustable filter configured to set a corner frequency of a channel response and a gain of the channel response, the adjustable filter adding a zero to the channel response before to a pole of the serial input signal. The methods and systems selectively apply, by a bandwidth booster component, compensation to signal attenuation of the serial input signal in a first mode of operation and of one or more test signals in a second mode of operation of a serial link receiver. The methods and systems generate, by one or more continuous time linear equalizers configured to receive on an output of the bandwidth booster, one or more output signals of the receiver based on an output signal from the bandwidth booster component.
Disclosed is an improved approach to implement sharing of delay calculations for replicated portions of a design, where input slews may be different between those replicated design portions. This allows the system to experience runtime improvements for timing analysis of electronic designs.
A memory view generator evaluates a Liberty file characterizing an NVM module to generate a memory view file for the NVM module. The memory view file includes a port alias identifying ports of the NVM module. The port alias for a set of ports of the NVM module characterizes a type of port in the set of ports. The memory view file includes a port action identifying ports of the NVM module that have a static value and a port access identifying ports of the NVM module that have a dynamic value. The memory view file has an address limit characterizing a number of words in the NVM module and an address partition characterizing address bits and data bits. The memory view file includes a read delay that defines a number of clock cycles needed to hold an address bus stable after a strobe port transitions to an inactive state.
G06F 12/08 - Addressing or allocationRelocation in hierarchically structured memory systems, e.g. virtual memory systems
G11C 29/44 - Indication or identification of errors, e.g. for repair
G11C 29/48 - Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
56.
Control algorithm generator for non-volatile memory module
An NVM algorithm generator that evaluates a Liberty file characterizing an NVM module and a memory view of the NVM module that identifies ports and associated operations of the NVM module to generate a control algorithm. The control algorithm includes a read algorithm that includes an order of operations for assigning values to ports of the NVM module to assert a read condition of a strobe port, executing a memory read on the NVM module and setting values to the ports on the NVM module to assert a complement of a program condition. The control algorithm also includes a program algorithm that includes an order of operations for assigning values to ports of the NVM module to assert the program condition of the strobe port, executing a memory write and setting values to the ports on the NVM module to assert the complement of the program condition.
Provided is an improved method, system, and computer program product to implement simulation for photonic devices. A composite, multi-domain simulation model is disclosed, with connected domain-specific representations that allow the use of the most relevant simulator technology for a given domain. The model has external connection points either expressed as actual ports or virtual ones, embodied by simulator API calls in the model.
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules
58.
System and method for poison information propagation in a storage device
Systems and methods for propagating poison information are provided. Embodiments include receiving write data having a poison flag asserted indicating the data to be written to a memory device is erroneous. Embodiments further include converting the write data to a pre-fixed data pattern and generating a parity code, based upon, at least in part, the pre-fixed data pattern. Embodiments may also include injecting a correctable error into the write-data or parity code and writing the write data and parity code into the memory device. The correctable error injection may occur in the data or in the parity code and during the read the comparison may occur accordingly.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
59.
Test-point flop sharing with improved testability in a circuit design
A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that is configured to evaluate the circuit netlist to determine compatibility of the test-point nodes in the circuit netlist. The test-point flop allocation module can further allocate each of the test-point flops to a test-point sharing group comprising a plurality of compatible test-point nodes. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design, the circuit layout comprising the functional logic and scan-chains comprising the test-point flops allocated to the test-point sharing groups in response to the circuit netlist. The circuit layout is employable to fabricate an integrated circuit (IC) chip.
A circuit and method are described for generating a low jitter output clock having an arbitrary non-integer divide ratio relative to a high-frequency clock. Integer divide ratios of the high-frequency clock may be achieved by dividing the high-frequency clock by the reference clock and phase locking the output clock to the high-frequency clock. Non-integer divide ratios can be achieved by dividing the high-frequency clock by the nearest integer, rounded down, and then delaying the resultant output clock by the modulus of the division. The delay can then be rotated across to create a clock with a non-integer divide ratio relative to the high-frequency clock. By doing so, a high-frequency clock may be used that is not constrained by having a frequency that is an integer multiple of each desired component-specific output clock signal.
H03L 7/183 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
61.
System and method for intelligent intent recognition based electronic design
Embodiments include herein are directed towards a system and method for intelligent intent recognition based electronic design. Embodiments may include receiving, using a processor, a natural language input from a user at an intent recognition model. Embodiments may also include performing intent recognition on the natural language input at the intent recognition model and providing an output from the intent recognition model to a command generator. Embodiments may further include generating a command based upon, at least in part, the output and executing the command at a target tool environment.
Methods and systems for providing concise data for analyzing checker completeness, in the context of formal verification analysis of circuit designs. The methods and systems concisely report information useful to a human user (e.g., circuit designer or verification engineer) for efficiently determining what manual action should be taken next to resolve holes in verification coverage. The reported information can include lists of signals on which checkers can be written, which lists can be ranked, can be limited to a subset of interest signals, and can include corresponding cover items for each reported interest signal. The present systems and methods thereby improve on reporting provided to the user, permitting the user to more quickly advance a formal verification process toward full coverage of the relevant portions of a circuit design.
Embodiments include receiving fixed size error checking and correction data blocks and metadata at a memory controller. Embodiments may include performing data to symbol mapping based upon the fixed size data blocks and providing an output of the data to symbol mapping to a first encoder without metadata configured for full detection correction of single device error and to a second encoder with metadata configured for partial detection correction of single device error. Embodiments may include receiving data at a memory based upon an output from the first encoder and the second encoder and receiving data from the memory at a first decoder without metadata configured for full detection correction of single device error and at a second decoder with metadata configured for partial detection correction. Embodiments may include re-mapping symbol data from the first decoder and the second decoder to actual data and generating output data blocks and metadata.
The present disclosure relates to a method for use with an electronic design. Embodiments may include simulating a processor model and a hardware model, each executed with a corresponding simulator thread on a simulation platform. Embodiments may also include simulating embedded software using the processor model. The simulating may include updating a given register of the processor model that stores a value that changes in response to switching between processes within the embedded software. Embodiments may further include setting a simulator breakpoint and a software breakpoint and enabling debugging of both non-virtual and virtual addresses at the software breakpoint without leaving the software breakpoint.
Methods and systems are disclosed for optimizing compilation efforts for design debug based on formal analyses. The method includes accessing a circuit design, automatically determining a segment as being a design region of interest, identifying a behavior within the segment for performing at least one verification test, compiling the segment without compiling a remainder of the circuit design, and providing performance indicators corresponding to the behavior within the segment based on the segment as compiled.
G06F 30/33 - Design verification, e.g. functional simulation or model checking
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
66.
Multi-threaded network routing based on partitioning
Various embodiments provide for multi-threaded network routing of a circuit design based on partitioning networks of the circuit design, which can enable partitioning routing tasks for the circuit design. More particularly, some embodiments iteratively partition networks of a circuit design into groups of networks, which enable various embodiments to schedule routing tasks for those groups of networks to available threads such that no two networks of the circuit design with overlapping routing regions are routed at the same time, and such that idle time of each thread (e.g., time where thread has no work or is waiting for another thread to finish) can be minimized.
Embodiments of the invention provide a system, media, and method for deep learning applications in physical design verification. Generally, the approach includes maintaining a pattern library for use in training machine learning model(s). The pattern library being generated adaptively and supplemented with new patterns after review of new patterns. In some embodiments, multiple types of information may be included in the pattern library, including validation data, and parameter and anchoring data used to generate the patterns. In some embodiments, the machine learning processes are combined with traditional design rule analysis. The patterns being generated and adapted using a lossless process that encodes the information of a corresponding area of a circuit layout.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
(1) Computer hardware and recorded computer software for electronics design; computer hardware and recorded computer software for analyzing, designing, simulating, and optimizing computational fluid and solid dynamics; computer hardware and recorded computer software for multi-physics and engineering analysis, design, simulation, and optimization; downloadable cloud computing software for multi-physics and engineering analysis, design, simulation, and optimization; downloadable cloud computing software for non-electronic design automation (EDA) tools, computational fluid dynamics, multiphysics design, and turbomachinery parts; computer hardware and recorded computer software for the design, testing, fabrication, and installation of turbomachinery and engines; downloadable cloud computing software for the design, testing, fabrication, and installation of turbomachinery and engines; downloadable computer numerical software platform integrating multiphysics design, simulation and optimization software systems for computational fluid and solid dynamics; downloadable cloud computing software for analyzing, designing, simulating, and optimizing computational fluid and solid dynamics; computers, downloadable computer programs and computer software, namely, downloadable computer aided design software for electronics, downloadable computer aided design software for analog electronics, downloadable computer aided design software for radio frequency electronics, downloadable graphical user interface software, downloadable computer aided design software for electromagnetics, downloadable computer aided design software for electronic systems, downloadable computer aided design software for digital electronics, downloadable interfacing software modules for computer aided design software, downloadable computer aided design software for physical objects, namely, mobile phones, mobile network base stations, circuit boards, semiconductor chips, micro-electro-mechanical sensors; computer hardware and recorded computer software for use in computer-aided design for electronic systems being comprised of one or more semiconductor chips; computer hardware and recorded computer software for use in computer chip design; downloadable cloud computing software for designing, modeling, emulating, fabricating, simulating, testing, installing, implementing, and verifying electronic circuitry, integrated circuits, semiconductors, printed circuit boards, related electronic products, and electronic systems, and user documentation in the nature of manuals sold as a unit therewith; downloadable cloud computing software for modeling, emulating, fabricating, simulating, testing, implementing, and verifying electronic component design, and user documentation in the nature of manuals sold as a unit therewith; downloadable databases of electronic computer aided design software, downloadable computer software manuals for all of the aforementioned software. (1) Providing temporary use of non-downloadable computer software for use in analyzing, designing, simulating, optimizing and computing applications across the multiphysics system analysis space; design and development of software and hardware for others for use in connection with the design, development, fabrication, testing and installation of electronic systems; design of new electronics products for others; technical support, namely, troubleshooting of computer software and hardware problems and consultation services in connection therewith; consultation services in the field of electronic product design and design implementation; scientific and technological services, namely, research and design in the field of computer hardware, computer software and software integration, computer chip hardware, microprocessors, semiconductor devices, architecture instruction for computer hardware and microprocessor, and processor and memory architectures; providing technological information in the field of computer hardware, computer processor chip design and architecture, computer technology, software, instruction set architectures, and processor architectures; computer services, namely, semiconductor product modeling, design and implementation; design and development of software and hardware for others for use in connection with the design, development, fabrication, testing and installation of electronic systems; design of new electronics products for others; technical support, namely, troubleshooting of computer software and hardware problems and consultation services in connection therewith; consultation services in the field of electronic product design and design implementation; design and development of cloud software for numerical software platform integrating multiphysics design, simulation and optimization software systems for computational fluid and solid dynamics; design and development of cloud computing software for analyzing, designing, simulating, and optimizing computational fluid and solid dynamics; design and development of cloud computing software for multi-physics and engineering analysis, design, simulation, and optimization; provision of online non-downloadable cloud computing software for non-electronic design automation (EDA) tools, computational fluid dynamics, multiphysics design, and turbomachinery parts.
69.
Emulation system supporting representation of four-state signals
An emulation processor may be configured to support emulating unknown binary logic based on non-arbitrariness of the unknown binary logic. For example, an unknown binary logic signal may take the finite binary values of 0 and 1. The circuitry in the emulation processor is configured to generate and propagate outputs based on the interactions of known input binary signals with the unknown input binary signals having non-arbitrary states. The emulation processor may support the both combinational and sequential operations associated with the unknown binary logic.
G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computerOutput arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines
70.
Method and system for debugging metastability in digital circuits
Systems and methods of debugging a design under test for metastability issues using formal verification. In one aspect, the method includes determining, by a server, that a functionality of the DUT failed an assertion; generating, by the server, a plurality of first waveforms for a plurality of clock domain crossing (CDC) pairs that are in a cone of influence of the assertion; applying, by the server, a constraint including a condition to the plurality of waveforms; and generating, by the server, one or more second waveforms for a first subset of the plurality of CDC pairs, wherein the first subset of the CDC pairs satisfied the condition.
G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include receiving a selection of an instance associated with an electronic design at an electronic design schematic displayed on a graphical user interface. Embodiments may also include selecting a corresponding instance within an electronic design layout displayed on a graphical user interface. Embodiments may further include receiving a selection of a source topology and routing at the electronic design layout displayed on the graphical user interface, based upon at least in part, the source topology.
An IC test engine generates a plurality of two-cycle delay test patterns that target a first set of multicycle faults and/or defects of a fabricated IC chip based on an IC design. Each two-cycle delay test pattern includes a scan-in shift window operating at a test clock frequency, and a capture window with a launch cycle and a capture cycle operating at a functional clock frequency. The IC test engine fault simulates the plurality of two-cycle delay test patterns against a second set of multicycle faults and/or defects in the IC design utilizing sim-shifting, such that a state of the IC design after at least a last two shift clock cycles of a scan-in shift in window of each two-cycle delay test pattern of the plurality of two-cycle delay test patterns are fault simulated to provide two fault initialization cycles for detection of a multicycle delay fault and/or defect.
An integrated circuit (IC) test engine generates N-cycle at-speed test patterns for testing for candidate faults and/or defects of a first set of transition faults and/or defects of an IC design. A diagnostics engine that receives test result data characterizing application of the N-cycle at-speed test patterns to a fabricated IC chip based on the IC design by an ATE, in which the test result data includes a set of miscompare values characterizing a difference between an expected result and a result measured by the ATE for a given N-cycle at-speed test pattern. The diagnostics engine employs a fault simulator to fault-simulate the N-cycle at-speed test patterns against a fault model that includes a first set of transition faults and/or defects and fault-simulate a subset of the N-cycle at-speed test patterns against a fault model that includes multicycle transition faults and/or defects utilizing sim-shifting.
The present disclosure relates to packing transaction layer (TL) packets at a link layer of a protocol stack. In some examples, channel type data identify a type of message channel for a first TL packet can be generated. A set of slot formats for a slot for packing the first TL packet can be identified based on the channel type data and a slot format database. A respective slot format of the set of slot formats can be selected for the slot based on a message type of the first TL packet, and a message type of a second TL packet. The first TL packet and the second TL packet can be packed into the slot having the selected respective slot format during generation of a link layer packet.
Embodiments included herein are directed towards a transmitter circuit. The circuit may include a most significant bit (“MSB”) main driver and a most significant bit boost driver operatively connected to the MSB main driver. The circuit may also include a least significant bit (“LSB”) main driver and a least significant bit boost driver operatively connected to the LSB main driver, wherein the MSB main driver and the LSB main driver are configured to receive two parallel non-return-to-zero (“NRZ”) data inputs.
The present disclosure relates to dynamically updating a delay line code. A method for updating the delay line code may include receiving a strobe input at a coarse delay line. The method may further include receiving a coarse delay cell code at the coarse delay line. The method may also include generating a first clock path based upon a first chain of interleaved logic gates included within the coarse delay line. The method may additionally include generating a second clock path based upon a second chain of interleaved logic gates included within the coarse delay line. The method may further include receiving the first clock path, and the second clock path, and a fine delay cell code at a fine delay cell. The method may also include generating a strobe delayed output based upon the first clock path, and the second clock path, and the fine delay code.
H03K 5/134 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices with field-effect transistors
H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
Various embodiments provide for context-aware circuit design layout construct, which may be part of electronic design automation (EDA). In particular, some embodiments enable use of a circuit design layout construct with a layout of a circuit design (hereafter, a circuit design layout), where a programmable pattern of layout shapes of the circuit design layout construct can be inserted into a circuit design layout and can be adapted based on context information associated with the location of its placement within the circuit design layout.
A method for optimizing a verification regression includes obtaining data, by a processor, of previously executed runs of at least one verification regression session; extracting from the data, by the processor, values of one or a plurality of control knobs and values of one or a plurality verification metrics that were recorded during the execution for each of the previously executed runs of said at least one verification regression; finding, by the processor, correlation between said one or a plurality of the control knobs and each said one or a plurality of verification metrics, and generating a set of one or a plurality of control conditions based on the found correlation; and applying, by the processor, the generated set of one or a plurality of control conditions on the verification environment or on the DUT, or on both, to obtain a new verification regression session.
Aspects of the present disclosure address systems and methods for driver resizing using a transition-based capacitance increase margin. An integrated circuit (IC) design stored in a database in memory is accessed. The IC design comprises a net comprising a set of driver cells. A capacitance increase margin for resizing an initial driver cell is determined based on a total capacitance of the net and transition time target associated with the initial driver cell. An alternative driver cell is selected from a library to resize the initial driver cell and is used to replace the initial driver cell in the net. The alternative driver is selected such that a pin capacitance of the alternative driver cell exceeds an initial pin capacitance corresponding to the initial driver cell by no more than the capacitance increase margin.
Implementations may include a method of accelerated modification of an emulation processor system, by loading, by a first emulation processor, a first portion of processor instructions into one or more registers of the first emulation processor, in response to a selection of a first programming mode associated with the first emulation processor, and loading, by a second emulation processor operatively coupled with the first emulation processor, a second portion of the processor instructions into one or more registers of the second emulation processor, in response to a selection of a first programming mode associated with the second emulation processor.
09 - Scientific and electric apparatus and instruments
Goods & Services
Downloadable computer software for use to automate design and building of integrated circuits, and manuals therewith sold as a unit; Computer hardware and recorded computer software for electronics design; computers, downloadable computer programs and computer software, namely, downloadable computer aided design software for electronics, downloadable computer aided design software for analog electronics, downloadable computer aided design software for radio frequency electronics, downloadable graphical user interface software, downloadable computer aided design software for electromagnetics, downloadable computer aided design software for electronic systems, downloadable computer aided design software for digital electronics, downloadable interfacing software modules for computer aided design software, downloadable computer aided design software for physical objects, namely, mobile phones, mobile network base stations, circuit boards, semiconductor chips, micro-electro-mechanical sensors; Computer hardware and recorded computer software for use in computer-aided design for electronic systems being comprised of one or more semiconductor chips; Computer hardware and recorded computer software for use in computer chip design; downloadable cloud computing software for designing, modeling, emulating, fabricating, simulating, testing, installing, implementing, and verifying electronic circuitry, integrated circuits, semiconductors, printed circuit boards, related electronic products, and electronic systems, and user documentation in the nature of manuals sold as a unit therewith; downloadable cloud computing software for modeling, emulating, fabricating, simulating, testing, implementing, and verifying electronic component design, and user documentation in the nature of manuals sold as a unit therewith; downloadable databases of electronic computer aided design software, downloadable computer software manuals for all of the aforementioned software
82.
METHOD AND SYSTEM TO FACILITATE REVIEW OF SCHEMATICS FOR AN ELECTRONIC DESIGN
Disclosed is a method and system for visualizing schematic changes for an electronic design, where multiple schematic view interfaces are provided such that a first schematic interface displays an older schematic version and a second schematic interface displays a newer schematic version. Coordination is performed between the multiple schematic views such that an element within any of the first or second schematic views is appropriately highlighted based upon a user input.
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 30/12 - Geometric CAD characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD
83.
System and method for routing in an electronic design
Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include enabling data transmission between plurality of protocol adapters, each of the protocol adapters including one ingress port and one egress port, wherein the ingress port of each of the plurality of protocol adapters maintains an active connection with a single egress port at one time. Embodiments may further include transmitting data between the plurality of protocol adapters using a distributed routing matrix that provides an interface between the plurality of protocol adapters.
Quantized softmax layers in neural networks are described. Some embodiments involve receiving, at an input to a softmax layer of a neural network from an intermediate layer of the neural network, a non-normalized output comprising a plurality of intermediate network decision values. Then for each intermediate network decision value of the plurality of intermediate network decision values, the embodiment involves: calculating a difference between the intermediate network decision value and a maximum network decision value; requesting, from a lookup table, a corresponding lookup table value using the difference between the intermediate network decision value and the maximum network decision value; and selecting the corresponding lookup table value as a corresponding decision value. A normalized output is then generated comprising the corresponding lookup table value for said each intermediate network decision value of the plurality of intermediate network decision values.
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G10L 25/30 - Speech or voice analysis techniques not restricted to a single one of groups characterised by the analysis technique using neural networks
G06F 17/18 - Complex mathematical operations for evaluating statistical data
Various embodiments provide for quantizing a trained neural network with removal of normalization with respect to at least one layer of the quantized neural network, such as a quantized multiple fan-in layer (e.g., element-wise add or sum layer).
An approach is disclosed herein for dynamic design switching for high performance mixed signal simulation. Disclosed herein is a new approach to simulation processes that allows for different segments of a design to be swapped out without requiring re-elaboration. This is an improvement over current techniques and decreases the amount of time need to simulate a design. In some embodiments, the technique illustrated herein is combined with an automated triggering mechanism that controls the selection of alternate representations for the same element base on those triggers. In some embodiments a new multiplexor structure is provided that is specifically tailored to solving the present issue.
G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G06F 30/38 - Circuit design at the mixed level of analogue and digital signals
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
87.
Model-based simulation result predictor for circuit design
Various embodiments provide for predicting a simulation result for a circuit design using a machine learning model, which can be used as part of a process of an electronic design automation (EDA) system that measures a circuit design (e.g., timing, power, voltage, current, etc.). In particular, various embodiments described herein can enable modeling simulated time measurements of a circuit design, and can enable such modeling with minimal usage of simulation result data.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
88.
Live offset cancellation of the decision feedback equalization data slicers
A receiver utilizes loop-unrolled decision feedback equalization (DFE). For each sample, two comparators, each configured with different thresholds, sample an input signal. The output of one of these comparators is selected and used as the output of the receiver and may be optionally input to additional DFE circuitry. The output of the other (non-selected) comparator is used to adjust an input offset voltage of that same comparator. Adjustments to the offset voltages of the comparators may be based on a statistical analysis of the respective outputs of the two comparators when not selected. Adjustments to the offset voltages of the comparators may be based on comparisons between the respective outputs of the two comparators when not selected to the outputs of a reference comparator that has been calibrated for minimal or zero offset.
Embodiments include herein are directed towards a system and method for monitoring compliance patterns. Embodiments may include a re-timer device-under-test configured to transmit a truncated compliance pattern associated with a PCIe compliance mode. Embodiments may further include a BFM monitor configured to receive the truncated compliance pattern and to identify a communication signal associated with the truncated compliance pattern. The BFM monitor may be further configured to discard at least one unexpected symbol on at least one lane associated with the communication signal and to collect compliance patterns on all lanes of the communication signal. The BFM monitor may be further configured to align one or more lane FIFOs based upon skew and to enable one or more compliance pattern checkers.
The present disclosure relates to a computer-implemented method for automatically determining pin placement associated with an electronic design. Embodiments may include receiving, using at least one processor, at least one layout associated with the electronic design and separating the at least one layout into one or more grids. Embodiments may also include extracting one or more connectivity features from the one or more grids, wherein the one or more connectivity features include instance-pin and pin information. Embodiments may also include training a machine learning model, based upon, at least in part, the one or more connectivity features and receiving the machine learning model and a test layout at a predictor engine. Embodiments may further include providing a user with a pin placement recommendation based upon, at least in part, the machine learning model and the test layout.
A tuned single-coil inductor is implemented between a signal driver output and external contact of an ESD-protected integrated circuit (IC) die and more specifically between the parasitic capacitances of the signal driver and the contact-coupled ESD (electrostatic discharge) element to form a Pi (π) filter that enhances signaling bandwidth at the target signaling rate of the IC die. The signal driver may be implemented with output-stage data serialization circuitry disposed in series between source terminals of a thick-oxide drive transistor and a power rail to avoid explicit level-shifting circuitry between the relatively low core voltage domain and relatively high I/O voltage domain.
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
High-speed signal propagation circuits are biased by a temperature-compensating signal-swing calibrator to yield a target output signal amplitude across process, voltage and temperature corners, avoiding the power-consumptive over-biasing conventionally employed to avoid under-amplitude conditions in slow-process, low-voltage and/or high temperature conditions.
A circuit and method are provided for setting a phase relationship between a first signal and a second signal having a known frequency relationship to a master signal but having an unknown phase relationship to each other. One or more phase signals is generated based on the master signal, the phase signals having different phases from each other. One of these phase signals is selected based on the phase of the first signal and a target phase delay between the first signal and second signal. The second signal is generated based on the phase and frequency of the selected phase signal.
An approach is described for a method, product, and apparatus for a machine learning process using weight sharing within a systolic array having reduced memory bandwidth. According to some embodiments, this approach includes providing a systolic array that includes processing elements which each have some number of storage elements for storing weights. For example, the weights can be reused for different data sets by identifying/capturing a current state of the storage elements, generating a plan to transition to a target state of those storage elements, and application of the transition plan such that weights that are already stored in those storage elements can be reused and/or relocate. This lowers the bandwidth requirements for weight memory by allowing weights that have previously been read into the systolic array to be reused.
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
95.
Signaling compression and decompression associated with a partially unrolled decision feedback equalizer (DFE)
Technologies for signaling compression inside a partially unrolled decision feedback equalizer (DFE) are described. The signaling compression associated with partially unrolled DFE results in multiplexers selecting a 1-bit output value from one of two 1-bit input values, which are decoding the actual multi-bit candidate levels and transforming the selected 1-bit output value to a multi-bit sliced value by adding to it a pointer value of a pulse-amplitude modulation (PAM) level. The signaling compression reduces the power and area of an N-tap DFE, where N is a positive integer.
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
96.
Voltage controlled oscillator (VCO) with adaptive temperature compensation
Aspects of the present disclosure include systems and methods for temperature adaptive voltage controlled oscillators. In one example, a voltage controlled oscillator includes a cross junction circuit electrically coupled to a temperature dependent input current, and an inductor circuit electrically coupled to the cross junction circuit. The voltage controlled oscillator additionally includes a capacitor bank circuit electrically coupled to the inductor circuit, and an input node that receives a control voltage. The voltage controlled oscillator further includes an output node configured to provide an oscillation frequency output, wherein the oscillation frequency output is controlled by the control voltage.
Techniques are disclosed relating to an apparatus that includes a plurality of memory access control registers that are programmable with respective address ranges within an address space. The apparatus further includes a memory access circuit configured to receive a command for performing a memory access, the command specifying an address corresponding to a location in a memory circuit. In response to the address being located within an address range of a particular one of the plurality of memory access control registers, the memory access circuit is configured to perform the command using override memory parameters that have been programmed into the particular memory access control register instead of a default set of attributes for the address space.
A prefetch circuit coupled to a cache memory circuit includes a storage circuit that stores multiple virtual-to-physical address map entries. In response to receiving an indication of a miss for an access request to the cache memory circuit, the prefetch circuit generates a prefetch address and compares it to a demand address included in the access request. In response to determining that the demand address and the prefetch address are in different memory pages, the prefetch circuit generates a prefetch request using physical page information retrieved from the storage circuit.
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
99.
Queue circuit for controlling access to a memory circuit
A queue circuit that manages access to a memory circuit in a computer system includes multiple sets of entries for storing access requests. The entries in one set of entries are assigned to corresponding sources that generate access requests to the memory circuit. The entries in the other set of entries are floating entries that can be used to store requests from any of the sources. Upon receiving a request from a particular source, the queue circuit checks the entry assigned to the particular source and, if the entry is unoccupied, the queue circuit stores the request in the entry. If, however, the entry assigned to the particular source is occupied, the queue circuit stores the request in one of the floating entries.
The present disclosure relates to applying genetic optimization to a routing strategy associated with an electronic design. Embodiments may include receiving pin and net information from an electronic design file and determining a minimum spanning tree for all pins associated with each net. Embodiments may include identifying pairs of connected pins and representing the pins as at least one line segment without layer information. Embodiments may include generating a crossing map based upon the line segments and assigning random layer information to each of the line segments. Embodiments may further include performing crossover and mutation operations to the line segments using hyperparameters and evaluating a fitness of the line segments. Embodiments may also include instantiating vias based upon a layer to which the line segment was assigned.
