Abstract

A computer based media, method and system for developing at least one context frame that summarizes a measure performance situation for one or more levels of one or more organizations, providing applications for managing the measure performance that adapt to the performance situation by using a context frame and a database that automatically captures and incorporates any changes in the measure performance situation.

IPC Classes  ?

• G06Q 40/00 - FinanceInsuranceTax strategiesProcessing of corporate or income taxes
• G06Q 10/06 - Resources, workflows, human or project managementEnterprise or organisation planningEnterprise or organisation modelling
• G06Q 30/02 - MarketingPrice estimation or determinationFundraising
• G06F 16/951 - IndexingWeb crawling techniques

Abstract

A method and device for using a set of APIs are provided. Some of the functions which used to be performed by software are now accelerated through hardware.

IPC Classes  ?

• G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computerOutput arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
• G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
• H01L 29/66 - Types of semiconductor device
• H01L 29/872 - Schottky diodes
• H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof

Abstract

A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

IPC Classes  ?

• H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 21/762 - Dielectric regions
• H01L 23/047 - ContainersSeals characterised by the shape the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
• H01L 23/051 - ContainersSeals characterised by the shape the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
• H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
• H01L 23/498 - Leads on insulating substrates
• H01L 23/66 - High-frequency adaptations
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 21/8234 - MIS technology
• H01L 23/552 - Protection against radiation, e.g. light
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/40 - Electrodes

Abstract

WE/2 is applied to both unselected word and bit lines not connected to the selected memory cell during the reading, programming, and erasing actions for the selected memory cell.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

IPC Classes  ?

• H01L 21/336 - Field-effect transistors with an insulated gate
• H01L 21/8234 - MIS technology
• H01L 21/762 - Dielectric regions
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
• H01L 29/66 - Types of semiconductor device

Abstract

A nonvolatile semiconductor memory device include: a two terminal structured variable resistive element, wherein resistive characteristics defined by current-voltage characteristics at both ends transit between low and high resistance states stably by applying a voltage satisfying predetermined conditions to the both ends. A transition from the low resistance state to the high resistance state occurs by applying a voltage of a first polarity whose absolute value is at or higher than first threshold voltage, and the reverse transition occurs by applying a voltage of a second polarity whose absolute value is at or higher than a second threshold voltage. A load circuit is connected to the variable resistive element in series having an adjustable load resistance. A voltage generation circuit applies a voltage to both ends of a serial circuit. The variable resistive element can transit between the states by adjusting a resistance of the load circuit.

IPC Classes  ?

• G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor

Abstract

A system operative to execute and train at least one avatar for each user of an interactive environment comprising a knowledge engine operative to continuously monitor each user's response to events in the interactive environment while each user controls the at least one avatar, a knowledge base operative to store each of the monitored user responses to events in the interactive environment and an action engine operative to control one or more actions of the at least one avatar for each user in the interactive environment based on the stored monitored responses regardless of each user's control of the at least one avatar.

IPC Classes  ?

• G06F 15/18 - in which a program is changed according to experience gained by the computer itself during a complete run; Learning machines (adaptive control systems G05B 13/00;artificial intelligence G06N)
• G06N 99/00 - Subject matter not provided for in other groups of this subclass

Abstract

In a liquid crystal display (LCD) device having a thin film transistor (TFT), the TFT includes a source electrode, a drain electrode and a semiconductor layer. At least one of the source electrode and drain electrode includes a first layer including copper and a second layer forming an oxide layer and covering the first layer. The semiconductor layer has a substantially linear current-voltage relationship with said source electrode or drain electrode including said first and second layers, when a voltage is applied between the semiconductor layer and said source electrode or drain electrode.

IPC Classes  ?

• G02F 1/136 - Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
• G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
• H01L 29/786 - Thin-film transistors
• G02F 1/1362 - Active matrix addressed cells
• G02F 1/1343 - Electrodes
• H01L 29/45 - Ohmic electrodes
• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength.

IPC Classes  ?

• H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H01L 29/40 - Electrodes
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

Abstract

A method of forming an oxide film on a surface of a copper alloy, including the steps of providing a copper alloy including copper and an element selected from the group consisting of Mn, Zn, Ga, Li, Ge, Sr, Ag, Ba, Pr and Nd, and diffusing atoms of the element to a surface of the copper alloy so as to form an oxide film on the surface of the copper alloy, wherein a concentration of the element in the copper alloy is more than 0.1 and not more than 20 atomic percentage and within a solubility limit of the element in the copper.

IPC Classes  ?

• G02F 1/1343 - Electrodes
• G02F 1/13 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
• H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof

Abstract

A variable resistive element comprising a configuration that an area of an electrically contributing region of a variable resistor body is finer than that constrained by an upper electrode or a lower electrode and its manufacturing method are provided. A bump electrode material is formed on a lower electrode arranged on a base substrate. The bump electrode material is contacted to a variable resistor body at a surface different from a contact surface to the lower electrode. The variable resistor body is contacted to an upper electrode at a surface different from a contact surface to the bump electrode material. Thus, a cross point region between the bump electrode material (the variable resistor body) and the upper electrode becomes an electrically contributing region of the variable resistor body, and then an area thereof can be reduced compared with that of the region regarding the conventional variable resistive element.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
• H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
• H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier

Abstract

A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

IPC Classes  ?

• H01L 31/119 - Devices sensitive to very short wavelength, e.g. X-rays, gamma-rays or corpuscular radiation characterised by field-effect operation, e.g. MIS type detectors
• H01L 31/062 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the metal-insulator-semiconductor type
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 23/047 - ContainersSeals characterised by the shape the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
• H01L 23/051 - ContainersSeals characterised by the shape the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
• H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
• H01L 23/66 - High-frequency adaptations
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 21/762 - Dielectric regions
• H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
• H01L 23/498 - Leads on insulating substrates
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/40 - Electrodes
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched

Abstract

Exemplary semiconductor device packaging structure and packaging method are provided. The packaging method uses an adhesive layer to bond multiple wafer pieces onto a first surface of a carrier substrate, each adjacent two of the wafer pieces having a gap formed therebetween for exposing a part of the adhesive layer. A packaging layer is filled in each of the gaps. At least one through silicon via is formed each of the wafer pieces to expose a bonding pad formed on an active surface of the wafer pieces. Redistribution circuit layers are formed on back surfaces of the respective wafer pieces and filled into the through silicon vias for electrical connection with the bonding pads. A sawing process is performed to saw starting from each of the packaging layers to a second surface of the carrier substrate, and thereby multiple semiconductor device packaging structures are obtained.

IPC Classes  ?

• H01L 23/495 - Lead-frames
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

A semiconductor structure and a manufacturing method thereof are provided. The method includes the following steps. Firstly, a semiconductor substrate having an active surface and a back surface is provided. The active surface is opposite to the back surface, and the semiconductor substrate includes at least one grounding pad disposed on the active surface. Secondly, at least one through silicon via is formed through the semiconductor substrate from the back surface to the active surface thus exposing the grounding pad. Then, a conductive layer is formed on the back surface of the semiconductor substrate and filled into the through silicon via to electrically connect to the grounding pad and the semiconductor substrate.

IPC Classes  ?

• H01L 21/311 - Etching the insulating layers

Abstract

In accordance with one or more embodiments, a flange package comprises a flange and an interposer having two or more fingers disposed in an interposer trench. The flange has a mold lock formed about a periphery of the interposer trench. A dielectric ring comprising a dielectric material is formed in the interposer trench, and in and around the periphery of the mold lock. A semiconductor die is disposed within the dielectric ring having gate pads and source pads formed on a first side, and having drain pads disposed on a second side of the die. The gate pads are coupled to the interposer and the source pads are coupled to the flange. A gate lead is coupled to the interposer and a drain lead is coupled to the drain pads. Other embodiments are disclosed.

IPC Classes  ?

• H01L 29/02 - Semiconductor bodies

Abstract

In a package process of backside illumination image sensor, a wafer including a plurality of pads is provided. A first carrier is processed to form a plurality of blind vias therein. The first carrier is adhered to the wafer so that the blind vias face to the pads correspondingly. A spacing layer is formed and a plurality of sensing components are disposed. A second carrier is adhered on the spacing layer. Subsequently, a carrier thinning process is performed so that the blind vias become the through holes. An insulating layer is formed on the first carrier. An electrically conductive layer is formed on the insulating layer and filled in the though holes to electrically connect to the pads. The package process can achieve the exact alignment of the through holes and the pads, thereby increasing the package efficiency and improving the package quality.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

An image sensing device includes an image sensing chip, an optical module and a protecting element. The image sensing chip has a front surface defining an image sensing region thereon. The optical module includes a barrel and at least one transparent element. The barrel is directly disposed on the front surface and around the image sensing region. The transparent element is disposed in the barrel and faces to the image sensing region. The protecting element covers an area of the front surface outside the optical module and surrounds the barrel. The image sensing device has a thin thickness.

IPC Classes  ?

• H04N 5/225 - Television cameras
• H04N 9/04 - Picture signal generators

Abstract

A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength.

IPC Classes  ?

• H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes

Abstract

In a liquid crystal display (LCD) device having a thin film transistor (TFT), the TFT includes a source electrode, a drain electrode and a semiconductor layer. At least one of the source electrode and drain electrode includes a first layer including copper and a second layer forming an oxide layer and covering the first layer. The semiconductor layer has a substantially linear current-voltage relationship with said source electrode or drain electrode including said first and second layers, when a voltage is applied between the semiconductor layer and said source electrode or drain electrode.

IPC Classes  ?

• G02F 1/136 - Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit

Abstract

Embodiments of methods, systems, apparatuses, and computer-readable may relate to interactive testing of source code. The method may include executing at least a part of the source code at the processing device and presenting the execution to a user. One or more gestures of the user may be captured while executing the part, where the user provides the gestures based on the execution presented to the user. The gestures may then be associated with the executing part, and a report may be generated that comprises information for the executing part associated with the captured gestures.

IPC Classes  ?

• G06F 9/44 - Arrangements for executing specific programs

Abstract

Embodiments of methods and systems for managing translation of a source code of a computer application, at a processing device, are described. A pre-translation analysis of the source code may be performed to determine a plurality of look-alike code snippets. Thereafter, a report may be generated for indicating at least one parameter associated with the plurality of look-alike code snippets. Subsequently, at least one of the plurality of look-alike code snippets may be modified with at least one pre-stored code snippet, based on the at least one parameter.

IPC Classes  ?

• G06F 9/45 - Compilation or interpretation of high level programme languages

Abstract

Managing assets during translation of source application to a target application may involve analyzing the source application to generate a database of characteristics of source assets. Thereafter, performance metrics for a target platform may be determined based on the characteristics of the source assets. Subsequently, the source assets may be processed based on the performance metrics to generate target assets.

IPC Classes  ?

• G06F 9/45 - Compilation or interpretation of high level programme languages

Abstract

Embodiments of the invention may involve managing translation of a source code of a computer application in a first programming language to a target code in a second programming language, at a processing device. A pre-translation analysis of the source code may be performed to determine a part of the source code that is not supported in the second programming language. Thereafter, a report may be generated for indicating modifications to the determined part of the source code. Subsequently, the determined part of the source code may be modified based on the report to generate an intermediate code.

IPC Classes  ?

• G06F 9/45 - Compilation or interpretation of high level programme languages

Abstract

A stacking carrier and a stacking method are provided. The stacking method is used between a wafer and a stacking carrier having the same shape. The stacking method includes the following steps. Firstly, an adhesive layer is coated on a surface of the carrier. Then, the adhesive layer corresponding to an edge of the carrier is partially removed, thereby defining at least one adhesive layer indentation. Afterwards, the wafer is stacked on the carrier through the adhesive layer having the adhesive layer indentation.

IPC Classes  ?

• H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof

Abstract

In a package process of backside illumination image sensor, a wafer including a plurality of pads is provided. A first carrier is processed to form a plurality of blind vias therein. The first carrier is adhered to the wafer so that the blind vias face to the pads correspondingly. A spacing layer is formed and a plurality of sensing components are disposed. A second carrier is adhered on the spacing layer. Subsequently, a carrier thinning process is performed so that the blind vias become the through holes. An insulating layer is formed on the first carrier. An electrically conductive layer is formed on the insulating layer and filled in the though holes to electrically connect to the pads. The package process can achieve the exact alignment of the through holes and the pads, thereby increasing the package efficiency and improving the package quality.

IPC Classes  ?

• H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof

Abstract

A silicon based substrate includes a silicon wafer, a first circuit substrate and a second circuit substrate. The silicon wafer includes a first surface and a second surface and at least a through silicon via. The first circuit substrate is disposed on the first surface and includes a plurality of first dielectric layers and a plurality of first conductive trace layers alternately stacked. The second circuit substrate is disposed on the second surface and includes a plurality of second dielectric layers and a plurality of second conductive trace layers alternately stacked. The trace density of the first conductive trace layers is higher than the trace density of the second conductive trace layers. Otherwise, the first dielectric layer includes an inorganic material and the second dielectric layer includes an organic material. A manufacturing method of the silicon based substrate is also provided.

IPC Classes  ?

• H01L 29/40 - Electrodes

Abstract

Exemplary semiconductor device packaging structure and packaging method are provided. The packaging method uses an adhesive layer to bond multiple wafer pieces onto a first surface of a carrier substrate, each adjacent two of the wafer pieces having a gap formed therebetween for exposing a part of the adhesive layer. A packaging layer is filled in each of the gaps. At least one through silicon via is formed each of the wafer pieces to expose a bonding pad formed on an active surface of the wafer pieces. Redistribution circuit layers are formed on back surfaces of the respective wafer pieces and filled into the through silicon vias for electrical connection with the bonding pads. A sawing process is performed to saw starting from each of the packaging layers to a second surface of the carrier substrate, and thereby multiple semiconductor device packaging structures are obtained.

IPC Classes  ?

• H01L 23/12 - Mountings, e.g. non-detachable insulating substrates

Abstract

A method for manufacturing semiconductor device includes the following steps. First, a carrier substrate and a plurality of pieced segments of wafer are provided. Each of the pieced segments of wafer has an active surface and a back surface on opposite sides thereof. Further, there is at least a bonding pad disposed on the active surface. Next, an adhering layer is formed between the carrier substrate and the active surfaces of the pieced segments of wafer, so as to make the pieced segments of wafer adhere to the carrier substrate. Next, a through silicon via is formed in each of the pieced segments of wafer to electrically connect to the bonding pad correspondingly. Then, the pieced segments of wafer are separated from the carrier substrate.

IPC Classes  ?

• H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
• H01L 21/44 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 21/50 - Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups or

Abstract

A semiconductor process includes the following steps. Firstly, a conductive substrate is provided. Then, at least one insulating pattern is formed on the conductive substrate. Thereafter at least one metal pattern is formed on the insulating pattern. After that, a passivation layer is formed on the conductive substrate to cover the metal pattern by an electroplating process.

IPC Classes  ?

• H01L 29/72 - Transistor-type devices, i.e. able to continuously respond to applied control signals
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

A semiconductor structure and a manufacturing method thereof are provided. The method includes the following steps. Firstly, a semiconductor substrate having an active surface and a back surface is provided. The active surface is opposite to the back surface, and the semiconductor substrate includes at least one grounding pad disposed on the active surface. Secondly, at least one through silicon via is formed through the semiconductor substrate from the back surface to the active surface thus exposing the grounding pad. Then, a conductive layer is formed on the back surface of the semiconductor substrate and filled into the through silicon via to electrically connect to the grounding pad and the semiconductor substrate.

IPC Classes  ?

• H01L 21/4763 - Deposition of non-insulating-, e.g. conductive-, resistive-, layers on insulating layersAfter-treatment of these layers

Abstract

An image sensing device includes an image sensing chip, an optical module and a protecting element. The image sensing chip has a front surface defining an image sensing region thereon. The optical module includes a barrel and at least one transparent element. The barrel is directly disposed on the front surface and around the image sensing region. The transparent element is disposed in the barrel and faces to the image sensing region. The protecting element covers an area of the front surface outside the optical module and surrounds the barrel. The image sensing device has a thin thickness.

IPC Classes  ?

• H04N 5/225 - Television cameras

Abstract

A software installation system comprises an interface component that receives a request to access data resident upon a flash memory card. An installation component compares a unique identifier associated with the data with a unique identifier embedded within the flash memory card, and the installation component determines whether to allow access to the data based at least in part upon the comparison. The installation component prohibits access to the data if the unique identifier associated with the data does not match the unique identifier embedded within the flash memory card.

IPC Classes  ?

• G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures

Abstract

Briefly, in accordance with one or more embodiments, a semiconductor device is manufactured by forming at least two or more cavities below a surface of a semiconductor substrate wherein the at least two or more cavities are spaced apart from each other by a selected distance, filling at least a portion of the at least two or more cavities with a dielectric material to form at least two or more dielectric structures, removing a portion of the substrate between the at least two or more dielectric structures to form at least one additional cavity, and covering the at least one additional cavity.

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

Systems and methods are disclosed which allow a person to pre-set preferred calling times for receiving incoming calls. During these pre-set times (which could vary from day to day) calls that arrive are interrupted such that ringing tone is not applied to at least some of the telephones at the user's premises. The caller is informed that the user prefers not to receive calls until the pre-set time. In one embodiment, the caller is given the option of leaving a message or, if the caller desires, completing the call. The system can be implemented by a call answer machine at the customer's premises while in another embodiment the interrupt occurs at a central switching point.

IPC Classes  ?

• H04M 1/00 - Substation equipment, e.g. for use by subscribers

Abstract

A software installation system comprises an interface component that receives a request to access data resident upon a flash memory card. An installation component compares a unique identifier associated with the data with a unique identifier embedded within the flash memory card, and the installation component determines whether to allow access to the data based at least in part upon the comparison. The installation component prohibits access to the data if the unique identifier associated with the data does not match the unique identifier embedded within the flash memory card.

IPC Classes  ?

• G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures

Abstract

The present invention provides a voice coder for voice communication that employs a multi-microphone system as part of an improved approach to enhancing signal quality and improving the signal to noise ratio for such voice communications, where there is a special relationship between the position of a first microphone and a second microphone to provide the communication device with certain advantageous physical and acoustic properties. In addition, the communication device can have certain physical characteristics and design features. In a two microphone arrangement, the first microphone is located in a location directed toward the speech source, while the second microphone is located in a location that provides a voice signal with significantly lower signal-to-noise ratio (SNR).

IPC Classes  ?

• G10L 21/02 - Speech enhancement, e.g. noise reduction or echo cancellation

Abstract

An apparatus for use with communication devices, the communication devices being configured to send and receive SMS messages, the apparatus includes a memory configured to store information indicative of the communication devices that are configured to process an SMS message of a first type, a processor configured to receive an SMS message of the first type from a first communication device, wherein the received SMS message includes contact information related to a user of the first communication device, analyze the received SMS message to determine information indicative of a destination address of the SMS message, the destination address corresponding to a second communication device, determine whether the second communication device is configured to receive SMS messages of the first type using the information indicative of the destination address and the information stored in the memory, send an outgoing SMS message to the second communication device wherein the outgoing SMS message is of the first type if it is determined that the second communication device is configured to receive SMS messages of the first type, and the outgoing SMS message is of a second type if it is determined that the second communication device is not configured to receive SMS messages of the first type.

IPC Classes  ?

• H04W 4/00 - Services specially adapted for wireless communication networksFacilities therefor

Abstract

A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength.

IPC Classes  ?

• H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS

Abstract

The present invention is directed to a system and method in which advantage is taken of the fact that a great percentage of the general public have on their person some form of communication device. When such communication devices are within certain pre-defined physical locations their relative position can serve to allow communications to be directed to the device simply by using the location of that device as a network address. In one embodiment, the defined space is a public conveyance, such as an airplane, train or bus, having defined seating. In such a situation, the network address for a device is the seat location of the device.

IPC Classes  ?

• H04L 12/28 - Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]

Abstract

In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a structure includes a dielectric material and a void below a surface of a substrate. The structure further includes a doped dielectric material over the dielectric material, over the first void, wherein at least a portion of the dielectric material is between at least a portion of the substrate and at least a portion of the doped dielectric material. Other embodiments are described and claimed.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 21/764 - Air gaps
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

A system for providing multiple graphical representations for wireless network devices indicating status of the devices. The generated graphical representations of the devices are indicative of radio frequency channels the devices are operating on, as well as whether devices are on, off or in a standby mode. A device in standby mode monitors the wireless network to determine when it can resume normal operation. A menu or other interface construct is generated to enable a user to determine additional properties of the devices, such as addresses. Device representations may also indicate that devices are operating within the wireless network, but do not support one or more functions associated the system for managing the wireless network.

IPC Classes  ?

• H04M 1/00 - Substation equipment, e.g. for use by subscribers

Abstract

In accordance with one or more embodiments, a semiconductor device comprises a semiconductor die having a heat region disposed on at least one portion of the semiconductor die, and a diamond substrate disposed proximate to the semiconductor die, wherein the diamond substrate is capable of dissipating heat from the diamond substrate via at least one or more bumps coupling the diamond substrate to the heat region of the semiconductor die.

IPC Classes  ?

• H01L 23/06 - ContainersSeals characterised by the material of the container or its electrical properties
• H01L 23/047 - ContainersSeals characterised by the shape the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
• H01L 23/373 - Cooling facilitated by selection of materials for the device

Abstract

Embodiments of the invention may provide methods and/or systems for converting a source application to a platform-independent application. Source programming language code of the source application may be translated to target programming language code of the platform-independent application. The source programming language code may comprise Connected Limited Device Configuration (CLDC) code, and the platform-independent programming language may be independent of one or more device platforms. Further, one or more source resources associated with the source application may be converted to one or more target resources.

IPC Classes  ?

• G06F 9/44 - Arrangements for executing specific programs

Abstract

The present invention is a system and method for modeling faces from images captured from a single or a plurality of image capturing systems at different times. The method first determines the demographics of the person being imaged. This demographic classification is then used to select an approximate three dimensional face model from a set of models. Using this initial model and properties of camera projection, the model is adjusted leading to a more accurate face model.

IPC Classes  ?

• G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
• G06K 9/36 - Image preprocessing, i.e. processing the image information without deciding about the identity of the image

Abstract

A content delivery system which supports fragment requests without specifying the source address, including an assembling device, a relay server, and fractional-storage servers. The assembling device issues a client-request to receive enough erasure-coded fragments to reconstruct a portion of streaming content. The relay server receives the client-request, selects a plurality of fractional-storage servers that together store enough fragments to reconstruct the portion, and transmits, to the fractional-storage servers, fragment pull protocol requests for these sufficient fragments, on behalf of the assembling device. And the fractional-storage servers transmit the requested fragments to the assembling device in response to the fragment requests.

IPC Classes  ?

• G06F 15/173 - Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star or snowflake

Abstract

Distributing pull protocol requests via a relay server and thereby reducing the number of outgoing packets used by a fragment pull protocol, including the steps of aggregating, by an assembling device, a plurality of fragment pull protocol requests into an aggregated message; transmitting the aggregated message to a relay server, whereby the relay server distributes the requests to at least two fractional-storage servers; and receiving, by the assembling device from the at least two fractional-storage servers, a plurality of fragments in response to the aggregated message.

IPC Classes  ?

• G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
• H04L 29/08 - Transmission control procedure, e.g. data link level control procedure
• G06F 17/30 - Information retrieval; Database structures therefor
• H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups

Abstract

Adaptation of data centers' bandwidth contribution to distributed streaming operations, including data centers comprising fractional-storage CDN servers storing erasure-coded fragments encoded with a redundancy factor R greater than one, assembling devices obtaining the fragments from subsets of the servers, and measuring fragment delivery parameters, and at least one decision component that occasionally changes at least some of the servers of the subsets to generally improve the measured parameters. Wherein the smaller the number of subsets in which the servers of a data center participate, the lower the center's fragment delivery throughput, the higher the center's cost of delivering a fragment, and the higher the likelihood of reducing the amount of bandwidth acquired from that data center by the operator of the system.

IPC Classes  ?

• G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

Abstract

A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength.

IPC Classes  ?

• H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS

Abstract

A semiconductor device is formed having a pedestal. The pedestal includes at least two dielectric layers. The pedestal has a sidewall and a major surface. A conductive layer is formed overlying the pedestal. A vertical portion of the conductive layer adjacent to the sidewall of the pedestal is a gate of the transistor. The portion of the conductive layer overlying the major surface can be used as interconnect. The gate and gate interconnect are contiguous and formed in a single process. A conductive shield layer may be integrated into the pedestal. The conductive shield layer functions as a faraday shield that reduces gate to drain capacitance of the device.

IPC Classes  ?

• H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS
• H01L 21/336 - Field-effect transistors with an insulated gate

Abstract

A semiconductor device is formed having lower gate to drain capacitance. A trench (80) is formed adjacent to a drain (20) of the semiconductor device. Trench (80) has a sidewall surface (100) and a surface (90). A doped region (110) is implanted through the sidewall surface (100) of trench (80). A dielectric layer (150) overlies the sidewall surface (100) of trench (80). A shield layer (170) overlies the dielectric layer (150). The shield layer (170) is between a portion of drain (20) and a portion of the gate and gate interconnect of the semiconductor device thereby reducing gate to drain capacitance. The shield layer (170) overlies a minority portion of the surface (90) of trench (80). A second shield layer (270) further reduces gate to drain capacitance.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A semiconductor device is formed having lower gate-to-drain capacitance. The semiconductor device having an active region (1300) and a dielectric platform region (1310). A trench (80) is formed adjacent to a drain (20) of the semiconductor device to a first depth. The etch process for forming trench (80) etches the dielectric platform region (1310) to a first depth. A second trench (210) is etched in trench (80) to further isolate areas in the active region (1300). The etch process for forming the second trench (210) etches the dielectric platform region (1310) to form a support structure for the dielectric platform in the substrate. The dielectric platform, the trench (80), and the second trench (210) is capped and sealed. The dielectric platform is made approximately planar to the major surface of the substrate by forming the support structure from the first depth to the second depth.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A semiconductor device having reduced input capacitance is disclosed. The semiconductor device includes a pedestal region having a gate overlying a sidewall of the pedestal region and gate interconnect overlying a major surface of the pedestal region. The pedestal region includes a conductive shield layer (260). The conductive shield layer (260) is isolated from the gate of the transistor by more than one dielectric layer (330, 340, and 350) to reduce input capacitance. The pedestal region includes an air gap region (1525) to further lower the dielectric constant of the pedestal region between the gate/gate interconnect and the conductive shield layer (260).

IPC Classes  ?

• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

Abstract

Using a distributed storage to its maximum bandwidth including the following steps: for each group of at least one assembling device, selecting a subgroup of fractional-storage CDN servers according to at least one criterion, whereby a plurality of server subgroups are selected for a plurality of assembling device groups. And retrieving, using a pull protocol, by the assembling devices from the subgroups of servers, erasure-coded fragments associated with multiple segments of contents, until the aggregated bandwidth used for retrieving the fragments approaches the aggregated bandwidth of the servers included in the subgroups, and as long as the aggregated bandwidth used for delivering each segment does not exceed the aggregated bandwidth of the servers storing the fragments generated from the segment.

IPC Classes  ?

• G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
• G06F 15/173 - Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star or snowflake

Abstract

Methods and systems for maximum bandwidth broadcast-like streams, including a plurality of assembling devices; each assembling device retrieves, approximately simultaneously, erasure-coded fragments from a plurality of fractional-storage CDN servers, whereby the broadcast-like streaming contents are reconstructed from the fragments, and wherein different mixtures of broadcast-like streaming contents can be retrieved by the assembling devices until the aggregated bandwidth used by the assembling devices to retrieve the fragments approaches the aggregated fragment delivery bandwidth capabilities of the servers.

IPC Classes  ?

• G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
• G06F 15/173 - Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star or snowflake

Abstract

Fast segment reconstruction from erasure-coded fragments, including the steps of requesting, by an assembling device using a fragment pull protocol, from a plurality of fractional-storage servers, a first quantity of erasure-coded fragments associated with one or more segments of streaming content; the first quantity of fragments is requested approximately according to the sequential order of the segments, and the first quantity of fragments is more than the minimal quantity of fragments needed for reconstructing the one or more segments. And receiving, by the assembling device, a second decodable quantity of fragments as a response; whereby the second quantity of fragments may be smaller than the first quantity due to a failure condition.

IPC Classes  ?

• G06F 15/173 - Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star or snowflake

Abstract

Retrieving erasure-coded fragments associated with approximately sequential segments, including the steps of requesting a first set of the fragments, using a fragment pull protocol, by an assembling device from a plurality of fractional-storage servers, and requesting a second set of erasure-coded fragments, using the fragment pull protocol, to compensate for the fragments of the first set that failed to arrive at the assembling device. And wherein while requesting the first-set fragments associated with a certain segment, at least one compensation request is made for a second-set fragment associated with a prior segment.

IPC Classes  ?

• G06F 15/173 - Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star or snowflake

Abstract

Methods and devices for controlling the rate of a pull protocol, including the steps of requesting, from a plurality of fractional-storage servers by an assembling device utilizing a fragment pull protocol, erasure-coded fragments at a first rate that is estimated to approximately result in a target fragment reception throughput. And requesting, by the assembling device, additional erasure-coded fragments instead of fragments that have already been requested but have failed to arrive at the assembling device.

IPC Classes  ?

• G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
• G06F 15/173 - Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star or snowflake

Abstract

Methods and systems for broadcast-like effect using fractional-storage servers that receive and store erasure-coded fragments, which are generated on-the-fly from segments of streaming content arriving in real-time. Shortly thereafter, assembling devices obtain the fragments and reconstruct the segments at a rate that allows approximately real-time presentation of the streaming content including the segments.

IPC Classes  ?

• G06F 15/173 - Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star or snowflake

Abstract

Obtaining a broadcast-like streaming content by an assembling device from a distributed storage. The assembling device obtains erasure-coded fragments associated with sequential segments of streaming content from fractional-storage servers, approximately at the same rate that the fragments are being stored on the servers and shortly after the fragments are stored. And wherein the streaming content is segmented, encoded into the fragments, and stored on the servers progressively as the streaming content is made available.

IPC Classes  ?

• G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
• G06F 15/173 - Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star or snowflake

Abstract

Combining push and pull protocols, including the steps of pushing approximately a minimal decodable set of erasure-coded fragments to an assembling device, determining the fragment loss at the assembling device, and pulling additional erasure-coded fragments, using a fragment pull protocol, to compensate for the fragment loss. Optionally, the system includes a CDN streaming server and a fractional-storage CDN server, both storing unique erasure-coded fragments associated with segments of streaming content. The CDN streaming server pushes streams of fragments to a plurality of assembling devices, and the fractional-storage CDN server provides fragments associated with recently pushed segments in response to fragment pull protocol requests by the assembling devices.

IPC Classes  ?

• G06F 15/173 - Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star or snowflake

Abstract

Fault tolerance in a distributed streaming system including fractional-storage CDN servers storing erasure-coded fragments encoded with a redundancy factor greater than one from segments of streaming contents. Each server delivers fragments, at a certain fragment delivery throughput, to multiple assembling devices using a fragment pull protocol, wherein a reduction in the fragment delivery throughput of one of the servers triggers a process in which at least some of the other servers approximately immediately increase their fragment delivery throughput as a reaction to the fragment pull protocol, to compensate for the reduced throughput.

IPC Classes  ?

• G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
• H04L 29/08 - Transmission control procedure, e.g. data link level control procedure
• G06F 17/30 - Information retrieval; Database structures therefor
• H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups

Abstract

Obtaining erasure-coded fragments using push and pull protocols, including the steps of receiving a first set of erasure-coded fragments associated with segments via a transmission using push protocol, whereby the first set is not sufficient for reconstructing some of the segments; and retrieving a second set of erasure-coded fragments using a fragment pull protocol, wherein the first and the second sets together are sufficient for reconstructing the segments.

IPC Classes  ?

• G06F 15/173 - Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star or snowflake

Abstract

Reduction of peak-to-average traffic ratio in distributed streaming systems, including a large number of fractional-storage CDN servers accessed via the Internet, and storing erasure-coded fragments encoded with a redundancy factor greater than one from streaming contents, and a very large number of assembling devices obtaining the fragments from the servers in order to reconstruct the streaming contents. The assembling devices are spread over different time zones spanning at least three hours and balance the bandwidth load between the servers.

IPC Classes  ?

• G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
• H04L 29/08 - Transmission control procedure, e.g. data link level control procedure
• G06F 17/30 - Information retrieval; Database structures therefor
• H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups

Abstract

Load-balancing a distributed system by replacing overloaded servers, including the steps of retrieving, by an assembling device using a fragment pull protocol, erasure-coded fragments associated with segments, from a set of fractional-storage servers. Occasionally, while retrieving the fragments, identifying at least one server from the set that is loaded to a degree requiring replacement, and replacing, using the fragment pull protocol, the identified server with a substitute server that is not loaded to the degree requiring replacement. Wherein the substitute server and the remaining servers of the set are capable of delivering enough erasure-coded fragments in the course of reconstructing the segments.

IPC Classes  ?

• G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
• G06F 17/30 - Information retrieval; Database structures therefor
• H04L 29/08 - Transmission control procedure, e.g. data link level control procedure
• H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups

Abstract

Controlling fragment load on shared links, including a large number of fractional-storage CDN servers storing erasure-coded fragments encoded with a redundancy factor greater than one from contents, and a large number of assembling devices configured to obtain the fragments from sub-sets of the servers. At least some of the servers share their Internet communication link with other Internet traffic, and the fragment traffic via the shared link is determined by the number of sub-sets in which the servers accessed via the shared link participate. Wherein the maximum number of sub-sets in which the servers accessed via the shared link are allowed to participate is approximately a decreasing function of the throughput of the other Internet traffic via the shared link.

IPC Classes  ?

• G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
• H04L 29/08 - Transmission control procedure, e.g. data link level control procedure
• G06F 17/30 - Information retrieval; Database structures therefor
• H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups

Abstract

A system and method for securing communications in a wireless network includes the steps of authenticating members of the wireless network, generating a member private key to be used by the members of the wireless network, and distributing the member private key to each of the members of the wireless network. A member is authenticated based on the ability of the member to be physically proximate to at least one other member of the wireless network at a given instant. The member private key is generated by one of the members, hereinafter referred to as a master member, in response to a changing value stored at the one of the members. The member private key is then securely distributed to each of the members in the WLAN network.

IPC Classes  ?

• H04M 1/66 - Substation equipment, e.g. for use by subscribers with means for preventing unauthorised or fraudulent calling
• H04M 1/68 - Circuit arrangements for preventing eavesdropping
• H04M 3/16 - Automatic or semi-automatic exchanges with lock-out or secrecy provision in party-line systems

Abstract

In a liquid crystal display (LCD) device having a thin film transistor (TFT), the TFT includes a source electrode, a drain electrode and a semiconductor layer. At least one of the source electrode and drain electrode includes a first layer including copper and a second layer forming an oxide layer and covering the first layer. The semiconductor layer has a substantially linear current-voltage relationship with said source electrode or drain electrode including said first and second layers, when a voltage is applied between the semiconductor layer and said source electrode or drain electrode.

IPC Classes  ?

• G02F 1/136 - Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit

Abstract

A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

Abstract

In accordance with one or more embodiments, a flange package comprises a flange and an interposer having two or more fingers disposed in an interposer trench. The flange has a mold lock formed about a periphery of the interposer trench. A dielectric ring comprising a dielectric material is formed in the interposer trench, and in and around the periphery of the mold lock. A semiconductor die is disposed within the dielectric ring having gate pads and source pads formed on a first side, and having drain pads disposed on a second side of the die. The gate pads are coupled to the interposer and the source pads are coupled to the flange. A gate lead is coupled to the interposer and a drain lead is coupled to the drain pads. Other embodiments are disclosed.

IPC Classes  ?

• H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like

Abstract

A system and method for graphically representing associations between wireless network devices in a way that visually indicates the maximum amount of throughput between the associated devices, as well as a channel that is currently selected for communications between the associated devices. The thickness of a line between the associated devices may indicate the maximum throughput between the devices, whereas the color of the line may indicate the channel on which the associated devices are currently communicating. Other visual characteristics of lines generated between associated devices may be used to visually represent maximum possible throughput and current channel selection. Associations between the devices in the wireless network may be determined by checking a list of associated stations maintained in each access point.

IPC Classes  ?

• G01R 31/08 - Locating faults in cables, transmission lines, or networks

Abstract

A human machine interface (HMI) device comprises a power recognition component that determines at least one power source that is providing power to the HMI device, wherein the at least one power source is one of a host device providing power by way of a Universal Serial Bus connection, an AC power source, a DC power source, and a battery. A selector component can automatically select a subset of functionalities to enable with respect to the HMI from amongst several possible functionalities based at least in part upon the at least one determined power source.

IPC Classes  ?

• G05B 11/00 - Automatic controllers
• G05B 13/02 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric
• G06F 19/00 - Digital computing or data processing equipment or methods, specially adapted for specific applications (specially adapted for specific functions G06F 17/00;data processing systems or methods specially adapted for administrative, commercial, financial, managerial, supervisory or forecasting purposes G06Q;healthcare informatics G16H)

Abstract

Embodiments of the invention provide a platform-independent application development framework for programming an application. The framework comprises a content interface configured to provide an Application Programming Interface (API) to program the application comprising a programming code to be executed on one or more platforms. The API provided by the framework is independent of the one or more platforms. The framework further comprises an application environment configured to provide an infrastructure that is independent of the one or more platforms and one or more plug-in interfaces configured to provide an interface between the application environment and the one or more platforms.

IPC Classes  ?

• G06F 9/44 - Arrangements for executing specific programs

Abstract

Embodiments of the methods and apparatus for automatic cross language program code translation are provided. One or more characters of a source programming language code are tokenized to generate a list of tokens. Thereafter, the list of tokens is parsed to generate a grammatical data structure comprising one or more data nodes. The grammatical data structure may be an abstract syntax tree. The one or more data nodes of the grammatical data structure are processed to generate a document object model comprising one or more portable data nodes. Subsequently, the one or more portable data nodes in the document object model are analyzed to generate one or more characters of a target programming language code.

IPC Classes  ?

• G06F 9/45 - Compilation or interpretation of high level programme languages
• G06F 11/00 - Error detectionError correctionMonitoring

Abstract

A manufacturing method for a variable resistive element according to which a stable switching operation can be achieved with excellent reproducibility is provided. A conductive thin film is deposited on a semiconductor substrate and patterned to a predetermined form, and after that, a first interlayer insulating film is deposited. An opening is then created in a predetermined location on the first interlayer insulating film in such a manner that the upper surface of the conductive thin film is exposed and the thickness of the conductive thin film formed at the bottom of this opening is reduced through processing, and after that, an oxidation process is carried out on the periphery of the exposed conductive thin film. As a result, a variable resistor film is formed in the peripheral region of the opening, and this variable resistor film divides the conductive thin film into a first electrode and a second electrode.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

Abstract

A method and apparatus for building relationship opportunities for event participants with similar interests before, during and after the event are disclosed. The method includes creating a profile of a first user registered for an event, the profile includes terms indicative of preferences and characteristics of the first user. The method also includes receiving an inquiry from the first user for at least one match based on at least one keyword and providing a list of matches to the user in response to the inquiry, wherein the match is a second user sharing similar interests with the first user.

IPC Classes  ?

• G06Q 90/00 - Systems or methods specially adapted for administrative, commercial, financial, managerial or supervisory purposes, not involving significant data processing

Abstract

A nonvolatile semiconductor memory device include: a two terminal structured variable resistive element, wherein resistive characteristics defined by current-voltage characteristics at both ends transit between low and high resistance states stably by applying a voltage satisfying predetermined conditions to the both ends. A transition from the low resistance state to the high resistance state occurs by applying a voltage of a first polarity whose absolute value is at or higher than first threshold voltage, and the reverse transition occurs by applying a voltage of a second polarity whose absolute value is at or higher than a second threshold voltage. A load circuit is connected to the variable resistive element in series having an adjustable load resistance. A voltage generation circuit applies a voltage to both ends of a serial circuit. The variable resistive element can transit between the states by adjusting a resistance of the load circuit.

IPC Classes  ?

• G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor

Abstract

In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed.

IPC Classes  ?

• H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS

Abstract

In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed.

IPC Classes  ?

• H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof

Abstract

In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed.

IPC Classes  ?

• H01L 21/336 - Field-effect transistors with an insulated gate
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 21/8234 - MIS technology
• H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof

Abstract

An access point in a wireless network includes an external indication of the access point's proximity to another access point. The external indication can be a LED that blinks at a rate that is related to the proximity of the access point to the other access point. An access point is also capable of producing a network map that indicates the access point's proximity relative to other access points that are coupled to the network. The access point is further capable of monitoring wireless network traffic to ascertain whether wireless network traffic has exceeded a threshold, and if so, releasing some client devices so that wireless network traffic no longer exceeds the threshold. The access point is also capable of automatically choosing one of a plurality of radio frequencies on which to operate. The access point chooses a frequency after evaluating frequencies on which other access points may be operating.

IPC Classes  ?

• H04W 40/00 - Communication routing or communication path finding

Abstract

In accordance with one or more embodiments, a semiconductor structure includes a semiconductor substrate, a first semiconductor material over the semiconductor substrate, and a second semiconductor material over a portion the first semiconductor material, wherein the second semiconductor material comprises silicon-germanium-carbon (SiGeC) and wherein the first semiconductor material is a silicon epitaxial layer. The semiconductor structure further includes an active device, wherein a portion of the active device is formed in the second semiconductor material and a dielectric structure extending from the first surface of the first semiconductor material into the semiconductor substrate through the first semiconductor material.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 31/0328 - Inorganic materials including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups
• H01L 31/0336 - Inorganic materials including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups in different semiconductor regions, e.g. Cu2X/CdX hetero-junctions, X being an element of Group VI of the Periodic System
• H01L 31/072 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
• H01L 31/109 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PN heterojunction type
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
• H01L 31/036 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
• H01L 31/0376 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including amorphous semiconductors
• H01L 31/20 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor material
• H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed

Abstract

Within an industrial automation environment, a human-machine interface (HMI) is provided comprising a HMI computer, a display electrically coupled with the computer, and a controller wirelessly coupled with the computer. The controller is configured to detect motion of the controller, and wirelessly transmit motion data related to the motion of the controller to the HMI computer. The HMI computer is configured to receive industrial automation data, wirelessly receive motion data from the controller, process the motion data into control data, and select a first set of industrial automation data for display in response to the control data.

IPC Classes  ?

• G06F 19/00 - Digital computing or data processing equipment or methods, specially adapted for specific applications (specially adapted for specific functions G06F 17/00;data processing systems or methods specially adapted for administrative, commercial, financial, managerial, supervisory or forecasting purposes G06Q;healthcare informatics G16H)

Abstract

A variable resistive element comprising a configuration that an area of an electrically contributing region of a variable resistor body is finer than that constrained by an upper electrode or a lower electrode and its manufacturing method are provided. A bump electrode material is formed on a lower electrode arranged on a base substrate. The bump electrode material is contacted to a variable resistor body at a surface different from a contact surface to the lower electrode. The variable resistor body is contacted to an upper electrode at a surface different from a contact surface to the bump electrode material. Thus, a cross point region between the bump electrode material (the variable resistor body) and the upper electrode becomes an electrically contributing region of the variable resistor body, and then an area thereof can be reduced compared with that of the region regarding the conventional variable resistive element.

IPC Classes  ?

• H01L 47/00 - Bulk negative resistance effect devices, e.g. Gunn-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof

Abstract

Briefly, in accordance with one or more embodiments, a dielectric platform is at least partially formed in a semiconductor substrate and extending at least partially below a surface of a semiconductor substrate. The dielectric platform may include structural pillars formed by backfilling a first plurality of cavities etched in the substrate, and a second plurality of cavities formed by etching away sacrificial pillars disposed between the structural pillars. The second plurality of cavities may be capped to hermetically seal the second plurality of cavities to impart the dielectric constant of the material contained therein, for example air, to the characteristic dielectric constant of the dielectric platform. Alternatively, the second plurality of cavities may be backfilled with a material having a lower dielectric constant than the substrate, for example silicon dioxide where the substrate comprises silicon.

IPC Classes  ?

• H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof

Abstract

In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a structure includes a dielectric material and a void below a surface of a substrate. The structure further includes a doped dielectric material over the dielectric material, over the first void, wherein at least a portion of the dielectric material is between at least a portion of the substrate and at least a portion of the doped dielectric material. Other embodiments are described and claimed.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 21/764 - Air gaps
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method to manufacture a semiconductor structure includes forming a cavity in a substrate. A portion of the substrate is doped, or a doped material is deposited over a portion of the substrate. At least a portion of the doped substrate or at least a portion of the doped material is converted to a dielectric material to enclose the cavity. The forming of the cavity may occur before or after the doping of the substrate or the depositing of the doped material. Other embodiments are described and claimed.

IPC Classes  ?

• H01L 21/76 - Making of isolation regions between components
• H01L 21/425 - Bombardment with radiation with high-energy radiation producing ion implantation
• H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers
• H01L 21/469 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layers

Abstract

In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material to form a first protrusion and a cavity having a boundary that is below a surface of the semiconductor material, wherein the first protrusion extends from the boundary of the cavity. The method further includes forming a non-conformal material over a first portion of the first protrusion using an angled deposition of the non-conformal material, wherein the angle of deposition of the non-conformal material is non-perpendicular to the surface of the semiconductor material. Other embodiments are described and claimed.

IPC Classes  ?

• H01L 29/02 - Semiconductor bodies

Abstract

In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material to form a cavity that extends at least about one micron or greater below the surface of the semiconductor material, filling the cavity with a sacrificial material, forming a dielectric material over the sacrificial material and over at least a portion of the surface of the semiconductor material, and removing a portion of the dielectric material to form an opening to expose a portion of the sacrificial material, wherein the opening has a width that is substantially less than a width of the cavity and the dielectric material is rigid or substantially rigid. The method further includes removing the sacrificial material. Other embodiments are described and claimed.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

Abstract

In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material using an electrochemical etch to form a first cavity, a second cavity, wherein the first cavity is isolated from the second cavity, a first protrusion is between the first cavity and the second cavity, and the semiconductor material comprises silicon. The method further includes performing a thermal oxidation to convert a portion of the silicon of the semiconductor material to silicon dioxide and forming a first dielectric material over the first cavity, over the second cavity, over at least a portion of the semiconductor material, and over at least a portion of the first protrusion. Other embodiments are described and claimed.

IPC Classes  ?

• H01L 21/76 - Making of isolation regions between components

Abstract

In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material using an orientation-dependent etch to form a first cavity, a second cavity, wherein the first cavity is isolated from the second cavity, a first protrusion is between the first cavity and the second cavity, and the semiconductor material comprises silicon. The method further includes performing a thermal oxidation to convert a portion of the silicon of the semiconductor material to silicon dioxide and forming a first dielectric material over the first cavity, over the second cavity, over at least a portion of the semiconductor material, and over at least a portion of the first protrusion. Other embodiments are described and claimed.

IPC Classes  ?

• H01L 21/76 - Making of isolation regions between components

Abstract

A semiconductor memory device (1) comprises a memory cell array (100) in which memory cells each have a variable resistance element and the memory cells in the same row are connected to a common word line and the memory cells in the same column are connected to a common bit line, wherein during a predetermined memory action, the voltage amplitude of the voltage pulse applied to an end of at least one of the selected word line and the selected bit line is adjusted based on the position of the selected memory cell in the memory cell array (100) so that the effective voltage amplitude of a voltage pulse applied to the variable resistance element of the selected memory cell to be programmed or erased falls within a certain range regardless of the position in the memory cell array (100).

IPC Classes  ?

• G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor

Abstract

WE/2 is applied to both unselected word and bit lines not connected to the selected memory cell during the reading, programming, and erasing actions for the selected memory cell.

IPC Classes  ?

• G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor

Abstract

In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a capacitor embedded in a dielectric material below the surface of a semiconductor substrate is disclosed. Other embodiments are described and claimed.

IPC Classes  ?

• H01L 27/108 - Dynamic random access memory structures

Abstract

In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a semiconductor device includes a plurality of rectilinear structures, wherein the plurality of rectilinear structures comprise silicon dioxide and extend from a surface of a semiconductor material to a distance of at least about three microns or greater below the surface of the semiconductor material and wherein a first rectilinear structure of the plurality of rectilinear structures is perpendicular to, or substantially perpendicular to, a second rectilinear structure of the plurality of rectilinear structures. Other embodiments are described and claimed.

IPC Classes  ?

• H01L 23/66 - High-frequency adaptations

Abstract

A content request, storage, and configuration system is provided for attendees of live events or performances, which associates pieces of content with one or more keywords, and configures the content for the benefit of a user. Content owners load content into the system or link content elsewhere to the system, and optionally designate a set of actions to be taken. Keywords are assigned to the content and actions by the system based on user input and/or auto-generation by the system. Thus, while attending a live event or performance, any of a variety of methods, including but not limited to Short Message Service (SMS) and instant messaging, are used by a user to communicate these keywords to the system, to indicate user interest in the associated content. Receipt by the system of the keywords from the user triggers the system to retrieve the relevant pieces of content, associate said content with the user making the request, and to take the designated actions if appropriate. In addition, users may designate that the system retrieve the relevant pieces of content and associate said content with other users.

IPC Classes  ?

• G06F 17/30 - Information retrieval; Database structures therefor

Abstract

Provided are a variable resistive element having a configuration that the area of an electrically contributing region in a variable resistor body is smaller than the area defined by an upper electrode or a lower electrode, and a method for manufacturing the variable resistive element. The cross section of a current path, in which an electric current flows through between the two electrodes via the variable resistor body at the time of applying the voltage pulse to between the two electrodes, is formed with a line width of narrower than that of any of the two electrodes and of smaller than a minimum work dimension regarding manufacturing processes, so that its area can be made smaller than that of the electrically contributing region in the variable resistive element of the prior art.

IPC Classes  ?

• H01C 7/10 - Non-adjustable resistors formed as one or more layers or coatingsNon-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
• H01C 7/13 - Non-adjustable resistors formed as one or more layers or coatingsNon-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material current-responsive

Abstract

In various embodiments, semiconductor components and methods to manufacture these components are disclosed. In one embodiment, a method to manufacture a semiconductor component is disclosed. The semiconductor includes a heat sink and a semiconductor die that has a first terminal on a top surface of the semiconductor die, a second terminal on the top surface of the die, and a third terminal on the bottom surface of the die. The method includes attaching a first portion of a leadframe structure to the first terminal of the semiconductor die. The method further includes attaching the second terminal of the semiconductor die to the heat sink after the attaching of the first portion of the leadframe structure to the first terminal of the semiconductor die, wherein the leadframe structure is spaced apart from the heat sink and is electrically isolated from the heat sink. Other embodiments are described and claimed.

IPC Classes  ?

• H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation

Abstract

An apparatus for use with communication devices, the communication devices being configured to send and receive SMS messages, the apparatus includes a memory configured to store information indicative of the communication devices that are configured to process an SMS message of a first type, a processor configured to receive an SMS message of the first type from a first communication device, wherein the received SMS message includes contact information related to a user of the first communication device, analyze the received SMS message to determine information indicative of a destination address of the SMS message, the destination address corresponding to a second communication device, determine whether the second communication device is configured to receive SMS messages of the first type using the information indicative of the destination address and the information stored in the memory, send an outgoing SMS message to the second communication device wherein the outgoing SMS message is of the first type if it is determined that the second communication device is configured to receive SMS messages of the first type, and the outgoing SMS message is of a second type if it is determined that the second communication device is not configured to receive SMS messages of the first type.

IPC Classes  ?

• H04W 4/00 - Services specially adapted for wireless communication networksFacilities therefor

Abstract

A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth