Xcerra Corporation

United States of America

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        Patent 82
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Date
2023 4
2022 2
2021 3
2020 3
Before 2020 78
IPC Class
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer 25
G01R 1/04 - HousingsSupporting membersArrangements of terminals 21
G01R 1/067 - Measuring probes 16
G01R 1/073 - Multiple probes 11
G01R 31/319 - Tester hardware, i.e. output processing circuits 8
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NICE Class
09 - Scientific and electric apparatus and instruments 7
40 - Treatment of materials; recycling, air and water treatment, 5
11 - Environmental control apparatus 1
42 - Scientific, technological and industrial services, research and design 1
Status
Pending 3
Registered / In Force 87

1.

SYSTEM AND METHOD FOR ATTENUATING AND/OR TERMINATING RF CIRCUIT

      
Application Number 18132238
Status Pending
Filing Date 2023-04-07
First Publication Date 2023-08-03
Owner XCERRA CORPORATION (USA)
Inventor
  • Feng, Yukang
  • Steckler, Nadia
  • Mroczkowski, Jason
  • Hattis, James

Abstract

A high-speed circuit assembly includes a high-speed circuit including at least one waveguide/transmission line, and a radiation absorbing material disposed in contact with or in close proximity with the waveguide/transmission line.

IPC Classes  ?

  • G01R 1/04 - HousingsSupporting membersArrangements of terminals
  • H01R 13/646 - Details of coupling devices of the kinds covered by groups or specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
  • H01P 3/08 - MicrostripsStrip lines

2.

REFLECTIVE AND INTERFERENCE CONTROLLED ABSORPTIVE CONTACTOR

      
Document Number 03227337
Status Pending
Filing Date 2022-07-13
Open to Public Date 2023-01-26
Owner XCERRA CORPORATION (USA)
Inventor
  • Feng, Yukang
  • Mroczkowski, Jason
  • Steckler, Nadia
  • Lonks, Aaren
  • Cavegn, Marty
  • Hattis, James
  • Hanks, Mike

Abstract

An apparatus (100) including a contactor (102) having a hole (106) and including a radio frequency absorptive material (108) and a probe (104) inserted in the hole (106) to couple a test signal to a device under test, such as an integrated circuit (206), is disclosed. A test system for testing integrated circuits (206) including a contactor (102) including a radio frequency absorptive material (108) is disclosed. A method for making the contactor (102) is also disclosed, where the radio frequency absorptive material (108) is formed by 3D printing, moulding, coating or micro-machining.

IPC Classes  ?

  • G01R 1/04 - HousingsSupporting membersArrangements of terminals

3.

REFLECTIVE AND INTERFERENCE CONTROLLED ABSORPTIVE CONTACTOR

      
Application Number US2022036905
Publication Number 2023/003729
Status In Force
Filing Date 2022-07-13
Publication Date 2023-01-26
Owner XCERRA CORPORATION (USA)
Inventor
  • Feng, Yukang
  • Mroczkowski, Jason
  • Steckler, Nadia
  • Lonks, Aaren
  • Cavegn, Marty
  • Hattis, James
  • Hanks, Mike

Abstract

An apparatus (100) including a contactor (102) having a hole (106) and including a radio frequency absorptive material (108) and a probe (104) inserted in the hole (106) to couple a test signal to a device under test, such as an integrated circuit (206), is disclosed. A test system for testing integrated circuits (206) including a contactor (102) including a radio frequency absorptive material (108) is disclosed. A method for making the contactor (102) is also disclosed, where the radio frequency absorptive material (108) is formed by 3D printing, moulding, coating or micro-machining.

IPC Classes  ?

  • G01R 1/04 - HousingsSupporting membersArrangements of terminals

4.

REFLECTIVE AND INTERFERENCE CONTROLLED ABSORPTIVE CONTACTOR

      
Application Number 17384133
Status Pending
Filing Date 2021-07-23
First Publication Date 2023-01-26
Owner XCERRA CORPORATION (USA)
Inventor
  • Feng, Yukang
  • Mroczkowski, Jason
  • Steckler, Nadia
  • Lonks, Aaren
  • Cavegn, Marty
  • Hattis, James
  • Hanks, Mike

Abstract

An apparatus including a contactor having a hole and including a radio frequency absorptive material and a probe inserted in the hole to couple a test signal to a device under test is disclosed. A test system for testing integrated circuits including a contactor including a radio frequency absorptive material is disclosed. A method for making the contactor is also disclosed.

IPC Classes  ?

5.

Calibration system

      
Application Number 17246096
Grant Number 12044726
Status In Force
Filing Date 2021-04-30
First Publication Date 2022-11-03
Grant Date 2024-07-23
Owner XCERRA CORPORATION (USA)
Inventor
  • Reid, William
  • Lonks, Aaren

Abstract

A verification probe system is configured to verify an automated test platform and includes: an integrated circuit test probe assembly; and a moveable platform configured to position the integrated circuit test probe assembly proximate one of more conductive pins included within a test socket assembly of the automated test platform.

IPC Classes  ?

6.

Coaxial probe

      
Application Number 16989406
Grant Number 12111343
Status In Force
Filing Date 2020-08-10
First Publication Date 2022-02-10
Grant Date 2024-10-08
Owner Xcerra Corporation (USA)
Inventor
  • Feng, Yukang
  • Mroczkowski, Jason
  • Cavegn, Marty

Abstract

An apparatus and method for the manufacturing and use in a semiconductor test system is disclosed. The apparatus includes a signal probe and a dielectric sleeve surrounding the signal probe. A method includes forming a mold to receive a component of a contactor assembly, inserting the component into the mold, and forming a dielectric sleeve in at least one of the one or more signal probe holes through an injection molding process. The component includes one or more signal probe holes.

IPC Classes  ?

  • G01R 3/00 - Apparatus or processes specially adapted for the manufacture of measuring instruments
  • G01R 1/067 - Measuring probes
  • G01R 1/073 - Multiple probes
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • H01L 21/66 - Testing or measuring during manufacture or treatment

7.

Test socket assembly with antenna and related methods

      
Application Number 16911222
Grant Number 11662363
Status In Force
Filing Date 2018-10-19
First Publication Date 2021-11-25
Grant Date 2023-05-30
Owner XCERRA CORPORATION (USA)
Inventor
  • Mroczkowski, Jason
  • Han, Dongmei
  • Landa, Victor

Abstract

A test socket assembly includes a contactor body having one or more compliant interconnects, and a socket opening sized and configured to receive a device under test therein. The test socket assembly further includes a lead frame assembly disposed within the contactor body and electrically coupled with the one or more compliant interconnects, and one or more antennas at least partially disposed within the contactor body, the one or more antennas configured to directly and wirelessly communicate to the device under test when the device is disposed within the socket opening.

IPC Classes  ?

  • G01R 1/04 - HousingsSupporting membersArrangements of terminals

8.

System and method for attenuating and/or terminating RF circuit

      
Application Number 17142987
Grant Number 11650227
Status In Force
Filing Date 2021-01-06
First Publication Date 2021-07-22
Grant Date 2023-05-16
Owner XCERRA CORPORATION (USA)
Inventor
  • Feng, Yukang
  • Steckler, Nadia
  • Mroczkowski, Jason
  • Hattis, James

Abstract

A high-speed circuit assembly includes a high-speed circuit including at least one waveguide/transmission line, and a radiation absorbing material disposed in contact with or in close proximity with the waveguide/transmission line.

IPC Classes  ?

  • G01R 1/04 - HousingsSupporting membersArrangements of terminals
  • H01R 13/646 - Details of coupling devices of the kinds covered by groups or specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
  • H01P 3/08 - MicrostripsStrip lines

9.

Dielectric resonating test contactor and method

      
Application Number 17127751
Grant Number 12123897
Status In Force
Filing Date 2020-12-18
First Publication Date 2021-06-24
Grant Date 2024-10-22
Owner Xcerra Corporation (USA)
Inventor
  • Hattis, James
  • Evans, Travis
  • Muzammil, Waqas
  • Feng, Yukang
  • Mroczkowski, Jason
  • Cavegn, Marty

Abstract

A test contactor is disclosed. The test contactor includes two or more dielectric layers and a test probe embedded in the one or more dielectric layers. The test contactor traverses the one or more dielectric layers. The test probe to include an input signal port and an output signal port and the test probe to transmit a test signal from the input signal port to the output signal port.

IPC Classes  ?

  • G01R 1/067 - Measuring probes
  • G01R 1/02 - General constructional details
  • G01R 1/04 - HousingsSupporting membersArrangements of terminals
  • G01R 1/073 - Multiple probes
  • G01R 31/26 - Testing of individual semiconductor devices
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • H01R 13/22 - Contacts for co-operating by abutting
  • H01R 13/405 - Securing in non-demountable manner, e.g. moulding, riveting

10.

Test socket assembly with waveguide antenna probe

      
Application Number 16778677
Grant Number 11391765
Status In Force
Filing Date 2020-01-31
First Publication Date 2020-08-13
Grant Date 2022-07-19
Owner XCERRA CORPORATION (USA)
Inventor
  • Han, Dongmei
  • Gubert, Benoit
  • Feng, Yukang

Abstract

A test socket assembly including a contactor body having a socket opening sized and configured to receive a device under test therein, and one or more waveguides at least partially disposed within the contactor body or external to the contactor body. The assembly further including at least one waveguide antenna probe coupled with the one or more waveguides, where the at least one waveguide antenna probe including a first set of sides and a second set of sides, at least one of the first set of sides are flared out away from the longitudinal axis.

IPC Classes  ?

  • G01R 29/08 - Measuring electromagnetic field characteristics
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

11.

HIGH FREQUENCY CIRCUIT WITH RADAR ABSORBING MATERIAL TERMINATION COMPONENT AND RELATED METHODS

      
Application Number US2019050040
Publication Number 2020/051514
Status In Force
Filing Date 2019-09-06
Publication Date 2020-03-12
Owner XCERRA CORPORATION (USA)
Inventor
  • Mroczkowski, Jason
  • Steckler, Nadia
  • Hattis, James
  • Lonks, Aaren

Abstract

A high speed circuit assembly includes a high speed circuit including at least one transmission line extending to a transmission line end, and radar absorbing material disposed adjacent the transmission line.

IPC Classes  ?

12.

Spring-loaded probe having folded portions and probe assembly

      
Application Number 16466217
Grant Number 11268981
Status In Force
Filing Date 2017-12-14
First Publication Date 2020-02-27
Grant Date 2022-03-08
Owner XCERRA CORPORATION (USA)
Inventor
  • Treibergs, Valts
  • Brandes, James
  • Evans, Travis

Abstract

A test probe for use with a testing apparatus. The test probe includes a first portion, a second portion, and a third portion, with hinges between the first and second portions and the second and third portions. The first portion folded at the first hinge over the second portion, the third portion folded at the second hinge over the second portion, where the second portion is stacked between the first portion and the third portion. The test probe is compressible from a first uncompressed state to a second compressed state.

IPC Classes  ?

13.

Hybrid probe head assembly for testing a wafer device under test

      
Application Number 16424198
Grant Number 11041881
Status In Force
Filing Date 2019-05-28
First Publication Date 2019-12-05
Grant Date 2021-06-22
Owner XCERRA CORPORATION (USA)
Inventor
  • Treibergs, Valts
  • Nelson, Mitchell

Abstract

A hybrid probe head assembly for testing a wafer device under test includes a housing, at least a portion of a lead frame assembly disposed in the housing, the lead frame assembly including a at least one cantilever portion, the at least one cantilever portion including an undeflected position and a deflected position, where the lead frame assembly hinges between the undeflected position and the deflected position at a lead frame pivot point, and the at least one cantilever portion extends to a wafer contact. In the undeflected position, the at least one cantilever portion is disposed at a 8-12 degree angle, and in the deflected position, the at least one cantilever portion is disposed at a 2-4 degree angle. One or more spring probes are disposed within the housing and have a wafer contact tip.

IPC Classes  ?

14.

HYBRID PROBE HEAD ASSEMBLY FOR TESTING A WAFER DEVICE UNDER TEST

      
Application Number US2019034204
Publication Number 2019/231928
Status In Force
Filing Date 2019-05-28
Publication Date 2019-12-05
Owner XCERRA CORPORATION (USA)
Inventor
  • Treibergs, Valts
  • Nelson, Mitchell

Abstract

A hybrid probe head assembly for testing a wafer device under test includes a housing, at least a portion of a lead frame assembly disposed in the housing, the lead frame assembly including a at least one cantilever portion, the at least one cantilever portion including an undeflected position and a deflected position, where the lead frame assembly hinges between the undeflected position and the deflected position at a lead frame pivot point, and the at least one cantilever portion extends to a wafer contact. In the undeflected position, the at least one cantilever portion is disposed at a 8 - 12 degree angle, and in the deflected position, the at least one cantilever portion is disposed at a 2 - 4 degree angle. One or more spring probes are disposed within the housing and have a wafer contact tip.

IPC Classes  ?

15.

TEST SOCKET ASSEMBLY AND RELATED METHODS

      
Application Number US2018050028
Publication Number 2019/168561
Status In Force
Filing Date 2018-09-07
Publication Date 2019-09-06
Owner XCERRA CORPORATION (USA)
Inventor
  • Treibergs, Valts
  • Sikorski, Dan

Abstract

A test socket assembly for coupling a device under test to a test apparatus includes a housing, and a pivotable link, elastomer, and slidable mount at least partially disposed within a cavity of the housing. The pivotable link and slidable mount are disposed adjacent to the elastomer such that the elastomer biases both the first contact end of the link and the PCB contact members of the slidable mount toward out of the housing. The slidable mount has a side wall defined by a side wall plane, where the side wall plane is vertically slidable along an inner side wall of the housing.

IPC Classes  ?

  • G01R 1/04 - HousingsSupporting membersArrangements of terminals

16.

TEST SOCKET ASSEMBLY WITH HYBRID RING COUPLER AND RELATED METHODS

      
Application Number US2018067235
Publication Number 2019/168587
Status In Force
Filing Date 2018-12-21
Publication Date 2019-09-06
Owner XCERRA CORPORATION (USA)
Inventor
  • Mroczkowski, Jason
  • Steckler, Nadia
  • Hanks, Mike
  • Garman, Pat

Abstract

A test socket assembly includes a frame assembly having one or more compliant interconnects, and a socket opening sized and configured to receive a device under test therein. The test socket assembly further includes a lead frame assembly disposed adjacent to the frame assembly and electrically coupled with the one or more compliant interconnects. The lead frame assembly includes a hybrid ring coupler.

IPC Classes  ?

  • G01R 1/04 - HousingsSupporting membersArrangements of terminals

17.

CAPACITIVE TEST NEEDLE FOR MEASURING ELECTRICALLY CONDUCTIVE LAYERS IN PRINTED CIRCUIT BOARD HOLES

      
Application Number EP2019051148
Publication Number 2019/141777
Status In Force
Filing Date 2019-01-17
Publication Date 2019-07-25
Owner XCERRA CORP. (USA)
Inventor
  • Weiss, Stefan
  • Yuschuk, Oleh
  • Weindel, Christian

Abstract

The invention relates to a test needle for measuring electrically conductive layers in holes in printed circuit boards, and to a test probe having a test needle of this type and a finger tester for testing printed circuit boards which has a test needle of this type or a test probe of this type. The test needle has a capacitive measuring element which is connected to a capacitive measuring device by means of a cable. The cable is shielded and therefore only the capacitive measuring element is able to form a capacitive coupling with additional electrically conductive elements. As a result, this capacitive coupling can be determined with high spatial resolution.

IPC Classes  ?

18.

TEST SOCKET ASSEMBLY WITH ANTENNA AND RELATED METHODS

      
Application Number US2018056694
Publication Number 2019/133097
Status In Force
Filing Date 2018-10-19
Publication Date 2019-07-04
Owner XCERRA CORPORATION (USA)
Inventor
  • Mroczkowski, Jason
  • Han, Dongmei
  • Landa, Victor

Abstract

A test socket assembly includes a contactor body having one or more compliant interconnects, and a socket opening sized and configured to receive a device under test therein. The test socket assembly further includes a lead frame assembly disposed within the contactor body and electrically coupled with the one or more compliant interconnects, and one or more antennas at least partially disposed within the contactor body, the one or more antennas configured to directly and wirelessly communicate to the device under test when the device is disposed within the socket opening.

IPC Classes  ?

  • G01R 1/04 - HousingsSupporting membersArrangements of terminals
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

19.

TEST SOCKET ASSEMBLY WITH LINEAR SPRING DAMPER ASSISTED CANTILEVER CONTACTS

      
Application Number US2018050059
Publication Number 2019/133079
Status In Force
Filing Date 2018-09-07
Publication Date 2019-07-04
Owner XCERRA CORPORATION (USA)
Inventor
  • Treibergs, Valts
  • Nelson, Mitchell

Abstract

A test socket assembly includes a socket housing having one or more spring probes therein, and a lead frame assembly including one or more cantilever members. The test socket assembly further includes at least one linear spring damper disposed within the socket housing adjacent the lead frame assembly and supporting the cantilever members, the at least one linear spring damper extending from a first end to a second end, the second end disposed adjacent to a second movable end portion of the one or more cantilever members.

IPC Classes  ?

  • G01R 1/04 - HousingsSupporting membersArrangements of terminals
  • G01R 1/067 - Measuring probes

20.

TEST SOCKET ASSEMBLY WITH WAVEGUIDE TRANSITION AND RELATED METHODS

      
Application Number US2018055058
Publication Number 2019/133093
Status In Force
Filing Date 2018-10-09
Publication Date 2019-07-04
Owner XCERRA CORPORATION (USA)
Inventor
  • Mccarthy, Dick
  • Morse, Jim
  • Lonks, Aaren
  • Yu, Wei
  • Han, Dongmei
  • Evans, Travis
  • Hanson, Scott
  • Steckler, Nadia
  • Hattis, James
  • Garman, Pat
  • Mroczkowski, Jason

Abstract

A test socket assembly includes a contactor body, the contactor body having a socket opening sized and configured to receive a device under test therein. A lead frame assembly is disposed within the contactor body, the lead frame assembly includes at least a portion of a waveguide transition. At least one transmission line is disposed within the lead frame assembly, the at least one transmission line configured to communicate to the device under test when the device under test is disposed within the socket opening. One or more rectangular waveguides are at least partially disposed within the contactor body or external to the contactor body, and the waveguide transition is configured to provide a transition between the at least one transmission line and the rectangular waveguide, the waveguide transition disposed within the contactor body.

IPC Classes  ?

21.

TESTING DEVICE AND METHOD FOR TESTING A PRINTED CIRCUIT BOARDS

      
Application Number EP2018053236
Publication Number 2018/146234
Status In Force
Filing Date 2018-02-09
Publication Date 2018-08-16
Owner XCERRA CORP. (USA)
Inventor
  • Weindel, Christian
  • Ott, Bernd-Ulrich
  • Brandt, Peter

Abstract

The invention relates to a testing device and to a method for testing printed circuit boards, in particular unpopulated or partially populated printed circuit boards. The testing device is a finger tester having a shuttle or two sub-shuttles (5, 6), which can alternately move a printed circuit board to be tested to a testing region. In addition, the sub-shuttles can be used to jointly hold a large printed circuit board.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

22.

MULTI-NODE TESTING SYSTEM AND METHOD

      
Application Number US2017060144
Publication Number 2018/128699
Status In Force
Filing Date 2017-11-06
Publication Date 2018-07-12
Owner XCERRA CORPORATION (USA)
Inventor
  • Petrov, Todor K.
  • Liggiero, Richard

Abstract

An automated microtester array, for simultaneously testing a plurality of devices under test, includes a plurality of automated microtesters, wherein each of the plurality of automated microtesters is configured to test a plurality of devices under test. A central computing system is configured to automate the testing of the plurality of devices under test coupled to the plurality of automated microtesters. A method and computer program product for instructing a plurality of automated microtesters to load an automated test process; and instructing the plurality of automated microtesters in execute the automated test process.

IPC Classes  ?

23.

SPRING-LOADED PROBE HAVING FOLDED PORTIONS AND PROBE ASSEMBLY

      
Application Number US2017066343
Publication Number 2018/112166
Status In Force
Filing Date 2017-12-14
Publication Date 2018-06-21
Owner XCERRA CORPORATION (USA)
Inventor
  • Treibergs, Valts
  • Brandes, James
  • Evans, Travis

Abstract

A test probe for use with a testing apparatus. The test probe includes a first portion, a second portion, and a third portion, with hinges between the first and second portions and the second and third portions. The first portion folded at the first hinge over the second portion, the third portion folded at the second hinge over the second portion, where the second portion is stacked between the first portion and the third portion. The test probe is compressible from a first uncompressed state to a second compressed state.

IPC Classes  ?

  • G01R 1/067 - Measuring probes
  • H01R 13/24 - Contacts for co-operating by abutting resilientContacts for co-operating by abutting resiliently mounted

24.

MULTI-NODE TESTING SYSTEM AND METHOD

      
Application Number US2017060137
Publication Number 2018/089295
Status In Force
Filing Date 2017-11-06
Publication Date 2018-05-17
Owner XCERRA CORPORATION (USA)
Inventor
  • Petrov, Todor K.
  • Liggiero, Richard

Abstract

An automated microtester, for simultaneously testing a plurality of devices under test, includes a processing system including a plurality of processor assemblies. A plurality of test sites are configured to releasably engage a plurality of devices under test. An instrumentation system is controllable by the processing system and is configured to provide one or more input signals to the plurality of test sites and read one or more monitored signals from the plurality of test sites.

IPC Classes  ?

  • G01R 31/26 - Testing of individual semiconductor devices
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 31/319 - Tester hardware, i.e. output processing circuits
  • G06F 11/273 - Tester hardware, i.e. output processing circuits

25.

LINK SOCKET SLIDING MOUNT WITH PRELOAD

      
Application Number US2017056175
Publication Number 2018/085015
Status In Force
Filing Date 2017-10-11
Publication Date 2018-05-11
Owner XCERRA CORPORATION (USA)
Inventor
  • Magnuson, Aaron
  • Yakushev, Sergey
  • Treibergs, Valts
  • Sikorski, Dan

Abstract

A test socket with a link and mount system is used to couple a device under test to a testing apparatus for quick and reliable testing of microchips post-production. The socket includes a pivoting link that connects to the DUT, an elastomer for biasing the link in a first preferred orientation, and a mount that operates as a fulcrum to rotate the link into engagement with the DUT. The mount includes projections that extend below a bottom surface of the socket, such that engagement of the mount with the test device at the projections translates the mount parallel to a diagonal support wall in the socket such that the mount is driven away from the bottom surface of the socket and also toward the elastomer. The socket includes a gap above the mount to allow for movement of the mount within the socket, eliminating the fixed arrangement and the non-compliant loads that accompany the engagement of the mount to the test apparatus. The mount projections carry a small preload that ensures successful contact with the test equipment without the risk of damaging the test equipment with rigid contact surfaces.

IPC Classes  ?

  • H01R 12/71 - Coupling devices for rigid printing circuits or like structures
  • G01R 1/04 - HousingsSupporting membersArrangements of terminals
  • H01R 4/48 - Clamped connectionsSpring connections using a spring, clip or other resilient member
  • H01R 12/00 - Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocksCoupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structuresTerminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
  • H01R 13/00 - Details of coupling devices of the kinds covered by groups or
  • H01R 13/11 - Resilient sockets

26.

Link socket sliding mount with preload

      
Application Number 15341368
Grant Number 10101360
Status In Force
Filing Date 2016-11-02
First Publication Date 2018-05-03
Grant Date 2018-10-16
Owner Xcerra Corporation (USA)
Inventor
  • Magnuson, Aaron
  • Yakushev, Sergey
  • Treibergs, Valts
  • Sikorski, Dan

Abstract

A test socket with a link and mount system is used to couple a device under test to a testing apparatus for quick and reliable testing of microchips post-production. The socket includes a pivoting link that connects to the DUT, an elastomer for biasing the link in a first preferred orientation, and a mount that operates as a fulcrum to rotate the link into engagement with the DUT. The mount includes projections that extend below a bottom surface of the socket, such that engagement of the mount with the test device at the projections translates the mount parallel to a diagonal support wall in the socket such that the mount is driven away from the bottom surface of the socket and also toward the elastomer. The socket includes a gap above the mount to allow for movement of the mount within the socket, eliminating the fixed arrangement and the non-compliant loads that accompany the engagement of the mount to the test apparatus. The mount projections carry a small preload that ensures successful contact with the test equipment without the risk of damaging the test equipment with rigid contact surfaces.

IPC Classes  ?

  • G01R 1/04 - HousingsSupporting membersArrangements of terminals
  • G01R 31/26 - Testing of individual semiconductor devices
  • H01R 12/85 - Coupling devices connected with low or zero insertion force contact pressure producing means, contacts activated after insertion of printed circuits or like structures
  • H01R 9/05 - Connectors arranged to contact a plurality of the conductors of a multiconductor cable for coaxial cables

27.

Test socket assembly and related methods

      
Application Number 15809712
Grant Number 11088051
Status In Force
Filing Date 2017-11-10
First Publication Date 2018-04-05
Grant Date 2021-08-10
Owner XCERRA CORPORATION (USA)
Inventor
  • Treibergs, Valts
  • Nelson, Mitchell
  • Mroczkowski, Jason

Abstract

A socket assembly including a housing that has one or more spring probes therein. The socket assembly further includes a leadframe assembly that has one or more cantilever members, and the leadframe assembly has microwave structures and a flexible ground plane. The socket assembly further includes an elastomeric spacer adjacent the leadframe assembly, the elastomeric spacer having one or more holes receiving the spring probes therethrough.

IPC Classes  ?

28.

COMPACT TESTING SYSTEM

      
Application Number US2016055780
Publication Number 2018/063418
Status In Force
Filing Date 2016-10-06
Publication Date 2018-04-05
Owner XCERRA CORPORATION (USA)
Inventor
  • Brown, Benjamin
  • Poffenberger, Russel

Abstract

An automated test platform includes a CPU subsystem housed in an enclosure and configured to execute an automated test process. A test head is housed in the enclosure and is configured to apply one or more test signals to a device under test. A power supply is housed in the enclosure and is configured to provide electrical power to the CPU subsystem and the test head.

IPC Classes  ?

  • G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
  • G06F 9/00 - Arrangements for program control, e.g. control units
  • G06F 11/26 - Functional testing

29.

Testing system and method

      
Application Number 15703319
Grant Number 10379154
Status In Force
Filing Date 2017-09-13
First Publication Date 2018-03-22
Grant Date 2019-08-13
Owner Xcerra Corporation (USA)
Inventor
  • Brown, Benjamin
  • Rangwala, Niraj
  • Mcconnell, David
  • Massenn, Howard

Abstract

A method, computer program product, computing system, and an automated test platform for testing at least one device under test includes a test head configured to receive the at least one device under test. A processing system is configured to: provide a voltage signal having a plurality of voltages to the at least one device under test, and monitor a current flow into the at least one device under test during each of the plurality of voltages, thus generating a plurality of monitored current values that correspond to the plurality of voltages. The plurality of monitored current values are stored.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 1/073 - Multiple probes
  • G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
  • G01R 31/319 - Tester hardware, i.e. output processing circuits

30.

Testing system and method

      
Application Number 15703351
Grant Number 10444278
Status In Force
Filing Date 2017-09-13
First Publication Date 2018-03-22
Grant Date 2019-10-15
Owner Xcerra Corporation (USA)
Inventor
  • Brown, Benjamin
  • Rangwala, Niraj
  • Mcconnell, David
  • Ho, Peter
  • Maassen, Howard

Abstract

A method, computer program product, computing system, and an automated test platform for testing at least one device under test includes a test head configured to receive the at least one device under test. A processing system is configured to: provide a voltage signal having a plurality of voltages to the at least one device under test, monitor a current flow into the at least one device under test during each of the plurality of voltages, thus generating a plurality of monitored current values that correspond to the plurality of voltages, and determine if one or more of the plurality of monitored current values exceeds one or more of a plurality of current thresholds.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 1/073 - Multiple probes
  • G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
  • G01R 31/319 - Tester hardware, i.e. output processing circuits

31.

TESTING SYSTEM AND METHOD

      
Application Number US2017051275
Publication Number 2018/052938
Status In Force
Filing Date 2017-09-13
Publication Date 2018-03-22
Owner XCERRA CORPORATION (USA)
Inventor
  • Brown, Benjamin
  • Rangwala, Niraj
  • Mcconnell, David
  • Massenn, Howard

Abstract

A method, computer program product, computing system, and an automated test platform for testing at least one device under test includes a test head configured to receive the at least one device under test. A processing system is configured to: provide a voltage signal having a plurality of voltages to the at least one device under test, and monitor a current flow into the at least one device under test during each of the plurality of voltages, thus generating a plurality of monitored current values that correspond to the plurality of voltages. The plurality of monitored current values are stored.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 1/067 - Measuring probes
  • G01R 31/319 - Tester hardware, i.e. output processing circuits
  • G01R 35/00 - Testing or calibrating of apparatus covered by the other groups of this subclass
  • H01L 21/66 - Testing or measuring during manufacture or treatment

32.

TESTING SYSTEM AND METHOD

      
Application Number US2017051281
Publication Number 2018/052944
Status In Force
Filing Date 2017-09-13
Publication Date 2018-03-22
Owner XCERRA CORPORATION (USA)
Inventor
  • Brown, Benjamin
  • Rangwala, Niraj
  • Mcconnell, David
  • Massenn, Howard
  • Ho, Peter

Abstract

A method, computer program product, computing system, and an automated test platform for testing at least one device under test includes a test head configured to receive the at least one device under test. A processing system is configured to: provide a voltage signal having a plurality of voltages to the at least one device under test, monitor a current flow into the at least one device under test during each of the plurality of voltages, thus generating a plurality of monitored current values that correspond to the plurality of voltages, and determine if one or more of the plurality of monitored current values exceeds one or more of a plurality of current thresholds.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 1/067 - Measuring probes
  • G01R 31/319 - Tester hardware, i.e. output processing circuits
  • G01R 35/00 - Testing or calibrating of apparatus covered by the other groups of this subclass
  • H01L 21/66 - Testing or measuring during manufacture or treatment

33.

POSITIONING DEVICE FOR A PARALLEL TESTER FOR TESTING PRINTED CIRCUIT BOARDS AND PARALLEL TESTER FOR TESTING PRINTED CIRCUIT BOARDS

      
Application Number EP2016063989
Publication Number 2017/025230
Status In Force
Filing Date 2016-06-17
Publication Date 2017-02-16
Owner XCERRA CORP. (USA)
Inventor
  • Dehmel, Rüdiger
  • Kassbaum, Torsten

Abstract

The invention relates to a positioning device for a parallel tester (1), a parallel tester (1) and to a method for testing a printed circuit board. One aspect to the invention relates to fine adjusting a positioning device wherein the test adapter (14) can be secured to an inner holding part (28) of a holding device, and the inner holding part (28) can be moved in relation to the remaining positioning device. Exclusively one or more pivot joints and/or one or more air bearings and/or more magnetic bearings are provided as bearings.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

34.

INTEGRATED CIRCUIT (IC) TEST SOCKET WITH FARADAY CAGE BACKGROUND

      
Application Number US2015023839
Publication Number 2016/160009
Status In Force
Filing Date 2015-04-01
Publication Date 2016-10-06
Owner XCERRA CORPORATION (USA)
Inventor Landa, Victor

Abstract

An integrated circuit test socket includes a highly conductive compliant material that is cut and installed into the test socket. The conductive material draws electrical charge away from the test socket, leading to more accurate testing. The test socket base is grounded, and a ground current runs through the base and into conductive strips. The configuration forms an electromagnetic impulse shield, protecting the chip from electromagnetic interference. The compliance of the shield material allows the shield to be sealed when activated, ensuring that the electromagnetic impulse shield is complete around the semi-conductor chip.

IPC Classes  ?

  • G01R 1/02 - General constructional details
  • G01R 1/067 - Measuring probes
  • G01R 1/18 - Screening arrangements against electric or magnetic fields, e.g. against earth's field
  • H01L 21/66 - Testing or measuring during manufacture or treatment

35.

Automated test platform for testing short circuits

      
Application Number 14674479
Grant Number 09720032
Status In Force
Filing Date 2015-03-31
First Publication Date 2016-10-06
Grant Date 2017-08-01
Owner Xcerra Corporation (USA)
Inventor
  • Chen, Wai-Kong
  • Harris, David

Abstract

An automated test platform for testing a first device under test includes N voltage sources for providing N different voltages. A cross matrix switching system is coupled to the N voltage sources, the cross matrix switch being configured to provide the N different voltages to M discrete test points within the first device under test, wherein M is larger than N. An N voltage measuring system is coupled to the first device under test, the N voltage measuring system being configured to measure the voltage potential present on the M discrete test points.

IPC Classes  ?

  • G01R 31/26 - Testing of individual semiconductor devices
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 31/319 - Tester hardware, i.e. output processing circuits

36.

Integrated circuit chip tester with an anti-rotation link

      
Application Number 14310824
Grant Number 09425529
Status In Force
Filing Date 2014-06-20
First Publication Date 2015-12-24
Grant Date 2016-08-23
Owner XCERRA CORPORATION (USA)
Inventor Landa, Victor

Abstract

A socket for testing or connecting an integrated circuit is disclosed having a platform for receiving the integrated circuit and adapted to overlay a piece of test equipment or other board, the platform formed with an array of slots each locating a portion of a two-piece connector assembly. When the integrated circuit is seated on the platform, the two piece connector assemblies pivot so as to make contact between a contact pad on the IC and the board for establishing or evaluating signal transmission by the IC. The platform houses a resilient elongate elastomer that biases the connector assembly out of the platform to make contact with the board or test equipment. When the IC is placed on the platform, the bias of the resilient tubular member is overcome and an electrical connection is established across the connector assembly.

IPC Classes  ?

  • H01R 13/64 - Means for preventing, inhibiting or avoiding incorrect coupling
  • H01R 12/85 - Coupling devices connected with low or zero insertion force contact pressure producing means, contacts activated after insertion of printed circuits or like structures
  • H01R 12/70 - Coupling devices
  • H01R 13/22 - Contacts for co-operating by abutting

37.

Test socket assembly and related methods

      
Application Number 14743879
Grant Number 10037933
Status In Force
Filing Date 2015-06-18
First Publication Date 2015-12-24
Grant Date 2018-07-31
Owner Xcerra Corporation (USA)
Inventor
  • Treibergs, Valts
  • Nelson, Mitchell
  • Mroczkowski, Jason

Abstract

A socket assembly including a housing that has one or more spring probes therein. The socket assembly further includes a leadframe assembly that has one or more cantilever members, and the leadframe assembly has microwave structures and a flexible ground plane. The socket assembly further includes an elastomeric spacer adjacent the leadframe assembly, the elastomeric spacer having one or more holes receiving the spring probes therethrough.

IPC Classes  ?

  • G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • H01L 23/495 - Lead-frames
  • G01R 1/04 - HousingsSupporting membersArrangements of terminals
  • H05K 5/04 - Metal casings
  • H05K 7/10 - Plug-in assemblages of components

38.

INTEGRATED CIRCUIT CHIP TESTER WITH AN ANTI-ROTATION LINK

      
Application Number US2015027136
Publication Number 2015/195201
Status In Force
Filing Date 2015-04-22
Publication Date 2015-12-23
Owner XCERRA CORPORATION (USA)
Inventor Landa, Victor

Abstract

A socket for testing or connecting an integrated circuit is disclosed having a platform for receiving the integrated circuit and adapted to overlay a piece of test equipment or other board, the platform formed with an array of slots each locating a portion of a two-piece connector assembly. When the integrated circuit is seated on the platform, the two piece connector assemblies pivot so as to make contact between a contact pad on the IC and the board for establishing or evaluating signal transmission by the IC. The platform houses a resilient elongate elastomer that biases the connector assembly out of the platform to make contact with the board or test equipment. When the IC is placed on the platform, the bias of the resilient tubular member is overcome and an electrical connection is established across the connector assembly.

IPC Classes  ?

  • H01R 12/85 - Coupling devices connected with low or zero insertion force contact pressure producing means, contacts activated after insertion of printed circuits or like structures
  • H01R 12/87 - Coupling devices connected with low or zero insertion force contact pressure producing means, contacts activated after insertion of printed circuits or like structures acting automatically by insertion of rigid printed or like structures
  • H01R 13/15 - Pins, blades or sockets having separate spring member for producing or increasing contact pressure

39.

TEST SOCKET ASSEMBLY AND RELATED METHODS

      
Application Number US2015036513
Publication Number 2015/195970
Status In Force
Filing Date 2015-06-18
Publication Date 2015-12-23
Owner XCERRA CORPORATION (USA)
Inventor
  • Treibergs, Valts
  • Nelson, Mitchell
  • Mroczkowski, Jason

Abstract

A socket assembly including a housing that has one or more spring probes therein. The socket assembly further includes a leadframe assembly that has one or more cantilever members, and the leadframe assembly has microwave structures and a flexible ground plane. The socket assembly further includes an elastomeric spacer adjacent the leadframe assembly, the elastomeric spacer having one or more holes receiving the spring probes therethrough.

IPC Classes  ?

  • G01R 1/04 - HousingsSupporting membersArrangements of terminals

40.

DEBUGGING SYSTEM AND METHOD

      
Application Number US2015028793
Publication Number 2015/168551
Status In Force
Filing Date 2015-05-01
Publication Date 2015-11-05
Owner XCERRA CORPORATION (USA)
Inventor
  • Petrov, Todor K.
  • Harrison, Ian

Abstract

A debugging system for debugging an automated test process used on an automated test platform. The debugging system includes a debugging subsystem and a debugging coupler electrically coupled to the debugging subsystem. The debugging coupler is configured to be releasably electrically coupleable to a test head of the automated test platform.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

41.

ACCORDION

      
Application Number 014718977
Status Registered
Filing Date 2015-10-23
Registration Date 2016-02-23
Owner Xcerra Corporation (USA)
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

Electrical connectors, contacts and test probes. Design of electrical connectors, contacts and test probes to customer specifications.

42.

INTEGRATED CIRCUIT (IC) TEST SOCKET USING KELVIN BRIDGE

      
Application Number US2015017380
Publication Number 2015/130708
Status In Force
Filing Date 2015-02-24
Publication Date 2015-09-03
Owner XCERRA CORPORATION (USA)
Inventor
  • Tiengtum, Pongsak
  • Landa, Victor

Abstract

An integrated circuit test socket is adapted to use with Kelvin connectors by creating closely spaced connectors and counter-rotating links that are nested to conserve space. The connectors are shaped to make contact with a chip and communicate force and sense signals to a tester, allowing a measure of the chip's actual resistance.

IPC Classes  ?

  • G01R 1/04 - HousingsSupporting membersArrangements of terminals
  • H01R 13/24 - Contacts for co-operating by abutting resilientContacts for co-operating by abutting resiliently mounted
  • H01L 21/66 - Testing or measuring during manufacture or treatment

43.

Test probe assembly and related methods

      
Application Number 14394252
Grant Number 09829506
Status In Force
Filing Date 2013-03-14
First Publication Date 2015-03-12
Grant Date 2017-11-28
Owner Xcerra Corporation (USA)
Inventor
  • Treibergs, Valts
  • Magnuson, Aaron
  • Yakushev, Sergey
  • Hanson, Scott

Abstract

A test probe assembly includes a first elongate electrically conductive plunger that extends from a proximal first plunger end to a distal first plunger end, and is defined in part by a central longitudinal axis. The first plunger has a first spring latch at the distal first plunger end. At least a portion of the first plunger has an arc with a first plunger outer contact point opposite the first spring latch relative to the longitudinal axis. The first plunger is disposed in a spring. The first plunger outer contact point in contact with the inner diameter of the spring, and the first spring latch engages at least a portion of the spring. A method includes disposing a first plunger within a spring along a spring longitudinal axis, disposing a second probe within the spring along the spring longitudinal axis, and engaging the spring latch and the second plunger spring latch with the spring, for instance by capturing an end coil of the spring with the spring latch of at least one of the spring latch or the second plunger spring latch.

IPC Classes  ?

  • G01R 1/067 - Measuring probes
  • G01R 1/04 - HousingsSupporting membersArrangements of terminals
  • G01R 3/00 - Apparatus or processes specially adapted for the manufacture of measuring instruments

44.

Wiring board for testing loaded printed circuit board

      
Application Number 14529033
Grant Number 09753058
Status In Force
Filing Date 2014-10-30
First Publication Date 2015-02-26
Grant Date 2017-09-05
Owner Xcerra Corporation (USA)
Inventor
  • Swart, Mark A.
  • Snyder, Kenneth R.
  • Koolis, Stephen J.
  • Tackett, Douglas W.

Abstract

A wiring board for transmission of test signals between test point locations on a circuit board under test and an external analyzer having compliant contacts making electrical contact with a pad positioned on a conductive surface circuit layer having a trace extending to a second pad having a hole for receipt of an interface pin having a swaged head electrically connected to the external analyzer.

IPC Classes  ?

  • G01R 31/20 - Preparation of articles or specimens to facilitate testing
  • G01R 1/073 - Multiple probes
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 31/319 - Tester hardware, i.e. output processing circuits

45.

Distortion measurement and correction system and method

      
Application Number 14452949
Grant Number 09152747
Status In Force
Filing Date 2014-08-06
First Publication Date 2015-02-12
Grant Date 2015-10-06
Owner Xcerra Corporation (USA)
Inventor Liggiero, Richard

Abstract

∘. The magnitude and phase of the distortion component of the first source may be determined based upon, at least in part, the first and second differential residual signal.

IPC Classes  ?

  • G01R 13/00 - Arrangements for displaying electric variables or waveforms
  • G06F 17/50 - Computer-aided design
  • G01R 27/28 - Measuring attenuation, gain, phase shift, or derived characteristics of electric four-pole networks, i.e. two-port networksMeasuring transient response
  • H03H 7/065 - Parallel T-filters
  • H03H 11/12 - Frequency selective two-port networks using amplifiers with feedback
  • H03M 1/00 - Analogue/digital conversionDigital/analogue conversion
  • H03H 11/04 - Frequency selective two-port networks
  • H03H 11/32 - Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns
  • H03H 7/01 - Frequency selective two-port networks

46.

Cross-bar unit for a test apparatus for circuit boards, and test apparatus containing the former

      
Application Number 14209646
Grant Number 09989583
Status In Force
Filing Date 2014-03-13
First Publication Date 2014-09-18
Grant Date 2018-06-05
Owner Xcerra Corporation (USA)
Inventor
  • Romanov, Victor
  • Ott, Bernd-Ulrich

Abstract

A cross-bar unit for a test apparatus for circuit boards having at least one cross-bar spanning a test field in which a circuit board to be tested may be placed, and is configured to hold positioning units for test fingers in a linearly traversable manner so that the test fingers are able to scan at least part of the test field. The cross-bar unit is configured to hold at least two linear guides, independent of one another, for guiding in each case at least one of the positioning units.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

47.

CROSSMEMBER UNIT FOR A TEST APPARATUS FOR PRINTED CIRCUIT BOARDS, AND TEST APPARATUS HAVING SAID CROSSMEMBER UNIT

      
Application Number EP2014054727
Publication Number 2014/140029
Status In Force
Filing Date 2014-03-11
Publication Date 2014-09-18
Owner XCERRA CORP. (USA)
Inventor
  • Romanov, Victor
  • Ott, Bernd-Ulrich

Abstract

The invention relates to a crossmember unit (2) for a test apparatus (1) for printed circuit boards, wherein the crossmember unit (2) has at least one crossmember (9), which spans a test area in which a printed circuit board to be tested can be arranged, and is designed to receive positioning units (6) for test fingers (8) in a linearly movable manner in such a way that the test fingers (8) can scan at least a portion of the test area. According to the invention, the crossmember unit (2) is designed to receive at least two linear guides (5), which are independent of one another, for guiding in each case at least one of the positioning units (6). The invention is also directed to a test apparatus (1) having at least one crossmember unit (2) of this kind.

IPC Classes  ?

48.

Socket mount

      
Application Number 14136931
Grant Number 08998621
Status In Force
Filing Date 2013-12-20
First Publication Date 2014-08-21
Grant Date 2015-04-07
Owner XCERRA CORPORATION (USA)
Inventor
  • Landa, Victor
  • Tiengtum, Pongsak
  • Mashayekh, Dan

Abstract

A socket mount for use in connection with an integrated circuit test socket having a body with fastener holes, a plurality of electrical connector links, and a plurality of elastomer elements biasing said links, the socket mount comprising a block having a flat upper surface, a flat lower surface, and four flat edges defining a square, and respective fastener holes aligned with the fastener holes in the test socket, a first groove oriented perpendicularly with respect to a flat edge along the flat lower surface, and a second groove oriented diagonally from a first edge to a second edge along the flat lower surface, the grooves having a length equal to a length of elastomer in the test socket.

IPC Classes  ?

  • H01R 12/00 - Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocksCoupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structuresTerminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
  • H01L 23/32 - Holders for supporting the complete device in operation, i.e. detachable fixtures
  • G01R 1/04 - HousingsSupporting membersArrangements of terminals
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01R 12/71 - Coupling devices for rigid printing circuits or like structures

49.

Automated test platform utilizing segmented data sequencers to provide time controlled test sequences to device under test

      
Application Number 13749199
Grant Number 09459978
Status In Force
Filing Date 2013-01-24
First Publication Date 2014-07-24
Grant Date 2016-10-04
Owner Xcerra Corporation (USA)
Inventor
  • Fritzsche, William A.
  • Jula, James Michael
  • Alton, Timothy
  • Poffenberger, Russell Elliott
  • Amy, Michael E.

Abstract

A segmented subsystem, for use within an automated test platform, includes a first subsystem segment including a first data sequencer configured to coordinate the execution of one or more instructions within the first subsystem segment. A second subsystem segment includes a second data sequencer configured to coordinate the execution of one or more instructions within the second subsystem segment.

IPC Classes  ?

  • G06F 11/273 - Tester hardware, i.e. output processing circuits
  • G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

50.

Scalable test platform

      
Application Number 13749332
Grant Number 09336108
Status In Force
Filing Date 2013-01-24
First Publication Date 2014-07-24
Grant Date 2016-05-10
Owner Xcerra Corporation (USA)
Inventor
  • Fritzsche, William A.
  • Currin, Jeffery D.
  • Poffenberger, Russell Elliott
  • Alton, Timothy
  • Davis, Michael Gordon

Abstract

A method, computer program product, and computing system for, upon the occurrence of a computer-related event, comparing code utilized by one or more subsystems included within a scalable test platform to code available from a remote location. If the code available from the remote location is newer than the code utilized by one or more subsystems, the code available from the remote location is obtained, thus defining newer code. The code utilized by one or more subsystems is updated with the newer code.

IPC Classes  ?

  • G06F 11/263 - Generation of test inputs, e.g. test vectors, patterns or sequences
  • G06F 11/36 - Prevention of errors by analysis, debugging or testing of software
  • G06F 9/44 - Arrangements for executing specific programs
  • G06F 9/445 - Program loading or initiating
  • G07C 3/00 - Registering or indicating the condition or the working of machines or other apparatus, other than vehicles
  • G07C 3/08 - Registering or indicating the production of the machine either with or without registering working or idle time

51.

Automated test platform utilizing status register polling with temporal ID

      
Application Number 13749641
Grant Number 09213616
Status In Force
Filing Date 2013-01-24
First Publication Date 2014-07-24
Grant Date 2015-12-15
Owner XCerra Corporation (USA)
Inventor
  • Fritzsche, William A.
  • Poffenberger, Russell Elliott
  • Petrov, Todor K.
  • Amy, Michael E.

Abstract

A segmented subsystem, for use within an automated test platform, includes a first subsystem segment configured to execute one or more instructions within the first subsystem segment. A second subsystem segment is configured to execute one or more instructions within the second subsystem segment. The first subsystem segment includes: a first functionality, a second functionality, and a status polling engine. The status polling engine is configured to: determine a first status for the first functionality and a second status for the second functionality, and generate a consolidated status indicator for the first subsystem segment based, at least in part, upon the first status for the first functionality and the second status for the second functionality.

IPC Classes  ?

  • G06F 11/27 - Built-in tests
  • G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
  • G06F 11/273 - Tester hardware, i.e. output processing circuits
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

52.

Connector / cable assembly

      
Application Number 13749155
Grant Number 09297830
Status In Force
Filing Date 2013-01-24
First Publication Date 2014-07-24
Grant Date 2016-03-29
Owner Xcerra Corporation (USA)
Inventor
  • Mccarthy, Richard
  • Hannaford, Christopher Joel
  • Zarzalejo, Lisette J.
  • Therrien, Roger H.

Abstract

A high voltage connector assembly includes a plurality of pin assemblies, each of the plurality of pin assemblies having a first end and a second end. The first end of each of the plurality of pin assemblies is configured to releasably electrically engage a load board. A plurality of pin pads, wherein the second end of each of the plurality of pin assemblies is configured to electrically engage a pin pad included within the plurality of pin pads. A plurality of connector pads are electrically coupled to the plurality of pin pads, wherein each of the plurality of connector pads is configured to be electrically coupled to a wire-based conductor included within a plurality of wire-based conductors. A potting compound is configured to encapsulate the plurality of connector pads.

IPC Classes  ?

  • G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R 1/04 - HousingsSupporting membersArrangements of terminals
  • H01R 13/24 - Contacts for co-operating by abutting resilientContacts for co-operating by abutting resiliently mounted
  • G01R 1/067 - Measuring probes
  • H01R 12/71 - Coupling devices for rigid printing circuits or like structures
  • H01R 12/73 - Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures connecting to other rigid printed circuits or like structures

53.

Scalable test platform in a PCI express environment with direct memory access

      
Application Number 13749260
Grant Number 09430348
Status In Force
Filing Date 2013-01-24
First Publication Date 2014-07-24
Grant Date 2016-08-30
Owner Xcerra Corporation (USA)
Inventor
  • Fritzsche, William A.
  • Currin, Jeffery D.
  • Poffenberger, Russell Elliott
  • Alton, Timothy
  • Davis, Michael Gordon

Abstract

A scalable test platform includes a PCIe-based event fabric. One or more CPU subsystems are coupled to the PCIe-based event fabric and configured to execute an automated test process. One or more instrument subsystems are coupled to the PCIe-based event fabric and configured to interface one or more devices under test.

IPC Classes  ?

  • G06F 11/273 - Tester hardware, i.e. output processing circuits
  • G06F 11/263 - Generation of test inputs, e.g. test vectors, patterns or sequences
  • G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

54.

Scalable test platform in a PCI express environment with direct memory access

      
Application Number 13749308
Grant Number 09430349
Status In Force
Filing Date 2013-01-24
First Publication Date 2014-07-24
Grant Date 2016-08-30
Owner Xcerra Corporation (USA)
Inventor
  • Fritzsche, William A.
  • Currin, Jeffery D.
  • Poffenberger, Russell Elliott
  • Alton, Timothy
  • Davis, Michael Gordon

Abstract

A scalable test platform includes a PCIe-based event fabric. One or more instrument subsystems are coupled to the PCIe-based event fabric and configured to interface one or more devices under test and generate captured test data. One or more digital signal processing subsystems are coupled to the PCIe-based event fabric and configured to process the captured test data.

IPC Classes  ?

  • G06F 11/273 - Tester hardware, i.e. output processing circuits
  • G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

55.

Media tagging

      
Application Number 14115120
Grant Number 09521175
Status In Force
Filing Date 2012-10-05
First Publication Date 2014-03-27
Grant Date 2016-12-13
Owner XCERRA CORPORATION (USA)
Inventor Rogers, Henk B.

Abstract

Tagging techniques use user interface features such as face icons that can be manipulated by a variety of cursors to tag media items including but not limited to photos. Tagged items can be presented automatically in response to establishing network communications between two devices.

IPC Classes  ?

  • G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
  • H04L 29/06 - Communication control; Communication processing characterised by a protocol
  • G10L 15/00 - Speech recognition
  • G06F 17/30 - Information retrieval; Database structures therefor

56.

Multi-domain execution of tests on electronic devices

      
Application Number 11520202
Grant Number 08649993
Status In Force
Filing Date 2006-09-12
First Publication Date 2014-02-11
Grant Date 2014-02-11
Owner XCERRA CORPORATION (USA)
Inventor Gilet, Lionel

Abstract

A device under test is divided into multiple test domains, and test conditions for each of the multiple test domains are defined separately, so that each test domain has its own test pattern, timing data, and other test conditions. Each test domain can start and stop independently, and run at different speeds. Further, triggers are used to specify how the tests executed in the different test domains interact and communicate with one another. Any test domain can generate or wait for a trigger from any other test domain. A test domain can wait for a trigger from a test domain in a CPU.

IPC Classes  ?

  • G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R 31/14 - Circuits therefor

57.

Spring contact assembly

      
Application Number 13546980
Grant Number 08523579
Status In Force
Filing Date 2012-07-11
First Publication Date 2012-11-08
Grant Date 2013-09-03
Owner XCERRA CORPORATION (USA)
Inventor
  • Johnston, Charles J.
  • Chabineau, Scott
  • Treibergs, Valts
  • Yakushev, Sergey
  • Swart, Mark
  • Kottmeyer, Edward A.

Abstract

A spring contact assembly having a first plunger with a tail portion having a flat contact surface and a second plunger having a tail portion with a flat contact surface wherein the flat contact surfaces are overlapping and are surrounded by an external compression spring such that the sliding engagement of the flat surfaces increases during compression of the spring.

IPC Classes  ?

  • H01R 13/24 - Contacts for co-operating by abutting resilientContacts for co-operating by abutting resiliently mounted

58.

Integrated circuit socket connector

      
Application Number 29366291
Grant Number D0668625
Status In Force
Filing Date 2010-07-22
First Publication Date 2012-10-09
Grant Date 2012-10-09
Owner XCERRA CORPORATION (USA)
Inventor Tiengtum, Pongsak

59.

Method and apparatus for identifying and reducing spurious frequency components

      
Application Number 13090560
Grant Number 08415941
Status In Force
Filing Date 2011-04-20
First Publication Date 2011-08-11
Grant Date 2013-04-09
Owner XCERRA CORPORATION (USA)
Inventor
  • Max, Solomon
  • Hannaford, Christopher Joel
  • Necoechea, R. Warren

Abstract

A method for identifying and reducing spurious frequency components is provided. A method in accordance with at least one embodiment of the present disclosure may include generating a digital sinusoidal waveform at a direct digital synthesizer (DDS) and receiving the digital sinusoidal waveform at an audio digital-to-analog converter. The method may further include converting the digital sinusoidal waveform to an analog sinusoidal waveform containing spurious frequency components, combining the analog sinusoidal waveform with an analog distortion correction waveform to generate a composite output waveform and receiving the composite output waveform at notch filter circuitry. The method may also include filtering the composite output waveform to generate a filtered composite output waveform and amplifying a difference between the filtered composite output waveform and a signal from a circuit-under-test (CUT) to generate an amplified analog signal. The method may also include converting the amplified analog signal to an amplified digital signal. Of course, additional implementations are also within the scope of the present disclosure.

IPC Classes  ?

  • G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof

60.

Wiring board for testing loaded printed circuit board

      
Application Number 12959765
Grant Number 08907694
Status In Force
Filing Date 2010-12-03
First Publication Date 2011-06-23
Grant Date 2014-12-09
Owner Xcerra Corporation (USA)
Inventor
  • Swart, Mark A.
  • Snyder, Kenneth R.

Abstract

A wiring board for transmission of test signals between test point locations on a circuit board under test and an external analyzer having compliant contacts making electrical contact with a pad positioned on a conductive surface circuit layer having a trace extending to a second pad having a hole for receipt of an interface pin electrically connected to the external analyzer.

IPC Classes  ?

  • G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 31/319 - Tester hardware, i.e. output processing circuits

61.

Loaded printed circuit board test fixture and method for manufacturing the same

      
Application Number 12963322
Grant Number 08648616
Status In Force
Filing Date 2010-12-08
First Publication Date 2011-06-23
Grant Date 2014-02-11
Owner XCERRA CORPORATION (USA)
Inventor
  • St. Onge, Gary F.
  • Gold, Scott F.
  • Miczek, Matthew T.

Abstract

A test fixture for testing loaded printed circuit boards having a plurality of test points having a probe plate including an array of widely spaced high force spring test probes in compliant contact with solid translator pins located in a translator fixture removably positioned over the probe plate. The test fixture includes optimization software wherein translation of the test signals are optimized by providing the shortest interconnect distance in the x-y plane between the test points on the printed circuit board and the test probes in the probe plate. The fixture further includes an unpowered opens device for testing components on the loaded printed circuit board.

IPC Classes  ?

62.

Integrated circuit socket with a two-piece connector with a rocker arm

      
Application Number 12841866
Grant Number 07918669
Status In Force
Filing Date 2010-07-22
First Publication Date 2011-04-05
Grant Date 2011-04-05
Owner XCERRA CORPORATION (USA)
Inventor Tiengtum, Pongsak

Abstract

A socket for testing or connecting an integrated circuit is disclosed having a platform for receiving the integrated circuit and adapted to overlay a piece of test equipment or other board, the platform formed with an array of slots each locating a portion of a two-piece connector assembly. When the integrated circuit is seated on the platform, the two piece connector assemblies pivot so as to make contact between a contact pad on the IC and the board for establishing or evaluating signal transmission by the IC. The platform houses a resilient tubular member that biases the connector assembly in a disengaged position out of contact with the board or test equipment. When the IC is placed on the platform, the bias of the resilient tubular member is overcome and an electrical connection is established across the connector assembly.

IPC Classes  ?

  • H01R 12/00 - Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocksCoupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structuresTerminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
  • G01R 31/02 - Testing of electric apparatus, lines, or components for short-circuits, discontinuities, leakage, or incorrect line connection

63.

Spring contact assembly

      
Application Number 12912683
Grant Number 08231416
Status In Force
Filing Date 2010-10-26
First Publication Date 2011-02-17
Grant Date 2012-07-31
Owner XCERRA CORPORATION (USA)
Inventor
  • Johnston, Charles J.
  • Chabineau, Scott
  • Treibergs, Valts
  • Yakushev, Sergey
  • Swart, Mark
  • Kottmeyer, Edward A.

Abstract

A spring contact assembly having a first plunger with a tail portion having a flat contact surface and a second plunger having a tail portion with a flat contact surface wherein the flat contact surfaces are overlapping and are surrounded by an external compression spring such that the sliding engagement of the flat surfaces increases during compression of the spring.

IPC Classes  ?

  • H01R 13/24 - Contacts for co-operating by abutting resilientContacts for co-operating by abutting resiliently mounted

64.

Device and method for aligning and holding a plurality of singulated semiconductor components in receiving pockets of a terminal carrier

      
Application Number 12887429
Grant Number 08678365
Status In Force
Filing Date 2010-09-21
First Publication Date 2011-01-13
Grant Date 2014-03-25
Owner XCERRA CORPORATION (USA)
Inventor
  • Hofmann, Thomas
  • Schaule, Max

Abstract

In a device and a method for aligning and holding a plurality of singulated semi-conductor components in receiving pockets of a terminal carrier that are separated from each other, the terminal carrier has spring elements, which are part of a spring plate. The spring plate has a plurality of recesses disposed next to each other for forming a corresponding plurality of receiving pockets for the semi-conductor components, wherein the spring elements are formed from the spring plate in one piece.

IPC Classes  ?

  • B23Q 3/00 - Devices holding, supporting, or positioning, work or tools, of a kind normally removable from the machine

65.

Contact base

      
Application Number 12742888
Grant Number 08282428
Status In Force
Filing Date 2009-06-12
First Publication Date 2010-12-09
Grant Date 2012-10-09
Owner XCERRA CORPORATION (USA)
Inventor Gschwendtberger, Gerhard

Abstract

In a contact base with a plurality of contact springs for making contact with electronic components, in particular ICs, the contact springs each have an elongate contact blade, the longitudinal center plane of said contact blade being situated parallel to the bending plane of the spring arm of the contact spring. Furthermore, the spring arm is formed in such a way that, when a pin is pressed, the contact blade moves in a direction which differs from the feed direction of the component in such a way that the contact blade moves along the pin.

IPC Classes  ?

  • H01R 4/48 - Clamped connectionsSpring connections using a spring, clip or other resilient member

66.

Testing a transceiver

      
Application Number 11546806
Grant Number 07849374
Status In Force
Filing Date 2006-10-11
First Publication Date 2010-12-07
Grant Date 2010-12-07
Owner XCERRA CORPORATION (USA)
Inventor
  • Necoechea, R. Warren
  • Burnett, Timothy
  • Zhang, Fengming
  • Hou, Harry

Abstract

A filter includes at least a pin diode, an inductive element, and a varactor diode coupled as a resonant circuit. The filter injects data dependent jitter into a digital data signal with a given data rate for testing a transceiver.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

67.

Scrub inducing compliant electrical contact

      
Application Number 12629790
Grant Number 08324919
Status In Force
Filing Date 2009-12-02
First Publication Date 2010-09-30
Grant Date 2012-12-04
Owner XCERRA CORPORATION (USA)
Inventor
  • Chabineau-Lovgren, Scott
  • Sargeant, Steve B.
  • Swart, Mark A.

Abstract

The contact assembly having a contact member with a contact tip positioned within holes in a test socket or probe plate wherein the contact tip or the hole in the probe plate or test socket has a cam surface to provide lateral movement of the contact tip across a surface of a test location during compression of the contact member to induce scrubbing on the surface of the test site.

IPC Classes  ?

  • G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere

68.

Test systems and methods for integrated circuit devices

      
Application Number 10840851
Grant Number 07765443
Status In Force
Filing Date 2004-05-07
First Publication Date 2010-07-27
Grant Date 2010-07-27
Owner XCERRA CORPORATION (USA)
Inventor
  • Syed, Ahmed Rashid
  • West, Burnell G.

Abstract

One embodiment of the invention is a portion of a test system that includes a timing generation circuit and a formatter that are coupled together, which are on a single CMOS (complementary metal oxide semiconductor) integrated circuit. The timing Generation circuit generates software words. The formatter receives the software words and provides a specified number of transitions per second and a specified edge placement resolution and accuracy. It is noted that the formatter includes a drive circuit and a response circuit. Specifically, the drive circuit includes a plurality of slices, where each slice receives an independent data stream and produces an independent formatted level. The response circuit includes a plurality of slices, where each slice receives an independent data stream and produces an independent strobe marker.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

69.

System and method for thermal limit control

      
Application Number 12341162
Grant Number 07969177
Status In Force
Filing Date 2008-12-22
First Publication Date 2010-06-24
Grant Date 2011-06-28
Owner XCERRA CORPORATION (USA)
Inventor
  • Perkins, Philip Earle
  • Limoges, Jr., Stephen Frederick
  • Yan, Xiaomin
  • Mcginley, James William
  • Therrien, Roger Henry

Abstract

This disclosure relates to a system and method for pulse generation. A system in accordance with the present disclosure may include a power dissipating element configured to receive power from a power source. At least one of the power source and the power dissipating element may be configured to generate a first signal. The system may further include a measuring instrument in communication with the power source. The measuring instrument may be configured to measure the first signal and to provide an input corresponding to a measured signal to a duty cycle limiter. The system may also include a pulse controller operatively connected to the power source. The pulse controller may be configured to control a duty cycle of the first signal and to receive a second signal from the duty cycle limiter. The pulse controller may be configured to disable at least one of the power source and the power dissipating element if the duty cycle limiter has determined that a maximum condition has been exceeded. Other embodiments are also within the scope of the present disclosure.

IPC Classes  ?

  • G01R 31/26 - Testing of individual semiconductor devices

70.

Loadboard enhancements for automated test equipment

      
Application Number 11824333
Grant Number 07615990
Status In Force
Filing Date 2007-06-28
First Publication Date 2009-11-10
Grant Date 2009-11-10
Owner XCERRA CORPORATION (USA)
Inventor Shimanouchi, Masashi

Abstract

An enhanced loadboard and method for enhanced automated test equipment (ATE) signaling. More specifically, embodiments provide an effective mechanism for reducing signal degradation and error interjection by replacing one or more relays with signal splitters for directing signals between one or more pins of a coupled ATE instrument, where the signal splitters reduce loadboard size and operating cost.

IPC Classes  ?

  • G01R 31/02 - Testing of electric apparatus, lines, or components for short-circuits, discontinuities, leakage, or incorrect line connection

71.

Spring contact assembly

      
Application Number 12206659
Grant Number 07862391
Status In Force
Filing Date 2008-09-08
First Publication Date 2009-03-19
Grant Date 2011-01-04
Owner XCERRA CORPORATION (USA)
Inventor
  • Johnston, Charles J.
  • Chabineau, Scott
  • Treibergs, Valts
  • Yakushev, Sergey
  • Swart, Mark
  • Kottmeyer, Edward A.

Abstract

A spring contact assembly having a first plunger with a tail portion having a flat contact surface and a second plunger having a tail portion with a flat contact surface wherein the flat contact surfaces are overlapping and are surrounded by an external compression spring such that the sliding engagement of the flat surfaces increases during compression of the spring.

IPC Classes  ?

  • H01R 13/24 - Contacts for co-operating by abutting resilientContacts for co-operating by abutting resiliently mounted

72.

System, method, and apparatus for distortion analysis

      
Application Number 12170334
Grant Number 08239434
Status In Force
Filing Date 2008-07-09
First Publication Date 2009-03-05
Grant Date 2012-08-07
Owner XCERRA CORPORATION (USA)
Inventor
  • Max, Solomon
  • Hannaford, Christopher Joel

Abstract

A system, method, and apparatus for distortion analysis is provided. A method in accordance with at least one embodiment of the present disclosure may include receiving a clock frequency at a direct digital synthesizer (DDS) and generating at least one stream of phase numbers via said DDS. The method may further include generating a digital sine wave using, at least in part, said clock frequency and said at least one stream of phase numbers. Of course, additional implementations are also within the scope of the present disclosure.

IPC Classes  ?

73.

System and method for distortion analysis

      
Application Number 12118217
Grant Number 07957924
Status In Force
Filing Date 2008-05-09
First Publication Date 2009-02-12
Grant Date 2011-06-07
Owner XCERRA CORPORATION (USA)
Inventor
  • Liggiero, Iii, Richard
  • Reiss, Alan J.

Abstract

A method, circuit, and computer program product for receiving a first intermediate signal that is at least partially based upon a first reference signal. A second intermediate signal is received that is a time-shifted version of the first intermediate signal. An output signal is generated that is based upon the difference between the first intermediate signal and the second intermediate signal. An anticipated differential change in the output signal is determined, the anticipated differential change to occur based upon a transition in the first reference signal. A realized differential change in the output signal is measured, the realized differential change occurring based upon a transition in the first reference signal. The realized differential change in the output signal is compared to the anticipated differential change in the output signal to determine a nonlinearity indicator.

IPC Classes  ?

  • G01R 29/00 - Arrangements for measuring or indicating electric quantities not covered by groups
  • G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

74.

Method and apparatus for identifying and reducing spurious frequency components

      
Application Number 12170401
Grant Number 08269480
Status In Force
Filing Date 2008-07-09
First Publication Date 2009-02-05
Grant Date 2012-09-18
Owner XCERRA CORPORATION (USA)
Inventor
  • Max, Solomon
  • Hannaford, Christopher Joel
  • Necoechea, R. Warren

Abstract

A method for identifying and reducing spurious frequency components is provided. A method in accordance with at least one embodiment of the present disclosure may include generating a digital sinusoidal waveform at a direct digital synthesizer (DDS) and receiving the digital sinusoidal waveform at an audio digital-to-analog converter. The method may further include converting the digital sinusoidal waveform to an analog sinusoidal waveform containing spurious frequency components, combining the analog sinusoidal waveform with an analog distortion correction waveform to generate a composite output waveform and receiving the composite output waveform at notch filter circuitry. The method may also include filtering the composite output waveform to generate a filtered composite output waveform and amplifying a difference between the filtered composite output waveform and a signal from a circuit-under-test (CUT) to generate an amplified analog signal. The method may also include converting the amplified analog signal to an amplified digital signal. Of course, additional implementations are also within the scope of the present disclosure.

IPC Classes  ?

  • G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof

75.

System and method for distortion analysis

      
Application Number 11774774
Grant Number 07919968
Status In Force
Filing Date 2007-07-09
First Publication Date 2009-01-15
Grant Date 2011-04-05
Owner XCERRA CORPORATION (USA)
Inventor Max, Solomon

Abstract

A method, circuit and system for determining at least one of an amplitude and a relative phase of a signal under test. A reference signal is generated based, at least in part, upon the at least one of the amplitude and the relative phase of the signal under test. The reference signal is combined with the signal under test to generate a residual signal indicative of a distortion within the signal under test. The residual signal is measured.

IPC Classes  ?

  • G01R 23/20 - Measurement of non-linear distortion

76.

Finger tester for testing unpopulated printed circuit boards and method for testing unpopulated printed circuit boards using a finger tester

      
Application Number 12097824
Grant Number 07859281
Status In Force
Filing Date 2006-11-15
First Publication Date 2008-11-06
Grant Date 2010-12-28
Owner XCERRA CORPORATION (USA)
Inventor Romanov, Victor

Abstract

A finger tester for testing non-componented printed circuit boards uses two or more test fingers, each having a test probe. A detection device is provided above each test probe for optical detection of the position above the circuit board of at least one contact tip of the test probe. The detection devices of the test fingers are each arranged in different vertically spaced planes, so that areas of the detection devices located above the test fingers are positioned above one another, aligned vertically to prevent contact during testing.

IPC Classes  ?

  • G01R 31/02 - Testing of electric apparatus, lines, or components for short-circuits, discontinuities, leakage, or incorrect line connection

77.

High speed, out-of-band differential pin driver

      
Application Number 11477971
Grant Number 07372302
Status In Force
Filing Date 2006-06-28
First Publication Date 2008-05-13
Grant Date 2008-05-13
Owner XCERRA CORPORATION (USA)
Inventor
  • Ohshima, Atsushi
  • Nomura, Toshihiro
  • Maassen, Howard

Abstract

A driver block for a differential pin driver that supports out-of-band signaling. The driver block includes a main enable switch that is controlled by a high speed driver inhibit (DINH) signal. The main enable switch controls coupling between a main current source and a differential pin driver output stage. The main enable switch is coupled in series with an output select switch that selects between a positive output and a negative output. The driver block also includes a positive enable switch for controlling coupling between the positive output and a positive level shifter that shifts voltages of the positive output. The driver block also includes a negative enable switch for controlling coupling between the negative output and a negative level shifter that shifts voltages of the negative output.

IPC Classes  ?

  • H03K 19/0175 - Coupling arrangementsInterface arrangements

78.

D-optimized switching converter

      
Application Number 11437777
Grant Number 07430130
Status In Force
Filing Date 2006-05-18
First Publication Date 2007-11-22
Grant Date 2008-09-30
Owner XCERRA CORPORATION (USA)
Inventor Devey, William

Abstract

1 remains as close a possible to a value for which circuit performance is substantially optimal with respect to a selected combination of performance criteria.

IPC Classes  ?

  • H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only

79.

Semiconductor integrated circuit tester with interchangeable tester module

      
Application Number 11258529
Grant Number 07307440
Status In Force
Filing Date 2005-10-25
First Publication Date 2007-04-26
Grant Date 2007-12-11
Owner XCERRA CORPORATION (USA)
Inventor
  • Miller, Wayne H.
  • Ramos, Carlos R.
  • Young, Peter S.

Abstract

A test head for an integrated circuit tester includes a main chassis defining a chamber that is open at the top. Tester modules are installed in the chamber, each tester module being removable as a unit from the chamber and including a tester module chassis, multiple pin electronics cards, and a tester module interface structure exposed at the top of the chamber. A test head interface structure is engageable with the tester module interface structures of the tester modules for connecting the tester module interface structures to a device interface unit.

IPC Classes  ?

  • G01R 31/02 - Testing of electric apparatus, lines, or components for short-circuits, discontinuities, leakage, or incorrect line connection

80.

Electrical contact probe with compliant internal interconnect

      
Application Number 11450231
Grant Number 07256593
Status In Force
Filing Date 2006-06-08
First Publication Date 2006-12-14
Grant Date 2007-08-14
Owner XCERRA CORPORATION (USA)
Inventor Treibergs, Valts

Abstract

A compliant electrical interconnect having a first component and a second component interlockingly engaged with the first component. Each component has two cantilever arms lockingly engaged and continuously biased against each other. Contact springs are captivated by the cantilever arms providing a contact force for the first and second components.

IPC Classes  ?

  • G01R 31/02 - Testing of electric apparatus, lines, or components for short-circuits, discontinuities, leakage, or incorrect line connection

81.

Bit synchronization for high-speed serial device testing

      
Application Number 11120368
Grant Number 07296195
Status In Force
Filing Date 2005-05-02
First Publication Date 2006-11-02
Grant Date 2007-11-13
Owner XCERRA CORPORATION (USA)
Inventor Sakaitani, Kris

Abstract

An apparatus for testing electronic devices employs a programmable device to adjust the timing of the strobes such that the strobes sample the bit stream from a device under test at or near the center of the bit position. The strobe time adjustment is performed based on pairs of strobe readings made around a number of different bit positions. The programmable device examines the pairs of strobe reading made around each of the different bit positions to determine whether or not a bit transition has occurred there. The programmable device selects the bit positions around which a bit transition has not occurred as eye candidates, and defines the center of the largest contiguous region of eye candidates as the center of the bit position.

IPC Classes  ?

  • G06K 5/04 - Verifying the alignment of markings

82.

Integrated circuit tester

      
Application Number 11223421
Grant Number 07034520
Status In Force
Filing Date 2005-09-09
First Publication Date 2006-04-25
Grant Date 2006-04-25
Owner XCERRA CORPORATION (USA)
Inventor
  • Miller, Wayne H.
  • Paretich, Chris S.
  • Lubin, James K.
  • Firestone, Stuart M.

Abstract

A product change tool for selectively engaging a product change element with an IC tester interface and disengaging the product change element from the tester interface includes a mobile frame mounted to a base frame and constrained to move relative to the base frame along an axis of linear movement, and a force mechanism for urging the mobile frame to move along the axis of linear movement relative to the base frame. The force mechanism includes first and second links pivotally connected together at their proximal ends and secured at their distal ends to the mobile frame and the base frame respectively. The distal ends of the links are spaced apart along the axis of linear movement and the proximal ends of the links are between the distal ends relative to that axis. An actuator is coupled to the proximal ends of the links for urging the proximal ends of the links in directions transverse to the axis of linear movement, whereby the spacing of the distal ends of the links along the axis changes and the mobile frame moves relative to the base frame along the axis.

IPC Classes  ?

  • G01R 31/26 - Testing of individual semiconductor devices

83.

ECT

      
Application Number 004363073
Status Registered
Filing Date 2005-03-30
Registration Date 2006-04-18
Owner Xcerra Corporation (USA)
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 40 - Treatment of materials; recycling, air and water treatment,

Goods & Services

Printed circuit board probing and testing equipment, testers, test fixtures and kits for making test fixtures and parts therefor, test probes, translator modules for making electrical test connections to integrated circuit packages, test adapters for aligning a pattern of test probes with a product under test, electronic test receivers, sockets for semi-conductor testing, circuit board handling equipment; computer software for use in conducting product tests and test fixture and repair software. Construction of circuit board test fixtures to customer specifications; testing of circuit boards and circuit devices for customers.

84.

EVERETT CHARLES TECHNOLOGIES

      
Application Number 004362927
Status Registered
Filing Date 2005-03-30
Registration Date 2006-04-18
Owner Xcerra Corporation (USA)
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 40 - Treatment of materials; recycling, air and water treatment,

Goods & Services

Testers, test fixtures, and test fixture kits for printed wiring boards; components for all the aforesaid testers and test fixtures; test probes; translator modules for making electrical test connections to integrated circuit packages. Providing customised test fixtures to customer specifications.

85.

ECT

      
Serial Number 78593816
Status Registered
Filing Date 2005-03-23
Registration Date 2006-11-07
Owner XCERRA CORPORATION ()
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 40 - Treatment of materials; recycling, air and water treatment,

Goods & Services

PRINTED CIRCUIT BOARD PROBING AND TESTING EQUIPMENT, NAMELY, TESTERS; TEST FIXTURES; KITS FOR MAKING TEST FIXTURES AND PARTS THEREFOR, NAMELY, SUPPORT PLATES, GASKETS, GAS HINGES AND VACUUM CONNECTORS; TEST PROBES; TRANSLATOR MODULES FOR MAKING ELECTRICAL TEST CONNECTIONS TO INTEGRATED CIRCUIT PACKAGES; TEST ADAPTERS FOR ALIGNING A PATTERN OF TEST PROBES WITH A PRODUCT UNDER TEST; ELECTRONIC TEST RECEIVERS; SOCKETS FOR SEMI-CONDUCTOR TESTING; CIRCUIT BOARD HANDLING EQUIPMENT; AND SOFTWARE FOR USE IN CONDUCTING PRODUCT TESTS AND TEST FIXTURE AND REPAIR SOFTWARE CONSTRUCTION OF CIRCUIT BOARD TEST FIXTURES TO CUSTOMER SPECIFICATIONS

86.

ECT

      
Serial Number 78593835
Status Registered
Filing Date 2005-03-23
Registration Date 2006-11-07
Owner XCERRA CORPORATION ()
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 40 - Treatment of materials; recycling, air and water treatment,

Goods & Services

PRINTED CIRCUIT BOARD PROBING AND TESTING EQUIPMENT, NAMELY, TESTERS; TEST FIXTURES; KITS FOR MAKING TEST FIXTURES AND PARTS THEREFOR, NAMELY, SUPPORT PLATES, GASKETS, GAS HINGES AND VACUUM CONNECTORS, TEST PROBES; TRANSLATOR MODULES FOR MAKING ELECTRICAL TEST CONNECTIONS TO INTEGRATED CIRCUIT PACKAGES; TEST ADAPTERS FOR ALIGNING A PATTERN OF TEST PROBES WITH A PRODUCT UNDER TEST; ELECTRONIC TEST RECEIVERS; SOCKETS FOR SEMI-CONDUCTOR TESTING; CIRCUIT BOARD HANDLING EQUIPMENT; AND SOFTWARE FOR USE IN CONDUCTING PRODUCT TESTS AND TEST FIXTURE AND REPAIR SOFTWARE CONSTRUCTION OF CIRCUIT BOARD TEST FIXTURES TO CUSTOMER SPECIFICATIONS

87.

High resolution clock signal generator

      
Application Number 09824898
Grant Number 07805628
Status In Force
Filing Date 2001-04-02
First Publication Date 2002-11-28
Grant Date 2010-09-28
Owner XCERRA CORPORATION (USA)
Inventor Kushnick, Eric B.

Abstract

p/(M*N) seconds when the integers N and M are relatively prime.

IPC Classes  ?

  • G06F 1/08 - Clock generators with changeable or programmable clock frequency

88.

EVERETT CHARLES TECHNOLOGIES

      
Serial Number 74243815
Status Registered
Filing Date 1992-02-06
Registration Date 1994-05-31
Owner XCERRA CORPORATION ()
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 40 - Treatment of materials; recycling, air and water treatment,

Goods & Services

printed wiring board probing and testing equipment; namely, testers, test fixtures, and kits for making test fixture and parts therefor; test probes for making electrical test connections; translator modules for making electrical test connections to integrated circuit packages construction of printed wiring board test fixtures to customer specifications

89.

FASTITE

      
Serial Number 73642017
Status Registered
Filing Date 1987-01-28
Registration Date 1987-12-01
Owner XCERRA CORPORATION ()
NICE Classes  ? 09 - Scientific and electric apparatus and instruments

Goods & Services

ELECTRICAL WIRE TERMINATION RECEPTACLE FOR MINIATURE SPRING PROBES

90.

POGO

      
Application Number 050119800
Status Registered
Filing Date 1983-03-31
Registration Date 1984-03-09
Owner Xcerra Corporation (USA)
NICE Classes  ? 11 - Environmental control apparatus

Goods & Services

(1) Electrical contacts.