A High Electron Mobility Transistor comprising a source and a drain, a III-N buffer layer and a III-N barrier layer jointly forming a 2DEG in the buffer layer between the source and the drain, a first gate electrode configured to receive a gate bias voltage and a second gate electrode located between the drain and the first gate and conductively connected to the source via the 2DEG.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
2.
ISOLATION STRUCTURE FOR MICRO-TRANSFER-PRINTABLE DEVICES
A semiconductor structure suitable for micro-transfer printing comprises a semiconductor substrate and a patterned insulation layer disposed on or over the semiconductor substrate. The insulation layer pattern forms one or more etch vias in contact with the semiconductor substrate. In some embodiments, each etch via is exposed. A semiconductor device is disposed on the patterned insulation layer and is surrounded by an isolation material in one or more isolation vias that are adjacent to the etch via. The etch via can be at least partially filled with a semiconductor material that is etchable with a common etchant as the semiconductor substrate. In some embodiments, the etch via is empty and the semiconductor substrate is patterned to forma gap that separates at least a part of the semiconductor device from the semiconductor substrate and forms a tether physically connecting the semiconductor device to an anchor (e.g., a portion of the semiconductor substrate or the patterned insulation layer).
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
3.
Method for the formation of transistors PDSO1 and FDSO1 on a same substrate
The present invention relates to a method for forming an electronic device intended to accommodate at least one fully depleted transistor of the FDSOI type and at least one partially depleted transistor of the PDSOI type, from a stack of layers (10) comprising at least one insulating layer (100) topped with at least one active layer (200) made of a semiconductor material, the method comprising at least one step of dry etching and one step of height adjustment between at least two etched elements.
H01L 21/76 - Making of isolation regions between components
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
A CMOS image sensor pixel (200) comprising a photosensitive element (101) for generating a charge in response to incident light; a plurality of charge storage elements (103); a plurality of transfer gates (102) for enabling the transfer of charge between the photosensitive element and an associated one of the charge storage elements; and one or more first electrical connections (201) for placing at least two of the plurality of charge storage elements in mutual electrical contact.
A method for manufacturing a system in a wafer for measuring an absolute and a relative pressure includes etching a shallow and a deep cavity in the wafer. A top wafer is applied and the top wafer is thinned for forming a first respectively second membrane over the shallow respectively deep cavity, and for forming in the top wafer first respectively second bondpads at the first respectively second membrane resulting in a first respectively second sensor. Back grinding the wafer results in an opened deep cavity and a still closed shallow cavity. The first bondpads of the first sensor measure an absolute pressure and the second bondpads of the second sensor measure a relative pressure. The etching in the first step defines the edges of the first membrane and of the second membrane in respectively the sensors formed from the shallow and the deep cavity.
H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
G01F 1/34 - Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow by using mechanical effects by measuring pressure or differential pressure
G01L 9/00 - Measuring steady or quasi-steady pressure of a fluid or a fluent solid material by electric or magnetic pressure-sensitive elementsTransmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
G01L 15/00 - Devices or apparatus for measuring two or more fluid pressure values simultaneously
B81B 7/04 - Networks or arrays of similar microstructural devices
B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
There is provided a transistor comprising a source, gate and a drain, the source, gate and drain being arranged next to each other in a lengthwise direction of the transistor. The gate comprises a layer of an at least partially conductive material, wherein said layer has a recess such that, at a lengthwise position within the recess, the width of said layer is smaller than at a lengthwise position outside the recess.
A semiconductor chip for measuring a magnetic field based on the Hall effect. The semiconductor chip comprises an electrically conductive well having a first conductivity type, in a substrate having a second conductivity type. The semiconductor chip comprises at least four well contacts arranged at the surface of the well, and having the first conductivity type. The semiconductor chip comprises a plurality of buffer regions interleaved with the well contacts and having the first conductivity type. The buffer regions are highly conductive and the buffer region dimensions are such that at least part of the current from a well contact transits through one of its neighboring buffer regions.
H01L 43/04 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details of Hall-effect devices
9.
ANTI-REFLECTIVE TREATMENT OF THE REAR SIDE OF A SEMICONDUCTOR WAFER
The invention relates to a method for producing a semiconductor wafer, wherein an optical anti-reflective layer (4) is formed on the rear side of the wafer, in order to optimise the optical access (17) to or from the CMOS components (10) via the rear side (32) of the wafer (1). The CMOS components (10) are only produced after an anti-reflective layer (4), the etch stop layers (5, 6) formed thereon, the bonding layer (7) and the bonded carrier wafer (8) have been formed. After the formation of the CMOS components, the etch stop layers (5, 6), the bonding layer (7) and the bonded carrier wafer (8) are thinned and removed at least selectively by means of grinding or by means of lithography (16) or masked etching.
Invention achieves reduced amount of terminals to control a test mode, test function and test results of a given standard for at least one "wrapped core" (40,100) (a core 100 surrounded by a wrapper boundary register (40) as "wrapper chain"). Test flexibility and speed of testing the core (100) are also improved. Suggested serial test interface comprises a state machine (210) and an instruction register (213) for wrapper‐instructions, supplied through a single physical data input terminal (1a). The state machine (210) reads wrapper‐ instructions held by the instruction register (213) and generates on‐chip wrapper control signals (30) of the given standard for the wrapper boundary register (40) of the core (100). At least one wrapper‐instruction read from the Instruction Register (213) provides at least one wrapper control signal (30). The single input terminal (1a) also supplies an input test signal SDI for coupling to the wrapper boundary register (40) as on chip logical input test signal WSI. A single output terminal (1b) returns an output test signal SDO from an output WSO of the wrapper boundary register (40). Invention may apply to IEEE 1500 control signals.
A window opening in a semiconductor component is produced on the basis of a gate structure which serves as an efficient etch resist layer in order to reliably etch an insulation layer stack without exposing the photosensitive semiconductor area. The polysilicon in the gate structure is then removed on the basis of an established gate etching process, with the gate insulation layer preserving the integrity of the photosensitive semiconductor material.
H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
H01L 31/028 - Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic System
H01L 31/113 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect photo- transistor being of the conductor-insulator- semiconductor type, e.g. metal- insulator-semiconductor field-effect transistor
A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes at least one termination portion provided adjacent to the drift portion. The at least one termination portion comprises a Super Junction structure.
A method of fabricating a tunnel oxide layer for a semiconductor memory device, the method comprising: fabricating on a substrate a first oxide layer by an in-situ-steam- generation process; and fabricating at least one further oxide layer by a furnace oxidation process, wherein during fabrication of the at least one further oxide layer, reactive gases penetrate the first oxide layer and react with the silicon substrate to form at least a first portion of the at least one further oxide layer beneath the first oxide layer.
In a semiconductor component or device, a lateral power effect transistor is produced as an LDMOS transistor in such a way that, in combination with a trench isolation region (12) and the heavily doped feed guiding region (28, 28A), an improved potential profile is achieved in the drain drift region (8) of the transistor. For this purpose, in advantageous embodiments, it is possible to use standard implantation processes of CMOS technology, without additional method steps being required.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
A MOS device assembly comprising at least a first transistor (110) and a second transistor (111), each having a gate region. The dimensions of the gate region of the first transistor are different from the dimensions of the gate region of the second transistor and the transconductance of the MOS device assembly is substantially uniform when the gate regions of the first and second transistors are biased using the same voltage.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H03F 1/32 - Modifications of amplifiers to reduce non-linear distortion
16.
INTERCONNECT DEVICE, ELECTRONIC DEVICE, AND METHOD OF USING A SELF-HEATABLE CONDUCTIVE PATH OF THE INTERCONNECT DEVICE
An interconnect device (12) having terminal pads (26), a positioning area (13) for arranging a semiconductor element (15) at the positioning area (13), and a plurality of conductive paths (16), wherein at least a subset thereof is prepared for electrically connecting an arranged semiconductor element (15) to at least a subset of the terminal pads (26), wherein a self-heatable one (16H) of the plurality of conductive paths (16) has a total resistance (R) of more than 90 Ohms. An electronic device (10) comprises said interconnect device (12) and a semiconductor element (15) arranged at the positioning area (13) and electrically connected by conductive paths (16) to at least a subset of the terminal pads (26). A self-heatable conductive path (16H) of the interconnect device (12) described above may be used to increase temperature (T) of a semiconductor element (15) by more than 10° K by arranging and electrically connecting the interconnect device (12) to the semiconductor element (15) and by applying voltage (U) to the self-heatable conductive path (16) arranged in the interconnect device (12).
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
A semiconductor device comprising: at least one strained semiconductor layer to change the probability of an electron tunnelling from a first area to a second area.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
A trench MOSFET comprises: an epitaxial layer;a body region on the epitaxial layer, the body region and the epitaxial layer forming a first interface; a trench; a trench bottom oxide in the trench; and polysilicon in the trench, the trench bottom oxide and the polysilicon forming a second interface;wherein the first and second interfaces are substantially aligned or are at substantially the same level.
The disclosed method of manufacturing (110, 120, 130, 140) a semiconductor device (12) has the steps (112, 114, 116) of: forming at least one wall (33) of a body (44) of the semiconductor device (12) by etching at least one trench (22) for a gate (42) of the semiconductor device (12) into the body (44); and performing a slanted implantation doping (126, 128) into the at least one wall (33) of the body (44), after the etching (112) of the at least one trench (22) and prior to coating the at least one trench (22) with an insulating layer (29). A semiconductor device (12) comprises at least one trench (22) for a gate (42) of the semiconductor device (12); and a body (44) having at least one wall (33) of the at least one trench (22), wherein a deviation (64) of a doping concentration (62) along a distance (66) in depth-direction (do) of the at least one trench (22) in a surface (33) of the at least one wall (33) is less than ten percent of a maximum value (68) of the doping concentration (62) along the distance (66).
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
A depletion type DMOS transistor comprises a gap in electrode material allowing incorporation of a well dopant species into the underlying semiconductor material. During subsequent dopant diffusion a continuous well region is obtained having an extended lateral extension without having an increased depth. The source dopant species is implanted after masking the gap. Additional channel implantation is performed prior to forming the gate dielectric material.
A CMOS or bipolar based Ion Sensitive Field Effect Transistor (ISFET) comprising an ion sensitive recess for holding a liquid wherein the recess is formed at least partly on top of a gate of the transistor. There is also provided a method of manufacturing an I on Sensitive Field Effect Transistor (ISFET) utilising CMOS processing steps, the method comprising forming an ion sensitive recess for holding a liquid at least partly on top of a gate of the transistor.
The invention relates to a method for producing silicon semiconductor wafers and components having layer structures of III-V layers for integrating III-V semiconductor components. The method employs SOI silicon semiconductor wafers having varying substrate orientations, and the III-V semiconductor layers are produced in trenches (28, 43, 70) produced by etching within certain regions (38, 39), which are electrically insulated from each other, of the active semiconductor layer (24, 42) by means of a cover layer or cover layers (29) using MOCVD methods.
An at least partially conductive element, for example a poly silicon ring, is provided over the base emitter junction of a bipolar junction transistor. When the at least partially conductive element is charged the recombination current is reduced in regions of the base adjacent to the element. This results in improved linearity of the gain of the transistor.
A method of reducing contamination of contact pads in a metallization system of a semiconductor device. Fluorine contamination of contact pads in a semiconductor device can be reduced by appropriately covering the sidewall portions of a metallization system in the scribe lane in order to significantly reduce or suppress the out diffusion of fluorine species, which may react with the exposed surface areas of the contact pads. The quality of the bond contacts is enhanced, possibly without requiring any modifications in terms of design rules and electrical specifications.
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
26.
Method for fabricating semiconductor wafers for the integration of silicon components with HEMTs, and appropriate semiconductor layer arrangement
A window opening in a semiconductor component is produced on the basis of a gate structure which serves as an efficient etch resist layer in order to reliably etch an insulation layer stack without exposing the photosensitive semiconductor area. The polysilicon in the gate structure is then removed on the basis of an established gate etching process, with the gate insulation layer preserving the integrity of the photosensitive semiconductor material.
The present invention provides semiconductor devices and methods for fabricating the same, in which superior dielectric termination of drift regions is accomplished by a plurality of intersecting trenches with intermediate semiconductor islands. Thus, a deep trench arrangement can be achieved without being restricted by the overall width of the isolation structure.
H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof
H01L 21/76 - Making of isolation regions between components
A semiconductor component with straight insulation trenches formed in a semiconductor material providing semiconductor areas laterally insulated from each other. Each insulation trench has a uniform width along its longitudinal direction represented by a central line. The semiconductor component has an intersecting area into which at least three of the straight insulation trenches lead. A center of the intersecting area is defined as a point of intersection of the continuations of the center lines. A central semiconductor area disposed in the intersecting area is connected with one of the semiconductor areas and contains the center of the intersecting area.
In an integrated circuit an inductor metal layer is provided separately to the top metal layer, which includes the power and signal routing metal lines. Consequently, high performance inductors can be provided, for instance by using a moderately high metal thickness substantially without requiring significant modifications of the remaining metallization system.
H01L 29/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor bodies or of electrodes thereof
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
STI divot formation is minimized and STI field height mismatch between different regions is eliminated. A nitride cover layer (150) having a thickness less than 150 then a oxide cover layer (160) having a thickness less than 150 is deposited acting as implant buffer after pad oxide removal following the STI CMP process. This nitride or oxide stack is selectively removed by masking prior to gate oxidation of each LV (low voltage) region (GX1), MV (intermediate voltage) region (GX3) and HV (high voltage) region (GX5) respectively followed by a gate poly deposition.
H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
A semiconductor device comprising a semiconductor substrate and a composite capacitor structure on the semiconductor substrate, wherein the composite capacitor structure comprises a capacitor stack comprising a lower and an upper capacitor, respectively comprising first and second dielectric materials, wherein the first and second dielectric materials are different materials and/or have different thicknesses from each other. This can minimize the voltage dependence of the capacitance of the composite capacitor structure. It is also possible to provide a composite capacitor structure on the semiconductor substrate, wherein the composite capacitor structure comprises at least a first and a second capacitor stack, each comprising a lower and an upper capacitor. The capacitors can be MIM capacitors.
H01G 7/06 - Capacitors in which the capacitance is varied by non-mechanical meansProcesses of their manufacture having a dielectric selected for the variation of its permitivity with applied voltage, i.e. ferroelectric capacitors
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
33.
Orientation of an electronic CMOS structure with respect to a buried structure in the case of a bonded and thinned-back stack of semiconductor wafers
A method for aligning an electronic CMOS structure with respect to a buried structure in the case of a bonded and thinned back stack of semiconductor wafers. The method for aligning the electronic CMOS structure may include forming alignment marks in the process of fabricating the structure to be buried on a front side, which is used for bonding of the semiconductor wafer, which includes the structure to be buried. The alignment marks may be formed on the edge of the semiconductor wafer. The method for aligning the electronic CMOS structure may include providing a cover wafer with first thinned portions of the wafer thickness provided from the bonding side at positions corresponding to positions of the alignment marks. After the thinning of the cover wafer a plan view of the alignment mark is obtained after the wafer bonding that initially results in a burying of the structures, wherein subsequently the resulting wafer stack is thinned to a certain degree with respect to the cover wafer, thereby making visible the at least one alignment mark, and by means of the alignment mark masks of method steps for fabricating the electronic structure on the surface of the thinned cover wafer are aligned.
In a semiconductor component, a lateral power field effect transistor is produced as an LDMOS transistor in such a way that, in combination with a trench isolation region (12) and a heavily doped field guiding region (28, 28A), an improved potential profile is achieved in a drain drift region (8) of the transistor. For this purpose, in advantageous embodiments, it is possible to use standard implantation processes of CMOS technology, without additional method steps being required.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
The disclosed method of manufacturing (1 10, 120, 130, 140) a semiconductor device (12) has the steps (1 12, 1 14, 1 16) of: forming at least one wall (33) of a body (44) of the semiconductor device (12) by etching at least one trench (22) for a gate (42) of the semiconductor device (12) into the body (44); and performing a slanted implantation doping (126, 128) into the at least one wall (33) of the body (44), after the etching (1 12) of the at least one trench (22) and prior to coating the at least one trench (22) with an insulating layer (29). A semiconductor device (12) comprises at least one trench (22) for a gate (42) of the semiconductor device (12); and a body (44) having at least one wall (33) of the at least one trench (22), wherein a deviation (64) of a doping concentration (62) along a distance (66) in depth-direction (do) of the at least one trench (22) in a surface (33) of the at least one wall (33) is less than ten percent of a maximum value (68) of the doping concentration (62) along the distance (66).
A high voltage metal oxide semiconductor (HVMOS) transistor (1) comprises a drift region (8) comprising a material having a mobility which is higher than a mobility of Si. There is also provided a method of manufacturing said transistor, the method comprising forming a drift region comprising a material having a mobility which is higher than a mobility of Silicon. The material can be a Si-Ge strained material. The on- resistance is reduced compared to a transistor with a drift region made of Si, so that the trade-off between breakdown voltage and on-resistance is improved.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
37.
DMOS Transistor Having an Increased Breakdown Voltage and Method for Production
A depletion type DMOS transistor comprises a gap in electrode material allowing incorporation of a well dopant species into the underlying semiconductor material. During subsequent dopant diffusion a continuous well region is obtained having an extended lateral extension without having an increased depth. The source dopant species is implanted after masking the gap. Additional channel implantation is performed prior to forming the gate dielectric material.
The power transistor configured to be integrated into a trench-isolated thick layer SOI-technology with an active silicon layer with a thickness of about 50 μm. The power transistor may have a lower resistance than the DMOS transistor and a faster switch-off behavior than the IGBT.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
39.
Production of isolation trenches with different sidewall dopings
a) in the second trench (34). By means of isotropic etching the material layer is removed from the second trench, but residual material of the material layer is maintained in the first trench. A further doping of sidewalls of the first trench or of the second trench in the presence of the residual material is then performed.
A semiconductor device with an integrated circuit on a semiconductor substrate comprises a Hall effect sensor in a first active region and a lateral high voltage MOS transistor in a second active region. The semiconductor device of the present invention is characterized in that the structure of the integrated Hall effect sensor is strongly related with the structure of a high-voltage DMOS transistor. The integrated Hall effect sensor is in some features similar to a per se known high-voltage DMOS transistor having a double RESURF structure. The control contacts of the Hall effect sensor correspond to the source and drain contacts of the high-voltage DMOS transistor. The semiconductor device of the present invention allows a simplification of the process integration.
Location-related adjustment of the operating temperature distribution or power distribution of a semiconductor power component, and component for carrying out said method
Described is a method for adjusting an operating temperature of MOS power components composed of a plurality of identical individual cells and a component for carrying out the method. As a characteristic feature, the gate electrode network (4) of the active chip region is subdivided into several gate electrode network sectors (B1, B2, B3) which are electrically isolated from one another by means of isolating points and to each of which a different gate voltage is fed via corresponding contacts.
H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
G05D 23/19 - Control of temperature characterised by the use of electric means
H03K 17/14 - Modifications for compensating variations of physical values, e.g. of temperature
H03K 17/08 - Modifications for protecting switching circuit against overcurrent or overvoltage
42.
METHOD FOR PRODUCING SILICON SEMICONDUCTOR WAFERS COMPRISING A LAYER FOR INTEGRATING III-V SEMICONDUCTOR COMPONENTS
The invention relates to a method for producing silicon semiconductor wafers and components having layer structures of III-V layers for integrating III-V semiconductor components. The method employs SOI silicon semiconductor wafers having varying substrate orientations, and the III-V semiconductor layers are produced in trenches (28, 43, 70) produced by etching within certain regions (38, 39), which are electrically insulated from each other, of the active semiconductor layer (24, 42) by means of a cover layer or cover layers (29) using MOCVD methods.
The invention describes a method for fabricating silicon semiconductor wafers with the layer structures from III-V semiconductor layers for the integration of HEMTs based on III-V semiconductor layers with silicon components. SOI silicon semiconductor wafers are used, the active semiconductor layer of which has the III-V semiconductor layers (24) of the HEMT design (2) placed on it stretching over two mutually insulated regions (24a, 24b) of the active silicon layer. An appropriate layer arrangement is likewise disclosed.
H01L 21/8258 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by , , or
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
44.
SEMICONDUCTOR COMPONENT WITH A WINDOW OPENING AS AN INTERFACE FOR AMBIENT COUPLING
A window opening in a semiconductor component is produced on the basis of a gate structure which serves as an efficient etch resist layer in order to reliably etch an insulation layer stack without exposing the photosensitive semiconductor area. The polysilicon in the gate structure is then removed on the basis of an established gate etching process, with the gate insulation layer preserving the integrity of the photosensitive semiconductor material.
A capacitor has first and second conducting plates and a dielectric region between the plates, wherein the dielectric region comprises two dielectric materials for each of which the variation of capacitance with voltage can be approximated by a polynomial having a linear coefficient and a quadratic coefficient, and wherein the quadratic coefficients of the two dielectric materials are of opposite sign. The capacitor comprises for example a first capacitor (42) and a second capacitor (44) that one connected in an anti-parallel manner. The insulating layer (18) of the first capacitor comprises silicon nitride and the insulating layer (16) of the second capacitor comprises silicon dioxide
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
46.
REDUCTION OF FLUORINE CONTAMINATION OF BOND PADS OF SEMICONDUCTOR DEVICES
A method of reducing contamination of contact pads in a metallization system of a semiconductor device. Fluorine contamination of contact pads in a semiconductor device can be reduced by appropriately covering the sidewall portions of a metallization system in the scribe lane in order to significantly reduce or suppress the out diffusion of fluorine species, which may react with the exposed surface areas of the contact pads. The quality of the bond contacts is enhanced, possibly without requiring any modifications in terms of design rules and electrical specifications.
A PN junction comprises first and second areas of silicon, wherein one of said first and second areas is n-type silicon and the other of said first and second areas is p-type silicon, wherein said first area has one or more projections which at least partially overlap with said second area, so as to form at least one cross-over point, said cross-over point being a point at which an edge of said first area crosses over an edge of said second area.
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
48.
Test structure for highly accelerated electromigration tests for thick metallization systems of solid state integrated circuits
A test structure and a process for the electromigration test of integrated circuits is suggested, in which metallization planes consisting of strip conductors of a usual thickness (11) are connected with metallization planes consisting of substantially thicker strip conductors (12) as they are required for the connection of components of higher performance.
G01N 27/62 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating the ionisation of gases, e.g. aerosolsInvestigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electric discharges, e.g. emission of cathode
H01L 21/66 - Testing or measuring during manufacture or treatment
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
49.
METHOD OF MANUFACTURING AN ORGANIC LIGHT EMITTING DIODE BY LIFT-OFF
A method of manufacturing an Organic Light Emitting Diode (OLED). The method comprises using a solution or a solvent for removing a photo-resist (102) used for patterning, which photo-resist is at least partly covered with a material (103) other than photo-resist. The method of manufacturing the OLED thus comprises a lift-off process. The new method provides the benefits of low cost manufacturing and high OLED performance.
H01L 51/00 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
H01L 51/52 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for light emission, e.g. organic light emitting diodes (OLED) or polymer light emitting devices (PLED) - Details of devices
A transistor arranged to have an improved Safe Operating Area. The transistor has a Source, Drain, insulator and a Gate comprising one or more discrete Gate structures located at least partly over a second well, wherein at least one of the one or more discrete Gate structures does not substantially overlap with the insulator. The transistor may also be arranged such that the Source is disposed substantially between the Drain and the Gate.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A system and a method for testing the ESD behavior, wherein a circuit (7) is automatically tested at circuit diagram level in that technology-specific ESD data is provided in database (2) for each circuit component present in the circuit, without requiring complex circuit simulations, for example based on front end or back end data, by taking into account the layout.
Methods of forming, on a substrate, a first lateral high-voltage MOS transistor and a second lateral high-voltage MOS transistor complementary to said first one are disclosed. According to one embodiment, the method includes (1) providing a substrate of a first conductivity type including a first active region for said first lateral high-voltage MOS transistor and a second active region for said second lateral high-voltage MOS transistor and (2) forming at least one first doped region of the first conductivity type in the first active region and forming in the second active region a drain extension region of the second conductivity type extending from a substrate surface to an interior of the substrate, including a concurrent implantation of dopants through openings of one and the same mask into the first and second active regions. Forming of the at least one first doped region may be a sub step of a superior step of forming a double RESURF structure in the first lateral high-voltage MOS transistor, and forming the double RESURF structure may include forming doped RESURF regions as two first doped regions, one thereof above and one thereof below the drift region of the first lateral high-voltage MOS transistor, and as two further doped regions, one thereof above and one thereof below the drain extension regions of the second lateral high-voltage MOS transistor, wherein the first doped RESURF regions have an inverse conductivity type with respect to the drift region and the further doped regions have inverse conductivity type as compared to the drain extension region.
Disclosed is a semiconductor structure for producing a handle wafer contact in trench insulated SOI discs which may be used as a deep contact (7, 6, 30′) to the handle wafer (1) of a thick SOI disc as well as for a trench insulation (40). Therein, the same method steps are used for both structures which are used as deep contact to the handle wafer of the thick SOI disc as well as trench insulation.
H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof
54.
Light-blocking layer sequence having one or more metal layers for an integrated circuit and method for the production of the layer sequence
b, 1) for the purpose of absorption. A moth eye structure is provided on the silicon layer. Thereby, a radiation incident by reflection is minimized in such a way that also stray light can effectively be kept from the light sensitive area below the light blocking layer sequence (504).
The present invention provides semiconductor devices and methods for fabricating the same, in which superior dielectric termination of drift regions is accomplished by a plurality of intersecting trenches with intermediate semiconductor islands. Thus, a deep trench arrangement can be achieved without being restricted by the overall width of the isolation structure.
It is the purpose of the invention to provide a MOS transistor (20) which guarantees a voltage as high as possible, has a required area as small as possible and which enables the integration into integrated smart power circuits. It results there from as an object of the invention to form the edge structure of the transistors such that it certainly fulfils the requirements on high breakthrough voltages, a good isolation to the surrounding region and requires a minimum of surface on the silicon disc anyway. This is achieved with an elongated MOS power transistor having drain (30) and source (28) for high rated voltages above 100V, wherein the transistor comprises an isolating trench (22) in the edge area for preventing an early electrical breakthrough below the rated voltage. The trench is lined with an isolating material (70, 72), wherein the isolating trench terminates the circuit component.
A semiconductor device comprising: a p or p+ doped portion; an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion; an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and said at least one doped portion meet; and at least one additional portion which is arranged for significantly reducing the variation of the electric field strength in said region when a voltage difference is applied between the doped portions.
In an integrated circuit an inductor metal layer is provided separately to the top metal layer, which includes the power and signal routing metal lines. Consequently, high performance inductors can be provided, for instance by using a moderately high metal thickness substantially without requiring significant modifications of the remaining metallization system.
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
59.
SEMICONDUCTOR DEVICE FOR A HIGH VOLTAGE APPLICATION
A lateral high voltage semiconductor device comprises a first semiconductor region, a second semiconductor region arranged laterally to the first semiconductor region, and a drift region there between The drift region has a p drift sub-region and an n drift sub-region, forming a super junction The device comprises an insulating layer on a substrate, between the substrate and the super junction, wherein a substrate depletion region is formed, and wherein one of the first and second semiconductor regions extends past the insulating layer to the substrate The insulating layer may also be formed with an extension completely insulating the super junction arrangement from the substrate, and the device further comprises a further semiconductor region of the second conductivity type extending from an outer level of the super junction arrangement past the insulating layer to the substrate and being insulated from the super junction arrangement
STI divot formation is minimized and STI field height mismatch between different regions is eliminated. A nitride cover layer (150) having a thickness less than 150 then a oxide cover layer (160) having a thickness less than 150 is deposited acting as implant buffer after pad oxide removal following the STI CMP process. This nitride or oxide stack is selectively removed by masking prior to gate oxidation of each LV (low voltage)region (GX1), MV (intermediate voltage) region (GX3) and HV (high voltage) region (GX5) respectively followed by a gate poly deposition.
A method of manufacturing an Organic Light Emitting Diode (OLED). A substrate (101) is provided, and a plurality of pixel electrodes (102) is formed on the substrate resulting in at least one gap (105) between two adjacent pixel electrodes. A dielectric material (103) is deposited in the gap. The resulting structure is subjected to a process which ensures that at least a portion of the surface of the pixel electrodes is not covered by the dielectric material. At least the portion of the surface of the pixel electrodes is covered with a layer of an organic compound so as to form the OLED.
H01L 27/32 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes
H01L 51/52 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for light emission, e.g. organic light emitting diodes (OLED) or polymer light emitting devices (PLED) - Details of devices
62.
PRODUCTION OF HIGH ALIGNMENT MARKS AND SUCH ALIGNMENT MARKS ON A SEMICONDUCTOR WAFER
The invention relates to production of alignment marks on a semiconductor wafer with the use of a light-opaque layer (17), wherein, before the light-opaque layer (17) is applied, by means of the etching of cavities, free-standing pillar groups are produced in the cavities and then the light-opaque layer (17) is applied. The pillars are produced with a height of above 1 μm, which, moreover, is greater than a thickness of the light-opaque layer (17) to be applied in the cavities as layer portions (17x; 17y). The cavities are formed with a width such that they are filled only partly with the layer portions (17x; 17y) when the light-opaque layer (17) is applied. The high, freely positioned alignment marks produced by the method as pillar series (16x; 16y), having a plurality of individual pillars (16a; 16a') in a cavity (12a, 12y), of a scribing trench on the semiconductor wafer are likewise described.
The invention relates to a BiMOS semiconductor component having a semiconductor substrate wherein, in a first active region, a depletion-type MOS transistor is formed comprising additional source and drain doping regions of the first conductivity type extending in the downward direction past the depletion region into the body doping region while, in a second active region, (101), a bipolar transistor (100) is formed, the base of which comprises a body doping region (112) and the collector of which comprises a deep pan (110), wherein an emitter doping region (114) of the first conductivity type and a base connection doping region (118) of the second conductivity type are formed in the body doping region. The semiconductor element can be produced with a particularly low process expenditure because it uses the same basic structure for the doping regions in the bipolar transistor as are used in the MOS transistor of the same semiconductor component.
a) for improving the optical behavior of components and devices and/or for improving the behavior of sensors by enlarging the active surface area. The nanostructure (2) is produced in a self-masking fashion by means of RIE etching and its material composition can be modified and it can be provided with suitable cover layers.
H01L 31/062 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the metal-insulator-semiconductor type
65.
Hermetic sealing and electrical contacting of a microelectromechanical structure, and microsystem (MEMS) produced therewith
a) by means of a conductive solder glass (8). Said methods and microsystems make it possible to simplify through-plating, reduce the failure rate, and increase reliability.
A method for producing VDMOS transistors in which a specific layer arrangement and a specific method sequence allow setting up an improved gate contact when simultaneously producing source and gate contacts using a single contact hole mask (photo mask).
The invention is based on a method for orienting an electronic CMOS structure with respect to a buried structure in the case of a bonded and thinned-back stack of semiconductor wafers. The method is intended to avoid "front side to rear side" orientation(s). The proposed method for orienting the electronic CMOS structure uses the formation of alignment marks (7;7a,7b) in the process of producing the structure to be buried on a front side, which is used for bonding, of the semiconductor wafer (1) which carries the structure (2) to be buried. The alignment marks (7) are formed on the edge of the semiconductor wafer. A cover wafer (5) is provided with first thinned portions (10a;10b) of the wafer thickness, which thinned portions are made from the bonding side, at locations whose positions correspond to the alignment marks (7). A plan view of the alignment marks (7) becomes possible after wafer bonding. For this purpose, the first thinned portions of the cover wafer (5) are formed, from the bonding side thereof, so as to reduce an edge of each thinned part of the cover wafer (5). A second operation of thinning the cover wafer (5) of the wafer stack (6) produced by the bonding operation is carried out to a particular extent, as a result of which the alignment marks (7;7a,7b) become visible. Masks for producing the electronic structure (40h) can be oriented on a surface (8a) of the thinned cover wafer (8) using the alignment marks (7;7a,7b).
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
H01L 21/50 - Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups or
68.
SEMICONDUCTOR COMPONENT WITH ISOLATION TRENCH INTERSECTIONS
The invention relates to the geometric design (as a layout) of points of intersection and junctions of isolation trenches 10 (trenches) having a high aspect ratio for trench-isolated smart power technologies comprising thick (ca. 50 μm thick) active layers 24 in SOI silicon wafers 20, 22, 24. Through the geometric design of the isolation trenches 10a, 10b, 10c, 10d, the manufacturing process is simplified. The number of manufacturing steps required is reduced. Error rates and manufacturing costs are reduced.
An integrable power transistor for voltages of around 700 V is described, which can be produced with an active silicon layer having a thickness of approximately 50 µm using thick-film SOI technology. The construction is a combination of a DMOS transistor with a vertical drift zone and a unipolar conduction mechanism with a lateral IGBT. The drain region of the vertical DMOS transistor is formed by a buried, highly doped, lateral layer (6) and led to the surface by the vertical, highly doped layer (5) at the trench sidewall (4). The drain connection (14) of the DMOS transistor is configured such that it simultaneously functions as a connection of the IGBT emitter.
Disclosed is a method for electrically controlling the operating temperature of MOS-controlled semiconductor power components. In said method, the electric resistance of the gate electrode material, and thus the temperature, is measured between two contact points (8, 9) on the gate electrode (4) by means of a test voltage that is superimposed on the gate voltage (UG) during operation of the component, the temperature coefficient of the electric resistance being known. The power loss on the gate electrode is adjusted by means of the gate voltage according to the measured temperature. If a plurality of pairs of contact points are provided, at least one of which is disposed in parts of the gate electrode (4) that are electrically isolated from each other, the temperature can be measured and controlled in a location-specific and accurate manner and quasi without delay. Components comprising additional contacts for carrying out said method are also described.
The invention is intended to specify an electrical measuring method for an operating temperature and a modified component for carrying out the method which improves the monitoring of the component. Measured temperature values are intended to be delivered without any time delay and without requiring additional surfaces for temperature sensors. Location-related temperature values need to be able to be measured. The invention proposes a method for said location-related electrical measurement of the operating temperature of a likewise proposed MOS power component with a gate electrode network comprising a material whose temperature coefficient of the electrical resistance is known. The gate electrode network is divided into a plurality of measuring sections with contact point pairs which are respectively connected to contacts (71.1, 72.1; 71.2, 72.2; 71.3, 7; 72.3, 7). The contact points in each contact point pair are at a certain distance from one another, and each of the measuring sections situated between the contact point pairs is respectively electrically insulated from the other measuring sections, so that there is no electrical influencing between the measuring sections. The electrical resistances of the measuring sections are measured directly on the gate electrode network during the operation of the semiconductor power component when gate voltages are applied between the contact points of the gate electrode (4) using measuring voltages (u1,u2,u3) superimposed on the gate voltages. The electrical resistances of the measuring sections are used to determine the temperatures of the MOS semiconductor power component on the measuring sections.
G01K 7/16 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using resistive elements
72.
LOCATION-RELATED ADJUSTMENT OF THE OPERATING TEMPERATURE DISTRIBUTION OR POWER DISTRIBUTION OF A SEMICONDUCTOR POWER COMPONENT, AND COMPONENT FOR CARRYING OUT SAID METHOD
Described are a method for adjusting the operating temperature of MOS power components consisting of a plurality of identical individual cells as well as a component for carrying out said method. As a characteristic feature, the gate electrode network (4) of the active chip region is subdivided into several gate electrode network sectors (B1, B2, B3) which are electrically isolated from one another by means of isolating points and to each of which a different gate voltage is fed via corresponding contacts.
G01K 7/16 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using resistive elements
G05D 23/19 - Control of temperature characterised by the use of electric means
73.
LOCATION-RELATED ADJUSTMENT OF THE OPERATING TEMPERATURE DISTRIBUTION OR POWER DISTRIBUTION OF A SEMICONDUCTOR POWER COMPONENT, AND COMPONENT FOR CARRYING OUT SAID METHOD
Described is a method for adjusting the operating temperature of MOS power components composed of a plurality of identical individual cells as well as a component for carrying out said method. As a characteristic feature, the gate electrode network (4) of the active chip region is subdivided into several gate electrode network sectors (B1, B2, B3) which are electrically isolated from one another by means of isolating points and to each of which a different gate voltage is fed via corresponding contacts.
a) for improving the optical behavior of components and apparatuses and/or improving the behavior of sensors by increasing the active surface area. The nanostructure (2) is produced by means of a special RIE etching process, can be modified regarding the composition of the materials thereof, and can be provided with adequate coatings. The amount of material used for the base layer (3) can be reduced by supplying a buffer layer (406). Many applications are disclosed.
A DMOS-transistor having enhanced dielectric strength includes a first well region. A highly doped source region is located in the first well region and is complementarily doped thereto. A highly doped bulk connection region is located in the first well region and has the same type of doping as the first well region. A gate electrode and a gate insulation layer for forming a transistor channel are included on a surface of the first well region. The DMOS-transistor further comprises an isolation structure, a highly doped drain doping region, and a second well complementarily doped to the first well region. The second well accommodates the first well region and the drain doping region. A highly doped region is formed at least adjacent to the second well and has the same type of doping as the second well for enhancing the dielectric strength of the highly doped source region.
What is proposed is a test structure for checking the positional precision of the process steps of a metallization process in the manufacture of microelectronic circuits. An electrically conducting substrate layer (1) has a geometrically limited surface extent. Provided are a first electrically insulating layer (2) disposed on top of the substrate layer (1) and a conductive layer (3) to be contacted lying on top of the first electrically insulating layer (2), said conductive layer having a geometrically limited surface extent matched relative to the pre-defined positional precision and size of four penetrating conductors (4). A second electrically insulating layer (5) located on top of the conductive layer (3) has four penetrating conductors (4) that lie in a definite position relative to one another and to the conductive layer (3) to be contacted. An electrically conducting connection layer (6) located on top of the second electrically insulating layer (5) is connected to the penetrating conductors (4). By overlapping the surface extent of the penetrating conductors (4) with the conductive layer (3) contact is achieved between the connection layer (6) and the conductive layer. At least one electrical connection to the substrate layer (1) and at least one electrical connection to the connection layer (6) is provided, wherein when a voltage is applied to the connections (7, 8) a determination must be made whether a current path exists between the connection layer (6) and the substrate layer (1). The test structure is used in a method for checking the positional precision in the manufacture of ICs.
A Voltage-Adaptor capable of converting an externally supplied high voltage connected e.g. to the drain of a MOS or other semiconductor device to a lower voltage. The device comprises a first structure (225) comprising an at least partially conducting material, the voltage adaptor being arranged to influence a first voltage at a portion of a second structure (222) comprising a semiconductor material such that the first voltage at said portion of the second structure is different from a second voltage applied to the second structure, wherein the first structure is arranged to be connected to a bias voltage, and the voltage adaptor further comprises an insulating material (155) arranged to separate the first and second structures.
A Metal Oxide Semiconductor (MOS) transistor comprising: a source; a gate; and a drain, the source, gate and drain being located in or on a well structure of a first doping polarity located in or on a substrate; wherein at least one of the source and the drain comprises a first structure comprising: a first region forming a first drift region, the first region being of a second doping polarity opposite the first doping polarity; a second region of the second doping polarity in or on the first region, the second region being a well region and having a doping concentration which is higher than the doping concentration of the first region; and a third region of the second doping polarity in or on the second region. Due to the presence of the second region the transistor may have a lower ON resistance when compared with a similar transistor which does not have the second region. The breakdown voltage may be influenced only to a small extent.
Disclosed is an arrangement for testing an embedded circuit as part of a whole circuit located on a semiconductor wafer. Disclosed is an integrated semiconductor arrangement comprising a whole circuit (8) with inputs and outputs (7), an embedded circuit (1) that is part of the whole circuit (8) and is equipped with embedded inputs and outputs which are not directly connected to the inputs and outputs (7) of the whole circuit (8); a test circuit (2, 5, 6) that is connected to the embedded inputs and outputs in order to feed and read out signals during a test phase. A separate supply voltage connection (3) is provided which is used for separately supplying the embedded circuit (1) and the test circuit (2, 5, 6) independently of a supply voltage of the whole circuit (8) such that the inputs of the whole circuit do not have to be connected for testing the embedded circuit while only the inputs and outputs that are absolutely indispensable for testing the embedded circuit need to be connected to a test system.
G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
G01R 31/02 - Testing of electric apparatus, lines, or components for short-circuits, discontinuities, leakage, or incorrect line connection
G01R 31/26 - Testing of individual semiconductor devices
G01R 31/36 - Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
80.
TESTING MECHANICAL-ELECTRICAL PROPERTIES OF MICROELECTROMECHANICAL SENSORS (MEMS)
The invention relates to testing acoustic microelectromechanical sensors. To this end, a test device is proposed for the mechanical-electrical properties of microelectromechanical sensors (MEMS) comprising parts that can vibrate mechanically and that are present in a plurality on a carrier film (1). The test device (4) has a test card and contact pins (5) to be placed on contact points of the microelectromechanical sensors are connected to the test card by means of electrical connections. A sound source (6) is present that can be positioned at a predefined distance from the carrier film (1). A reference sensor (7) is present at a certain distance from the sound source (6). Sound guiding channels are designed for a sound transmission connection between the sound source (6), one of the microelectromechanical sensors on the carrier film (1), and the reference sensor (7). Said construction is mechanically robust and therefore insusceptible to interference and allows a vibration-damped behavior of the sound source relative to interfering vibrations from outside. Corresponding interference due to mechanical vibrations in the area around the sound source is thereby reduced.
A system and a method for checking the ESD behavior, wherein a circuit (7) is automatically checked on the circuit plan level, in that technology-specific ESD data are provided in a database (2) for all components occurring in the circuit and are used for analyzing the ESD behavior, without complex circuit simulations being necessary, for example, based on front end or back end data, in consideration of the layout.
In an integrated circuit, a light-sensitive area is protected from radiation, in that a light-blocking layer sequence (504) is disposed above the light-sensitive area. The light-blocking layer sequence has one or more metal layers (504a) and a silicon layer (503b, 1) for absorption. A moth-eye structure (504c) is provided on the silicon layer. A reflection of the incident radiation is thus minimized so that diffused light can also be effectively kept away from the light-sensitive area below the light-blocking layer sequence (504).
A description is given of a method for producing isolation trenches (32, 34) with different sidewall dopings on a silicon-based substrate wafer for use in a trench-isolated smart power technology. In this case, a first trench (32) having a first width and a second trench (34) having a second width, which is greater than the first width, are formed using a hard mask (30). The sidewalls of the first and second trenches are doped in accordance with a first doping type in order to produce sidewalls having a first doping. A material layer (50, 51, 60, 51) is deposited with a thickness determined so as to fill the first trench (32) completely to beyond the hard mask and to maintain a gap (34a) in the second trench (34). By means of isotropic etching, the material layer is removed from the second trench, but residual material of the material layer is maintained in the first trench. A further doping of sidewalls of the first trench or of the second trench in the presence of the residual material is then performed.
For bonding a donor wafer (1) and a system wafer (9), an edge bead (3) of an epitaxial layer (2) on the donor wafer is flattened or completely removed by an etching, such that a reliable contact after bonding through to the edge region (5, 6) is possible. The etching mask is produced with the aid of a resist layer (4) and also by removal of resist at the edge, free exposure and development without a special photomask.
A method of manufacturing a semiconductor device comprises the steps of, in sequence: depositing a first silicon layer; patterning the first silicon layer to obtain a first silicon region; implanting a first dopantinto a first part of the first silicon region, the first part ofthe first silicon region defined using a first mask; depositing a second silicon layer; patterning the second silicon layer to obtain a second silicon region; and implanting a second dopant into a second part of the first silicon region, the second part of the first silicon regiondefined by the first mask and the second silicon region. A device comprises a semiconductor layer (6); a first doped region (5) within the semiconductor layer; a second doped region (7) within the first doped region (5); and a silicon layer (9) disposed over a part of the semiconductor layer; wherein the silicon layer is disposed over a part of the first doped region (5) but not over the second doped region (7).
H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
H01L 21/77 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
86.
MIM CAPACITOR STRUCTURE AND METHODS OF MANUFACTURING THE SAME
A device comprises a substrate (22); a first MiM capacitor (10, 20, 11) disposed over the substrate; and a second MiM capacitor (10', 20', 11') disposed over the first MiM capacitor. The first MiM capacitor and the second MiM capacitor are electrically connected in parallel. The two MiM capacitors are vertically stacked one above the other. Each MiM capacitor comprises an interconnection layer (10, 10') of the CMOS process as one plate and a thinner conductive layer (11, 11') as the second plate, with an insulating layer (20, 20') disposed therebetween. This allows each MiM capacitor to be formed between two CMOS process interconnection layers. The second plate of the second MiM capacitor is substantially co-extensive with the second plate of the first MiM capacitor, and is disposed substantially directly over the second plate of the first MiM capacitor. The same mask may be used to pattern the second plate of the second MiM capacitor and the second plate of the first MiM capacitor. This minimises the number of masks required, and so minimises the mask investment cost.
A transistor comprising a source region, a gate (10), a drain region (13), a gate dielectric layer (11, 12) for isolating the gate from an underlying body (14, 6), and a well region (5) at least partially extending under the gate to create a channel region, wherein the gate dielectric layer comprises a thinner portion (12) and a thicker portion (11), and wherein the thickness of the thicker portion is no more than 200nm.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
88.
Layout method for vertical power transistors having a variable channel width
The invention relates to a simulation and/or layout process for vertical power transistors as DMOS or IGBT with variable channel width and variable gate drain capacity which can be drawn and/or designed by the designer with the respectively desired parameters of channel width and gate drain capacity and the parameters of volume resistance and circuit speed, which are correlated therewith, and whose electrical parameters can be described as a function of the geometrical gate electrode design. Here, both discrete and integrated vertical transistors may be concerned.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
The invention discloses a semiconductor structure for the production of a carrier wafer contact in trench-isolated SOI disks, wherein said semiconductor structure can be used as deep contact (7, 6, 30') to the carrier wafer (1) of a thick SOI disk and/or as trench isolation (40). For both structures, the same method steps are used for the use thereof as deep contact to the carrier wafer of the thick SOI disk and also as trench isolation.
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 21/786 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being other than a semiconductor body, e.g. insulating body
The invention relates to a method for selective material deposition for sensitive structures in microsystems technology for producing mechanical adjustment structures (6, 5) for a vapor penetration mask (8), the adjustment structures on the component disc (7) and the mask being created using the same structuring method. Complementary adjustment structures can be produced thereon with a very high degree of precision. KOH etching in silicon can be used in order to create equally inclined flanks (2, 2a) in a depression and a complementary protrusion.
The invention relates to a method and a through-vapor mask for depositing layers in a structured manner by means of a specially designed coating mask (1) which has structures (4) that accurately fit into complementary alignment structures (5) of the microsystem wafer (2) to be coated (8) in a structured manner such that the mask and the wafer can be accurately aligned relative to one another. Very precisely defined areas on the microsystem wafer are coated (8) through holes (7, 7') in the coating mask, e.g. by means of sputtering, CVD, or evaporation processes.
The present invention provides a method for fabricating a MOS transistor (100) with suppression of edge transistor effect. In one embodiment of an NMOS, an elongate implant limb (110, HOa, 114) extends from each of two sidewalls (14a, 14b) of a p-type well (14) to partially wrap around each respective longitudinal end of the gate (20) and to overlay a portion thereof. In another embodiment, the elongate implant limb (110, 110a) extends into the drain/source drift region (32, 42). The NMOS transistor (100) thus fabricated allows the NMOS transistor to operate at relatively high voltages with reduced drain leakage current but with no additional masks or process time in the process integration.
An SOI device comprises an isolation trench defining a vertical drift zone, a buried insulating layer to which the isolation trench extends, and an electrode region for emitting charge carriers that is formed adjacent to the insulating layer and that is in contact with the drift zone. The electrode region comprises first strip-shaped portions having a first type of doping and second strip-shaped portions having a second type of doping that is inverse to the first type of doping. A first sidewall doping of the first type of doping is provided at a first sidewall of the isolation trench and a second sidewall doping of the second type of doping is provided at a second sidewall of the isolation trench. The first strip-shaped portions are in contact with the first sidewall doping and the second strip-shaped portions are in contact with the second sidewall doping.
H01L 31/11 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by two potential barriers or surface barriers, e.g. bipolar phototransistor
H01L 27/082 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
H01L 27/102 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
2 deposition is then performed using a low pressure CVD process to deposit oxide near steps formed previously and/or at the displaced bottlenecks to seal the voids. The deposition process is stopped when the sealed portions of the oxide layer above the voids are grown above the semiconductor wafer surface.
The aim of the invention is to integrate low-voltage logic elements and high-voltage power elements in one and the same silicon circuit. Said aim is achieved by dielectrically chip regions having different potentials from each other with the aid of isolation trenches (10). In order to prevent voltage rises at sharp edges on the bottom of the isolation trenches, said edges are rounded in a simple process, part of the insulating layer (2) being isotropically etched.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
96.
METHOD FOR PRODUCING AN ELECTRIC CARRIER WAFER CONTACT FOR A FRONT-SIDED CONNECTION
The invention relates to a method for producing an electric carrier wafer contact having a front-sided connection for CMOS-components in SOI-technology using thick layers (2) in the order of individual 쎽m on the silicon carrier layer (4). At the end of the CMOS-process, the carrier wafer is uncovered by etching a recess (6a) in the height of the bonding island, the entire stack that consists of intermediate insulator layers, the active silicon layer (2) and trenched oxide (3) being attacked by etching. In said area, the bonding island is formed by means of a metallisation layer that is structured in the subsequent process. Said layer establishes an electric connection with other bonding islands of the components later in the mounting process by wire bonding (7). Due to said method, costs are cut and output is increased. The thus produced components are extremely reliable and can be used in different applications, for example, on various electric potentials of substrate contacts for SOI-components.
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
97.
Method for the construction of vertical power transistors with differing powers by combination of pre-defined part pieces
A method for designing a first vertical MOS power transistor having a specified design power level. The method comprises the steps of composing a layout of the vertical MOS power transistor as a combination of at least partly differing layout part pieces, each of the part pieces having known design data, the part pieces including at least one first layout part piece comprising a given number of single transistor cells, and adjusting the specified design power level of the first vertical MOS power transistor by using the known design data of the part pieces and based on the layout combination of the part pieces.
The invention relates to a BiMOS semiconductor component having a semiconductor substrate wherein, in a first active region, a depletion-type MOS transistor is formed comprising additional source and drain doping regions of the first conductivity type extending in the downward direction past the depletion region into the body doping region while, in a second active region, (101), a bipolar transistor (100) is formed, the base of which comprises a body doping region (112) and the collector of which comprises a deep pan (110), wherein an emitter doping region (114) of the first conductivity type and a base connection doping region (118) of the second conductivity type are formed in the body doping region. The semiconductor element can be produced with a particularly low process expenditure because it uses the same basic structure for the doping regions in the bipolar transistor as are used in the MOS transistor of the same semiconductor component.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
99.
MASK-SAVING PRODUCTION OF COMPLEMENTARY LATERAL HIGH-VOLTAGE TRANSISTORS WITH A RESURF STRUCTURE
The invention relates to a method for the production of a first lateral high-voltage MOS transistor and a second lateral high-voltage MOS transistor complimentary thereto on a substrate, wherein the first and second lateral high-voltage MOS transistors each have a conductivity type opposite a drift region, comprising the steps of providing a substrate of a first conductivity type comprising a first active region for the first lateral high-voltage MOS transistor and a second active region for the second lateral high-voltage MOS transistor, and the producing at least one first doping region of the first conductivity type in the first active region and, on the other hand, in the second active region, a drain extension region of the first conductivity type extending from the substrate surface to the interior of the substrate, which allows a simultaneous implantation of doping material in the first and second active regions through respective mask openings of one and the same mask.
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
100.
SEMICONDUCTOR COMPONENT WITH INTEGRATED HALL EFFECT SENSOR
The invention relates to a semiconductor component with an integrated circuit on a semiconductor substrate, comprising in a first active region a Hall effect sensor and, in a second active region, a lateral high-voltage MOS transistor. The semiconductor component according to the present invention is characterized in that the structure of the integrated Hall effect sensor is strongly dependent upon the structure of a high-voltage DMOS transistor. The integrated Hall effect sensor is similar in some structural elements to a high-voltage DMOS transistor with a double RESURF structure that is known per se. The control contacts of the Hall effect sensor correspond to source and drain contacts of the high-voltage DMOS transistor. The semiconductor component according to the present invention thus allows a simplification of the process integration.
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
