There is provided a semiconductor device including: an emitter electrode which is provided above an semiconductor substrate, and which has a first main region, a second main region, and a third main region; a gate pad which is provided above the semiconductor substrate; a gate metal layer which is electrically connected to the gate pad; and a gate runner portion which is electrically connected to the gate metal layer, in which a plurality of trench portions have a plurality of gate trench portions, the emitter electrode has a first emitter bridge portion which connects the first main region to the second main region, and a second emitter bridge portion which connects the second main region to the third main region, and below the first emitter bridge portion, a gate trench portion different from a gate trench portion which is provided below the second emitter bridge portion is provided.
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
2.
PANEL STRUCTURE, DOOR PANEL, AND METHOD OF MANUFACTURING PANEL STRUCTURE
A panel structure including: a first surface plate and a second surface plate forming a pair; and a core plate disposed between the first and second surface plates, the core plate having a plurality of protrusions arranged in a matrix on a first main surface thereof facing the first surface plate. Each of the plurality of protrusions has a protrusion tip surface facing the first surface plate. The core plate and the first surface plate are bonded to each other such that each of the protrusion tip surfaces is in contact with the first surface plate and is constrained by a plurality of planar separate constraint regions corresponding to a planar shape of said each protrusion tip surface.
A method of manufacturing a semiconductor device, including: preparing a semiconductor substrate having a single crystal silicon region, and a polycrystalline silicon region; forming an interlayer insulating film covering the single and polycrystalline silicon regions; forming in the interlayer insulating film, a plurality of first contact holes exposing the single crystal silicon region and a second contact hole exposing the polycrystalline silicon region; performing an ion implantation in the single crystal silicon region exposed by the first contact holes; etching the single and polycrystalline silicon regions, thereby concurrently forming a plurality of first contact trenches and a second contact trench respectively continuous with the plurality of first contact holes and the second contact hole; and forming a first electrode and a second electrode respectively electrically connected to the single crystal silicon region in the first contact trenches and the polycrystalline silicon region in the second contact trench.
A semiconductor device, including first and second semiconductor chips, an output terminal, a positive terminal, a negative terminal, and an insulated circuit substrate. The insulated circuit substrate has first to third conductive circuit pattern disposed on an insulating plate. The first conductive circuit pattern includes a first mounting portion on which the first semiconductor chip is mounted, and a first terminal portion to which the output terminal is bonded. The second conductive circuit pattern includes a second mounting portion on which the second semiconductor chip is mounted, and a second terminal portion to which the positive terminal is bonded. The third conductive circuit pattern includes a third terminal portion to which the negative terminal is bonded. The first and second mounting portions have a gap therebetween. The first to third terminal portions are sequentially arranged in the gap on the upper surface of the insulating plate.
Provided is a semiconductor device that can suppress warpage of a semiconductor module. The semiconductor device includes a semiconductor module including a heat dissipation plate, an electrically-conductive plate bonded to a top surface of the heat dissipation plate by a first resin sheet, and a semiconductor chip bonded to a top surface of the electrically-conductive plate by a bonding material. A cooler is bonded to a bottom surface of the semiconductor module by a second resin sheet. A resin sheet having higher electrical insulation than the second resin sheet is used as the first resin sheet. A resin sheet having higher thermal conductivity than the first resin sheet is used as the second resin sheet.
H10D 80/20 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising capacitors, power FETs or Schottky diodes
A silicon carbide semiconductor device, including: a semiconductor substrate; a first semiconductor region; a second semiconductor region; a device element structure having a pn junction; a peripheral region surrounding a periphery of the device element structure; a first electrode; a second electrode; a plurality of withstand voltage regions; and a voltage withstanding structure configured by the withstand voltage regions and having an overall impurity concentration gradually decreasing in a direction from an active region to a termination region. The peripheral region has an outer end that is orthogonal to the first main surface. Bottoms of the withstand voltage regions are positioned deeper in a depth direction from a bottom of the peripheral region. A first withstand voltage region, which is an innermost one of the withstand voltage regions, surrounds the peripheral region so as to cover an outer-side corner of the bottom of the peripheral region.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
Provided is a technology capable of effectively utilizing power of a distributed power supply at the time of power failure of a higher-level power system. A power system 1 according to an embodiment of the present disclosure comprises: a high-voltage battery 41 mounted on an electric vehicle 40; an inverter device 43 mounted on the electric vehicle 40 and electrically connected to the high-voltage battery 41; an electric load 21 provided in a home HM or a facility FC; a power supply unit 22 provided in the home HM or the facility FC and electrically connected to a power system 10 to supply power to the electric load 21; a power connection unit PC for electrically connecting between the power supply unit 22 and the electric vehicle 40; and a switch 23 for switching the electrical connection/disconnection between the power supply unit 22 and the power system 10. The switch 23 is switched to a disconnection state at the time of power failure of the power system 10. The inverter device 43 operates so as to function as a predetermined power supply for the power supply unit 22 using the power of the high-voltage battery 41 at the time of power failure of the power system 10.
H02J 3/32 - Arrangements for balancing the load in a network by storage of energy using batteries with converting means
B60L 55/00 - Arrangements for supplying energy stored within a vehicle to a power network, i.e. vehicle-to-grid [V2G] arrangements
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
H02J 7/34 - Parallel operation in networks using both storage and other DC sources, e.g. providing buffering
8.
STEAM-GENERATING HEAT PUMP DEVICE, METHOD FOR CONTROLLING STEAM-GENERATING HEAT PUMP DEVICE, AND PROGRAM FOR CALCULATING FLOW RATE OF SEPARATED CIRCULATING WATER
Provided are: a steam-generating heat pump device in which the flow rate of separated circulating water can be determined; a method for controlling the steam-generating heat pump device; and a program for calculating the flow rate of separated circulating water. A steam-generating heat pump device 10 includes a steam-generating part 14 and a heat pump part 12. The steam-generating part 14 comprises a condenser 22 and a gas-liquid separator 34 and includes a thermosyphon circuit where confluence water formed by the confluence of supply water supplied from a feedwater pump 38 with separated circulating water, which has been separated by the gas-liquid separator 34, at a confluence point J is boiled in the condenser 22 and returned to the gas-liquid separator 34. The heat pump part 12 vaporizes a refrigerant with heat collected from heat source water, compresses the refrigerant, and boils the confluence water with the refrigerant in the condenser 22. A control unit 16 calculates a flow rate Mc of the separated circulating water on the basis of a weighted-mean equation from a temperature Tc of the separated circulating water before the confluence point J of the separated circulating water, a temperature Tp0 of the supply water before the confluence point J, a flow rate Mp of the supply water, and a temperature Tj of the confluence water.
Provided is a technology capable of improving the manufacturing yield of a semiconductor device. A semiconductor device (1A) according to an embodiment of the present technology comprises: an insulating circuit board (10) in which a first conductive plate (11b) and a second conductive plate (11c) that are electrically separated from each other are provided to the side of the insulating circuit board (10) that is toward one surface part and a heat dissipation plate (13) is provided to the side that is reverse of the one surface part; a transistor chip (20) which is mounted on the first conductive plate (11b); a temperature sensor chip (30) which has a main surface part (31a) and a rear surface part (31b) that are positioned on opposite sides of the temperature sensor chip (30), where each of an anode electrode (32a) and an cathode electrode (32b) is disposed on the main surface part (31a) and the rear surface part (31b) is connected to the second conductive plate (11c); and a conductive path (51) which electrically connects the second conductive plate (11c) and either electrode among the anode electrode (31a) and the cathode electrode (31b).
There is provided a semiconductor device including: a SiC substrate which has an upper surface and a lower surface; an element structure which is formed on the upper surface of the SiC substrate; a lower surface region which is exposed on at least a part of the lower surface of the SiC substrate, and which has a crystal structure different from that on an upper surface side; and a lower surface electrode which is in contact with the lower surface of the SiC substrate, in a region including at least the lower surface region, in which the lower surface region includes 3C-SiC, and a silicide layer is not formed between the lower surface electrode and the lower surface of the SiC substrate.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
There is provided a semiconductor device including: a SiC substrate which has an upper surface and a lower surface; an element structure which is formed on the upper surface of the SiC substrate; a metal silicide portion which is formed at a part of the lower surface of the SiC substrate; and a lower surface electrode which is in contact with the metal silicide portion and with an exposed region of the lower surface which is not covered by the metal silicide portion, in which at least a part of the exposed region has a crystal structure different from that of a contact region of the SiC substrate which is in contact with the metal silicide portion.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
A switching control circuit for a power supply circuit including a transformer and a transistor controlling an inductor current flowing through the transformer. The switching control circuit includes: a driver circuit driving the transistor, based on a feedback voltage corresponding to an output voltage and an current flowing through the transistor; a first detection circuit detecting whether the current flowing through the transistor is greater than a first current; a second detection circuit detecting whether a load current flowing through a load of the power supply circuit is greater than a second current; and a control circuit controlling the driver circuit to stop switching the transistor, when the inductor current flowing through the transistor has been greater than the first current for a first time period, or when the load current has been greater than the second current for a second time period longer than the first time period.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A non-condensable gas reinjection system is provided for use in a geothermal power plant including a gas-liquid separator configured to separate geothermal fluid obtained from a production well into a first gas and a first liquid, an evaporator configured to exchange heat between the first gas and a working fluid, a turbine configured to be rotated by the working fluid discharged from the evaporator, and a condenser configured to cool the working fluid that has rotated the turbine and to condense the working fluid into a liquid. The non-condensable gas reinjection system includes: a pump configured to pressurize a third liquid to be sent to a reinjection well; and an ejector configured to be driven by the third liquid, suction a non-condensable gas contained in the first gas and remaining uncondensed in the evaporator, and discharge a fourth liquid in which the third liquid and the non-condensable gas are mixed.
F24T 10/20 - Geothermal collectors using underground water as working fluidGeothermal collectors using working fluid injected directly into the ground, e.g. using injection wells and recovery wells
F03B 13/00 - Adaptations of machines or engines for special useCombinations of machines or engines with driving or driven apparatusPower stations or aggregates
F22B 1/16 - Methods of steam generation characterised by form of heating method by exploitation of the heat content of hot heat carriers the heat carrier being hot liquid or hot vapour, e.g. waste liquid, waste vapour
Provided is a semiconductor device comprising a semiconductor substrate, trench portions, mesa portions, an emitter electrode, and an interlayer dielectric film with a contact hole formed therein, wherein the mesa portions include a channel mesa portion having a first conductivity type emitter region on an upper surface of the semiconductor substrate and a second conductivity type base region between the emitter region and the drift region, and connected to the emitter electrode by the contact hole; and a floating mesa portion with no contact hole above or in which a length of the contact hole above is shorter than that of the contact hole above the channel mesa portion, and at a lower end of at least one of the trench portions sandwiching the channel mesa portion, a second conductivity type second trench bottom region having a higher concentration than the base region is provided.
A switching control circuit for a power factor correction circuit configured to generate an output voltage from an alternating current (AC) voltage, the power factor correction circuit including an inductor configured to receive a rectified voltage corresponding to the AC voltage, and a transistor configured to control an inductor current flowing through the inductor. The switching control circuit is configured to control switching of the transistor. The switching control circuit includes: a driving signal output circuit configured to, when a peak value of the inductor current in a half cycle of the AC voltage is smaller than and greater than a first predetermined value, output a driving signal to operate the power factor correction circuit in a critical mode and in a continuous mode, respectively; and a driver circuit configured to drive the transistor, in response to the driving signal.
An ejector-type cooling device 10A includes a condenser 18, a refrigerant pump 12, a steam generator 14, an evaporator 20, an ejector 16, and an intermediate heat exchanger 24, the cooling device 10A further comprising: a drive pressure sensor 41 for detecting the drive pressure of a drive flow; a drive temperature sensor 42 for detecting the drive temperature of the drive flow; and a control unit 50A for calculating a drive saturation temperature on the basis of the drive pressure, and performing feedback control for reducing or stopping the rotation speed of the refrigerant pump 12 when the degree of drive overheating, which is the difference between the drive temperature and the drive saturation temperature, is less than a preset reference value.
This steam-generating heat pump device operates stably without being affected by a temperature condition. A steam-generating heat pump device 10A comprises: a steam generation section 14 which constitutes a thermosiphon circuit including a condenser 22 and a gas-liquid separator 34 and in which, of liquid-phase separated circulation water and separated blow water to be blown down that have been separated in the gas-liquid separator 34, the separated circulation water merges at a junction point J with supply water supplied from a water supply pump 38 after exchanging heat with a high temperature fluid in a supercooler 24, and the resulting merged water is boiled in the condenser 22 and supplied to the gas-liquid separator 34; a heat pump section 12 that boils the merged water in the condenser 22 using a refrigerant; a supply water bypass passage 50 provided in parallel with a supply water passage of the supercooler 24; a first switching valve 54a for opening/closing the supply water passage; and a second switching valve 54b for opening/closing the supply water bypass passage 50.
F22B 1/16 - Methods of steam generation characterised by form of heating method by exploitation of the heat content of hot heat carriers the heat carrier being hot liquid or hot vapour, e.g. waste liquid, waste vapour
F22D 1/18 - Feed-water heaters, e.g. preheaters with water tubes arranged otherwise than in the boiler furnace, fire tubes, or flue ways and heated indirectly
A columnar polycrystalline SiC ingot (3) is produced by forming a polycrystalline SiC film (2) at a constant thickness over the entire side surface (1a) of a columnar support substrate (1) by means of a CVD method. A plurality of polycrystalline SiC wafers (4) can be easily produced from the polycrystalline SiC ingot (3) by means of existing slicing. In addition, as another processing of the polycrystalline SiC ingot (3), a plurality of polycrystalline SiC support substrates, each of which can be used as the support substrate (1), can be produced by vertically cleaving the polycrystalline SiC ingot (3). In addition, a plurality of polycrystalline SiC support substrates, each of which can be used as the support substrate (1), can be produced by pulverizing SiC processing debris generated during the slicing or the cleaving of the polycrystalline SiC ingot (3) by means of an existing pulverization method to obtain a powder material (5), and by sintering the powder material (5). This improves the mass productivity of the polycrystalline SiC ingot (3) and the polycrystalline SiC wafers (4).
A semiconductor device, including: a semiconductor substrate having an active region and a termination region surrounding a periphery of the active region in a plan view; a first semiconductor region provided on a surface of the semiconductor substrate; a second semiconductor region provided in the first semiconductor region at a surface thereof, in an end portion of the termination region; an insulating film provided at the surface of the first semiconductor region; and a polyimide film selectively provided at a surface of the insulating film. The insulating film covers the first and second semiconductor regions. The polyimide film covers the surface of the insulating film. The semiconductor device further has, in the end portion of the termination region, an uneven portion through which the first semiconductor region and the second semiconductor region are exposed.
A method of manufacturing a trench-type silicon carbide semiconductor device that includes a drift layer of a first conductivity type, a base layer of a second conductivity type formed on the drift layer, and a plurality of trenches penetrating through the base layer and reaching the drift layer. The method includes forming a co-doped region of the first conductivity type by introducing a first impurity of the first conductivity type and a second impurity of the second conductivity type into a portion of the drift layer between two of the plurality of trenches.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
Provided is a semiconductor device comprising a semiconductor substrate having an upper surface and a drift region, trench portions provided inwardly from the upper surface of the semiconductor substrate, mesa portions each being a region sandwiched between two of the trench portions; an emitter electrode, and an interlayer dielectric film with a contact hole formed, wherein the mesa portions include a channel mesa portion having a first conductivity type emitter region and a second conductivity type base region on the upper surface and connected to the emitter electrode by the contact hole, and a hole-extraction mesa portion with no channel formed and connected to the emitter electrode by the contact hole, and a first conductivity type first trench bottom region having a higher concentration than the drift region is provided at a lower end of at least one of the trench portions sandwiching the hole-extraction mesa portion.
Provided is a semiconductor device comprising a semiconductor substrate, a front-surface-side metal layer provided above the semiconductor substrate, and a protective film provided above the semiconductor substrate. The protective film has: a first end portion having a first taper angle; and a second end portion having a second taper angle different from the first taper angle. Also provided is a method for manufacturing a semiconductor device, the method comprising: a step for providing a front-surface-side metal layer above a semiconductor substrate; and a step for providing, above the semiconductor substrate, a protective film in which a first end portion and a second end portion have different taper angles.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
Provided is a method for manufacturing an insulated-gate semiconductor device capable of suppressing latch-up breakdown. This method for manufacturing an insulated-gate semiconductor device comprises: a step for forming a second conductivity-type base region (3) on the upper surface side of a first conductivity-type drift layer (1) provided on a semiconductor substrate (100); a step for forming a contact trench (8) in the depth direction from the upper surface of the base region (3); a step for forming a second conductivity-type base contact region (9) having a higher impurity concentration than the base region (3), the step including a step for ion-implanting a second conductivity-type impurity into the lower surface of the contact trench (8); a step for forming first conductivity-type main electrode regions (4a, 4b), the step including a step for obliquely ion-implanting a first conductivity-type impurity into the side surface of the contact trench (8); and a step for embedding a contact part (11) in the contact trench (8).
There is provided a semiconductor device including a transistor portion and a diode portion, wherein the transistor portion includes: an emitter region which includes a first emitter section of the first conductivity type and a second emitter section which is provided below the first emitter section and has a lower doping concentration than the first emitter section; a trench contact portion which extends from the front surface of the semiconductor substrate in a depth direction of the semiconductor substrate; and a trench contact sidewall region which is provided on a sidewall of the trench contact portion and provided between the trench contact portion and the second emitter section, and the diode portion includes a first conductivity type region of the first conductivity type which is provided above the drift region and in contact with the front surface electrode portion.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
A power converter selectively uses a cell balance mode and a cell imbalance mode, the cell balance mode is a mode in which each of a plurality of single-phase AC output units superimposes only outputs of a number of power conversion cells corresponding to a minimum number of the numbers of available power conversion cells to output single phase AC, and the cell imbalance mode is a mode in which each of the plurality of single-phase AC output units superimposes outputs of all available power conversion cells to output the single-phase AC such that phase differences between line-to-line voltages of adjacent phases among phases are all equivalent.
H02M 5/458 - Conversion of AC power input into AC power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into DC by static converters using discharge tubes or semiconductor devices to convert the intermediate DC into AC using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
A semiconductor device includes: a first conductive plate connected to bottom surfaces of first semiconductor chips; a second conductive plate connected to bottom surfaces of second semiconductor chips; a third conductive plate connected to bottom surfaces of third and fourth semiconductor chips; a first external terminal connected to the first conductive plate; a second external terminal connected to top surfaces of the second semiconductor chips; a third external terminal connected to top surfaces of the third semiconductor chips; and a fourth external terminal connected to top surfaces of the first and fourth semiconductor chips. The first to third external terminals are disposed opposite to the fourth external terminal, and the first and second semiconductor chips are provided closer to the first and second external terminals than the third and fourth semiconductor chips.
This power conversion device comprises: a substrate on which a semiconductor element is mounted; and a smoothing capacitor having a P terminal, which is a positive terminal electrically connected to the substrate, and an N terminal, which is a negative terminal laminated on the P terminal and electrically connected to the substrate. The substrate and the smoothing capacitor are electrically connected, and at least one among the P terminal and the N terminal is in contact with a conductive layer on the surface of the substrate, thereby being electrically connected to the substrate.
H02M 7/48 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
28.
CONTROL SUBSTRATE, POWER CONVERSION DEVICE, AND VEHICLE
Provided is a control substrate comprising a gate drive unit for controlling driving of a semiconductor device, and a circuit board that has the gate drive unit mounted on the front surface and has a plurality of wiring layers. The circuit board has: a gate potential line electrically connected to a gate terminal of the semiconductor device; and a reference potential line electrically connected to a sub-terminal of the semiconductor device. In an outer layer on the back surface side of the circuit board, the periphery of the gate potential line is surrounded by the reference potential line. Provided is a power conversion device comprising: one or more semiconductor devices; a multilayer substrate on which the one or more semiconductor devices are mounted; and a control substrate.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 7/48 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
Provided is a power conversion device comprising: a semiconductor device including a semiconductor element; a laminated substrate having a plurality of wiring layers and electrically connected to the semiconductor device; a gate wiring part connected to a gate terminal of the semiconductor device; and a sub-wiring part connected to a sub-terminal of the semiconductor device. The sub-wiring part surrounds the periphery of the gate wiring part in an arbitrary cross-section of the laminated substrate, and at least a portion of the sub-wiring part is provided on a surface of the laminated substrate. Provided is a vehicle comprising said power conversion device.
H02M 7/48 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
Provided is a semiconductor module including a main circuit portion, a plurality of circuit electrodes, a plurality of main terminals, and a plurality of wires, in each of semiconductor chips, transistor portions and diode portions have a longitudinal side in a second direction, each of semiconductor chips has a plurality of end sides including a gate-side end side, each of the gate-side end sides is arranged facing a same side in a top view, the plurality of main terminals are arranged on a same side in relation to the main circuit portion so as not to sandwich the main circuit portion in a top view, each of the plurality of wires has a bonding portion, and a longitudinal direction of the bonding portion has an angle in relation to the second direction.
The present invention provides a semiconductor device in which JFET resistance is suppressed, and a manufacturing method for the same. Provided is a semiconductor device comprising: a drift layer (2) of a first conductivity type; a base region (5) of a second conductivity type provided on an upper surface side of the drift layer; a main region (6) of the first conductivity type provided on an upper surface side of the base region; a pair of trenches (8) sandwiching the main region and the base region from side surface sides; an insulated gate electrode structure embedded in each of the pair of trenches; and gate bottom protection regions (4) of the second conductivity type provided on lower sides of the trenches. The width of the base region sandwiched between the pair of trenches is 0.2 µm or less. The dimension of a bottom part of each of the trenches in the width direction gradually decreases downward. When a portion of each of the trenches that is in contact with the base region is defined as a first portion (82) and the width of the first portion is defined as a first width (d2), the width (d1) of each of the gate bottom protection regions is narrower than the first width (d2).
Provided is a power conversion device comprising a positive terminal, a negative terminal, and an output terminal. The power conversion device also comprises : a semiconductor device including a semiconductor element; a laminated substrate that has a plurality of wiring layers and that is electrically connected to the semiconductor device; a cooling body provided on a rear side of the laminated substrate; and a thermal interface provided between the laminated substrate and the cooling body. The laminated substrate has a main current region, and the thermal interface is provided below the main current region between the laminated substrate and the cooling body.
H02M 7/48 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
Provided is a power conversion device provided with a positive electrode terminal, a negative electrode terminal, and an output terminal. This power conversion device is provided with a semiconductor device including a semiconductor element, a laminated substrate that has a plurality of wiring layers including a pattern electrode and is electrically connected to the semiconductor device, an interlayer wiring part that at least partially penetrates the laminated substrate, and a temperature detection unit provided on the front surface of the laminated substrate. The semiconductor device is provided on the rear surface of the laminated substrate. The interlayer wiring part is connected to the semiconductor device and extends from the rear surface toward the front surface side of the laminated substrate. The temperature detection unit is provided above the pattern electrode.
H02M 7/48 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
An insulated gate semiconductor device includes: a drift layer of a first conductivity-type; a base region of a second conductivity-type provided on a top surface side of the drift layer; a main region of the first conductivity-type provided on a top surface side of the base region; and a gate electrode buried, with a gate insulating film interposed, in trenches dug downward from a top surface of the main region, wherein a plurality of mesa parts interposed between the trenches adjacent to each other are arranged in a matrix form, and a width of the respective mesa parts at least in one direction is set to 600 nanometers or smaller.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
A power system includes a plurality of power generation systems capable of supplying power to a power grid, wherein each of the plurality of power generation systems includes a renewable-energy-power-generation facility configured to generate power using renewable energy and a power generation controller configured to control, so as to follow a characteristic curve representative of a relationship between a stability indicator relating to stability of grid power in the power grid and power to be generated by the renewable-energy-power-generation facility, the power to be generated by the renewable-energy-power-generation facility in accordance with the stability indicator, and wherein the power generation controller is configured to adjust the characteristic curve in a direction that causes an increase in the power to be generated in a case in which a supply of renewable energy to the renewable-energy-power-generation facility increases after an occurrence of fluctuation in the stability indicator.
H02J 3/38 - Arrangements for parallelly feeding a single network by two or more generators, converters or transformers
G05B 13/04 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric involving the use of models or simulators
A semiconductor device comprising a semiconductor substrate having an upper surface, wherein the semiconductor substrate has a main transistor portion having a main gate trench portion including a main gate conductive portion, a sense transistor portion having a sense gate trench portion including a sense gate conductive portion, a gate pad provided above the upper surface of the semiconductor substrate, a main gate runner provided above the upper surface of the semiconductor substrate and extending from the gate pad to the main gate conductive portion, a sense gate runner disposed along the sense transistor portion, and a gate runner connection portion connecting the main gate runner and the sense gate runner, and a resistor portion is provided in the gate runner connection portion.
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
Provided is a semiconductor device comprising: an insulating plate; a semiconductor element provided above the insulating plate and having a first control electrode and a second control electrode; a plurality of first conductive patterns provided above the insulating plate and electrically connected to the first control electrode; and a plurality of second conductive patterns provided above the insulating plate and electrically connected to the second control electrode, wherein the plurality of first conductive patterns and the plurality of second conductive patterns are alternately arranged in a predetermined arrangement direction, the plurality of first conductive patterns are electrically connected to each other, and the plurality of second conductive patterns are electrically connected to each other.
A semiconductor device, including: a semiconductor substrate containing silicon carbide; a semiconductor device element provided on the semiconductor substrate; a poly-silicon layer provided on a main surface of the semiconductor substrate via an insulating film, the poly-silicon layer including a p-type first poly-silicon layer and an n-type second poly-silicon layer forming a pn junction therebetween; and a diode formed by the pn junction. The second poly-silicon layer contains phosphorus or antimony as a donor, and is so configured that a sheet resistance thereof at 25 degrees C is not less than 80 Ω/□ but not more than 400 Ω/□.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/60 - Impurity distributions or concentrations
H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 62/834 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
39.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
The semiconductor device includes: a drift layer of a first conductivity type; a base region of a second conductivity type, provided on a top surface side of the drift layer; a main region of the first conductivity type, provided on a top surface side of the base region; a first trench, and a second trench deeper than the first trench, the first trench and the second trench sandwiching the main region and the base region from lateral surface sides of the main region and the base region; insulated gate electrode structures buried in the first trench and the second trench; and a gate bottom protection region of the second conductivity type, provided at a bottom of the insulated gate electrode structure, the gate bottom protection region being provided for the second trench.
A semiconductor device includes pads arrayed between a region where a transistor portion or a diode portion is disposed and a first end side on an upper surface of a semiconductor substrate, and a gate runner portion that transfers a gate voltage to the transistor portion. The gate runner portion has a first gate runner disposed passing between the first end side of the semiconductor substrate and at least one of the pads in the top view, and a second gate runner disposed passing between at least one of the pads and the transistor portion in the top view. The transistor portion is also disposed in the inter-pad regions, the gate trench portion disposed in the inter-pad regions is connected to the first gate runner, and the gate trench portion arranged so as to face the second gate runner is connected to the second gate runner.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 84/40 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or with at least one component covered by groups or , e.g. integration of IGFETs with BJTs
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
41.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a trench gate semiconductor device having a diode formed by a pn junction between a first region of a first conductivity type and a second region of a second conductivity type, and at least two trenches with a mesa region in between. The method includes: forming the diode at a front side of the semiconductor substrate; forming an interlayer insulating film on the diode, the at least two trenches, and the mesa region; forming a plurality of contact holes penetrating the interlayer insulating film, and a plurality of contact trenches respectively continuous from the plurality of contact holes, thereby exposing a portion of each of the first region, the second region, and the mesa region, respectively; and ion-implanting an impurity of the first conductivity type in at least one of the exposed portions of the first region, the second region, and the mesa region.
Provided is a semiconductor device comprising a source electrode that is arranged above an upper surface of a semiconductor substrate and includes a first electrode portion and a second electrode portion, a temperature-sensing diode arranged between the first electrode portion and the second electrode portion and the cathode thereof being connected to the first electrode portion, an anode pad that is arranged between the first electrode portion and the second electrode portion and connected to the anode of the temperature-sensing diode, and an anode-side Zener diode that is arranged between the first electrode portion and the second electrode portion and connected to the anode pad and the second electrode portion.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
The purpose of the present invention is to provide a displacer device and a cooler with which it is possible, when highly efficient cooler performance is realized through addition of a magnetic cooling function, to ensure a constant-amplitude reciprocating motion performed by the displacer and achieve highly efficient cooling capacity as per a design. For this purpose, a magnetic cooling material 15 is disposed on the low-temperature-end side of a displacer 11, a magnetic circuit 40 for changing the magnetic state of the magnetic cooling material 15 is provided outside a storage container 50 corresponding to the magnetic cooling material 15, the magnetic circuit 40 magnetizes and demagnetizes the magnetic cooling material 15 according to the position of the displacer 11, a magnetic material 115 having a shape through which a working fluid can pass is disposed on the high-temperature-end side of the displacer 11, another magnetic circuit 140 for changing the magnetic state of the magnetic material 115 is provided outside the storage container 50 corresponding to the magnetic material 115, and the direction of electromagnetic force F1 acting on the magnetic cooling material 15 is different from the direction of electromagnetic force F2 acting on the magnetic material 115.
F25B 25/00 - Machines, plants or systems, using a combination of modes of operation covered by two or more of the groups
F25B 9/00 - Compression machines, plants or systems, in which the refrigerant is air or other gas of low boiling point
F25B 9/14 - Compression machines, plants or systems, in which the refrigerant is air or other gas of low boiling point characterised by the cycle used, e.g. Stirling cycle
F25B 21/00 - Machines, plants or systems, using electric or magnetic effects
A semiconductor device, including: a terminal portion including a first terminal, a second terminal, and a third terminal; and a clamping circuit connected to the first terminal, the second terminal and the third terminal. The clamping circuit is configured to: in response to a first overvoltage externally applied between the first terminal and the third terminal, cause a first overcurrent to flow from the first terminal to the third terminal to thereby clamp the first overvoltage, and in response to a second overvoltage externally applied between the second terminal and the first terminal, cause a second overcurrent to flow from the second terminal to the first terminal to thereby clamp the second overvoltage.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
A semiconductor power device having, in a top view thereof, a edge termination region located between an active region and a chip end surrounds the active region. The semiconductor power device includes a semiconductor substrate that has: a drain region of a first conductivity type; a plurality of drift regions of the first conductivity type and a plurality of partition regions of a second conductivity type alternately formed, one in contact with another, over the drain region, thereby forming a plurality of pn junctions, each extending in a depth direction; a connecting region of the second conductivity type formed on two or more of the drift regions in the edge termination region, thereby connecting two or more of the partition regions in the edge termination region; and at least one electrically-floating region of the first conductivity type, formed on the connecting region in the edge termination region.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
46.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface and having a drift region of a first conductivity type. The semiconductor substrate has a buffer region of the first conductivity type provided between the drift region and the lower surface and having a doping concentration higher than the doping concentration of the drift region. The buffer region has a decrease portion in which the doping concentration monotonously decreases from the lower surface toward the upper surface. The decrease portion contains hydrogen. In the decease portion, the chemical concentration of the hydrogen also monotonously decreases. In the decrease portion, a logarithmic gradient of the distribution of the doping concentration from the lower surface toward the upper surface is smaller than 0 and not smaller than -250 (/cm), and the length of the decrease portion is 15 μm or greater and is not greater than the thickness of the semiconductor substrate.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
Provided is a semiconductor module including: a first sense terminal portion and a first gate terminal portion arranged side by side in a first direction; a first transistor chip that constitutes a lower arm; a wiring substrate; a first wiring pattern that is electrically connected between the first transistor chip and an N terminal portion; a second wiring pattern that is electrically connected between the first transistor chip and the first wiring pattern; a first sense pattern that is electrically connected between the second wiring pattern and the first sense terminal portion, and that is separated from the second wiring pattern; and a first gate pattern that is electrically connected between a gate pad of the first transistor chip and the first gate terminal portion, wherein the first sense pattern and the first gate pattern are aligned in the first direction.
A semiconductor device, including: a semiconductor substrate having a termination region surrounding a periphery of an active region, the termination region having a residual scribe region at an outer periphery of the semiconductor substrate in a plan view, the semiconductor substrate having a main surface; a channel stopper region provided in the semiconductor substrate at the main surface, closer to the active region than is the residual scribe region; a first insulating layer provided on the main surface of the semiconductor substrate in the termination region, closer to the active region than is the residual scribe region, the first insulating layer covering the channel stopper region; and a second insulating layer provided on the main surface of the semiconductor substrate in the termination region, the second insulating layer being in the residual scribe region, the second insulating layer being thinner than the first insulating layer.
Provided is a control chip that is supplied with input power from a power supply circuit, and controls a switching device of a switching power supply which supplies output power to a load, including: at least two operating modes, including a power supply test mode for testing the power supply circuit and a normal operating mode; a feedback terminal to which a feedback signal is input according to an output voltage applied to the load; and a power supply test mode switching unit that switches between the power supply test mode and the normal operating mode according to a switch signal input to the feedback terminal.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A semiconductor module includes an accommodating member having a first main surface and a second main surface that face opposite directions, and a side surface between the first main surface and the second main surface; a mounting substrate accommodated in the accommodating member; a semiconductor chip mounted to the mounting substrate; and a connection terminal protruding from the side surface. The second main surface includes a base surface in which an opening is formed; and a first stepped surface positioned between the base surface and the side surface in plan view and recessed toward the first main surface with respect to the base surface. The mounting substrate has a heat dissipation surface positioned inside the opening, and a first groove recessed toward the first main surface and extending in an extending direction of the side surface is formed in the first stepped surface.
Provided is an induction heating device that heats an object, said induction heating device comprising: a first coil that generates an induced current in the object; a second coil that is provided so as to be separate from the first coil, that is disposed so as to face the first coil in the vicinity of an end of the object, and that weakens a magnetic flux generated in the vicinity of the end of the object by the first coil; and a movement mechanism that moves the position(s) of the first coil and/or the second coil.
An integrated circuit, including: a bias current circuit including a first resistor, the bias current circuit being configured to generate a first bias current, based on the first resistor and a reference voltage; a second resistor to which the first bias current is supplied; n diodes to which a second bias current is supplied, the n diodes being connected in series, the serially-connected diodes having a first node on a power supply side thereof and a second node on a ground side thereof; and a compensation circuit configured to apply a compensation voltage corresponding to a voltage generated at the second resistor, to the second node. The n is an integer equal to one or more. A temperature coefficient of the second resistor and a temperature coefficient of the first resistor are either one of positive or negative.
G05F 1/567 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
Provided is a semiconductor substrate with a transistor portion and a diode portion, wherein the plurality of trench portions have a plurality of gate trench portions and a plurality of dummy trench portions; and wherein the transistor portion has: a main region; and a boundary contact region, provided closer to the diode portion than to the main region, where an area proportion of contact holes provided in the interlayer dielectric film above a mesa portion is greater than that of the main region in a top view of the semiconductor substrate.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
The present disclosure is intended to provide a deterioration detection device and a semiconductor device capable of detecting deterioration of a detection object without being affected by a deterioration state of the detection object. A deterioration detection device includes: a first thermoelectric element installed at a first position of a semiconductor module; a second thermoelectric element arranged in the semiconductor module at a second position different from the first position; a light-emitting diode electrically connected to the first thermoelectric element and the second thermoelectric element; a phototransistor detecting light emitted by the light-emitting diode; and a detection circuit detecting deterioration of the semiconductor module based on a light detection value in the phototransistor.
A semiconductor module includes: one lead frame; a plurality of leads; a plurality of semiconductor chips; and an insulating substrate including a wiring layer. The plurality of semiconductor chips includes at least a first and a second semiconductor chip, each include a first and a second main electrode provided on their first and second main surfaces. A first main surface of the insulating substrate faces the lead frame, and a second main surface of the insulating substrate includes the wiring layer provided thereon. The first main electrode of the first semiconductor chip is electrically connected to the lead frame. The first main electrode of the second semiconductor chip is electrically connected to the wiring layer. A first wiring electrically connecting the second main electrode of the first semiconductor chip and a first lead of the plurality of leads to each other is provided.
Provided is a semiconductor device comprising: a plurality of transistor regions; a plurality of gates provided corresponding to the plurality of transistor regions; a gate pad disposed above a semiconductor substrate; a plurality of gate wiring parts provided corresponding to the plurality of transistor regions and electrically connected between the gates of the respective transistor regions and the gate pad; and a plurality of wiring resistance parts provided corresponding to the plurality of gate wiring parts.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
57.
SWITCHING CONTROL CIRCUIT, INTEGRATED CIRCUIT, AND POWER SUPPLY CIRCUIT
A switching control circuit for a power supply circuit that generates an output voltage from an AC voltage. The power supply circuit includes an output capacitor, an inductor receiving a rectified voltage corresponding to the AC voltage, a first transistor connected to the inductor at a connection node and controlling an inductor current, a second transistor located between the inductor and the output capacitor, and a first resistor between the output capacitor and the connection node, for detecting a first current flowing through the second transistor. The switching control circuit complementarily switches the first and second transistors, and includes: a detection circuit detecting a voltage across the first resistor; a first driver circuit driving the first transistor based on the output voltage and a detection result of the detection circuit; and a second driver circuit driving the second transistor to be turned on and off complementarily to the first transistor.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 7/217 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
H03K 17/13 - Modifications for switching at zero crossing
H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
A semiconductor device, including: a semiconductor unit disposed on a heat dissipation base, and including a first semiconductor chip having a first control electrode; an outer peripheral wall in contact with the heat dissipation base, and surrounding the semiconductor unit to define a storage region with the heat dissipation base; a first connection terminal provided apart from the semiconductor unit in the storage region; a first bonding wire electrically connecting the first connection terminal and the first control electrode; a sealing member sealing the storage area; and a first partition member provided above the first semiconductor chip in the storage region, to divide the storage region into a first region and a second region. The first connection terminal and the first bonding wire are in the first region, and the first connection terminal is in the second region, in a plan view of the semiconductor device.
The insulated gate semiconductor device includes: a drift layer; a current spreading layer provided on a top surface side of the drift layer; a base region provided on a top surface side of the current spreading layer; a main electrode region provided on a top surface side of the base region; a plurality of trenches extending through the main electrode region and the base region and arranged at a first interval in a plan view; and a gate electrode buried in each of the plurality of trenches via a gate insulating film and configured to form an inversion layer in a region of the base region which region is separated from an interface between the base region and the each of the plurality of trenches in response to voltage application. The current spreading layer includes a top-side portion located between two adjacent trenches among the plurality of trenches.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/60 - Impurity distributions or concentrations
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
60.
SUPERJUNCTION SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUPERJUNCTION SILICON CARBIDE SEMICONDUCTOR DEVICE
NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY (Japan)
Inventor
Tawara, Takeshi
Takenaka, Kensuke
Harada, Shinsuke
Sometani, Mitsuru
Abstract
A superjunction silicon carbide semiconductor device has: a silicon carbide semiconductor substrate; a first semiconductor layer of a first conductivity type; a parallel pn region in which first column regions of the first conductivity type and second column regions of a second conductivity type are disposed repeatedly alternating each other; a second semiconductor layer of the first conductivity type; first semiconductor regions of the first conductivity type, trenches, gate electrodes, first and second electrodes. Second semiconductor regions are doped with a dopant of the second conductivity type and provided in the first semiconductor layer, at bottom surfaces of and in contact with second column regions. At boundaries between the second semiconductor regions and the second column regions, a concentration of the dopant of the second conductivity type decreases to 1/10 or less of a maximum concentration of the dopant of the second conductivity type of the second semiconductor regions.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/60 - Impurity distributions or concentrations
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 62/834 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
A method of manufacturing a semiconductor device, including: forming a drift layer at a surface of a semiconductor substrate; forming a plurality of source regions at a surface of the drift layer, both the drift layer and the source regions containing silicon carbide; forming a silicide layer on the source regions; forming a barrier layer containing titanium (Ti) in contact with the silicide layer; and forming a main electrode in contact with the barrier layer. The forming the silicide layer includes: forming a single layer nickel (Ni) film or a two-layer Ni and Ti film; performing a first heat treatment on the film under an inert gas atmosphere, at a temperature between 400 degrees C and 600 degrees C; removing the film unreacted after the first heat treatment; and performing a second heat treatment on the film under the inert gas atmosphere, at a temperature lower than 1000 degrees C.
A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a pn parallel region having first column regions of the first conductivity type and second column regions of a second conductivity type that repeatedly alternate with each other, a second semiconductor layer of the second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, trenches, gate insulating films, gate electrodes, high-concentration regions of the second conductivity type provided at positions facing the trenches in a depth direction, connection regions of the second conductivity type selectively provided closer to the second semiconductor layer than are the high-concentration regions so as to be in contact with the high-concentration regions and the second semiconductor layer, first electrodes, and a second electrode.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
This non-condensable gas reduction system is used in a geothermal power plant and is provided with a gas-liquid separator for separating a geothermal fluid springing out from a production well into a first gas and a first liquid, a turbine rotated by the first gas, and a steam condenser for cooling the first gas which rotates the turbine and condensing the steam included in the first gas into a second liquid. The non-condensable gas reduction system includes a pump for pressurizing a third liquid to be sent to a reduction well, and an ejector that is driven by the third liquid, induces a non-condensable gas being included in the first gas and remaining in the steam condenser without being condensed, and discharges a fourth liquid in which the third liquid and the non-condensable gas are mixed together. The first liquid and the fourth liquid are mixed together and sent to the reduction well.
A semiconductor device includes: a drift layer including p-type columns and n-type columns alternately and repeatedly arranged; a base region provided on a top surface side of the drift layer; a main region provided on a top surface side of the base region; and an insulated gate electrode structure provided in contact with the base region and the main region, wherein a distribution of an impurity concentration of one of the p-type columns and the n-type columns in a depth direction is constant, and an impurity concentration of another one of the p-type columns and the n-type columns at each of an upper end and a lower end in the depth direction is lower than an average concentration of the other one in the depth direction, and the other one of the p-type columns and the n-type columns has a peak concentration between the upper end and the lower end in the depth direction.
H10D 62/00 - Semiconductor bodies, or regions thereof, of devices having potential barriers
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
The insulated gate semiconductor device includes: a drift layer; a base region of a second conductivity type; a main electrode region; a base contact region provided adjacent to the main electrode region; a plurality of trenches extending through the main electrode region and the base region and arranged at a first interval in a plan view; a gate electrode buried in each of the plurality of trenches via a gate insulating film and configured to form an inversion layer in a region of the base region which region is separated from an interface between the base region and the each of the plurality of trenches in response to voltage application; and a first semiconductor region of the first conductivity type provided in a part of the base region which part overlaps with the base contact region in a plan view, the first semiconductor region dividing the base region along an up-down direction.
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/60 - Impurity distributions or concentrations
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
Provided is a non-condensable gas reinjection system used in a geothermal power plant comprising: a gas-liquid separator that separates geothermal fluid spouting out of a production well into a first gas and a first liquid; an evaporator that exchanges heat between the first gas and a working medium; a turbine that is rotated by the working medium which is discharged from the evaporator; and a condenser that cools the working medium which rotated the turbine, and that condenses the working medium into a liquid. The non-condensable gas reinjection system comprises: a pump that pressurizes a third liquid which is sent to a reinjection well; and an ejector that is driven by the third liquid, that entrains a non-condensable gas which is contained in the first gas and remains in the evaporator without being condensed, and that discharges a fourth liquid in which the third liquid and the non-condensable gas are mixed. The first liquid and the fourth liquid are mixed and sent to the reinjection well.
A switching control circuit for a power supply circuit including an inductor, a first transistor controlling an inductor current , and a second transistor therebetween. The switching control circuit complementarily switches the first and second transistors, and includes: a time period output circuit outputting a first time period with the first transistor being off and the second transistor being on; and a drive signal output circuit outputting first and second drive signals to respectively switch the first and second transistors. The drive signal output circuit outputs the second drive signal to turn off the second transistor, in response to the first time period having elapsed since the inductor current has reached a predetermined value with the first transistor being off, and outputs the first drive signal to turn on the first transistor, in response to a second time period having elapsed after the lapse of the first time period.
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 7/217 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
A semiconductor device includes: a semiconductor substrate; a lower-layer insulating film provided on a top surface side of the semiconductor substrate; a resistive layer provided on a top surface side of the lower-layer insulating film; an interlayer insulating film provided on a top surface side of the lower-layer insulating film and the resistive layer; a first front-surface electrode provided on a top surface side of the interlayer insulating film and electrically connected to one end of the resistive layer; a second front-surface electrode provided on the top surface side of the interlayer insulating film separately from the first front-surface electrode and electrically connected to another end of the resistive layer; and a rear-surface electrode provided on a bottom surface side of the semiconductor substrate, wherein a resistor implemented by the resistive layer and a first capacitor in which the lower-layer insulating film on a lower side of the resistive layer serves as a dielectric are connected in parallel to the first front-surface electrode.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
A semiconductor device having: a first semiconductor layer; a gate insulating film formed on the first semiconductor layer; a gate electrode provided on the gate insulating film; an interlayer insulating film provided on the gate electrode; a contact hole penetrating through the interlayer insulating film; a front electrode selectively formed on the interlayer insulating film and in the contact hole; a sealing film selectively formed on the front electrode and the interlayer insulating film, to thereby define, in a top view, a first region in which the sealing film is formed, and a second region and a third region in which the sealing film is not formed, the second region separating the first region and the third region; and a first barrier metal sandwiched between the front electrode and the interlayer insulating film in the second region but not in the third region.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
The present invention suppresses generation of surge voltage during short off-pulse driving of a switching element. A power conversion device (1) comprises: a semiconductor element (1a) including a switching element (1a1); and a control circuit (1b). The control circuit (1b) generates a pulse signal (B) having an off-pulse width of a predetermined value starting from the falling edge (e10) of an off-pulse of a PWM signal (A) to be transmitted to the switching element (1a1), and controls the driving of the switching element (1a1) on the basis of the PWM signal (A) and the pulse signal (B). The control circuit (1b) converts a first off-pulse width (t0) less than a predetermined value into a second off-pulse width (T0) extended to the predetermined value.
The purpose of the present invention is to suppress generation of surge voltage during short on-pulse driving of a switching element. This power conversion device (1) comprises a switching element (1a1) and a control circuit (1b). The control circuit (1b) generates a pulse signal (B) having an on-pulse width of a predetermined value starting from a rising edge (e10) of an on-pulse of a PWM signal (A) transmitted to the switching element (1a1), and performs drive control of the switching element (1a1) on the basis of the PWM signal (A) and the pulse signal (B). The control circuit (1b) converts a first on-pulse width (t0) less than a predetermined value into a second on-pulse width (T0) extended to the predetermined value.
Provided is a semiconductor device comprising a drift region of a first conductivity type provided in a semiconductor substrate, a base region of a second conductivity type, an emitter region of a first conductivity type having a doping concentration higher than that of the drift region, a contact region of the second conductivity type, a trench contact portion, and trench portions extending in a predefined trench extending direction on a front-surface side of the semiconductor substrate, wherein the trench portions includes a gate trench portion and a dummy trench portion, and a mesa portion between the trench portions has a contact formation region where the contact region is provided below the emitter region on a sidewall of at least one trench portion, and a contact non-formation region where the contact region is not provided below the emitter region on a sidewall of the gate trench portion.
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
73.
INFORMATION PROCESSING SYSTEM AND INFORMATION PROCESSING METHOD
An information processing system for a drive system including a drive device that consumes power, generation of which causes emission of carbon dioxide gas, the drive system being a target system or a base system, the information processing system being configured to calculate a reduction contribution amount in emission reduction of the carbon dioxide gas using the target system as compared to the base system. The information processing system includes: a sensor measuring a first power consumption amount of the target system; and an information processing device including: a first conversion unit converting the first power consumption amount to a first emission amount; an acquisition unit acquiring a second power consumption amount of the base system; a second conversion unit converting the second power consumption amount to a second emission amount; and a calculation unit calculating a difference between the first and second emission amount as the reduction contribution amount.
There is provided a measurement apparatus for measuring a pressure difference of a fluid between a first position and a second position in a flow passage of the fluid, the measurement apparatus comprising a first pressure sensor which is provided at the first position and which outputs a first electric potential corresponding to a pressure of the fluid, a second pressure sensor which is provided at the second position and which outputs a second electric potential corresponding to a pressure of the fluid, and an electric potential difference detection unit which detects an electric potential difference between the first electric potential and the second electric potential, and converts the electric potential difference into the pressure difference.
G01F 1/36 - Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow by using mechanical effects by measuring pressure or differential pressure the pressure or differential pressure being created by the use of flow constriction
In a semiconductor module (1), a first gate pattern (62b-1) of a wiring board (60) is directly connected to a portion of semiconductor elements from among a plurality of semiconductor elements (50) via a gate wiring line (W2), and extends in a first direction (d1) parallel to an arrayed direction of these semiconductor elements (50). The second gate pattern (62b-2) is directly connected to another portion of semiconductor elements from among the plurality of semiconductor elements (50) via the gate wiring line (W2), and extends in the first direction (d1). A first resistance chip (R1) is mounted on the gate pattern in a current path from a gate terminal (41) to the first gate pattern (62b-1). A second resistance chip (R2) is mounted on the gate pattern in a current path from the gate terminal (41) to the second gate pattern (62b-2).
Provided is a semiconductor device comprising: a first conductive-type emitter region provided above a drift region, and having a dopant concentration higher than that of the drift region; a plurality of trench contact parts extending from the front surface of a semiconductor substrate towards the depth direction of the semiconductor substrate; and an emitter electrode provided above the front surface of the semiconductor substrate and electrically connected to the trench contact part. The plurality of trench parts include a gate trench part and a dummy trench part. The emitter region includes a first emitter portion provided in contact with the front surface of the semiconductor substrate, and a second emitter portion provided below the first emitter portion and having a dopant concentration lower than that of the first emitter portion. The trench contact part is provided in the dummy trench part.
A semiconductor device, including: an insulating film provided on a substrate; a cathode region and an anode region, with a low-concentration region therebetween, provided on the insulating film, the low-concentration region having a dopant concentration lower than that of the cathode region and that of the anode region; an interlayer insulating film covering the cathode region, the anode region, and the low-concentration region, the interlayer insulating film having a first contact hole and a second contact hole penetrating therethrough; a cathode electrode and an anode electrode provided on the interlayer insulating film, and connected to the cathode region and the anode region via the first contact hole and the second contact hole, respectively. In a top view of the semiconductor device, the cathode or anode electrode overlaps an upper portion of the low-concentration region by 4 μm or more in a direction from the cathode region to the anode region.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
A driving circuit includes a state terminal which outputs a state signal indicating a state of the driving circuit; a current-sensing terminal which outputs a sensing signal of a current flowing through a power device; and a state-signal generation unit connected to the state terminal, which, based on receiving driving power from a second power source different from a first power source connected to a high potential terminal of the driving circuit, generates the state signal, and a management apparatus distinguishes individually, based on the state signal and the sensing signal, whether or not the state of the driving circuit is in a normal state; whether or not the state of the driving circuit is in a loss-of-power state; and whether or not the state of the driving circuit is in a load-open state.
H03K 17/18 - Modifications for indicating state of switch
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
H03K 17/08 - Modifications for protecting switching circuit against overcurrent or overvoltage
79.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
Provided is a semiconductor device including: a semiconductor substrate having an upper surface and a lower surface; an interlayer dielectric film which is provided on the upper surface of the semiconductor substrate and in which a contact hole is formed; a barrier metal provided inside the contact hole; and a contact plug which is, inside the contact hole, filled above the barrier metal. An angle formed by a side wall of the contact hole and an upper surface of the interlayer dielectric film is larger than 70° and smaller than 90°.
A semiconductor device, including: a semiconductor substrate containing silicon carbide; a gate insulating film containing silicon oxide, provided on a surface of the semiconductor substrate; and a gate electrode provided on a surface of the gate insulating film. The semiconductor device has a plurality of germanium atoms and a plurality of alkaline earth metal atoms at an interface between the gate insulating film and the semiconductor substrate.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/60 - Impurity distributions or concentrations
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
81.
VENDING MACHINE, VENDING MACHINE SYSTEM, AND BANKNOTE PROCESSING DEVICE
This vending machine comprises: an accommodation unit that accommodates a product; a conveyance unit that conveys banknotes deposited through a deposit port; a control unit that controls conveyance of the banknotes by the conveyance unit; and a drive information acquisition unit that acquires drive information relating to the drive state of the conveyance unit and transmits the drive information to the control unit. On the basis of the drive information acquired by the drive information acquisition unit, the control unit detects extraction of the banknotes during conveyance by the conveyance unit.
G07D 11/235 - Means for sensing or detection for monitoring or indicating operating conditionsMeans for sensing or detection for detecting malfunctions
The insulated gate semiconductor device includes: a drift layer of a first-conductivity type; a base region of a second-conductivity type provided on a top surface side of the drift layer; a main electrode region of the first-conductivity type provided on a top surface side of the base region; a plurality of trenches extending through the main electrode region and the base region and arranged at a first interval in a plan view; a gate electrode buried in each of the plurality of trenches via a gate insulating film and configured to form an inversion layer in a region of the base region which region is separated from an interface between the base region and the each of the trenches in response to voltage application; and a gate bottom protection region of the second-conductivity type provided at a position separated downward from a bottom surface of the each of the trenches.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
To provide a pressure sensor comprising: a sensor portion, which is connected to a first pressure measurement hole into which a fluid flows in, and has a detector plane which detects pressure of the fluid; and a first reference potential portion that is conductive, which is provided between the first pressure measurement hole and the detector plane so as to be opposed to the detector plane, and is connected to a reference potential. In the pressure sensor, a distance between the first reference potential portion and the detector plane may be 1 cm or less. The first reference potential portion may be a mesh in which a plurality of wires are crossed.
G01L 19/06 - Means for preventing overload or deleterious influence of the measured medium on the measuring device or vice versa
F25B 49/00 - Arrangement or mounting of control or safety devices
G01L 9/00 - Measuring steady or quasi-steady pressure of a fluid or a fluent solid material by electric or magnetic pressure-sensitive elementsTransmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
G01L 9/06 - Measuring steady or quasi-steady pressure of a fluid or a fluent solid material by electric or magnetic pressure-sensitive elementsTransmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means by making use of variations in ohmic resistance, e.g. of potentiometers of piezo-resistive devices
G01L 19/00 - Details of, or accessories for, apparatus for measuring steady or quasi-steady pressure of a fluent medium insofar as such details or accessories are not special to particular types of pressure gauges
Provided is a semiconductor device including a transistor section and a diode section, the transistor section has a first transistor region and a second transistor region which is provided between the first transistor region and the diode section, a first mesa portion of the first transistor region has a first region of the first conductivity type, and a second mesa portion of the second transistor region has a second region of the first conductivity type with a doping concentration higher than that of the first region.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
Provided is a semiconductor device comprising a transistor portion and a diode portion, the device comprising: a drift region of a first conductivity type, provided in the semiconductor substrate; a plurality of trench portions extending in a predetermined trench extending direction on a front surface side of the semiconductor substrate; a base region of a second conductivity type, provided above the drift region; a first emitter region of the first conductivity type, provided at a front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a second emitter region of the first conductivity type, provided at the front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; and a trench sidewall region of the second conductivity type, provided above the drift region and having a doping concentration higher than that of the base region.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
A method of manufacturing a silicon carbide semiconductor device, including: preparing a semiconductor substrate containing silicon carbide and forming a semiconductor region therein, to consequently have a surface thereof oxidized; etching the oxidized surface using a gas free of oxygen atoms, thereby exposing a silicon carbide surface at the surface of the semiconductor substrate; depositing a silicon-containing layer containing silicon atoms and free of oxygen atoms to a thickness of 1 nm or more on the surface of the silicon carbide, without exposing the semiconductor substrate to an atmosphere containing oxygen atoms; depositing a silicon oxide film constituting a gate insulating film on the silicon-containing layer; performing a first heat treatment in an atmosphere containing nitrogen atoms, thereby nitriding the silicon-containing layer and the silicon carbide surface; performing a second heat treatment, thereby promoting oxidation of the silicon-containing layer; and subsequently forming a gate electrode on the gate insulating film.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
87.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor region of a second conductivity type, a plurality of second semiconductor regions of the first conductivity type, a plurality of trenches, a plurality of gate dielectrics, a plurality of gate electrodes, an oxide film covering the gate electrodes and the plurality of second semiconductor regions, a silicon nitride film provided on the oxide film, an interlayer dielectric film provided on the silicon nitride film, a plurality of contact vias, a barrier layer, a metal plug layer, a first electrode, and a second electrode.
An insulated gate semiconductor device includes: a drift layer of a first conductivity-type provided along an active part including an active element and an edge termination part surrounding a circumference of the active part; and a plurality of fin parts of the first conductivity-type provided separately from each other on a top surface side of the drift layer in the edge termination part so as to surround the circumference of the active part.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/00 - Electrodes of devices having potential barriers
89.
SEMICONDUCTOR MODULE AND MANUFACTURING METHOD FOR THE SAME
A semiconductor module includes a case and a sealing resin. The case includes, on an upper surface thereof, a first region and a second region that is thinner than the first region. A first opening and a recess that annularly surrounds the first opening are formed in the second region. The sealing resin fills the case.
A semiconductor device, including: a circuit board; a case which includes a housing member with a rectangular outer shape in a plan view of the semiconductor device and houses the circuit board, the housing member including an upper surface portion having a lower surface thereof facing an upper surface of the housed circuit board with a gap therebetween, the upper surface portion including a first edge portion at an edge thereof in the plan view; a first external connection terminal that is held by the first edge portion and protrudes from the first edge portion in a direction that is perpendicular to an upper surface of the first edge portion; and an encapsulating member that encapsulates the gap between the upper surface of the circuit board and the lower surface of the upper surface portion.
Provided is a semiconductor device that can prevent resin leakage during transfer molding and prevent poor appearance. The semiconductor device includes: semiconductor chips; a frame surrounding the semiconductor chips and covering the semiconductor chips from above; control terminals electrically connected to the semiconductor chips and projecting from a top surface side of the frame; and a sealing resin provided inside the frame and sealing the semiconductor chips.
A semiconductor device reduces on-resistance. The device includes a gate electrode, a first conductivity-type contact region, and super-junction drift layers. The drift layers form a first stripe pattern in which first- and second-conductivity-type column layers extending in a first direction are alternately arranged in a second direction. The gate electrode forms a second stripe pattern in which trench gates extending in the second direction are arranged in the first direction, and the two stripe patterns intersect in plan view. When the repetition period of the column layers is a first period and the repetition period of the trench gates is a second period, the second period is shorter than the first period. The contact region has a higher first-conductivity-type concentration and a larger second-direction width than the first column layer.
The insulated gate semiconductor device includes: a base region; a main electrode region provided on a top surface side of the base region; a plurality of trenches extending through the main electrode region and the base region and arranged at a first interval; a gate electrode buried in each of the trenches via a gate insulating film and configured to form an inversion layer in a region of the base region which region is separated from an interface between the base region and the each of the trenches in response to voltage application; an interlayer insulating film covering the gate electrode and having an opening exposing the main electrode region; and a contact electrode buried in the opening and having a bottom surface in contact with the main electrode region and a top surface wider in width than the main electrode region in an arrangement direction of the trenches.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
A semiconductor device, including: a first output conductive plate through which a first current flows in a first direction; a wiring member, including a bonding portion at one end thereof, to which a second current is input, and a wiring portion which is arranged to be adjacent to and opposite to an upper surface of the first output conductive plate and through which the second current input to the bonding portion flows in a second direction opposite to the first direction.
A semiconductor device, including: an insulated circuit board having a metal plate on a lowermost side thereof; a stress relaxation layer formed on a lower surface of the metal plate and having a linear expansion coefficient larger than that of the metal plate; and a cooling module including a placement surface on which a lower surface of the stress relaxation layer is arranged via a thermally conductive adhesive.
The semiconductor device includes an insulating circuit board having an insulating substrate and a first conductor layer and a second conductor layer provided separately from each other on an upper surface of the insulating substrate, a semiconductor chip mounted on the first conductor layer via solder, an external terminal having a joining part, the joining part being joined to a first joining region via solder, the first joining region being one region of an upper surface of the second conductor layer, a printed circuit board arranged above the semiconductor chip, a first pin terminal inserted into the printed circuit board and joined to a second joining region via solder, the second joining region being another one region of the upper surface of the second conductor layer, and a solder resist provided on an upper surface side of the second conductor layer and adjacent to the first joining region.
A semiconductor module for use in a semiconductor device having a water jacket. The semiconductor module includes: a substrate; a semiconductor element mounted on the substrate; a cooler that has a heat dissipation base, and a plurality of heat dissipation fins positioned on the heat dissipation base, on a side thereof opposite to the substrate, the cooler being configured to be attached to the water jacket for allowing cooling water to flow in a flow direction through the plurality of heat dissipation fins; and an insulating material integrally forming a bottom portion that extends along the flow direction, and faces tips of at least a first subset of the plurality of heat dissipation fins, and a sidewall that extends from the bottom portion toward the heat dissipation base, and faces at least a second subset of the plurality of heat dissipation fins.
A semiconductor module (1) comprises a semiconductor element (10) that has a surface electrode (12), a wiring board (20), a main current wiring (W1) that is joined to the surface electrode (12) and the wiring board (20), and an auxiliary conductor (W2) that is joined only to the surface electrode (12).
This power conversion device comprises a principal circuit board that has a principal circuit board front surface on which a semiconductor element is installed and a principal circuit board back surface that is on the reverse side from the principal circuit board front surface, a cooling part that is provided on the principal circuit board front surface side so as to be opposite the semiconductor element and dissipates heat produced from the semiconductor element, and a pressing part that presses the semiconductor element from the principal circuit board back surface side toward the cooling part side.
H02M 7/48 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
A semiconductor device includes: a base body of a first conductivity-type; a first well region of a second conductivity-type provided on a top surface side of the base body and provided with a high-side circuit; a voltage blocking structure provided to surround a circumference of the first well region; a level shifter provided in the voltage blocking structure; and first and second resistive field plates provided over the voltage blocking structure with an insulating film interposed, each having one end electrically connected to different semiconductor regions electrically connected to the high-side circuit.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
