There is provided a semiconductor device including: an emitter electrode which is provided above an semiconductor substrate, and which has a first main region, a second main region, and a third main region; a gate pad which is provided above the semiconductor substrate; a gate metal layer which is electrically connected to the gate pad; and a gate runner portion which is electrically connected to the gate metal layer, in which a plurality of trench portions have a plurality of gate trench portions, the emitter electrode has a first emitter bridge portion which connects the first main region to the second main region, and a second emitter bridge portion which connects the second main region to the third main region, and below the first emitter bridge portion, a gate trench portion different from a gate trench portion which is provided below the second emitter bridge portion is provided.
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
2.
PANEL STRUCTURE, DOOR PANEL, AND METHOD OF MANUFACTURING PANEL STRUCTURE
A panel structure including: a first surface plate and a second surface plate forming a pair; and a core plate disposed between the first and second surface plates, the core plate having a plurality of protrusions arranged in a matrix on a first main surface thereof facing the first surface plate. Each of the plurality of protrusions has a protrusion tip surface facing the first surface plate. The core plate and the first surface plate are bonded to each other such that each of the protrusion tip surfaces is in contact with the first surface plate and is constrained by a plurality of planar separate constraint regions corresponding to a planar shape of said each protrusion tip surface.
A method of manufacturing a semiconductor device, including: preparing a semiconductor substrate having a single crystal silicon region, and a polycrystalline silicon region; forming an interlayer insulating film covering the single and polycrystalline silicon regions; forming in the interlayer insulating film, a plurality of first contact holes exposing the single crystal silicon region and a second contact hole exposing the polycrystalline silicon region; performing an ion implantation in the single crystal silicon region exposed by the first contact holes; etching the single and polycrystalline silicon regions, thereby concurrently forming a plurality of first contact trenches and a second contact trench respectively continuous with the plurality of first contact holes and the second contact hole; and forming a first electrode and a second electrode respectively electrically connected to the single crystal silicon region in the first contact trenches and the polycrystalline silicon region in the second contact trench.
A semiconductor device, including first and second semiconductor chips, an output terminal, a positive terminal, a negative terminal, and an insulated circuit substrate. The insulated circuit substrate has first to third conductive circuit pattern disposed on an insulating plate. The first conductive circuit pattern includes a first mounting portion on which the first semiconductor chip is mounted, and a first terminal portion to which the output terminal is bonded. The second conductive circuit pattern includes a second mounting portion on which the second semiconductor chip is mounted, and a second terminal portion to which the positive terminal is bonded. The third conductive circuit pattern includes a third terminal portion to which the negative terminal is bonded. The first and second mounting portions have a gap therebetween. The first to third terminal portions are sequentially arranged in the gap on the upper surface of the insulating plate.
Provided is a semiconductor device that can suppress warpage of a semiconductor module. The semiconductor device includes a semiconductor module including a heat dissipation plate, an electrically-conductive plate bonded to a top surface of the heat dissipation plate by a first resin sheet, and a semiconductor chip bonded to a top surface of the electrically-conductive plate by a bonding material. A cooler is bonded to a bottom surface of the semiconductor module by a second resin sheet. A resin sheet having higher electrical insulation than the second resin sheet is used as the first resin sheet. A resin sheet having higher thermal conductivity than the first resin sheet is used as the second resin sheet.
H10D 80/20 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising capacitors, power FETs or Schottky diodes
A silicon carbide semiconductor device, including: a semiconductor substrate; a first semiconductor region; a second semiconductor region; a device element structure having a pn junction; a peripheral region surrounding a periphery of the device element structure; a first electrode; a second electrode; a plurality of withstand voltage regions; and a voltage withstanding structure configured by the withstand voltage regions and having an overall impurity concentration gradually decreasing in a direction from an active region to a termination region. The peripheral region has an outer end that is orthogonal to the first main surface. Bottoms of the withstand voltage regions are positioned deeper in a depth direction from a bottom of the peripheral region. A first withstand voltage region, which is an innermost one of the withstand voltage regions, surrounds the peripheral region so as to cover an outer-side corner of the bottom of the peripheral region.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
There is provided a semiconductor device including: a SiC substrate which has an upper surface and a lower surface; an element structure which is formed on the upper surface of the SiC substrate; a lower surface region which is exposed on at least a part of the lower surface of the SiC substrate, and which has a crystal structure different from that on an upper surface side; and a lower surface electrode which is in contact with the lower surface of the SiC substrate, in a region including at least the lower surface region, in which the lower surface region includes 3C-SiC, and a silicide layer is not formed between the lower surface electrode and the lower surface of the SiC substrate.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
A switching control circuit for a power supply circuit including a transformer and a transistor controlling an inductor current flowing through the transformer. The switching control circuit includes: a driver circuit driving the transistor, based on a feedback voltage corresponding to an output voltage and an current flowing through the transistor; a first detection circuit detecting whether the current flowing through the transistor is greater than a first current; a second detection circuit detecting whether a load current flowing through a load of the power supply circuit is greater than a second current; and a control circuit controlling the driver circuit to stop switching the transistor, when the inductor current flowing through the transistor has been greater than the first current for a first time period, or when the load current has been greater than the second current for a second time period longer than the first time period.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A non-condensable gas reinjection system is provided for use in a geothermal power plant including a gas-liquid separator configured to separate geothermal fluid obtained from a production well into a first gas and a first liquid, an evaporator configured to exchange heat between the first gas and a working fluid, a turbine configured to be rotated by the working fluid discharged from the evaporator, and a condenser configured to cool the working fluid that has rotated the turbine and to condense the working fluid into a liquid. The non-condensable gas reinjection system includes: a pump configured to pressurize a third liquid to be sent to a reinjection well; and an ejector configured to be driven by the third liquid, suction a non-condensable gas contained in the first gas and remaining uncondensed in the evaporator, and discharge a fourth liquid in which the third liquid and the non-condensable gas are mixed.
F24T 10/20 - Geothermal collectors using underground water as working fluidGeothermal collectors using working fluid injected directly into the ground, e.g. using injection wells and recovery wells
F03B 13/00 - Adaptations of machines or engines for special useCombinations of machines or engines with driving or driven apparatusPower stations or aggregates
F22B 1/16 - Methods of steam generation characterised by form of heating method by exploitation of the heat content of hot heat carriers the heat carrier being hot liquid or hot vapour, e.g. waste liquid, waste vapour
Provided is a semiconductor device comprising a semiconductor substrate, trench portions, mesa portions, an emitter electrode, and an interlayer dielectric film with a contact hole formed therein, wherein the mesa portions include a channel mesa portion having a first conductivity type emitter region on an upper surface of the semiconductor substrate and a second conductivity type base region between the emitter region and the drift region, and connected to the emitter electrode by the contact hole; and a floating mesa portion with no contact hole above or in which a length of the contact hole above is shorter than that of the contact hole above the channel mesa portion, and at a lower end of at least one of the trench portions sandwiching the channel mesa portion, a second conductivity type second trench bottom region having a higher concentration than the base region is provided.
A switching control circuit for a power factor correction circuit configured to generate an output voltage from an alternating current (AC) voltage, the power factor correction circuit including an inductor configured to receive a rectified voltage corresponding to the AC voltage, and a transistor configured to control an inductor current flowing through the inductor. The switching control circuit is configured to control switching of the transistor. The switching control circuit includes: a driving signal output circuit configured to, when a peak value of the inductor current in a half cycle of the AC voltage is smaller than and greater than a first predetermined value, output a driving signal to operate the power factor correction circuit in a critical mode and in a continuous mode, respectively; and a driver circuit configured to drive the transistor, in response to the driving signal.
There is provided a semiconductor device including: a SiC substrate which has an upper surface and a lower surface; an element structure which is formed on the upper surface of the SiC substrate; a metal silicide portion which is formed at a part of the lower surface of the SiC substrate; and a lower surface electrode which is in contact with the metal silicide portion and with an exposed region of the lower surface which is not covered by the metal silicide portion, in which at least a part of the exposed region has a crystal structure different from that of a contact region of the SiC substrate which is in contact with the metal silicide portion.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
A semiconductor device, including: a semiconductor substrate having an active region and a termination region surrounding a periphery of the active region in a plan view; a first semiconductor region provided on a surface of the semiconductor substrate; a second semiconductor region provided in the first semiconductor region at a surface thereof, in an end portion of the termination region; an insulating film provided at the surface of the first semiconductor region; and a polyimide film selectively provided at a surface of the insulating film. The insulating film covers the first and second semiconductor regions. The polyimide film covers the surface of the insulating film. The semiconductor device further has, in the end portion of the termination region, an uneven portion through which the first semiconductor region and the second semiconductor region are exposed.
A method of manufacturing a trench-type silicon carbide semiconductor device that includes a drift layer of a first conductivity type, a base layer of a second conductivity type formed on the drift layer, and a plurality of trenches penetrating through the base layer and reaching the drift layer. The method includes forming a co-doped region of the first conductivity type by introducing a first impurity of the first conductivity type and a second impurity of the second conductivity type into a portion of the drift layer between two of the plurality of trenches.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
Provided is a semiconductor device comprising a semiconductor substrate having an upper surface and a drift region, trench portions provided inwardly from the upper surface of the semiconductor substrate, mesa portions each being a region sandwiched between two of the trench portions; an emitter electrode, and an interlayer dielectric film with a contact hole formed, wherein the mesa portions include a channel mesa portion having a first conductivity type emitter region and a second conductivity type base region on the upper surface and connected to the emitter electrode by the contact hole, and a hole-extraction mesa portion with no channel formed and connected to the emitter electrode by the contact hole, and a first conductivity type first trench bottom region having a higher concentration than the drift region is provided at a lower end of at least one of the trench portions sandwiching the hole-extraction mesa portion.
There is provided a semiconductor device including a transistor portion and a diode portion, wherein the transistor portion includes: an emitter region which includes a first emitter section of the first conductivity type and a second emitter section which is provided below the first emitter section and has a lower doping concentration than the first emitter section; a trench contact portion which extends from the front surface of the semiconductor substrate in a depth direction of the semiconductor substrate; and a trench contact sidewall region which is provided on a sidewall of the trench contact portion and provided between the trench contact portion and the second emitter section, and the diode portion includes a first conductivity type region of the first conductivity type which is provided above the drift region and in contact with the front surface electrode portion.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
A power converter selectively uses a cell balance mode and a cell imbalance mode, the cell balance mode is a mode in which each of a plurality of single-phase AC output units superimposes only outputs of a number of power conversion cells corresponding to a minimum number of the numbers of available power conversion cells to output single phase AC, and the cell imbalance mode is a mode in which each of the plurality of single-phase AC output units superimposes outputs of all available power conversion cells to output the single-phase AC such that phase differences between line-to-line voltages of adjacent phases among phases are all equivalent.
H02M 5/458 - Conversion of AC power input into AC power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into DC by static converters using discharge tubes or semiconductor devices to convert the intermediate DC into AC using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
A semiconductor device includes: a first conductive plate connected to bottom surfaces of first semiconductor chips; a second conductive plate connected to bottom surfaces of second semiconductor chips; a third conductive plate connected to bottom surfaces of third and fourth semiconductor chips; a first external terminal connected to the first conductive plate; a second external terminal connected to top surfaces of the second semiconductor chips; a third external terminal connected to top surfaces of the third semiconductor chips; and a fourth external terminal connected to top surfaces of the first and fourth semiconductor chips. The first to third external terminals are disposed opposite to the fourth external terminal, and the first and second semiconductor chips are provided closer to the first and second external terminals than the third and fourth semiconductor chips.
Provided is a semiconductor module including a main circuit portion, a plurality of circuit electrodes, a plurality of main terminals, and a plurality of wires, in each of semiconductor chips, transistor portions and diode portions have a longitudinal side in a second direction, each of semiconductor chips has a plurality of end sides including a gate-side end side, each of the gate-side end sides is arranged facing a same side in a top view, the plurality of main terminals are arranged on a same side in relation to the main circuit portion so as not to sandwich the main circuit portion in a top view, each of the plurality of wires has a bonding portion, and a longitudinal direction of the bonding portion has an angle in relation to the second direction.
An insulated gate semiconductor device includes: a drift layer of a first conductivity-type; a base region of a second conductivity-type provided on a top surface side of the drift layer; a main region of the first conductivity-type provided on a top surface side of the base region; and a gate electrode buried, with a gate insulating film interposed, in trenches dug downward from a top surface of the main region, wherein a plurality of mesa parts interposed between the trenches adjacent to each other are arranged in a matrix form, and a width of the respective mesa parts at least in one direction is set to 600 nanometers or smaller.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
A power system includes a plurality of power generation systems capable of supplying power to a power grid, wherein each of the plurality of power generation systems includes a renewable-energy-power-generation facility configured to generate power using renewable energy and a power generation controller configured to control, so as to follow a characteristic curve representative of a relationship between a stability indicator relating to stability of grid power in the power grid and power to be generated by the renewable-energy-power-generation facility, the power to be generated by the renewable-energy-power-generation facility in accordance with the stability indicator, and wherein the power generation controller is configured to adjust the characteristic curve in a direction that causes an increase in the power to be generated in a case in which a supply of renewable energy to the renewable-energy-power-generation facility increases after an occurrence of fluctuation in the stability indicator.
H02J 3/38 - Arrangements for parallelly feeding a single network by two or more generators, converters or transformers
G05B 13/04 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric involving the use of models or simulators
A semiconductor device comprising a semiconductor substrate having an upper surface, wherein the semiconductor substrate has a main transistor portion having a main gate trench portion including a main gate conductive portion, a sense transistor portion having a sense gate trench portion including a sense gate conductive portion, a gate pad provided above the upper surface of the semiconductor substrate, a main gate runner provided above the upper surface of the semiconductor substrate and extending from the gate pad to the main gate conductive portion, a sense gate runner disposed along the sense transistor portion, and a gate runner connection portion connecting the main gate runner and the sense gate runner, and a resistor portion is provided in the gate runner connection portion.
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
Provided is a semiconductor device comprising: an insulating plate; a semiconductor element provided above the insulating plate and having a first control electrode and a second control electrode; a plurality of first conductive patterns provided above the insulating plate and electrically connected to the first control electrode; and a plurality of second conductive patterns provided above the insulating plate and electrically connected to the second control electrode, wherein the plurality of first conductive patterns and the plurality of second conductive patterns are alternately arranged in a predetermined arrangement direction, the plurality of first conductive patterns are electrically connected to each other, and the plurality of second conductive patterns are electrically connected to each other.
A semiconductor device, including: a semiconductor substrate containing silicon carbide; a semiconductor device element provided on the semiconductor substrate; a poly-silicon layer provided on a main surface of the semiconductor substrate via an insulating film, the poly-silicon layer including a p-type first poly-silicon layer and an n-type second poly-silicon layer forming a pn junction therebetween; and a diode formed by the pn junction. The second poly-silicon layer contains phosphorus or antimony as a donor, and is so configured that a sheet resistance thereof at 25 degrees C is not less than 80 Ω/□ but not more than 400 Ω/□.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/60 - Impurity distributions or concentrations
H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 62/834 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
25.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
The semiconductor device includes: a drift layer of a first conductivity type; a base region of a second conductivity type, provided on a top surface side of the drift layer; a main region of the first conductivity type, provided on a top surface side of the base region; a first trench, and a second trench deeper than the first trench, the first trench and the second trench sandwiching the main region and the base region from lateral surface sides of the main region and the base region; insulated gate electrode structures buried in the first trench and the second trench; and a gate bottom protection region of the second conductivity type, provided at a bottom of the insulated gate electrode structure, the gate bottom protection region being provided for the second trench.
A semiconductor device includes pads arrayed between a region where a transistor portion or a diode portion is disposed and a first end side on an upper surface of a semiconductor substrate, and a gate runner portion that transfers a gate voltage to the transistor portion. The gate runner portion has a first gate runner disposed passing between the first end side of the semiconductor substrate and at least one of the pads in the top view, and a second gate runner disposed passing between at least one of the pads and the transistor portion in the top view. The transistor portion is also disposed in the inter-pad regions, the gate trench portion disposed in the inter-pad regions is connected to the first gate runner, and the gate trench portion arranged so as to face the second gate runner is connected to the second gate runner.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 84/40 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or with at least one component covered by groups or , e.g. integration of IGFETs with BJTs
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
27.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a trench gate semiconductor device having a diode formed by a pn junction between a first region of a first conductivity type and a second region of a second conductivity type, and at least two trenches with a mesa region in between. The method includes: forming the diode at a front side of the semiconductor substrate; forming an interlayer insulating film on the diode, the at least two trenches, and the mesa region; forming a plurality of contact holes penetrating the interlayer insulating film, and a plurality of contact trenches respectively continuous from the plurality of contact holes, thereby exposing a portion of each of the first region, the second region, and the mesa region, respectively; and ion-implanting an impurity of the first conductivity type in at least one of the exposed portions of the first region, the second region, and the mesa region.
Provided is a semiconductor device comprising a source electrode that is arranged above an upper surface of a semiconductor substrate and includes a first electrode portion and a second electrode portion, a temperature-sensing diode arranged between the first electrode portion and the second electrode portion and the cathode thereof being connected to the first electrode portion, an anode pad that is arranged between the first electrode portion and the second electrode portion and connected to the anode of the temperature-sensing diode, and an anode-side Zener diode that is arranged between the first electrode portion and the second electrode portion and connected to the anode pad and the second electrode portion.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
A semiconductor device, including: a terminal portion including a first terminal, a second terminal, and a third terminal; and a clamping circuit connected to the first terminal, the second terminal and the third terminal. The clamping circuit is configured to: in response to a first overvoltage externally applied between the first terminal and the third terminal, cause a first overcurrent to flow from the first terminal to the third terminal to thereby clamp the first overvoltage, and in response to a second overvoltage externally applied between the second terminal and the first terminal, cause a second overcurrent to flow from the second terminal to the first terminal to thereby clamp the second overvoltage.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
A semiconductor power device having, in a top view thereof, a edge termination region located between an active region and a chip end surrounds the active region. The semiconductor power device includes a semiconductor substrate that has: a drain region of a first conductivity type; a plurality of drift regions of the first conductivity type and a plurality of partition regions of a second conductivity type alternately formed, one in contact with another, over the drain region, thereby forming a plurality of pn junctions, each extending in a depth direction; a connecting region of the second conductivity type formed on two or more of the drift regions in the edge termination region, thereby connecting two or more of the partition regions in the edge termination region; and at least one electrically-floating region of the first conductivity type, formed on the connecting region in the edge termination region.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
Provided is a semiconductor module including: a first sense terminal portion and a first gate terminal portion arranged side by side in a first direction; a first transistor chip that constitutes a lower arm; a wiring substrate; a first wiring pattern that is electrically connected between the first transistor chip and an N terminal portion; a second wiring pattern that is electrically connected between the first transistor chip and the first wiring pattern; a first sense pattern that is electrically connected between the second wiring pattern and the first sense terminal portion, and that is separated from the second wiring pattern; and a first gate pattern that is electrically connected between a gate pad of the first transistor chip and the first gate terminal portion, wherein the first sense pattern and the first gate pattern are aligned in the first direction.
A semiconductor device, including: a semiconductor substrate having a termination region surrounding a periphery of an active region, the termination region having a residual scribe region at an outer periphery of the semiconductor substrate in a plan view, the semiconductor substrate having a main surface; a channel stopper region provided in the semiconductor substrate at the main surface, closer to the active region than is the residual scribe region; a first insulating layer provided on the main surface of the semiconductor substrate in the termination region, closer to the active region than is the residual scribe region, the first insulating layer covering the channel stopper region; and a second insulating layer provided on the main surface of the semiconductor substrate in the termination region, the second insulating layer being in the residual scribe region, the second insulating layer being thinner than the first insulating layer.
Provided is a control chip that is supplied with input power from a power supply circuit, and controls a switching device of a switching power supply which supplies output power to a load, including: at least two operating modes, including a power supply test mode for testing the power supply circuit and a normal operating mode; a feedback terminal to which a feedback signal is input according to an output voltage applied to the load; and a power supply test mode switching unit that switches between the power supply test mode and the normal operating mode according to a switch signal input to the feedback terminal.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A semiconductor module includes an accommodating member having a first main surface and a second main surface that face opposite directions, and a side surface between the first main surface and the second main surface; a mounting substrate accommodated in the accommodating member; a semiconductor chip mounted to the mounting substrate; and a connection terminal protruding from the side surface. The second main surface includes a base surface in which an opening is formed; and a first stepped surface positioned between the base surface and the side surface in plan view and recessed toward the first main surface with respect to the base surface. The mounting substrate has a heat dissipation surface positioned inside the opening, and a first groove recessed toward the first main surface and extending in an extending direction of the side surface is formed in the first stepped surface.
An integrated circuit, including: a bias current circuit including a first resistor, the bias current circuit being configured to generate a first bias current, based on the first resistor and a reference voltage; a second resistor to which the first bias current is supplied; n diodes to which a second bias current is supplied, the n diodes being connected in series, the serially-connected diodes having a first node on a power supply side thereof and a second node on a ground side thereof; and a compensation circuit configured to apply a compensation voltage corresponding to a voltage generated at the second resistor, to the second node. The n is an integer equal to one or more. A temperature coefficient of the second resistor and a temperature coefficient of the first resistor are either one of positive or negative.
G05F 1/567 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
Provided is a semiconductor substrate with a transistor portion and a diode portion, wherein the plurality of trench portions have a plurality of gate trench portions and a plurality of dummy trench portions; and wherein the transistor portion has: a main region; and a boundary contact region, provided closer to the diode portion than to the main region, where an area proportion of contact holes provided in the interlayer dielectric film above a mesa portion is greater than that of the main region in a top view of the semiconductor substrate.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
The present disclosure is intended to provide a deterioration detection device and a semiconductor device capable of detecting deterioration of a detection object without being affected by a deterioration state of the detection object. A deterioration detection device includes: a first thermoelectric element installed at a first position of a semiconductor module; a second thermoelectric element arranged in the semiconductor module at a second position different from the first position; a light-emitting diode electrically connected to the first thermoelectric element and the second thermoelectric element; a phototransistor detecting light emitted by the light-emitting diode; and a detection circuit detecting deterioration of the semiconductor module based on a light detection value in the phototransistor.
A semiconductor module includes: one lead frame; a plurality of leads; a plurality of semiconductor chips; and an insulating substrate including a wiring layer. The plurality of semiconductor chips includes at least a first and a second semiconductor chip, each include a first and a second main electrode provided on their first and second main surfaces. A first main surface of the insulating substrate faces the lead frame, and a second main surface of the insulating substrate includes the wiring layer provided thereon. The first main electrode of the first semiconductor chip is electrically connected to the lead frame. The first main electrode of the second semiconductor chip is electrically connected to the wiring layer. A first wiring electrically connecting the second main electrode of the first semiconductor chip and a first lead of the plurality of leads to each other is provided.
A switching control circuit for a power supply circuit that generates an output voltage from an AC voltage. The power supply circuit includes an output capacitor, an inductor receiving a rectified voltage corresponding to the AC voltage, a first transistor connected to the inductor at a connection node and controlling an inductor current, a second transistor located between the inductor and the output capacitor, and a first resistor between the output capacitor and the connection node, for detecting a first current flowing through the second transistor. The switching control circuit complementarily switches the first and second transistors, and includes: a detection circuit detecting a voltage across the first resistor; a first driver circuit driving the first transistor based on the output voltage and a detection result of the detection circuit; and a second driver circuit driving the second transistor to be turned on and off complementarily to the first transistor.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 7/217 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
H03K 17/13 - Modifications for switching at zero crossing
H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
A semiconductor device, including: a semiconductor unit disposed on a heat dissipation base, and including a first semiconductor chip having a first control electrode; an outer peripheral wall in contact with the heat dissipation base, and surrounding the semiconductor unit to define a storage region with the heat dissipation base; a first connection terminal provided apart from the semiconductor unit in the storage region; a first bonding wire electrically connecting the first connection terminal and the first control electrode; a sealing member sealing the storage area; and a first partition member provided above the first semiconductor chip in the storage region, to divide the storage region into a first region and a second region. The first connection terminal and the first bonding wire are in the first region, and the first connection terminal is in the second region, in a plan view of the semiconductor device.
The insulated gate semiconductor device includes: a drift layer; a current spreading layer provided on a top surface side of the drift layer; a base region provided on a top surface side of the current spreading layer; a main electrode region provided on a top surface side of the base region; a plurality of trenches extending through the main electrode region and the base region and arranged at a first interval in a plan view; and a gate electrode buried in each of the plurality of trenches via a gate insulating film and configured to form an inversion layer in a region of the base region which region is separated from an interface between the base region and the each of the plurality of trenches in response to voltage application. The current spreading layer includes a top-side portion located between two adjacent trenches among the plurality of trenches.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/60 - Impurity distributions or concentrations
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
42.
SUPERJUNCTION SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUPERJUNCTION SILICON CARBIDE SEMICONDUCTOR DEVICE
NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY (Japan)
Inventor
Tawara, Takeshi
Takenaka, Kensuke
Harada, Shinsuke
Sometani, Mitsuru
Abstract
A superjunction silicon carbide semiconductor device has: a silicon carbide semiconductor substrate; a first semiconductor layer of a first conductivity type; a parallel pn region in which first column regions of the first conductivity type and second column regions of a second conductivity type are disposed repeatedly alternating each other; a second semiconductor layer of the first conductivity type; first semiconductor regions of the first conductivity type, trenches, gate electrodes, first and second electrodes. Second semiconductor regions are doped with a dopant of the second conductivity type and provided in the first semiconductor layer, at bottom surfaces of and in contact with second column regions. At boundaries between the second semiconductor regions and the second column regions, a concentration of the dopant of the second conductivity type decreases to 1/10 or less of a maximum concentration of the dopant of the second conductivity type of the second semiconductor regions.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/60 - Impurity distributions or concentrations
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 62/834 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
A method of manufacturing a semiconductor device, including: forming a drift layer at a surface of a semiconductor substrate; forming a plurality of source regions at a surface of the drift layer, both the drift layer and the source regions containing silicon carbide; forming a silicide layer on the source regions; forming a barrier layer containing titanium (Ti) in contact with the silicide layer; and forming a main electrode in contact with the barrier layer. The forming the silicide layer includes: forming a single layer nickel (Ni) film or a two-layer Ni and Ti film; performing a first heat treatment on the film under an inert gas atmosphere, at a temperature between 400 degrees C and 600 degrees C; removing the film unreacted after the first heat treatment; and performing a second heat treatment on the film under the inert gas atmosphere, at a temperature lower than 1000 degrees C.
A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a pn parallel region having first column regions of the first conductivity type and second column regions of a second conductivity type that repeatedly alternate with each other, a second semiconductor layer of the second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, trenches, gate insulating films, gate electrodes, high-concentration regions of the second conductivity type provided at positions facing the trenches in a depth direction, connection regions of the second conductivity type selectively provided closer to the second semiconductor layer than are the high-concentration regions so as to be in contact with the high-concentration regions and the second semiconductor layer, first electrodes, and a second electrode.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
A semiconductor device includes: a drift layer including p-type columns and n-type columns alternately and repeatedly arranged; a base region provided on a top surface side of the drift layer; a main region provided on a top surface side of the base region; and an insulated gate electrode structure provided in contact with the base region and the main region, wherein a distribution of an impurity concentration of one of the p-type columns and the n-type columns in a depth direction is constant, and an impurity concentration of another one of the p-type columns and the n-type columns at each of an upper end and a lower end in the depth direction is lower than an average concentration of the other one in the depth direction, and the other one of the p-type columns and the n-type columns has a peak concentration between the upper end and the lower end in the depth direction.
H10D 62/00 - Semiconductor bodies, or regions thereof, of devices having potential barriers
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
The insulated gate semiconductor device includes: a drift layer; a base region of a second conductivity type; a main electrode region; a base contact region provided adjacent to the main electrode region; a plurality of trenches extending through the main electrode region and the base region and arranged at a first interval in a plan view; a gate electrode buried in each of the plurality of trenches via a gate insulating film and configured to form an inversion layer in a region of the base region which region is separated from an interface between the base region and the each of the plurality of trenches in response to voltage application; and a first semiconductor region of the first conductivity type provided in a part of the base region which part overlaps with the base contact region in a plan view, the first semiconductor region dividing the base region along an up-down direction.
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/60 - Impurity distributions or concentrations
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
47.
SWITCHING CONTROL CIRCUIT AND POWER SUPPLY CIRCUIT
A switching control circuit for a power supply circuit including an inductor, a first transistor controlling an inductor current , and a second transistor therebetween. The switching control circuit complementarily switches the first and second transistors, and includes: a time period output circuit outputting a first time period with the first transistor being off and the second transistor being on; and a drive signal output circuit outputting first and second drive signals to respectively switch the first and second transistors. The drive signal output circuit outputs the second drive signal to turn off the second transistor, in response to the first time period having elapsed since the inductor current has reached a predetermined value with the first transistor being off, and outputs the first drive signal to turn on the first transistor, in response to a second time period having elapsed after the lapse of the first time period.
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 7/217 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
A semiconductor device includes: a semiconductor substrate; a lower-layer insulating film provided on a top surface side of the semiconductor substrate; a resistive layer provided on a top surface side of the lower-layer insulating film; an interlayer insulating film provided on a top surface side of the lower-layer insulating film and the resistive layer; a first front-surface electrode provided on a top surface side of the interlayer insulating film and electrically connected to one end of the resistive layer; a second front-surface electrode provided on the top surface side of the interlayer insulating film separately from the first front-surface electrode and electrically connected to another end of the resistive layer; and a rear-surface electrode provided on a bottom surface side of the semiconductor substrate, wherein a resistor implemented by the resistive layer and a first capacitor in which the lower-layer insulating film on a lower side of the resistive layer serves as a dielectric are connected in parallel to the first front-surface electrode.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
A semiconductor device having: a first semiconductor layer; a gate insulating film formed on the first semiconductor layer; a gate electrode provided on the gate insulating film; an interlayer insulating film provided on the gate electrode; a contact hole penetrating through the interlayer insulating film; a front electrode selectively formed on the interlayer insulating film and in the contact hole; a sealing film selectively formed on the front electrode and the interlayer insulating film, to thereby define, in a top view, a first region in which the sealing film is formed, and a second region and a third region in which the sealing film is not formed, the second region separating the first region and the third region; and a first barrier metal sandwiched between the front electrode and the interlayer insulating film in the second region but not in the third region.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
Provided is a semiconductor device comprising a drift region of a first conductivity type provided in a semiconductor substrate, a base region of a second conductivity type, an emitter region of a first conductivity type having a doping concentration higher than that of the drift region, a contact region of the second conductivity type, a trench contact portion, and trench portions extending in a predefined trench extending direction on a front-surface side of the semiconductor substrate, wherein the trench portions includes a gate trench portion and a dummy trench portion, and a mesa portion between the trench portions has a contact formation region where the contact region is provided below the emitter region on a sidewall of at least one trench portion, and a contact non-formation region where the contact region is not provided below the emitter region on a sidewall of the gate trench portion.
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
51.
INFORMATION PROCESSING SYSTEM AND INFORMATION PROCESSING METHOD
An information processing system for a drive system including a drive device that consumes power, generation of which causes emission of carbon dioxide gas, the drive system being a target system or a base system, the information processing system being configured to calculate a reduction contribution amount in emission reduction of the carbon dioxide gas using the target system as compared to the base system. The information processing system includes: a sensor measuring a first power consumption amount of the target system; and an information processing device including: a first conversion unit converting the first power consumption amount to a first emission amount; an acquisition unit acquiring a second power consumption amount of the base system; a second conversion unit converting the second power consumption amount to a second emission amount; and a calculation unit calculating a difference between the first and second emission amount as the reduction contribution amount.
There is provided a measurement apparatus for measuring a pressure difference of a fluid between a first position and a second position in a flow passage of the fluid, the measurement apparatus comprising a first pressure sensor which is provided at the first position and which outputs a first electric potential corresponding to a pressure of the fluid, a second pressure sensor which is provided at the second position and which outputs a second electric potential corresponding to a pressure of the fluid, and an electric potential difference detection unit which detects an electric potential difference between the first electric potential and the second electric potential, and converts the electric potential difference into the pressure difference.
G01F 1/36 - Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow by using mechanical effects by measuring pressure or differential pressure the pressure or differential pressure being created by the use of flow constriction
A driving circuit includes a state terminal which outputs a state signal indicating a state of the driving circuit; a current-sensing terminal which outputs a sensing signal of a current flowing through a power device; and a state-signal generation unit connected to the state terminal, which, based on receiving driving power from a second power source different from a first power source connected to a high potential terminal of the driving circuit, generates the state signal, and a management apparatus distinguishes individually, based on the state signal and the sensing signal, whether or not the state of the driving circuit is in a normal state; whether or not the state of the driving circuit is in a loss-of-power state; and whether or not the state of the driving circuit is in a load-open state.
H03K 17/18 - Modifications for indicating state of switch
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
H03K 17/08 - Modifications for protecting switching circuit against overcurrent or overvoltage
54.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
Provided is a semiconductor device including: a semiconductor substrate having an upper surface and a lower surface; an interlayer dielectric film which is provided on the upper surface of the semiconductor substrate and in which a contact hole is formed; a barrier metal provided inside the contact hole; and a contact plug which is, inside the contact hole, filled above the barrier metal. An angle formed by a side wall of the contact hole and an upper surface of the interlayer dielectric film is larger than 70° and smaller than 90°.
A semiconductor device, including: a semiconductor substrate containing silicon carbide; a gate insulating film containing silicon oxide, provided on a surface of the semiconductor substrate; and a gate electrode provided on a surface of the gate insulating film. The semiconductor device has a plurality of germanium atoms and a plurality of alkaline earth metal atoms at an interface between the gate insulating film and the semiconductor substrate.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/60 - Impurity distributions or concentrations
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
56.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device, including: an insulating film provided on a substrate; a cathode region and an anode region, with a low-concentration region therebetween, provided on the insulating film, the low-concentration region having a dopant concentration lower than that of the cathode region and that of the anode region; an interlayer insulating film covering the cathode region, the anode region, and the low-concentration region, the interlayer insulating film having a first contact hole and a second contact hole penetrating therethrough; a cathode electrode and an anode electrode provided on the interlayer insulating film, and connected to the cathode region and the anode region via the first contact hole and the second contact hole, respectively. In a top view of the semiconductor device, the cathode or anode electrode overlaps an upper portion of the low-concentration region by 4 μm or more in a direction from the cathode region to the anode region.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
The insulated gate semiconductor device includes: a drift layer of a first-conductivity type; a base region of a second-conductivity type provided on a top surface side of the drift layer; a main electrode region of the first-conductivity type provided on a top surface side of the base region; a plurality of trenches extending through the main electrode region and the base region and arranged at a first interval in a plan view; a gate electrode buried in each of the plurality of trenches via a gate insulating film and configured to form an inversion layer in a region of the base region which region is separated from an interface between the base region and the each of the trenches in response to voltage application; and a gate bottom protection region of the second-conductivity type provided at a position separated downward from a bottom surface of the each of the trenches.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
To provide a pressure sensor comprising: a sensor portion, which is connected to a first pressure measurement hole into which a fluid flows in, and has a detector plane which detects pressure of the fluid; and a first reference potential portion that is conductive, which is provided between the first pressure measurement hole and the detector plane so as to be opposed to the detector plane, and is connected to a reference potential. In the pressure sensor, a distance between the first reference potential portion and the detector plane may be 1 cm or less. The first reference potential portion may be a mesh in which a plurality of wires are crossed.
G01L 19/06 - Means for preventing overload or deleterious influence of the measured medium on the measuring device or vice versa
F25B 49/00 - Arrangement or mounting of control or safety devices
G01L 9/00 - Measuring steady or quasi-steady pressure of a fluid or a fluent solid material by electric or magnetic pressure-sensitive elementsTransmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
G01L 9/06 - Measuring steady or quasi-steady pressure of a fluid or a fluent solid material by electric or magnetic pressure-sensitive elementsTransmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means by making use of variations in ohmic resistance, e.g. of potentiometers of piezo-resistive devices
G01L 19/00 - Details of, or accessories for, apparatus for measuring steady or quasi-steady pressure of a fluent medium insofar as such details or accessories are not special to particular types of pressure gauges
Provided is a semiconductor device including a transistor section and a diode section, the transistor section has a first transistor region and a second transistor region which is provided between the first transistor region and the diode section, a first mesa portion of the first transistor region has a first region of the first conductivity type, and a second mesa portion of the second transistor region has a second region of the first conductivity type with a doping concentration higher than that of the first region.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
Provided is a semiconductor device comprising a transistor portion and a diode portion, the device comprising: a drift region of a first conductivity type, provided in the semiconductor substrate; a plurality of trench portions extending in a predetermined trench extending direction on a front surface side of the semiconductor substrate; a base region of a second conductivity type, provided above the drift region; a first emitter region of the first conductivity type, provided at a front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a second emitter region of the first conductivity type, provided at the front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; and a trench sidewall region of the second conductivity type, provided above the drift region and having a doping concentration higher than that of the base region.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
A method of manufacturing a silicon carbide semiconductor device, including: preparing a semiconductor substrate containing silicon carbide and forming a semiconductor region therein, to consequently have a surface thereof oxidized; etching the oxidized surface using a gas free of oxygen atoms, thereby exposing a silicon carbide surface at the surface of the semiconductor substrate; depositing a silicon-containing layer containing silicon atoms and free of oxygen atoms to a thickness of 1 nm or more on the surface of the silicon carbide, without exposing the semiconductor substrate to an atmosphere containing oxygen atoms; depositing a silicon oxide film constituting a gate insulating film on the silicon-containing layer; performing a first heat treatment in an atmosphere containing nitrogen atoms, thereby nitriding the silicon-containing layer and the silicon carbide surface; performing a second heat treatment, thereby promoting oxidation of the silicon-containing layer; and subsequently forming a gate electrode on the gate insulating film.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
62.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor region of a second conductivity type, a plurality of second semiconductor regions of the first conductivity type, a plurality of trenches, a plurality of gate dielectrics, a plurality of gate electrodes, an oxide film covering the gate electrodes and the plurality of second semiconductor regions, a silicon nitride film provided on the oxide film, an interlayer dielectric film provided on the silicon nitride film, a plurality of contact vias, a barrier layer, a metal plug layer, a first electrode, and a second electrode.
An insulated gate semiconductor device includes: a drift layer of a first conductivity-type provided along an active part including an active element and an edge termination part surrounding a circumference of the active part; and a plurality of fin parts of the first conductivity-type provided separately from each other on a top surface side of the drift layer in the edge termination part so as to surround the circumference of the active part.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/00 - Electrodes of devices having potential barriers
64.
SEMICONDUCTOR MODULE AND MANUFACTURING METHOD FOR THE SAME
A semiconductor module includes a case and a sealing resin. The case includes, on an upper surface thereof, a first region and a second region that is thinner than the first region. A first opening and a recess that annularly surrounds the first opening are formed in the second region. The sealing resin fills the case.
A semiconductor device, including: a circuit board; a case which includes a housing member with a rectangular outer shape in a plan view of the semiconductor device and houses the circuit board, the housing member including an upper surface portion having a lower surface thereof facing an upper surface of the housed circuit board with a gap therebetween, the upper surface portion including a first edge portion at an edge thereof in the plan view; a first external connection terminal that is held by the first edge portion and protrudes from the first edge portion in a direction that is perpendicular to an upper surface of the first edge portion; and an encapsulating member that encapsulates the gap between the upper surface of the circuit board and the lower surface of the upper surface portion.
Provided is a semiconductor device that can prevent resin leakage during transfer molding and prevent poor appearance. The semiconductor device includes: semiconductor chips; a frame surrounding the semiconductor chips and covering the semiconductor chips from above; control terminals electrically connected to the semiconductor chips and projecting from a top surface side of the frame; and a sealing resin provided inside the frame and sealing the semiconductor chips.
A semiconductor device reduces on-resistance. The device includes a gate electrode, a first conductivity-type contact region, and super-junction drift layers. The drift layers form a first stripe pattern in which first- and second-conductivity-type column layers extending in a first direction are alternately arranged in a second direction. The gate electrode forms a second stripe pattern in which trench gates extending in the second direction are arranged in the first direction, and the two stripe patterns intersect in plan view. When the repetition period of the column layers is a first period and the repetition period of the trench gates is a second period, the second period is shorter than the first period. The contact region has a higher first-conductivity-type concentration and a larger second-direction width than the first column layer.
The insulated gate semiconductor device includes: a base region; a main electrode region provided on a top surface side of the base region; a plurality of trenches extending through the main electrode region and the base region and arranged at a first interval; a gate electrode buried in each of the trenches via a gate insulating film and configured to form an inversion layer in a region of the base region which region is separated from an interface between the base region and the each of the trenches in response to voltage application; an interlayer insulating film covering the gate electrode and having an opening exposing the main electrode region; and a contact electrode buried in the opening and having a bottom surface in contact with the main electrode region and a top surface wider in width than the main electrode region in an arrangement direction of the trenches.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
A semiconductor device, including: a first output conductive plate through which a first current flows in a first direction; a wiring member, including a bonding portion at one end thereof, to which a second current is input, and a wiring portion which is arranged to be adjacent to and opposite to an upper surface of the first output conductive plate and through which the second current input to the bonding portion flows in a second direction opposite to the first direction.
A semiconductor device, including: an insulated circuit board having a metal plate on a lowermost side thereof; a stress relaxation layer formed on a lower surface of the metal plate and having a linear expansion coefficient larger than that of the metal plate; and a cooling module including a placement surface on which a lower surface of the stress relaxation layer is arranged via a thermally conductive adhesive.
The semiconductor device includes an insulating circuit board having an insulating substrate and a first conductor layer and a second conductor layer provided separately from each other on an upper surface of the insulating substrate, a semiconductor chip mounted on the first conductor layer via solder, an external terminal having a joining part, the joining part being joined to a first joining region via solder, the first joining region being one region of an upper surface of the second conductor layer, a printed circuit board arranged above the semiconductor chip, a first pin terminal inserted into the printed circuit board and joined to a second joining region via solder, the second joining region being another one region of the upper surface of the second conductor layer, and a solder resist provided on an upper surface side of the second conductor layer and adjacent to the first joining region.
A semiconductor module for use in a semiconductor device having a water jacket. The semiconductor module includes: a substrate; a semiconductor element mounted on the substrate; a cooler that has a heat dissipation base, and a plurality of heat dissipation fins positioned on the heat dissipation base, on a side thereof opposite to the substrate, the cooler being configured to be attached to the water jacket for allowing cooling water to flow in a flow direction through the plurality of heat dissipation fins; and an insulating material integrally forming a bottom portion that extends along the flow direction, and faces tips of at least a first subset of the plurality of heat dissipation fins, and a sidewall that extends from the bottom portion toward the heat dissipation base, and faces at least a second subset of the plurality of heat dissipation fins.
A semiconductor device includes: a base body of a first conductivity-type; a first well region of a second conductivity-type provided on a top surface side of the base body and provided with a high-side circuit; a voltage blocking structure provided to surround a circumference of the first well region; a level shifter provided in the voltage blocking structure; and first and second resistive field plates provided over the voltage blocking structure with an insulating film interposed, each having one end electrically connected to different semiconductor regions electrically connected to the high-side circuit.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
74.
SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR SUBSTRATE
A silicon carbide semiconductor device, including a semiconductor substrate having: a starting substrate containing silicon carbide and having a main surface; an epitaxial layer of a first conductivity type provided on the main surface of the starting substrate; and a base region of a second conductivity type provided on a side of the epitaxial layer opposite to the starting substrate. An impurity concentration distribution of the epitaxial layer continuously increases with a first impurity concentration gradient from a first depth position relatively close to a pn junction between the epitaxial layer and the base region toward a second depth position relatively close to the starting substrate, and has a gradient change point at at least one of the first depth position or the second depth position that connects to an impurity concentration gradient with an absolute value greater than that of the first impurity concentration gradient.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
75.
SIGNAL OUTPUT CIRCUIT, SWITCHING CONTROL CIRCUIT, AND SEMICONDUCTOR DEVICE
A signal output circuit outputting an output signal corresponding to an input signal, each of the input and output signals being at a logic level that is a first logic level or a second logic level. The signal output circuit includes: a first capacitor; a charge-discharge circuit configured to: charge the first capacitor when the input signal is at the second logic level and discharge the first capacitor when the output signal reaches the second logic level, and charge the first capacitor when the input signal is at the first logic level and discharges the first capacitor when the output signal reaches the first logic level, while the output signal is at the first logic level and the second logic level, respectively; and an inverting circuit inverting the logic level of the output signal, in response to a charge voltage of the first capacitor exceeding a reference voltage.
A semiconductor device, including: a circuit board; a wiring board facing the circuit board with a first gap therebetween, the wiring board having a wiring hole and a guide hole penetrating therethrough; a case; and a sealing member. The case includes: an armor member facing the wiring board with a second gap therebetween, an external connection terminal fixed to the armor member and having a lower end inserted into the wiring hole, a first spacer member protruding from a lower surface of the armor member to be inserted through the guide hole and having a lower end touching the circuit board, and a second spacer member protruding from the lower surface of the armor member having a lower end touching the wiring board. The sealing member fills the first gap and the second gap to thereby seal the wiring board.
There is provided a power storage system including: a DC bus; a plurality of batteries which are connected to the DC bus, and which are connected to each other in parallel; a plurality of diagnosis units each of which is provided for each of the plurality of batteries and measures a degradation state of a battery that is included in the plurality of batteries, by causing the battery to be discharged at a constant current or constant power; and a power conditioner which is connected to the DC bus, and which performs conversion between DC power and AC power, in which at least a part of power discharged from a battery under test among the plurality of batteries, the degradation state of which is being measured by the diagnosis unit, is charged into another at least one battery among the plurality of batteries, or is supplied to the power conditioner.
H02J 7/34 - Parallel operation in networks using both storage and other DC sources, e.g. providing buffering
G01R 31/3835 - Arrangements for monitoring battery or accumulator variables, e.g. SoC involving only voltage measurements
G01R 31/392 - Determining battery ageing or deterioration, e.g. state of health
H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A semiconductor device having a termination structure portion surrounding an active region. The semiconductor device includes: a semiconductor substrate; a first semiconductor layer provided on the semiconductor substrate; a parallel pn structure provided in the first semiconductor layer, including first and second column regions respectively being of first and second widths; first semiconductor regions provided in the parallel pn structure; second semiconductor regions selectively provided in the first semiconductor regions; a third semiconductor region provided in the parallel pn structure. The third semiconductor region has an end closer to the termination structure portion than a first position, and closer to the active region than a second position. An innermost second column region in the termination structure portion has a column end. The first and second positions are positions at distances equivalent to 50% of first and second widths, from the column end on inner and outer sides thereof, respectively.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/60 - Impurity distributions or concentrations
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
79.
TEMPERATURE DETECTING ELEMENT, SEMICONDUCTOR MODULE, AND MANUFACTURING METHOD OF TEMPERATURE DETECTING ELEMENT
Provided is a temperature detecting element, including: an anode electrode and a cathode electrode provided above the upper surface of the semiconductor substrate; a main cathode region of a first conductivity type connected to the cathode electrode; a main anode region of a second conductivity type, which is provided in contact with the main cathode region and connected to the anode electrode; and a conductive portion that connects one of the anode electrode and the cathode electrode to the lower surface of the semiconductor substrate at an identical potential.
G01K 7/01 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using semiconducting elements having PN junctions
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
Provided is a semiconductor device provided with an IGBT, comprising: a semiconductor substrate having upper and lower surfaces, throughout which bulk donors are distributed; a hydrogen peak including a local maximum arranged 25 μm or more away from the lower surface of the semiconductor substrate in a depth direction, at which a hydrogen chemical concentration shows a local maximum value; an upper tail where the hydrogen chemical concentration decreases in a direction from the local maximum toward the upper surface; and a lower tail where the hydrogen chemical concentration decreases in a direction from the local maximum toward the lower surface more gradually than the upper tail; and a first high concentration region having a donor concentration higher than a bulk donor concentration and including a region extending for 4 μm or more in a direction from the local maximum of the hydrogen peak toward the upper surface.
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/53 - Physical imperfections the imperfections being within the semiconductor body
H10D 84/60 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of BJTs
A semiconductor device includes: a semiconductor chip; a lead frame having a die pad at which the semiconductor chip is arranged, and a first lead and a second lead; a wire that connects the lead frame and the semiconductor chip; and a resin that seals the semiconductor chip. The die pad has a first surface and a second surface opposite to each other. The first lead has a first main body portion, a bent portion located at an end of the first main body portion, and an extending portion that extends from the bent portion to the die pad. The second lead has a second main body portion, and an end portion located at an end of the second main body portion inside the resin, and separated from the die pad. A height of the bent portion being higher than a height of the second lead.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
82.
BIAS CURRENT CIRCUIT, OVERCURRENT DETECTION CIRCUIT, AND SEMICONDUCTOR DEVICE
PROBLEM TO BE SOLVED: To provide new technique capable of performing overcurrent determination with low power consumption. ;SOLUTION: A bias current Iref made to flow through a differential amplifier part comprising an FET M01, M02, M03, and M04 is made to flow through a reference MOSFET (Metal Oxide Semiconductor Field Effect Transistor) Mr from which a voltage corresponding to a reference current can be obtained when making the reference current flow to obtain a level shift voltage Vis. A level of a detection voltage Vin corresponding to magnitude of a drain current of a main MOSFET Mm that is a target of overcurrent detection is shifted by the level shift voltage Vis, and it is applied to a gate terminal of the FET M03 that is one input of the differential amplifier part. A gate terminal of the FET M04 that is the other input of the differential amplifier part is connected to ground and is set as a round potential.
H02H 9/02 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
H02H 1/00 - Details of emergency protective circuit arrangements
H02H 7/12 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for convertersEmergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for rectifiers for static converters or rectifiers
83.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device, including: a semiconductor substrate; a first semiconductor layer provided on the semiconductor substrate; a second semiconductor layer provided on the first semiconductor layer; a first parallel pn structure and a second parallel pn structure provided in the second semiconductor layer, respectively in the active region and the termination structure portion; a plurality of second semiconductor regions, each provided in one of the first semiconductor regions in the active region; and a plurality of gate electrodes provided via gate insulating films in the active region. The first parallel pn structure includes first column regions and second column regions repeatedly alternating each other. The second parallel pn structure includes third column regions and fourth column regions repeatedly alternating each other. A column length of the second parallel pn structure is longer than that of the first parallel pn structure.
H10D 62/00 - Semiconductor bodies, or regions thereof, of devices having potential barriers
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
84.
SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS
Provided is a semiconductor device manufacturing method comprising: raising a temperature of a semiconductor substrate from a predetermined intake temperature to a predetermined deposition temperature; depositing, at a predetermined deposition position, a semiconductor layer on the semiconductor substrate at the deposition temperature; and lowering a temperature of the semiconductor substrate from the deposition temperature to a predetermined extraction temperature. The raising and the lowering may include at least one of: in the raising, moving the semiconductor substrate from an intake position to a temperature raising position different from the deposition position, or in the lowering, moving the semiconductor substrate from the deposition position to a temperature lowering position different from the deposition position.
A full-wave rectifier circuit having a first input line and a second input line that are configured to receive an alternating current (AC) voltage, an output line configured to output a full-wave rectified voltage, and a ground line that is grounded. The full-wave rectifier circuit further includes : a first diode, having an anode connected to the first input line and a cathode connected to the output line; a second diode, having an anode connected to the ground line and a cathode connected to the first input line; a third diode, having an anode connected to the second input line and a cathode connected to the output line; a fourth diode, having an anode connected to the ground line and a cathode connected to the second input line; and first to fourth capacitors connected in parallel with the first to fourth diodes, respectively.
H02M 1/14 - Arrangements for reducing ripples from DC input or output
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 7/219 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
A semiconductor device, including: a conductive plate; a case having a frame shape in a plan view of the semiconductor device, to thereby form an inner accommodating region in which the conductive plate is housed; and a terminal, including: a wiring portion that is partially fixed to the case and extends into the inner accommodating region, and a bonding portion including a bonding surface bonded to the conductive plate, and a main surface opposite to the bonding surface, and having indentations formed thereon. The wiring portion includes an extended portion extending from the case, the extended portion including a thinned portion that is thinner than all other portions of the terminal excluding the extended portion.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/057 - ContainersSeals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body the leads being parallel to the base
H01L 23/46 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A semiconductor device, including: an output unit that is connected to a load and includes a high-side switching element and a low-side switching element for driving the load; a high-side circuit, including a high-side operation detection circuit, which detects an operation state of the high-side switching element and generates first operation information, and a transmission circuit, which transmits the first operation information; and a low-side circuit, including a low-side operation detection circuit, which detects an operation state of the low-side switching element and generates second operation information, and an operation information notification circuit, which receives the first operation information transmitted from the high-side circuit by the transmission circuit and the second operation information, and notifies a periphery of data that includes at least one of the first operation information or the second operation information.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A semiconductor device, including: a multilayer substrate with a semiconductor element mounted thereon; and a main terminal having: a bonded portion bonded to a surface of the multilayer substrate, and extending in an extending direction; a vertical portion extending in a vertical direction; an extending portion extending toward outside of the multilayer substrate, and a bent portion interposed between the vertical portion and the extending portion, to thereby form: a narrow portion that includes the bonded portion, the vertical portion, the bent portion, and a first part of the extending portion, and a wide portion that includes a second part of the extending portion different from the first part. In a width direction perpendicular to the vertical direction and the extending direction, the wide portion is wider than the narrow portion, and the narrow portion is located on one end side of the wide portion.
H01L 23/047 - ContainersSeals characterised by the shape the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H10D 80/20 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising capacitors, power FETs or Schottky diodes
Provided is a semiconductor device including: a semiconductor substrate which has an upper surface and a lower surface; a drift region of a first conductivity type which is provided in the semiconductor substrate; a gate trench portion which is provided on an upper surface side of the semiconductor substrate and includes a gate conductive portion provided inside the semiconductor substrate and a gate dielectric film insulating the gate conductive portion from the semiconductor substrate; an adjacent trench portion which is arranged side by side with the gate trench portion in an array direction; and a base region of a second conductivity type which is provided in a mesa portion which is a region sandwiched between the gate trench portion and the adjacent trench portion.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/60 - Impurity distributions or concentrations
H10D 62/834 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
A semiconductor device, including: a semiconductor module having a lower surface; a cooling module including a placement surface on which the semiconductor module is placed, the placement surface being in contact with the lower surface of the semiconductor module; and a bonding member provided between the placement surface of the cooling module and the lower surface of the semiconductor module. The bonding member includes: an adhesive part that bonds the lower surface of the semiconductor module and the placement surface of the cooling module, and a spacer part that is provided at a periphery of the adhesive part, bonds the lower surface of the semiconductor module and the placement surface of the cooling module, and contains a first filler.
Provided is a semiconductor device, comprising: a circuit board with a wiring; a semiconductor device with a first main electrode and a second main electrode arranged on a first main surface; a bonding portion which bonds the first main electrode and the second main electrode to the wiring; and a resin portion provided in contact with the circuit board and the semiconductor device, in a region where the first main electrode and the second main electrode are not provided, wherein the bonding portion contains a resin; and the resin portion contains resin contains a resin of an identical component to the resin of the bonding portion.
H10D 80/20 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising capacitors, power FETs or Schottky diodes
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/367 - Cooling facilitated by shape of device
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
Provided is a semiconductor device including: a semiconductor substrate which has an upper surface and a lower surface and is provided with a drift region of a first conductivity type; an active portion which is provided in the semiconductor substrate; and an edge termination structure portion which is provided in the semiconductor substrate and provided between the active portion and an end portion of the semiconductor substrate at the upper surface of the semiconductor substrate, in which the edge termination structure portion includes an interlayer dielectric film which is provided on the upper surface of the semiconductor substrate, and a guard ring of a second conductivity type which is provided in the semiconductor substrate and is at least partially in contact with the interlayer dielectric film at the upper surface of the semiconductor substrate.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
A semiconductor module, including: a stacked substrate; a semiconductor device mounted on the stacked substrate via a bonding layer; an encapsulating resin encapsulating the semiconductor device, the bonding layer, and the stacked substrate; and a low-elastic-modulus element provided at a surface of the encapsulating resin above the semiconductor device, the low-elastic-modulus element having an elastic modulus that is lower than an elastic modulus of the encapsulating resin. The low-elastic-modulus element has a storage modulus that is a relative elastic modulus of 0.83% or more but less than 100%, when a storage modulus of the encapsulating resin is 100%.
A switching control circuit which controls a switching device included in a power source system which generates an output voltage from an AC input voltage, includes an input detection voltage acquisition unit which acquires an input detection voltage corresponding to the AC input voltage, a current detection voltage acquisition unit which acquires a current detection voltage generated in a current detection resistor which detects a current flowing through the switching device, a short circuit determination unit which determines, by comparing the current detection voltage with a predetermined short circuit threshold voltage, whether or not the current detection resistor is short circuited, and a driving unit which drives the switching device by a pulse width modulation method or a pulse frequency modulation method.
A silicon carbide semiconductor device, including: a semiconductor substrate, a first semiconductor region, a second semiconductor region, a plurality of third semiconductor regions; a plurality of fourth semiconductor regions; a plurality of fifth semiconductor regions; a plurality of trenches penetrating through the third semiconductor regions and the second semiconductor region and reaching the first semiconductor region; a plurality of gate electrodes provided in the plurality of trenches, via a plurality of gate insulating films, respectively; a first electrode connected to the fourth semiconductor regions and the third semiconductor regions; and a second electrode provided at a second main surface of the semiconductor substrate. The fifth semiconductor regions separates the second semiconductor region into first second-semiconductor-regions and second second-semiconductor-regions, each first second-semiconductor-region, but not second second-semiconductor-region, being directly adjacent to one of the gate insulating films. A thickness of each first second-semiconductor-region is in a range of 30 nm to 100 nm.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/60 - Impurity distributions or concentrations
H10D 62/834 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
An uninterruptible power supply includes an uninterruptible-power-supply module including a power converter to convert AC power supplied from an AC power supply and to supply converted AC power to a load, and a power conversion housing accommodating the power converter; a bus part arranged outside the power conversion housing to input/output power from/to the uninterruptible-power-supply modules; a module interrupter provided between the uninterruptible-power-supply module and the bus part to electrically disconnect the uninterruptible-power-supply module from the bus part; a bypass circuit part including a switching circuit for switching electrical conduction to supply AC power from a bypass AC power supply to the load; and a housing-accommodating part to accommodate the power conversion housing. A plurality of uninterruptible-power-supply modules is provided as the uninterruptible-power-supply module. The module interrupter includes a plurality of first interrupters and a plurality of second interrupters.
H02J 9/06 - Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over
A semiconductor device including a transistor portion and a diode portion has a cathode region of the first conductivity type which is provided on a back surface of the semiconductor substrate and has a higher doping concentration than that of the drift region, and a collector region of the second conductivity type which is provided on the back surface of the semiconductor substrate and has a higher doping concentration than that of the base region, and includes a mixed portion where a transistor region below which the collector region is provided and a diode region below which the cathode region is provided are alternately provided in the trench extension direction.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/53 - Physical imperfections the imperfections being within the semiconductor body
H10D 64/00 - Electrodes of devices having potential barriers
98.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device, including: a case having a frame shape in a plan view, an inner surface of the case surrounding a storage area; a conductive plate disposed in the storage area; and a terminal extending in an extending direction from the case to the storage area. The terminal has: a connection portion fixed to the case, and a bonding portion bonded to the conductive plate. The bonding portion includes: a bonding part having indentations on an upper surface thereof, and a low-rigidity part adjacent to the bonding part and being located between the bonding part and the inner surface. A thickness of the bonding portion decreases at the low-rigidity part and further decreases at the bonding part in the extending direction. In the plan view, the bonding part has a width larger than a width of a remaining portion of the bonding portion excluding the bonding part.
To suppress pump-out and degradation of a heat-dissipating adhesive layer of a power semiconductor module, and to provide a highly reliable semiconductor device, the present invention provides a semiconductor device including: a semiconductor module in which a laminated substrate (2) on which a semiconductor element (1) is mounted is sealed with a sealing material (8); a heat-dissipating plate (3) bonded to the laminated substrate; a heat-dissipating adhesive layer (4) provided in contact with the heat-dissipating plate, the layer including a rubber elastic body and a filler; a cooling component (6) provided in contact with the heat-dissipating adhesive layer; and a protective layer (5) that covers at least a part of a surface of the heat-dissipating adhesive layer, wherein the protective layer includes a silicone compound and a filler, and has a tensile strength of 0.2 to 4.5 MPa.
H01L 23/367 - Cooling facilitated by shape of device
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
100.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a semiconductor device with a configuration contributing to a decrease in size. The semiconductor device includes an insulated circuit substrate provided with conductive layers on the top surface side, semiconductor chips provided on the conductive layers, a wiring substrate provided on the semiconductor chips, and an output terminal having one end side and a negative-electrode terminal having one end side, each one end side being located between the conductive layers and the wiring substrate. The semiconductor device further includes inter-substrate connection pins having upper end sides inserted with pressure to first penetration holes provided in the wiring substrate and lower end sides inserted with pressure to second penetration holes provided in top surfaces of the output terminal and the negative-electrode terminal.
H10D 80/20 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising capacitors, power FETs or Schottky diodes
patents
